arm: mvebu: support for the new Armada XP development board(DB-MV784MP-GP)

This is the new Armada XP evaluation board from Marvell. It comes with
a RS232 port over USB, a SATA link, an internal SSD, 4 Ethernet
Gigabit links.

Support for USB (Host and device), SDIO, PCIe will be added as drivers
when they become available for Armada XP in mainline.

Tested-by: Simon Guinot <simon.guinot@sequanux.org>
Tested-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

1 files changed, 101 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
new file mode 100644
index 000000000000..3eea53106a1f
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -0,0 +1,101 @@
+/*
+ * Device Tree file for Marvell Armada XP development board
+ * (DB-MV784MP-GP)
+ *
+ * Copyright (C) 2013 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "armada-xp-mv78460.dtsi"
+
+/ {
+        model = "Marvell Armada XP Development Board DB-MV784MP-GP";
+        compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+
+                /*
+                 * 4 GB of plug-in RAM modules by default but only 3GB
+                 * are visible, the amount of memory available can be
+                 * changed by the bootloader according the size of the
+                 * module actually plugged
+                 */
+                reg = <0x00000000 0xC0000000>;
+        };
+
+        soc {
+                serial@d0012000 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012100 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012200 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012300 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+
+                sata@d00a0000 {
+                        nr-ports = <2>;
+                        status = "okay";
+                };
+
+                mdio {
+                        phy0: ethernet-phy@0 {
+                                reg = <16>;
+                        };
+
+                        phy1: ethernet-phy@1 {
+                                reg = <17>;
+                        };
+
+                        phy2: ethernet-phy@2 {
+                                reg = <18>;
+                        };
+
+                        phy3: ethernet-phy@3 {
+                                reg = <19>;
+                        };
+                };
+
+                ethernet@d0070000 {
+                        status = "okay";
+                        phy = <&phy0>;
+                        phy-mode = "rgmii-id";
+                };
+                ethernet@d0074000 {
+                        status = "okay";
+                        phy = <&phy1>;
+                        phy-mode = "rgmii-id";
+                };
+                ethernet@d0030000 {
+                        status = "okay";
+                        phy = <&phy2>;
+                        phy-mode = "rgmii-id";
+                };
+                ethernet@d0034000 {
+                        status = "okay";
+                        phy = <&phy3>;
+                        phy-mode = "rgmii-id";
+                };
+        };
+};