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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2015-03-03 09:41:12 -0500
committerGregory CLEMENT <gregory.clement@free-electrons.com>2015-03-04 09:42:34 -0500
commit538da83ddbeaa422a48e9bd0a12a0bc246c567f4 (patch)
tree87e0b7f847ea55f1a4e91bfb9227cf00da506d9f /arch/arm/boot/dts/armada-39x.dtsi
parent24c2573bdb9203259a822a4e3ed90795b273d3ab (diff)
ARM: mvebu: add Device Tree files for Armada 39x SoC and board
This commit adds the Device Tree files for the Armada 39x family of processors, as well as one Armada 398 Development Board. Like for other Marvell EBU families, a common armada-39x.dtsi contains the description of the common features of all Armada 39x SoCs, while armada-390.dtsi and armada-398.dtsi respectively describe the specificities of those SoCs. Finally, an armada-398-db.dts file is added to describe the Armada 398 Development Board itself. So far, the following features are supported: * SMP: dual Cortex-A9 * Basic ARM IPs: SCU, timer, GIC, L2 cache * Basic Marvell IPs: pin-muxing, clocks, system controller, MBus controller, MPIC interrupt controller, timer, CPU reset for SMP, PMSU. * I2C * SPI * SDHCI * XOR * NAND * UART * PCIe Additional features will be supported in the future. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-39x.dtsi')
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diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
new file mode 100644
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1/*
2 * Device Tree Include file for Marvell Armada 39x family of SoCs.
3 *
4 * Copyright (C) 2015 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include "skeleton.dtsi"
48#include <dt-bindings/interrupt-controller/arm-gic.h>
49#include <dt-bindings/interrupt-controller/irq.h>
50
51#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
52
53/ {
54 model = "Marvell Armada 39x family SoC";
55 compatible = "marvell,armada390";
56
57 aliases {
58 serial0 = &uart0;
59 serial1 = &uart1;
60 serial2 = &uart2;
61 serial3 = &uart3;
62 };
63
64 cpus {
65 #address-cells = <1>;
66 #size-cells = <0>;
67 enable-method = "marvell,armada-390-smp";
68
69 cpu@0 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a9";
72 reg = <0>;
73 };
74 cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a9";
77 reg = <1>;
78 };
79 };
80
81 soc {
82 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
83 "simple-bus";
84 #address-cells = <2>;
85 #size-cells = <1>;
86 controller = <&mbusc>;
87 interrupt-parent = <&gic>;
88 pcie-mem-aperture = <0xe0000000 0x8000000>;
89 pcie-io-aperture = <0xe8000000 0x100000>;
90
91 bootrom {
92 compatible = "marvell,bootrom";
93 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
94 };
95
96 internal-regs {
97 compatible = "simple-bus";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
101
102 L2: cache-controller@8000 {
103 compatible = "arm,pl310-cache";
104 reg = <0x8000 0x1000>;
105 cache-unified;
106 cache-level = <2>;
107 };
108
109 scu@c000 {
110 compatible = "arm,cortex-a9-scu";
111 reg = <0xc000 0x100>;
112 };
113
114 timer@c600 {
115 compatible = "arm,cortex-a9-twd-timer";
116 reg = <0xc600 0x20>;
117 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
118 clocks = <&coreclk 2>;
119 };
120
121 gic: interrupt-controller@d000 {
122 compatible = "arm,cortex-a9-gic";
123 #interrupt-cells = <3>;
124 #size-cells = <0>;
125 interrupt-controller;
126 reg = <0xd000 0x1000>,
127 <0xc100 0x100>;
128 };
129
130 spi0: spi@10600 {
131 compatible = "marvell,orion-spi";
132 reg = <0x10600 0x50>;
133 #address-cells = <1>;
134 #size-cells = <0>;
135 cell-index = <0>;
136 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&coreclk 0>;
138 status = "disabled";
139 };
140
141 spi1: spi@10680 {
142 compatible = "marvell,orion-spi";
143 reg = <0x10680 0x50>;
144 #address-cells = <1>;
145 #size-cells = <0>;
146 cell-index = <1>;
147 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&coreclk 0>;
149 status = "disabled";
150 };
151
152 i2c0: i2c@11000 {
153 compatible = "marvell,mv64xxx-i2c";
154 reg = <0x11000 0x20>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
158 timeout-ms = <1000>;
159 clocks = <&coreclk 0>;
160 status = "disabled";
161 };
162
163 i2c1: i2c@11100 {
164 compatible = "marvell,mv64xxx-i2c";
165 reg = <0x11100 0x20>;
166 #address-cells = <1>;
167 #size-cells = <0>;
168 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
169 timeout-ms = <1000>;
170 clocks = <&coreclk 0>;
171 status = "disabled";
172 };
173
174 i2c2: i2c@11200 {
175 compatible = "marvell,mv64xxx-i2c";
176 reg = <0x11200 0x20>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
180 timeout-ms = <1000>;
181 clocks = <&coreclk 0>;
182 status = "disabled";
183 };
184
185 i2c3: i2c@11300 {
186 compatible = "marvell,mv64xxx-i2c";
187 reg = <0x11300 0x20>;
188 #address-cells = <1>;
189 #size-cells = <0>;
190 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
191 timeout-ms = <1000>;
192 clocks = <&coreclk 0>;
193 status = "disabled";
194 };
195
196 uart0: serial@12000 {
197 compatible = "snps,dw-apb-uart";
198 reg = <0x12000 0x100>;
199 reg-shift = <2>;
200 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
201 reg-io-width = <1>;
202 clocks = <&coreclk 0>;
203 status = "disabled";
204 };
205
206 uart1: serial@12100 {
207 compatible = "snps,dw-apb-uart";
208 reg = <0x12100 0x100>;
209 reg-shift = <2>;
210 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
211 reg-io-width = <1>;
212 clocks = <&coreclk 0>;
213 status = "disabled";
214 };
215
216 uart2: serial@12200 {
217 compatible = "snps,dw-apb-uart";
218 reg = <0x12200 0x100>;
219 reg-shift = <2>;
220 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
221 reg-io-width = <1>;
222 clocks = <&coreclk 0>;
223 status = "disabled";
224 };
225
226 uart3: serial@12300 {
227 compatible = "snps,dw-apb-uart";
228 reg = <0x12300 0x100>;
229 reg-shift = <2>;
230 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
231 reg-io-width = <1>;
232 clocks = <&coreclk 0>;
233 status = "disabled";
234 };
235
236 pinctrl@18000 {
237 i2c0_pins: i2c0-pins {
238 marvell,pins = "mpp2", "mpp3";
239 marvell,function = "i2c0";
240 };
241
242 uart0_pins: uart0-pins {
243 marvell,pins = "mpp0", "mpp1";
244 marvell,function = "ua0";
245 };
246
247 uart1_pins: uart1-pins {
248 marvell,pins = "mpp19", "mpp20";
249 marvell,function = "ua1";
250 };
251
252 spi1_pins: spi1-pins {
253 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
254 marvell,function = "spi1";
255 };
256
257 nand_pins: nand-pins {
258 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
259 "mpp38", "mpp28", "mpp40", "mpp42",
260 "mpp35", "mpp36", "mpp25", "mpp30",
261 "mpp32";
262 marvell,function = "dev";
263 };
264 };
265
266 system-controller@18200 {
267 compatible = "marvell,armada-390-system-controller",
268 "marvell,armada-370-xp-system-controller";
269 reg = <0x18200 0x100>;
270 };
271
272 gateclk: clock-gating-control@18220 {
273 compatible = "marvell,armada-390-gating-clock";
274 reg = <0x18220 0x4>;
275 clocks = <&coreclk 0>;
276 #clock-cells = <1>;
277 };
278
279 coreclk: mvebu-sar@18600 {
280 compatible = "marvell,armada-390-core-clock";
281 reg = <0x18600 0x04>;
282 #clock-cells = <1>;
283 };
284
285 mbusc: mbus-controller@20000 {
286 compatible = "marvell,mbus-controller";
287 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
288 };
289
290 mpic: interrupt-controller@20a00 {
291 compatible = "marvell,mpic";
292 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
293 #interrupt-cells = <1>;
294 #size-cells = <1>;
295 interrupt-controller;
296 msi-controller;
297 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
298 };
299
300 timer@20300 {
301 compatible = "marvell,armada-380-timer",
302 "marvell,armada-xp-timer";
303 reg = <0x20300 0x30>, <0x21040 0x30>;
304 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
305 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
306 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
307 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
308 <&mpic 5>,
309 <&mpic 6>;
310 clocks = <&coreclk 2>, <&coreclk 5>;
311 clock-names = "nbclk", "fixed";
312 };
313
314 cpurst@20800 {
315 compatible = "marvell,armada-370-cpu-reset";
316 reg = <0x20800 0x10>;
317 };
318
319 pmsu@22000 {
320 compatible = "marvell,armada-390-pmsu",
321 "marvell,armada-380-pmsu";
322 reg = <0x22000 0x1000>;
323 };
324
325 xor@60800 {
326 compatible = "marvell,orion-xor";
327 reg = <0x60800 0x100
328 0x60a00 0x100>;
329 clocks = <&gateclk 22>;
330 status = "okay";
331
332 xor00 {
333 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
334 dmacap,memcpy;
335 dmacap,xor;
336 };
337 xor01 {
338 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
339 dmacap,memcpy;
340 dmacap,xor;
341 dmacap,memset;
342 };
343 };
344
345 xor@60900 {
346 compatible = "marvell,orion-xor";
347 reg = <0x60900 0x100
348 0x60b00 0x100>;
349 clocks = <&gateclk 28>;
350 status = "okay";
351
352 xor10 {
353 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
354 dmacap,memcpy;
355 dmacap,xor;
356 };
357 xor11 {
358 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
359 dmacap,memcpy;
360 dmacap,xor;
361 dmacap,memset;
362 };
363 };
364
365 flash@d0000 {
366 compatible = "marvell,armada370-nand";
367 reg = <0xd0000 0x54>;
368 #address-cells = <1>;
369 #size-cells = <1>;
370 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&coredivclk 0>;
372 status = "disabled";
373 };
374
375 sdhci@d8000 {
376 compatible = "marvell,armada-380-sdhci";
377 reg = <0xd8000 0x1000>, <0xdc000 0x100>;
378 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&gateclk 17>;
380 mrvl,clk-delay-cycles = <0x1F>;
381 status = "disabled";
382 };
383
384 coredivclk: clock@e4250 {
385 compatible = "marvell,armada-390-corediv-clock",
386 "marvell,armada-380-corediv-clock";
387 reg = <0xe4250 0xc>;
388 #clock-cells = <1>;
389 clocks = <&mainpll>;
390 clock-output-names = "nand";
391 };
392 };
393
394 pcie-controller {
395 compatible = "marvell,armada-370-pcie";
396 status = "disabled";
397 device_type = "pci";
398
399 #address-cells = <3>;
400 #size-cells = <2>;
401
402 msi-parent = <&mpic>;
403 bus-range = <0x00 0xff>;
404
405 ranges =
406 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
407 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
408 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
409 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
410 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
411 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
412 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
413 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
414 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
415 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
416 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
417 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
418
419 /*
420 * This port can be either x4 or x1. When
421 * configured in x4 by the bootloader, then
422 * pcie@4,0 is not available.
423 */
424 pcie@1,0 {
425 device_type = "pci";
426 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
427 reg = <0x0800 0 0 0 0>;
428 #address-cells = <3>;
429 #size-cells = <2>;
430 #interrupt-cells = <1>;
431 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
432 0x81000000 0 0 0x81000000 0x1 0 1 0>;
433 interrupt-map-mask = <0 0 0 0>;
434 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
435 marvell,pcie-port = <0>;
436 marvell,pcie-lane = <0>;
437 clocks = <&gateclk 8>;
438 status = "disabled";
439 };
440
441 /* x1 port */
442 pcie@2,0 {
443 device_type = "pci";
444 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
445 reg = <0x1000 0 0 0 0>;
446 #address-cells = <3>;
447 #size-cells = <2>;
448 #interrupt-cells = <1>;
449 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
450 0x81000000 0 0 0x81000000 0x2 0 1 0>;
451 interrupt-map-mask = <0 0 0 0>;
452 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
453 marvell,pcie-port = <1>;
454 marvell,pcie-lane = <0>;
455 clocks = <&gateclk 5>;
456 status = "disabled";
457 };
458
459 /* x1 port */
460 pcie@3,0 {
461 device_type = "pci";
462 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
463 reg = <0x1800 0 0 0 0>;
464 #address-cells = <3>;
465 #size-cells = <2>;
466 #interrupt-cells = <1>;
467 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
468 0x81000000 0 0 0x81000000 0x3 0 1 0>;
469 interrupt-map-mask = <0 0 0 0>;
470 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
471 marvell,pcie-port = <2>;
472 marvell,pcie-lane = <0>;
473 clocks = <&gateclk 6>;
474 status = "disabled";
475 };
476
477 /*
478 * x1 port only available when pcie@1,0 is
479 * configured as a x1 port
480 */
481 pcie@4,0 {
482 device_type = "pci";
483 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
484 reg = <0x2000 0 0 0 0>;
485 #address-cells = <3>;
486 #size-cells = <2>;
487 #interrupt-cells = <1>;
488 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
489 0x81000000 0 0 0x81000000 0x4 0 1 0>;
490 interrupt-map-mask = <0 0 0 0>;
491 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
492 marvell,pcie-port = <3>;
493 marvell,pcie-lane = <0>;
494 clocks = <&gateclk 7>;
495 status = "disabled";
496 };
497 };
498 };
499
500 clocks {
501 /* 2 GHz fixed main PLL */
502 mainpll: mainpll {
503 compatible = "fixed-clock";
504 #clock-cells = <0>;
505 clock-frequency = <2000000000>;
506 };
507 };
508};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 15:11:50 -0500