ARM: mvebu: add Device Tree for the Armada 385 DB board

The Armada 385 DB board is the development board from Marvell for the
Armada 385 SoC. This commit adds a Device Tree description for this
board, which enables the following features:

 * Network interfaces
 * I2C buses
 * SDIO
 * Serial port
 * SPI bus, with a SPI flash
 * PCIe interfaces

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

1 files changed, 101 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
new file mode 100644
index 000000000000..01b6cc76ddc8
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -0,0 +1,101 @@
+/*
+ * Device Tree file for Marvell Armada 385 evaluation board
+ * (DB-88F6820)
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "armada-385.dtsi"
+
+/ {
+        model = "Marvell Armada 385 Development Board";
+        compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>; /* 256 MB */
+        };
+
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+                          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+                internal-regs {
+                        spi@10600 {
+                                status = "okay";
+
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "w25q32";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <108000000>;
+                                };
+                        };
+
+                        i2c@11000 {
+                                status = "okay";
+                                clock-frequency = <100000>;
+                        };
+
+                        i2c@11100 {
+                                status = "okay";
+                                clock-frequency = <100000>;
+                        };
+
+                        serial@12000 {
+                                clock-frequency = <200000000>;
+                                status = "okay";
+                        };
+
+                        ethernet@30000 {
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii";
+                        };
+
+                        ethernet@70000 {
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii";
+                        };
+
+                        mdio {
+                                phy0: ethernet-phy@0 {
+                                        reg = <0>;
+                                };
+
+                                phy1: ethernet-phy@1 {
+                                        reg = <1>;
+                                };
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+                        /*
+                         * The two PCIe units are accessible through
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@2,0 {
+                                /* Port 1, Lane 0 */
+                                status = "okay";
+                        };
+                };
+        };
+};