ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level

For L2 cache controller node, cache-level property is mandatory. Let's
add it to Armada 370 and Armada XP device tree.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 50f259b20f94..00b50db57c9c 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -129,6 +129,7 @@
                                 compatible = "marvell,aurora-outer-cache";
                                 reg = <0x08000 0x1000>;
                                 cache-id-part = <0x100>;
+                                cache-level = <2>;
                                 cache-unified;
                                 wt-override;
                         };