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authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>2013-10-18 19:02:31 -0400
committerJason Cooper <jason@lakedaemon.net>2013-10-23 07:04:31 -0400
commitf039dfb51b36a2d7e4ac25e65ffbd03e3ac77a0c (patch)
tree55d4034cacbbf231f0efde5255d179264448a7e5 /arch/arm/boot/dts/armada-370-xp.dtsi
parent4675cf577e4bbe179df1cf10a6fab8854333d99d (diff)
ARM: mvebu: Add the core-divider clock to Armada 370/XP
The Armada 370/XP SoC has a clock provider called "Core Divider", that is derived from a fixed 2 GHz PLL clock. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-370-xp.dtsi')
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 13efe05a8c9f..00d6a798c705 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -138,6 +138,14 @@
138 status = "disabled"; 138 status = "disabled";
139 }; 139 };
140 140
141 coredivclk: corediv-clock@18740 {
142 compatible = "marvell,armada-370-corediv-clock";
143 reg = <0x18740 0xc>;
144 #clock-cells = <1>;
145 clocks = <&mainpll>;
146 clock-output-names = "nand";
147 };
148
141 timer@20300 { 149 timer@20300 {
142 reg = <0x20300 0x30>, <0x21040 0x30>; 150 reg = <0x20300 0x30>, <0x21040 0x30>;
143 interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 151 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;