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authorEnric Balletbo i Serra <eballetbo@gmail.com>2013-11-26 18:03:38 -0500
committerTony Lindgren <tony@atomide.com>2013-11-26 18:03:38 -0500
commit0710b679862dc730eb9900592649929da3ec824e (patch)
tree0972d2d712c578650af87fbaee910e546660ac3c /arch/arm/boot/dts/am335x-base0033.dts
parent50592dc30ca3617b7b66abd7071930e2489bff26 (diff)
ARM: dts: AM33XX BASE0033: add pinmux and hdmi node to enable display
Enable the hdmi output and the LCD Controller on IGEP AQUILA. Also configure the correct pinmux for output of video data from the SoC to the HDMI encoder. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/am335x-base0033.dts')
-rw-r--r--arch/arm/boot/dts/am335x-base0033.dts46
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts
index b4f95c2bbf74..620970c0c99a 100644
--- a/arch/arm/boot/dts/am335x-base0033.dts
+++ b/arch/arm/boot/dts/am335x-base0033.dts
@@ -13,4 +13,50 @@
13/ { 13/ {
14 model = "IGEP COM AM335x on AQUILA Expansion"; 14 model = "IGEP COM AM335x on AQUILA Expansion";
15 compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; 15 compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
16
17 hdmi {
18 compatible = "ti,tilcdc,slave";
19 i2c = <&i2c0>;
20 pinctrl-names = "default", "off";
21 pinctrl-0 = <&nxp_hdmi_pins>;
22 pinctrl-1 = <&nxp_hdmi_off_pins>;
23 status = "okay";
24 };
25};
26
27&am33xx_pinmux {
28 nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
29 pinctrl-single,pins = <
30 0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
31 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
32 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
33 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
34 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
35 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
36 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
37 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
38 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
39 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
40 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
41 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
42 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
43 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
44 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
45 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
46 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
47 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
48 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
49 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
50 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
51 >;
52 };
53 nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
54 pinctrl-single,pins = <
55 0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
56 >;
57 };
58};
59
60&lcdc {
61 status = "okay";
16}; 62};