diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-16 22:03:06 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-16 22:03:06 -0400 |
commit | 16d8775700f1815076f879719ce14b33f50a3171 (patch) | |
tree | 8525e6e6f12b6acf7cf2746853cc65549f3dbf4c /arch/arm/Kconfig | |
parent | e34551339a195aa548eaf698523714a8fe7f1984 (diff) | |
parent | 05e34754518b6a90d5c392790c032575fab12d66 (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (91 commits)
ARM: 6806/1: irq: introduce entry and exit functions for chained handlers
ARM: 6781/1: Thumb-2: Work around buggy Thumb-2 short branch relocations in gas
ARM: 6747/1: P2V: Thumb2 support
ARM: 6798/1: aout-core: zero thread debug registers in a.out core dump
ARM: 6796/1: Footbridge: Fix I/O mappings for NOMMU mode
ARM: 6784/1: errata: no automatic Store Buffer drain on Cortex-A9
ARM: 6772/1: errata: possible fault MMU translations following an ASID switch
ARM: 6776/1: mach-ux500: activate fix for errata 753970
ARM: 6794/1: SPEAr: Append UL to device address macros.
ARM: 6793/1: SPEAr: Remove unused *_SIZE macros from spear*.h files
ARM: 6792/1: SPEAr: Replace SIZE macro's with SZ_4K macros
ARM: 6791/1: SPEAr3xx: Declare device structures after shirq code
ARM: 6790/1: SPEAr: Clock Framework: Rename usbd clock and align apb_clk entry
ARM: 6789/1: SPEAr3xx: Rename sdio to sdhci
ARM: 6788/1: SPEAr: Include mach/hardware.h instead of mach/spear.h
ARM: 6787/1: SPEAr: Reorder #includes in .h & .c files.
ARM: 6681/1: SPEAr: add debugfs support to clk API
ARM: 6703/1: SPEAr: update clk API support
ARM: 6679/1: SPEAr: make clk API functions more generic
ARM: 6737/1: SPEAr: formalized timer support
...
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r-- | arch/arm/Kconfig | 134 |
1 files changed, 119 insertions, 15 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 166efa2a19cd..48a0628d93e8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -7,7 +7,7 @@ config ARM | |||
7 | select HAVE_MEMBLOCK | 7 | select HAVE_MEMBLOCK |
8 | select RTC_LIB | 8 | select RTC_LIB |
9 | select SYS_SUPPORTS_APM_EMULATION | 9 | select SYS_SUPPORTS_APM_EMULATION |
10 | select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI) | 10 | select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI) |
11 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) | 11 | select HAVE_OPROFILE if (HAVE_PERF_EVENTS) |
12 | select HAVE_ARCH_KGDB | 12 | select HAVE_ARCH_KGDB |
13 | select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL) | 13 | select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL) |
@@ -24,7 +24,7 @@ config ARM | |||
24 | select HAVE_PERF_EVENTS | 24 | select HAVE_PERF_EVENTS |
25 | select PERF_USE_VMALLOC | 25 | select PERF_USE_VMALLOC |
26 | select HAVE_REGS_AND_STACK_ACCESS_API | 26 | select HAVE_REGS_AND_STACK_ACCESS_API |
27 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7)) | 27 | select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) |
28 | select HAVE_C_RECORDMCOUNT | 28 | select HAVE_C_RECORDMCOUNT |
29 | select HAVE_GENERIC_HARDIRQS | 29 | select HAVE_GENERIC_HARDIRQS |
30 | select HAVE_SPARSE_IRQ | 30 | select HAVE_SPARSE_IRQ |
@@ -63,6 +63,10 @@ config GENERIC_CLOCKEVENTS_BROADCAST | |||
63 | depends on GENERIC_CLOCKEVENTS | 63 | depends on GENERIC_CLOCKEVENTS |
64 | default y if SMP | 64 | default y if SMP |
65 | 65 | ||
66 | config KTIME_SCALAR | ||
67 | bool | ||
68 | default y | ||
69 | |||
66 | config HAVE_TCM | 70 | config HAVE_TCM |
67 | bool | 71 | bool |
68 | select GENERIC_ALLOCATOR | 72 | select GENERIC_ALLOCATOR |
@@ -178,11 +182,6 @@ config FIQ | |||
178 | config ARCH_MTD_XIP | 182 | config ARCH_MTD_XIP |
179 | bool | 183 | bool |
180 | 184 | ||
181 | config ARM_L1_CACHE_SHIFT_6 | ||
182 | bool | ||
183 | help | ||
184 | Setting ARM L1 cache line size to 64 Bytes. | ||
185 | |||
186 | config VECTORS_BASE | 185 | config VECTORS_BASE |
187 | hex | 186 | hex |
188 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR | 187 | default 0xffff0000 if MMU || CPU_HIGH_VECTOR |
@@ -191,6 +190,22 @@ config VECTORS_BASE | |||
191 | help | 190 | help |
192 | The base address of exception vectors. | 191 | The base address of exception vectors. |
193 | 192 | ||
193 | config ARM_PATCH_PHYS_VIRT | ||
194 | bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)" | ||
195 | depends on EXPERIMENTAL | ||
196 | depends on !XIP_KERNEL && MMU | ||
197 | depends on !ARCH_REALVIEW || !SPARSEMEM | ||
198 | help | ||
199 | Patch phys-to-virt translation functions at runtime according to | ||
200 | the position of the kernel in system memory. | ||
201 | |||
202 | This can only be used with non-XIP with MMU kernels where | ||
203 | the base of physical memory is at a 16MB boundary. | ||
204 | |||
205 | config ARM_PATCH_PHYS_VIRT_16BIT | ||
206 | def_bool y | ||
207 | depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM | ||
208 | |||
194 | source "init/Kconfig" | 209 | source "init/Kconfig" |
195 | 210 | ||
196 | source "kernel/Kconfig.freezer" | 211 | source "kernel/Kconfig.freezer" |
@@ -346,7 +361,7 @@ config ARCH_FOOTBRIDGE | |||
346 | bool "FootBridge" | 361 | bool "FootBridge" |
347 | select CPU_SA110 | 362 | select CPU_SA110 |
348 | select FOOTBRIDGE | 363 | select FOOTBRIDGE |
349 | select ARCH_USES_GETTIMEOFFSET | 364 | select GENERIC_CLOCKEVENTS |
350 | help | 365 | help |
351 | Support for systems based on the DC21285 companion chip | 366 | Support for systems based on the DC21285 companion chip |
352 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | 367 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. |
@@ -457,6 +472,7 @@ config ARCH_IXP4XX | |||
457 | 472 | ||
458 | config ARCH_DOVE | 473 | config ARCH_DOVE |
459 | bool "Marvell Dove" | 474 | bool "Marvell Dove" |
475 | select CPU_V6K | ||
460 | select PCI | 476 | select PCI |
461 | select ARCH_REQUIRE_GPIOLIB | 477 | select ARCH_REQUIRE_GPIOLIB |
462 | select GENERIC_CLOCKEVENTS | 478 | select GENERIC_CLOCKEVENTS |
@@ -875,6 +891,16 @@ config PLAT_SPEAR | |||
875 | help | 891 | help |
876 | Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). | 892 | Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). |
877 | 893 | ||
894 | config ARCH_VT8500 | ||
895 | bool "VIA/WonderMedia 85xx" | ||
896 | select CPU_ARM926T | ||
897 | select GENERIC_GPIO | ||
898 | select ARCH_HAS_CPUFREQ | ||
899 | select GENERIC_CLOCKEVENTS | ||
900 | select ARCH_REQUIRE_GPIOLIB | ||
901 | select HAVE_PWM | ||
902 | help | ||
903 | Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. | ||
878 | endchoice | 904 | endchoice |
879 | 905 | ||
880 | # | 906 | # |
@@ -1007,6 +1033,8 @@ source "arch/arm/mach-versatile/Kconfig" | |||
1007 | 1033 | ||
1008 | source "arch/arm/mach-vexpress/Kconfig" | 1034 | source "arch/arm/mach-vexpress/Kconfig" |
1009 | 1035 | ||
1036 | source "arch/arm/mach-vt8500/Kconfig" | ||
1037 | |||
1010 | source "arch/arm/mach-w90x900/Kconfig" | 1038 | source "arch/arm/mach-w90x900/Kconfig" |
1011 | 1039 | ||
1012 | # Definitions to make life easier | 1040 | # Definitions to make life easier |
@@ -1048,7 +1076,7 @@ config XSCALE_PMU | |||
1048 | default y | 1076 | default y |
1049 | 1077 | ||
1050 | config CPU_HAS_PMU | 1078 | config CPU_HAS_PMU |
1051 | depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \ | 1079 | depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ |
1052 | (!ARCH_OMAP3 || OMAP3_EMU) | 1080 | (!ARCH_OMAP3 || OMAP3_EMU) |
1053 | default y | 1081 | default y |
1054 | bool | 1082 | bool |
@@ -1064,7 +1092,7 @@ endif | |||
1064 | 1092 | ||
1065 | config ARM_ERRATA_411920 | 1093 | config ARM_ERRATA_411920 |
1066 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" | 1094 | bool "ARM errata: Invalidation of the Instruction Cache operation can fail" |
1067 | depends on CPU_V6 | 1095 | depends on CPU_V6 || CPU_V6K |
1068 | help | 1096 | help |
1069 | Invalidation of the Instruction Cache operation can | 1097 | Invalidation of the Instruction Cache operation can |
1070 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. | 1098 | fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. |
@@ -1140,7 +1168,7 @@ config ARM_ERRATA_742231 | |||
1140 | 1168 | ||
1141 | config PL310_ERRATA_588369 | 1169 | config PL310_ERRATA_588369 |
1142 | bool "Clean & Invalidate maintenance operations do not invalidate clean lines" | 1170 | bool "Clean & Invalidate maintenance operations do not invalidate clean lines" |
1143 | depends on CACHE_L2X0 && ARCH_OMAP4 | 1171 | depends on CACHE_L2X0 |
1144 | help | 1172 | help |
1145 | The PL310 L2 cache controller implements three types of Clean & | 1173 | The PL310 L2 cache controller implements three types of Clean & |
1146 | Invalidate maintenance operations: by Physical Address | 1174 | Invalidate maintenance operations: by Physical Address |
@@ -1149,8 +1177,7 @@ config PL310_ERRATA_588369 | |||
1149 | clean operation followed immediately by an invalidate operation, | 1177 | clean operation followed immediately by an invalidate operation, |
1150 | both performing to the same memory location. This functionality | 1178 | both performing to the same memory location. This functionality |
1151 | is not correctly implemented in PL310 as clean lines are not | 1179 | is not correctly implemented in PL310 as clean lines are not |
1152 | invalidated as a result of these operations. Note that this errata | 1180 | invalidated as a result of these operations. |
1153 | uses Texas Instrument's secure monitor api. | ||
1154 | 1181 | ||
1155 | config ARM_ERRATA_720789 | 1182 | config ARM_ERRATA_720789 |
1156 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" | 1183 | bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" |
@@ -1164,6 +1191,17 @@ config ARM_ERRATA_720789 | |||
1164 | tables. The workaround changes the TLB flushing routines to invalidate | 1191 | tables. The workaround changes the TLB flushing routines to invalidate |
1165 | entries regardless of the ASID. | 1192 | entries regardless of the ASID. |
1166 | 1193 | ||
1194 | config PL310_ERRATA_727915 | ||
1195 | bool "Background Clean & Invalidate by Way operation can cause data corruption" | ||
1196 | depends on CACHE_L2X0 | ||
1197 | help | ||
1198 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | ||
1199 | operation (offset 0x7FC). This operation runs in background so that | ||
1200 | PL310 can handle normal accesses while it is in progress. Under very | ||
1201 | rare circumstances, due to this erratum, write data can be lost when | ||
1202 | PL310 treats a cacheable write transaction during a Clean & | ||
1203 | Invalidate by Way operation. | ||
1204 | |||
1167 | config ARM_ERRATA_743622 | 1205 | config ARM_ERRATA_743622 |
1168 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | 1206 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" |
1169 | depends on CPU_V7 | 1207 | depends on CPU_V7 |
@@ -1202,6 +1240,28 @@ config ARM_ERRATA_753970 | |||
1202 | This has the same effect as the cache sync operation: store buffer | 1240 | This has the same effect as the cache sync operation: store buffer |
1203 | drain and waiting for all buffers empty. | 1241 | drain and waiting for all buffers empty. |
1204 | 1242 | ||
1243 | config ARM_ERRATA_754322 | ||
1244 | bool "ARM errata: possible faulty MMU translations following an ASID switch" | ||
1245 | depends on CPU_V7 | ||
1246 | help | ||
1247 | This option enables the workaround for the 754322 Cortex-A9 (r2p*, | ||
1248 | r3p*) erratum. A speculative memory access may cause a page table walk | ||
1249 | which starts prior to an ASID switch but completes afterwards. This | ||
1250 | can populate the micro-TLB with a stale entry which may be hit with | ||
1251 | the new ASID. This workaround places two dsb instructions in the mm | ||
1252 | switching code so that no page table walks can cross the ASID switch. | ||
1253 | |||
1254 | config ARM_ERRATA_754327 | ||
1255 | bool "ARM errata: no automatic Store Buffer drain" | ||
1256 | depends on CPU_V7 && SMP | ||
1257 | help | ||
1258 | This option enables the workaround for the 754327 Cortex-A9 (prior to | ||
1259 | r2p0) erratum. The Store Buffer does not have any automatic draining | ||
1260 | mechanism and therefore a livelock may occur if an external agent | ||
1261 | continuously polls a memory location waiting to observe an update. | ||
1262 | This workaround defines cpu_relax() as smp_mb(), preventing correctly | ||
1263 | written polling loops from denying visibility of updates to memory. | ||
1264 | |||
1205 | endmenu | 1265 | endmenu |
1206 | 1266 | ||
1207 | source "arch/arm/common/Kconfig" | 1267 | source "arch/arm/common/Kconfig" |
@@ -1275,6 +1335,7 @@ source "kernel/time/Kconfig" | |||
1275 | config SMP | 1335 | config SMP |
1276 | bool "Symmetric Multi-Processing (EXPERIMENTAL)" | 1336 | bool "Symmetric Multi-Processing (EXPERIMENTAL)" |
1277 | depends on EXPERIMENTAL | 1337 | depends on EXPERIMENTAL |
1338 | depends on CPU_V6K || CPU_V7 | ||
1278 | depends on GENERIC_CLOCKEVENTS | 1339 | depends on GENERIC_CLOCKEVENTS |
1279 | depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ | 1340 | depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ |
1280 | MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ | 1341 | MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ |
@@ -1386,7 +1447,7 @@ config HZ | |||
1386 | 1447 | ||
1387 | config THUMB2_KERNEL | 1448 | config THUMB2_KERNEL |
1388 | bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" | 1449 | bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)" |
1389 | depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL | 1450 | depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL |
1390 | select AEABI | 1451 | select AEABI |
1391 | select ARM_ASM_UNIFIED | 1452 | select ARM_ASM_UNIFIED |
1392 | help | 1453 | help |
@@ -1396,6 +1457,37 @@ config THUMB2_KERNEL | |||
1396 | 1457 | ||
1397 | If unsure, say N. | 1458 | If unsure, say N. |
1398 | 1459 | ||
1460 | config THUMB2_AVOID_R_ARM_THM_JUMP11 | ||
1461 | bool "Work around buggy Thumb-2 short branch relocations in gas" | ||
1462 | depends on THUMB2_KERNEL && MODULES | ||
1463 | default y | ||
1464 | help | ||
1465 | Various binutils versions can resolve Thumb-2 branches to | ||
1466 | locally-defined, preemptible global symbols as short-range "b.n" | ||
1467 | branch instructions. | ||
1468 | |||
1469 | This is a problem, because there's no guarantee the final | ||
1470 | destination of the symbol, or any candidate locations for a | ||
1471 | trampoline, are within range of the branch. For this reason, the | ||
1472 | kernel does not support fixing up the R_ARM_THM_JUMP11 (102) | ||
1473 | relocation in modules at all, and it makes little sense to add | ||
1474 | support. | ||
1475 | |||
1476 | The symptom is that the kernel fails with an "unsupported | ||
1477 | relocation" error when loading some modules. | ||
1478 | |||
1479 | Until fixed tools are available, passing | ||
1480 | -fno-optimize-sibling-calls to gcc should prevent gcc generating | ||
1481 | code which hits this problem, at the cost of a bit of extra runtime | ||
1482 | stack usage in some cases. | ||
1483 | |||
1484 | The problem is described in more detail at: | ||
1485 | https://bugs.launchpad.net/binutils-linaro/+bug/725126 | ||
1486 | |||
1487 | Only Thumb-2 kernels are affected. | ||
1488 | |||
1489 | Unless you are sure your tools don't have this problem, say Y. | ||
1490 | |||
1399 | config ARM_ASM_UNIFIED | 1491 | config ARM_ASM_UNIFIED |
1400 | bool | 1492 | bool |
1401 | 1493 | ||
@@ -1644,6 +1736,18 @@ config ZBOOT_ROM | |||
1644 | Say Y here if you intend to execute your compressed kernel image | 1736 | Say Y here if you intend to execute your compressed kernel image |
1645 | (zImage) directly from ROM or flash. If unsure, say N. | 1737 | (zImage) directly from ROM or flash. If unsure, say N. |
1646 | 1738 | ||
1739 | config ZBOOT_ROM_MMCIF | ||
1740 | bool "Include MMCIF loader in zImage (EXPERIMENTAL)" | ||
1741 | depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL | ||
1742 | help | ||
1743 | Say Y here to include experimental MMCIF loading code in the | ||
1744 | ROM-able zImage. With this enabled it is possible to write the | ||
1745 | the ROM-able zImage kernel image to an MMC card and boot the | ||
1746 | kernel straight from the reset vector. At reset the processor | ||
1747 | Mask ROM will load the first part of the the ROM-able zImage | ||
1748 | which in turn loads the rest the kernel image to RAM using the | ||
1749 | MMCIF hardware block. | ||
1750 | |||
1647 | config CMDLINE | 1751 | config CMDLINE |
1648 | string "Default kernel command string" | 1752 | string "Default kernel command string" |
1649 | default "" | 1753 | default "" |
@@ -1877,7 +1981,7 @@ config FPE_FASTFPE | |||
1877 | 1981 | ||
1878 | config VFP | 1982 | config VFP |
1879 | bool "VFP-format floating point maths" | 1983 | bool "VFP-format floating point maths" |
1880 | depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON | 1984 | depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON |
1881 | help | 1985 | help |
1882 | Say Y to include VFP support code in the kernel. This is needed | 1986 | Say Y to include VFP support code in the kernel. This is needed |
1883 | if your hardware includes a VFP unit. | 1987 | if your hardware includes a VFP unit. |