diff options
author | Alexey Brodkin <abrodkin@synopsys.com> | 2013-06-26 06:02:18 -0400 |
---|---|---|
committer | Vineet Gupta <vgupta@synopsys.com> | 2013-06-28 05:37:20 -0400 |
commit | d0e63ed9411fb9fe95dac1690deb01f9ccb1701d (patch) | |
tree | 5540ed6824ffe5e075b21426548a6d1d2861a58b /arch/arc/plat-arcfpga | |
parent | 7d132055814ef17a6c7b69f342244c410a5e000f (diff) |
ARC: [plat-arcfpga] Enable arc_emac for ARCAngle4 Board
* Add arc_emac to DeviceTree DT description
"Documentation/devicetree/bindings/net/arc_emac.txt".
* Update defconfig correspondingly
[vgupta: tweaked changelog]
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/plat-arcfpga')
-rw-r--r-- | arch/arc/plat-arcfpga/include/plat/irq.h | 2 | ||||
-rw-r--r-- | arch/arc/plat-arcfpga/include/plat/memmap.h | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/arch/arc/plat-arcfpga/include/plat/irq.h b/arch/arc/plat-arcfpga/include/plat/irq.h index 41e335670f60..6adbc53c3a5b 100644 --- a/arch/arc/plat-arcfpga/include/plat/irq.h +++ b/arch/arc/plat-arcfpga/include/plat/irq.h | |||
@@ -16,8 +16,6 @@ | |||
16 | #define UART1_IRQ 10 | 16 | #define UART1_IRQ 10 |
17 | #define UART2_IRQ 11 | 17 | #define UART2_IRQ 11 |
18 | 18 | ||
19 | #define VMAC_IRQ 6 | ||
20 | |||
21 | #define IDE_IRQ 13 | 19 | #define IDE_IRQ 13 |
22 | #define PCI_IRQ 14 | 20 | #define PCI_IRQ 14 |
23 | #define PS2_IRQ 15 | 21 | #define PS2_IRQ 15 |
diff --git a/arch/arc/plat-arcfpga/include/plat/memmap.h b/arch/arc/plat-arcfpga/include/plat/memmap.h index 1663f3388085..5c78e6135a1f 100644 --- a/arch/arc/plat-arcfpga/include/plat/memmap.h +++ b/arch/arc/plat-arcfpga/include/plat/memmap.h | |||
@@ -15,8 +15,6 @@ | |||
15 | #define UART0_BASE 0xC0FC1000 | 15 | #define UART0_BASE 0xC0FC1000 |
16 | #define UART1_BASE 0xC0FC1100 | 16 | #define UART1_BASE 0xC0FC1100 |
17 | 17 | ||
18 | #define VMAC_REG_BASEADDR 0xC0FC2000 | ||
19 | |||
20 | #define IDE_CONTROLLER_BASE 0xC0FC9000 | 18 | #define IDE_CONTROLLER_BASE 0xC0FC9000 |
21 | 19 | ||
22 | #define AHB_PCI_HOST_BRG_BASE 0xC0FD0000 | 20 | #define AHB_PCI_HOST_BRG_BASE 0xC0FD0000 |