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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/alpha/kernel/sys_titan.c
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/alpha/kernel/sys_titan.c')
-rw-r--r--arch/alpha/kernel/sys_titan.c54
1 files changed, 21 insertions, 33 deletions
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index 9008d0f20c53..6994407e242a 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -65,10 +65,11 @@ titan_update_irq_hw(unsigned long mask)
65 register int bcpu = boot_cpuid; 65 register int bcpu = boot_cpuid;
66 66
67#ifdef CONFIG_SMP 67#ifdef CONFIG_SMP
68 cpumask_t cpm = cpu_present_map; 68 cpumask_t cpm;
69 volatile unsigned long *dim0, *dim1, *dim2, *dim3; 69 volatile unsigned long *dim0, *dim1, *dim2, *dim3;
70 unsigned long mask0, mask1, mask2, mask3, dummy; 70 unsigned long mask0, mask1, mask2, mask3, dummy;
71 71
72 cpumask_copy(&cpm, cpu_present_mask);
72 mask &= ~isa_enable; 73 mask &= ~isa_enable;
73 mask0 = mask & titan_cpu_irq_affinity[0]; 74 mask0 = mask & titan_cpu_irq_affinity[0];
74 mask1 = mask & titan_cpu_irq_affinity[1]; 75 mask1 = mask & titan_cpu_irq_affinity[1];
@@ -84,10 +85,10 @@ titan_update_irq_hw(unsigned long mask)
84 dim1 = &cchip->dim1.csr; 85 dim1 = &cchip->dim1.csr;
85 dim2 = &cchip->dim2.csr; 86 dim2 = &cchip->dim2.csr;
86 dim3 = &cchip->dim3.csr; 87 dim3 = &cchip->dim3.csr;
87 if (!cpu_isset(0, cpm)) dim0 = &dummy; 88 if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy;
88 if (!cpu_isset(1, cpm)) dim1 = &dummy; 89 if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy;
89 if (!cpu_isset(2, cpm)) dim2 = &dummy; 90 if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy;
90 if (!cpu_isset(3, cpm)) dim3 = &dummy; 91 if (!cpumask_test_cpu(3, &cpm)) dim3 = &dummy;
91 92
92 *dim0 = mask0; 93 *dim0 = mask0;
93 *dim1 = mask1; 94 *dim1 = mask1;
@@ -112,8 +113,9 @@ titan_update_irq_hw(unsigned long mask)
112} 113}
113 114
114static inline void 115static inline void
115titan_enable_irq(unsigned int irq) 116titan_enable_irq(struct irq_data *d)
116{ 117{
118 unsigned int irq = d->irq;
117 spin_lock(&titan_irq_lock); 119 spin_lock(&titan_irq_lock);
118 titan_cached_irq_mask |= 1UL << (irq - 16); 120 titan_cached_irq_mask |= 1UL << (irq - 16);
119 titan_update_irq_hw(titan_cached_irq_mask); 121 titan_update_irq_hw(titan_cached_irq_mask);
@@ -121,35 +123,22 @@ titan_enable_irq(unsigned int irq)
121} 123}
122 124
123static inline void 125static inline void
124titan_disable_irq(unsigned int irq) 126titan_disable_irq(struct irq_data *d)
125{ 127{
128 unsigned int irq = d->irq;
126 spin_lock(&titan_irq_lock); 129 spin_lock(&titan_irq_lock);
127 titan_cached_irq_mask &= ~(1UL << (irq - 16)); 130 titan_cached_irq_mask &= ~(1UL << (irq - 16));
128 titan_update_irq_hw(titan_cached_irq_mask); 131 titan_update_irq_hw(titan_cached_irq_mask);
129 spin_unlock(&titan_irq_lock); 132 spin_unlock(&titan_irq_lock);
130} 133}
131 134
132static unsigned int
133titan_startup_irq(unsigned int irq)
134{
135 titan_enable_irq(irq);
136 return 0; /* never anything pending */
137}
138
139static void
140titan_end_irq(unsigned int irq)
141{
142 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
143 titan_enable_irq(irq);
144}
145
146static void 135static void
147titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) 136titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
148{ 137{
149 int cpu; 138 int cpu;
150 139
151 for (cpu = 0; cpu < 4; cpu++) { 140 for (cpu = 0; cpu < 4; cpu++) {
152 if (cpu_isset(cpu, affinity)) 141 if (cpumask_test_cpu(cpu, &affinity))
153 titan_cpu_irq_affinity[cpu] |= 1UL << irq; 142 titan_cpu_irq_affinity[cpu] |= 1UL << irq;
154 else 143 else
155 titan_cpu_irq_affinity[cpu] &= ~(1UL << irq); 144 titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
@@ -158,8 +147,10 @@ titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
158} 147}
159 148
160static int 149static int
161titan_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) 150titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
151 bool force)
162{ 152{
153 unsigned int irq = d->irq;
163 spin_lock(&titan_irq_lock); 154 spin_lock(&titan_irq_lock);
164 titan_cpu_set_irq_affinity(irq - 16, *affinity); 155 titan_cpu_set_irq_affinity(irq - 16, *affinity);
165 titan_update_irq_hw(titan_cached_irq_mask); 156 titan_update_irq_hw(titan_cached_irq_mask);
@@ -189,20 +180,17 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
189{ 180{
190 long i; 181 long i;
191 for (i = imin; i <= imax; ++i) { 182 for (i = imin; i <= imax; ++i) {
192 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 183 irq_set_chip_and_handler(i, ops, handle_level_irq);
193 irq_desc[i].chip = ops; 184 irq_set_status_flags(i, IRQ_LEVEL);
194 } 185 }
195} 186}
196 187
197static struct irq_chip titan_irq_type = { 188static struct irq_chip titan_irq_type = {
198 .name = "TITAN", 189 .name = "TITAN",
199 .startup = titan_startup_irq, 190 .irq_unmask = titan_enable_irq,
200 .shutdown = titan_disable_irq, 191 .irq_mask = titan_disable_irq,
201 .enable = titan_enable_irq, 192 .irq_mask_ack = titan_disable_irq,
202 .disable = titan_disable_irq, 193 .irq_set_affinity = titan_set_irq_affinity,
203 .ack = titan_disable_irq,
204 .end = titan_end_irq,
205 .set_affinity = titan_set_irq_affinity,
206}; 194};
207 195
208static irqreturn_t 196static irqreturn_t