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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/alpha/kernel/sys_cabriolet.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/alpha/kernel/sys_cabriolet.c')
-rw-r--r--arch/alpha/kernel/sys_cabriolet.c448
1 files changed, 448 insertions, 0 deletions
diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c
new file mode 100644
index 000000000000..8e3374d34c95
--- /dev/null
+++ b/arch/alpha/kernel/sys_cabriolet.c
@@ -0,0 +1,448 @@
1/*
2 * linux/arch/alpha/kernel/sys_cabriolet.c
3 *
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996 Jay A Estabrook
6 * Copyright (C) 1998, 1999, 2000 Richard Henderson
7 *
8 * Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164,
9 * PC164 and LX164.
10 */
11
12#include <linux/config.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/bitops.h>
20
21#include <asm/ptrace.h>
22#include <asm/system.h>
23#include <asm/dma.h>
24#include <asm/irq.h>
25#include <asm/mmu_context.h>
26#include <asm/io.h>
27#include <asm/pgtable.h>
28#include <asm/core_apecs.h>
29#include <asm/core_cia.h>
30#include <asm/core_lca.h>
31#include <asm/tlbflush.h>
32
33#include "proto.h"
34#include "irq_impl.h"
35#include "pci_impl.h"
36#include "machvec_impl.h"
37
38
39/* Note mask bit is true for DISABLED irqs. */
40static unsigned long cached_irq_mask = ~0UL;
41
42static inline void
43cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
44{
45 int ofs = (irq - 16) / 8;
46 outb(mask >> (16 + ofs * 8), 0x804 + ofs);
47}
48
49static inline void
50cabriolet_enable_irq(unsigned int irq)
51{
52 cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
53}
54
55static void
56cabriolet_disable_irq(unsigned int irq)
57{
58 cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
59}
60
61static unsigned int
62cabriolet_startup_irq(unsigned int irq)
63{
64 cabriolet_enable_irq(irq);
65 return 0; /* never anything pending */
66}
67
68static void
69cabriolet_end_irq(unsigned int irq)
70{
71 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
72 cabriolet_enable_irq(irq);
73}
74
75static struct hw_interrupt_type cabriolet_irq_type = {
76 .typename = "CABRIOLET",
77 .startup = cabriolet_startup_irq,
78 .shutdown = cabriolet_disable_irq,
79 .enable = cabriolet_enable_irq,
80 .disable = cabriolet_disable_irq,
81 .ack = cabriolet_disable_irq,
82 .end = cabriolet_end_irq,
83};
84
85static void
86cabriolet_device_interrupt(unsigned long v, struct pt_regs *r)
87{
88 unsigned long pld;
89 unsigned int i;
90
91 /* Read the interrupt summary registers */
92 pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16);
93
94 /*
95 * Now for every possible bit set, work through them and call
96 * the appropriate interrupt handler.
97 */
98 while (pld) {
99 i = ffz(~pld);
100 pld &= pld - 1; /* clear least bit set */
101 if (i == 4) {
102 isa_device_interrupt(v, r);
103 } else {
104 handle_irq(16 + i, r);
105 }
106 }
107}
108
109static void __init
110common_init_irq(void (*srm_dev_int)(unsigned long v, struct pt_regs *r))
111{
112 init_i8259a_irqs();
113
114 if (alpha_using_srm) {
115 alpha_mv.device_interrupt = srm_dev_int;
116 init_srm_irqs(35, 0);
117 }
118 else {
119 long i;
120
121 outb(0xff, 0x804);
122 outb(0xff, 0x805);
123 outb(0xff, 0x806);
124
125 for (i = 16; i < 35; ++i) {
126 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
127 irq_desc[i].handler = &cabriolet_irq_type;
128 }
129 }
130
131 common_init_isa_dma();
132 setup_irq(16+4, &isa_cascade_irqaction);
133}
134
135#ifndef CONFIG_ALPHA_PC164
136static void __init
137cabriolet_init_irq(void)
138{
139 common_init_irq(srm_device_interrupt);
140}
141#endif
142
143#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
144/* In theory, the PC164 has the same interrupt hardware as the other
145 Cabriolet based systems. However, something got screwed up late
146 in the development cycle which broke the interrupt masking hardware.
147 Repeat, it is not possible to mask and ack interrupts. At all.
148
149 In an attempt to work around this, while processing interrupts,
150 we do not allow the IPL to drop below what it is currently. This
151 prevents the possibility of recursion.
152
153 ??? Another option might be to force all PCI devices to use edge
154 triggered rather than level triggered interrupts. That might be
155 too invasive though. */
156
157static void
158pc164_srm_device_interrupt(unsigned long v, struct pt_regs *r)
159{
160 __min_ipl = getipl();
161 srm_device_interrupt(v, r);
162 __min_ipl = 0;
163}
164
165static void
166pc164_device_interrupt(unsigned long v, struct pt_regs *r)
167{
168 __min_ipl = getipl();
169 cabriolet_device_interrupt(v, r);
170 __min_ipl = 0;
171}
172
173static void __init
174pc164_init_irq(void)
175{
176 common_init_irq(pc164_srm_device_interrupt);
177}
178#endif
179
180/*
181 * The EB66+ is very similar to the EB66 except that it does not have
182 * the on-board NCR and Tulip chips. In the code below, I have used
183 * slot number to refer to the id select line and *not* the slot
184 * number used in the EB66+ documentation. However, in the table,
185 * I've given the slot number, the id select line and the Jxx number
186 * that's printed on the board. The interrupt pins from the PCI slots
187 * are wired into 3 interrupt summary registers at 0x804, 0x805 and
188 * 0x806 ISA.
189 *
190 * In the table, -1 means don't assign an IRQ number. This is usually
191 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
192 */
193
194static inline int __init
195eb66p_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
196{
197 static char irq_tab[5][5] __initdata = {
198 /*INT INTA INTB INTC INTD */
199 {16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */
200 {16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */
201 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
202 {16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */
203 {16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */
204 };
205 const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5;
206 return COMMON_TABLE_LOOKUP;
207}
208
209
210/*
211 * The AlphaPC64 is very similar to the EB66+ except that its slots
212 * are numbered differently. In the code below, I have used slot
213 * number to refer to the id select line and *not* the slot number
214 * used in the AlphaPC64 documentation. However, in the table, I've
215 * given the slot number, the id select line and the Jxx number that's
216 * printed on the board. The interrupt pins from the PCI slots are
217 * wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806
218 * ISA.
219 *
220 * In the table, -1 means don't assign an IRQ number. This is usually
221 * because it is the Saturn IO (SIO) PCI/ISA Bridge Chip.
222 */
223
224static inline int __init
225cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
226{
227 static char irq_tab[5][5] __initdata = {
228 /*INT INTA INTB INTC INTD */
229 { 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */
230 { 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */
231 { 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */
232 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
233 { 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */
234 };
235 const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5;
236 return COMMON_TABLE_LOOKUP;
237}
238
239static inline void __init
240cabriolet_init_pci(void)
241{
242 common_init_pci();
243 ns87312_enable_ide(0x398);
244}
245
246static inline void __init
247cia_cab_init_pci(void)
248{
249 cia_init_pci();
250 ns87312_enable_ide(0x398);
251}
252
253/*
254 * The PC164 and LX164 have 19 PCI interrupts, four from each of the four
255 * PCI slots, the SIO, PCI/IDE, and USB.
256 *
257 * Each of the interrupts can be individually masked. This is
258 * accomplished by setting the appropriate bit in the mask register.
259 * A bit is set by writing a "1" to the desired position in the mask
260 * register and cleared by writing a "0". There are 3 mask registers
261 * located at ISA address 804h, 805h and 806h.
262 *
263 * An I/O read at ISA address 804h, 805h, 806h will return the
264 * state of the 11 PCI interrupts and not the state of the MASKED
265 * interrupts.
266 *
267 * Note: A write to I/O 804h, 805h, and 806h the mask register will be
268 * updated.
269 *
270 *
271 * ISA DATA<7:0>
272 * ISA +--------------------------------------------------------------+
273 * ADDRESS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
274 * +==============================================================+
275 * 0x804 | INTB0 | USB | IDE | SIO | INTA3 |INTA2 | INTA1 | INTA0 |
276 * +--------------------------------------------------------------+
277 * 0x805 | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 |
278 * +--------------------------------------------------------------+
279 * 0x806 | Rsrv | Rsrv | Rsrv | Rsrv | Rsrv |INTD3 | INTD2 | INTD1 |
280 * +--------------------------------------------------------------+
281 * * Rsrv = reserved bits
282 * Note: The mask register is write-only.
283 *
284 * IdSel
285 * 5 32 bit PCI option slot 2
286 * 6 64 bit PCI option slot 0
287 * 7 64 bit PCI option slot 1
288 * 8 Saturn I/O
289 * 9 32 bit PCI option slot 3
290 * 10 USB
291 * 11 IDE
292 *
293 */
294
295static inline int __init
296alphapc164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
297{
298 static char irq_tab[7][5] __initdata = {
299 /*INT INTA INTB INTC INTD */
300 { 16+2, 16+2, 16+9, 16+13, 16+17}, /* IdSel 5, slot 2, J20 */
301 { 16+0, 16+0, 16+7, 16+11, 16+15}, /* IdSel 6, slot 0, J29 */
302 { 16+1, 16+1, 16+8, 16+12, 16+16}, /* IdSel 7, slot 1, J26 */
303 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */
304 { 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel 9, slot 3, J19 */
305 { 16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 10, USB */
306 { 16+5, 16+5, 16+5, 16+5, 16+5} /* IdSel 11, IDE */
307 };
308 const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5;
309 return COMMON_TABLE_LOOKUP;
310}
311
312static inline void __init
313alphapc164_init_pci(void)
314{
315 cia_init_pci();
316 SMC93x_Init();
317}
318
319
320/*
321 * The System Vector
322 */
323
324#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET)
325struct alpha_machine_vector cabriolet_mv __initmv = {
326 .vector_name = "Cabriolet",
327 DO_EV4_MMU,
328 DO_DEFAULT_RTC,
329 DO_APECS_IO,
330 .machine_check = apecs_machine_check,
331 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
332 .min_io_address = DEFAULT_IO_BASE,
333 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
334
335 .nr_irqs = 35,
336 .device_interrupt = cabriolet_device_interrupt,
337
338 .init_arch = apecs_init_arch,
339 .init_irq = cabriolet_init_irq,
340 .init_rtc = common_init_rtc,
341 .init_pci = cabriolet_init_pci,
342 .pci_map_irq = cabriolet_map_irq,
343 .pci_swizzle = common_swizzle,
344};
345#ifndef CONFIG_ALPHA_EB64P
346ALIAS_MV(cabriolet)
347#endif
348#endif
349
350#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164)
351struct alpha_machine_vector eb164_mv __initmv = {
352 .vector_name = "EB164",
353 DO_EV5_MMU,
354 DO_DEFAULT_RTC,
355 DO_CIA_IO,
356 .machine_check = cia_machine_check,
357 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
358 .min_io_address = DEFAULT_IO_BASE,
359 .min_mem_address = CIA_DEFAULT_MEM_BASE,
360
361 .nr_irqs = 35,
362 .device_interrupt = cabriolet_device_interrupt,
363
364 .init_arch = cia_init_arch,
365 .init_irq = cabriolet_init_irq,
366 .init_rtc = common_init_rtc,
367 .init_pci = cia_cab_init_pci,
368 .kill_arch = cia_kill_arch,
369 .pci_map_irq = cabriolet_map_irq,
370 .pci_swizzle = common_swizzle,
371};
372ALIAS_MV(eb164)
373#endif
374
375#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66P)
376struct alpha_machine_vector eb66p_mv __initmv = {
377 .vector_name = "EB66+",
378 DO_EV4_MMU,
379 DO_DEFAULT_RTC,
380 DO_LCA_IO,
381 .machine_check = lca_machine_check,
382 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
383 .min_io_address = DEFAULT_IO_BASE,
384 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
385
386 .nr_irqs = 35,
387 .device_interrupt = cabriolet_device_interrupt,
388
389 .init_arch = lca_init_arch,
390 .init_irq = cabriolet_init_irq,
391 .init_rtc = common_init_rtc,
392 .init_pci = cabriolet_init_pci,
393 .pci_map_irq = eb66p_map_irq,
394 .pci_swizzle = common_swizzle,
395};
396ALIAS_MV(eb66p)
397#endif
398
399#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164)
400struct alpha_machine_vector lx164_mv __initmv = {
401 .vector_name = "LX164",
402 DO_EV5_MMU,
403 DO_DEFAULT_RTC,
404 DO_PYXIS_IO,
405 .machine_check = cia_machine_check,
406 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
407 .min_io_address = DEFAULT_IO_BASE,
408 .min_mem_address = DEFAULT_MEM_BASE,
409 .pci_dac_offset = PYXIS_DAC_OFFSET,
410
411 .nr_irqs = 35,
412 .device_interrupt = cabriolet_device_interrupt,
413
414 .init_arch = pyxis_init_arch,
415 .init_irq = cabriolet_init_irq,
416 .init_rtc = common_init_rtc,
417 .init_pci = alphapc164_init_pci,
418 .kill_arch = cia_kill_arch,
419 .pci_map_irq = alphapc164_map_irq,
420 .pci_swizzle = common_swizzle,
421};
422ALIAS_MV(lx164)
423#endif
424
425#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164)
426struct alpha_machine_vector pc164_mv __initmv = {
427 .vector_name = "PC164",
428 DO_EV5_MMU,
429 DO_DEFAULT_RTC,
430 DO_CIA_IO,
431 .machine_check = cia_machine_check,
432 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
433 .min_io_address = DEFAULT_IO_BASE,
434 .min_mem_address = CIA_DEFAULT_MEM_BASE,
435
436 .nr_irqs = 35,
437 .device_interrupt = pc164_device_interrupt,
438
439 .init_arch = cia_init_arch,
440 .init_irq = pc164_init_irq,
441 .init_rtc = common_init_rtc,
442 .init_pci = alphapc164_init_pci,
443 .kill_arch = cia_kill_arch,
444 .pci_map_irq = alphapc164_map_irq,
445 .pci_swizzle = common_swizzle,
446};
447ALIAS_MV(pc164)
448#endif
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