aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation
diff options
context:
space:
mode:
authorAntoine Tenart <antoine.tenart@free-electrons.com>2014-05-05 01:27:28 -0400
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-05-19 17:02:30 -0400
commite9673a752897c2127e5aefd4663016bca817a0fe (patch)
tree6e90156fb323183c8324cc99f81436dd9be4dcf1 /Documentation
parent414dcf8f30fb966490a08c6f2bb581a745395309 (diff)
dt-binding: ARM: add pinctrl binding docs for Marvell Berlin2 SoCs
Add pin control binding documentation to the SoC binding documentaion as pinctrl is part of chip/system control registers. The documentation also explains how to configure this group based controller. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/marvell,berlin.txt54
1 files changed, 54 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
index 744a7ea569d4..94013a9a8769 100644
--- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -41,6 +41,18 @@ Required properties:
41 BG2/BG2CD: chip control register set 41 BG2/BG2CD: chip control register set
42 BG2Q: chip control register set and cpu pll registers 42 BG2Q: chip control register set and cpu pll registers
43 43
44* Marvell Berlin2 system control binding
45
46Marvell Berlin SoCs have a system control register set providing several
47individual registers dealing with pinmux, padmux, and reset.
48
49Required properties:
50- compatible: should be one of
51 "marvell,berlin2-system-ctrl" for BG2
52 "marvell,berlin2cd-system-ctrl" for BG2CD
53 "marvell,berlin2q-system-ctrl" for BG2Q
54- reg: address and length of the system control register set
55
44* Clock provider binding 56* Clock provider binding
45 57
46As clock related registers are spread among the chip control registers, the 58As clock related registers are spread among the chip control registers, the
@@ -61,6 +73,23 @@ Clocks provided by core clocks shall be referenced by a clock specifier
61indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h 73indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
62for the corresponding index mapping. 74for the corresponding index mapping.
63 75
76* Pin controller binding
77
78Pin control registers are part of both register sets, chip control and system
79control. The pins controlled are organized in groups, so no actual pin
80information is needed.
81
82A pin-controller node should contain subnodes representing the pin group
83configurations, one per function. Each subnode has the group name and the muxing
84function used.
85
86Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
87a 'function' in the pin-controller subsystem.
88
89Required subnode-properties:
90- groups: a list of strings describing the group names.
91- function: a string describing the function used to mux the groups.
92
64Example: 93Example:
65 94
66chip: chip-control@ea0000 { 95chip: chip-control@ea0000 {
@@ -69,4 +98,29 @@ chip: chip-control@ea0000 {
69 reg = <0xea0000 0x400>; 98 reg = <0xea0000 0x400>;
70 clocks = <&refclk>, <&externaldev 0>; 99 clocks = <&refclk>, <&externaldev 0>;
71 clock-names = "refclk", "video_ext0"; 100 clock-names = "refclk", "video_ext0";
101
102 spi1_pmux: spi1-pmux {
103 groups = "G0";
104 function = "spi1";
105 };
106};
107
108sysctrl: system-controller@d000 {
109 compatible = "marvell,berlin2-system-ctrl";
110 reg = <0xd000 0x100>;
111
112 uart0_pmux: uart0-pmux {
113 groups = "GSM4";
114 function = "uart0";
115 };
116
117 uart1_pmux: uart1-pmux {
118 groups = "GSM5";
119 function = "uart1";
120 };
121
122 uart2_pmux: uart2-pmux {
123 groups = "GSM3";
124 function = "uart2";
125 };
72}; 126};