diff options
author | Kevin Cernekee <cernekee@gmail.com> | 2014-12-25 12:49:15 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-01 11:21:41 -0400 |
commit | e5a6fcc05831b269be35ec266639d901b43cba78 (patch) | |
tree | eda88fe484d7f780929eda786085d19d0f9eaec2 /Documentation | |
parent | 4b049a6b275db68c2c028937b89abd732dcdf536 (diff) |
MIPS: BMIPS: Delete the irqchip driver from irq.c
BCM3384/BCM63xx can use the common drivers/irqchip/irq-bcm7120-l2.c for
this purpose; BCM7xxx will use drivers/irqchip/irq-bcm7038-l1.c. We no
longer need this code under arch/mips.
[ralf@linux-mips.org: Fix conflicts.]
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8853/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt b/Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt deleted file mode 100644 index d4e0141d3620..000000000000 --- a/Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | * Interrupt Controller | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "brcm,bcm3384-intc" | ||
5 | |||
6 | Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs. | ||
7 | |||
8 | - reg: Address/length pairs for each mask/status register set. Length must | ||
9 | be 8. If multiple register sets are specified, the first set will | ||
10 | handle IRQ offsets 0..31, the second set 32..63, and so on. | ||
11 | |||
12 | - interrupt-controller: This is an interrupt controller. | ||
13 | |||
14 | - #interrupt-cells: Must be <1>. Just a simple IRQ offset; no level/edge | ||
15 | or polarity configuration is possible with this controller. | ||
16 | |||
17 | - interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or | ||
18 | from another INTC. | ||
19 | |||
20 | - interrupts: The IRQ on the parent controller. | ||
21 | |||
22 | Example: | ||
23 | periph_intc: periph_intc@14e00038 { | ||
24 | compatible = "brcm,bcm3384-intc"; | ||
25 | |||
26 | /* | ||
27 | * IRQs 0..31: mask reg 0x14e00038, status reg 0x14e0003c | ||
28 | * IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344 | ||
29 | */ | ||
30 | reg = <0x14e00038 0x8 0x14e00340 0x8>; | ||
31 | |||
32 | interrupt-controller; | ||
33 | #interrupt-cells = <1>; | ||
34 | |||
35 | interrupt-parent = <&cpu_intc>; | ||
36 | interrupts = <4>; | ||
37 | }; | ||