aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation
diff options
context:
space:
mode:
authorStephen Street <stephen@streetfiresound.com>2006-12-10 05:18:54 -0500
committerLinus Torvalds <torvalds@woody.osdl.org>2006-12-10 12:55:40 -0500
commit8d94cc50aa4f1448a6483975097805eb8d6be0e0 (patch)
tree87b93503ca5212b1a1af9d66928163abfcb25a31 /Documentation
parent6451956a24963d3eb1655fd039762ae42ac48da7 (diff)
[PATCH] spi: stabilize PIO mode transfers on PXA2xx systems
Stabilize PIO mode transfers against a range of word sizes and FIFO thresholds and fixes word size setup/override issues. 1) 16 and 32 bit DMA/PIO transfers broken due to timing differences. 2) Potential for bad transfer counts due to transfer size assumptions. 3) Setup function broken is multiple ways. 4) Per transfer bit_per_word changes break DMA setup in pump_tranfers. 5) False positive timeout are not errors. 6) Changes in pxa2xx_spi_chip not effective in calls to setup. 7) Timeout scaling wrong for PXA255 NSSP. 8) Driver leaks memory while busy during unloading. Known issues: SPI_CS_HIGH and SPI_LSB_FIRST settings in struct spi_device are not handled. Testing: This patch has been test against the "random length, random bits/word, random data (verified on loopback) and stepped baud rate by octaves (3.6MHz to 115kHz)" test. It is robust in PIO mode, using any combination of tx and rx thresholds, and also in DMA mode (which internally computes the thresholds). Much thanks to Ned Forrester for exhaustive reviews, fixes and testing. The driver is substantially better for his efforts. Signed-off-by: Stephen Street <stephen@streetfiresound.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/spi/pxa2xx16
1 files changed, 8 insertions, 8 deletions
diff --git a/Documentation/spi/pxa2xx b/Documentation/spi/pxa2xx
index a1e0ee20f595..f9717fe9bd85 100644
--- a/Documentation/spi/pxa2xx
+++ b/Documentation/spi/pxa2xx
@@ -102,7 +102,7 @@ struct pxa2xx_spi_chip {
102 u8 tx_threshold; 102 u8 tx_threshold;
103 u8 rx_threshold; 103 u8 rx_threshold;
104 u8 dma_burst_size; 104 u8 dma_burst_size;
105 u32 timeout_microsecs; 105 u32 timeout;
106 u8 enable_loopback; 106 u8 enable_loopback;
107 void (*cs_control)(u32 command); 107 void (*cs_control)(u32 command);
108}; 108};
@@ -121,7 +121,7 @@ the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
121to determine the correct value. An SSP configured for byte-wide transfers would 121to determine the correct value. An SSP configured for byte-wide transfers would
122use a value of 8. 122use a value of 8.
123 123
124The "pxa2xx_spi_chip.timeout_microsecs" fields is used to efficiently handle 124The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
125trailing bytes in the SSP receiver fifo. The correct value for this field is 125trailing bytes in the SSP receiver fifo. The correct value for this field is
126dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific 126dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
127slave device. Please note that the PXA2xx SSP 1 does not support trailing byte 127slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
@@ -162,18 +162,18 @@ static void cs8405a_cs_control(u32 command)
162} 162}
163 163
164static struct pxa2xx_spi_chip cs8415a_chip_info = { 164static struct pxa2xx_spi_chip cs8415a_chip_info = {
165 .tx_threshold = 12, /* SSP hardward FIFO threshold */ 165 .tx_threshold = 8, /* SSP hardward FIFO threshold */
166 .rx_threshold = 4, /* SSP hardward FIFO threshold */ 166 .rx_threshold = 8, /* SSP hardward FIFO threshold */
167 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ 167 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
168 .timeout_microsecs = 64, /* Wait at least 64usec to handle trailing */ 168 .timeout = 235, /* See Intel documentation */
169 .cs_control = cs8415a_cs_control, /* Use external chip select */ 169 .cs_control = cs8415a_cs_control, /* Use external chip select */
170}; 170};
171 171
172static struct pxa2xx_spi_chip cs8405a_chip_info = { 172static struct pxa2xx_spi_chip cs8405a_chip_info = {
173 .tx_threshold = 12, /* SSP hardward FIFO threshold */ 173 .tx_threshold = 8, /* SSP hardward FIFO threshold */
174 .rx_threshold = 4, /* SSP hardward FIFO threshold */ 174 .rx_threshold = 8, /* SSP hardward FIFO threshold */
175 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */ 175 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
176 .timeout_microsecs = 64, /* Wait at least 64usec to handle trailing */ 176 .timeout = 235, /* See Intel documentation */
177 .cs_control = cs8405a_cs_control, /* Use external chip select */ 177 .cs_control = cs8405a_cs_control, /* Use external chip select */
178}; 178};
179 179