iommu/tegra: gart: Fix register offset correctly

DT passes the exact GART register ranges without any overlapping with
MC register ranges. GART register offset needs to be adjusted by one
passed by DT correctly.

Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
index 2d87b9191fce..099d9362ebc1 100644
--- a/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
+++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
@@ -7,8 +7,8 @@ Required properties:
 
 Example:
 
-        gart: gart@7000f000 {
+        gart {
                 compatible = "nvidia,tegra20-gart";
-                reg = < 0x7000f000 0x00000100    /* controller registers */
-                        0x58000000 0x02000000 >; /* GART aperture */
+                reg = <0x7000f024 0x00000018    /* controller registers */
+                       0x58000000 0x02000000>;  /* GART aperture */
         };