Merge branch 'irq-irqdomain-arm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq domain ARM updates from Thomas Gleixner:
 "This set of changes make use of hierarchical irqdomains to provide:

   - MSI/ITS support for GICv3
   - MSI support for GICv2m
   - Interrupt polarity extender for GICv1

  Marc has come more cleanups for the existing extension hooks of GIC in
  the pipeline, but they are going to be 3.20 material"

* 'irq-irqdomain-arm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits)
  irqchip: gicv3-its: Fix ITT allocation
  irqchip: gicv3-its: Move some alloc/free code to activate/deactivate
  irqchip: gicv3-its: Fix domain free in multi-MSI case
  irqchip: gic: Remove warning by including linux/irqdomain.h
  irqchip: gic-v2m: Add DT bindings for GICv2m
  irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbell
  irqchip: mtk-sysirq: dt-bindings: Add bindings for mediatek sysirq
  irqchip: mtk-sysirq: Add sysirq interrupt polarity support
  irqchip: gic: Support hierarchy irq domain.
  irqchip: GICv3: Binding updates for ITS
  irqchip: GICv3: ITS: enable compilation of the ITS driver
  irqchip: GICv3: ITS: plug ITS init into main GICv3 code
  irqchip: GICv3: ITS: DT probing and initialization
  irqchip: GICv3: ITS: MSI support
  irqchip: GICv3: ITS: device allocation and configuration
  irqchip: GICv3: ITS: tables allocators
  irqchip: GICv3: ITS: LPI allocator
  irqchip: GICv3: ITS: irqchip implementation
  irqchip: GICv3: ITS command queue
  irqchip: GICv3: rework redistributor structure
  ...

3 files changed, 120 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/arm/gic-v3.txt b/Documentation/devicetree/bindings/arm/gic-v3.txt
index 33cd05e6c125..ddfade40ac59 100644
--- a/Documentation/devicetree/bindings/arm/gic-v3.txt
+++ b/Documentation/devicetree/bindings/arm/gic-v3.txt
@@ -49,11 +49,29 @@ Optional
   occupied by the redistributors. Required if more than one such
   region is present.
 
+Sub-nodes:
+
+GICv3 has one or more Interrupt Translation Services (ITS) that are
+used to route Message Signalled Interrupts (MSI) to the CPUs.
+
+These nodes must have the following properties:
+- compatible : Should at least contain  "arm,gic-v3-its".
+- msi-controller : Boolean property. Identifies the node as an MSI controller
+- reg: Specifies the base physical address and size of the ITS
+  registers.
+
+The main GIC node must contain the appropriate #address-cells,
+#size-cells and ranges properties for the reg property of all ITS
+nodes.
+
 Examples:
 
         gic: interrupt-controller@2cf00000 {
                 compatible = "arm,gic-v3";
                 #interrupt-cells = <3>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
                 interrupt-controller;
                 reg = <0x0 0x2f000000 0 0x10000>,       // GICD
                       <0x0 0x2f100000 0 0x200000>,      // GICR
@@ -61,11 +79,20 @@ Examples:
                       <0x0 0x2c010000 0 0x2000>,        // GICH
                       <0x0 0x2c020000 0 0x2000>;        // GICV
                 interrupts = <1 9 4>;
+
+                gic-its@2c200000 {
+                        compatible = "arm,gic-v3-its";
+                        msi-controller;
+                        reg = <0x0 0x2c200000 0 0x200000>;
+                };
         };
 
         gic: interrupt-controller@2c010000 {
                 compatible = "arm,gic-v3";
                 #interrupt-cells = <3>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
                 interrupt-controller;
                 redistributor-stride = <0x0 0x40000>;   // 256kB stride
                 #redistributor-regions = <2>;
@@ -76,4 +103,16 @@ Examples:
                       <0x0 0x2c060000 0 0x2000>,        // GICH
                       <0x0 0x2c080000 0 0x2000>;        // GICV
                 interrupts = <1 9 4>;
+
+                gic-its@2c200000 {
+                        compatible = "arm,gic-v3-its";
+                        msi-controller;
+                        reg = <0x0 0x2c200000 0 0x200000>;
+                };
+
+                gic-its@2c400000 {
+                        compatible = "arm,gic-v3-its";
+                        msi-controller;
+                        reg = <0x0 0x2c400000 0 0x200000>;
+                };
         };
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index b38608af66db..8112d0c3675a 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -97,3 +97,56 @@ Example:
                       <0x2c006000 0x2000>;
                 interrupts = <1 9 0xf04>;
         };
+
+
+* GICv2m extension for MSI/MSI-x support (Optional)
+
+Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
+This is enabled by specifying v2m sub-node(s).
+
+Required properties:
+
+- compatible        : The value here should contain "arm,gic-v2m-frame".
+
+- msi-controller    : Identifies the node as an MSI controller.
+
+- reg               : GICv2m MSI interface register base and size
+
+Optional properties:
+
+- arm,msi-base-spi  : When the MSI_TYPER register contains an incorrect
+                      value, this property should contain the SPI base of
+                      the MSI frame, overriding the HW value.
+
+- arm,msi-num-spis  : When the MSI_TYPER register contains an incorrect
+                      value, this property should contain the number of
+                      SPIs assigned to the frame, overriding the HW value.
+
+Example:
+
+        interrupt-controller@e1101000 {
+                compatible = "arm,gic-400";
+                #interrupt-cells = <3>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                interrupt-controller;
+                interrupts = <1 8 0xf04>;
+                ranges = <0 0 0 0xe1100000 0 0x100000>;
+                reg = <0x0 0xe1110000 0 0x01000>,
+                      <0x0 0xe112f000 0 0x02000>,
+                      <0x0 0xe1140000 0 0x10000>,
+                      <0x0 0xe1160000 0 0x10000>;
+                v2m0: v2m@0x8000 {
+                        compatible = "arm,gic-v2m-frame";
+                        msi-controller;
+                        reg = <0x0 0x80000 0 0x1000>;
+                };
+
+                ....
+
+                v2mN: v2m@0x9000 {
+                        compatible = "arm,gic-v2m-frame";
+                        msi-controller;
+                        reg = <0x0 0x90000 0 0x1000>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
new file mode 100644
index 000000000000..d680b07ec6e8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
@@ -0,0 +1,28 @@
+Mediatek 65xx/81xx sysirq
+
+Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
+interrupt.
+
+Required properties:
+- compatible: should be one of:
+        "mediatek,mt8135-sysirq"
+        "mediatek,mt8127-sysirq"
+        "mediatek,mt6589-sysirq"
+        "mediatek,mt6582-sysirq"
+        "mediatek,mt6577-sysirq"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Use the same format as specified by GIC in
+  Documentation/devicetree/bindings/arm/gic.txt
+- interrupt-parent: phandle of irq parent for sysirq. The parent must
+  use the same interrupt-cells format as GIC.
+- reg: Physical base address of the intpol registers and length of memory
+  mapped region.
+
+Example:
+        sysirq: interrupt-controller@10200100 {
+                compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                interrupt-parent = <&gic>;
+                reg = <0 0x10200100 0 0x1c>;
+        };