dt-bindings: Document EMAC Rockchip

This adds the necessary binding documentation for the EMAC Rockchip platform
driver found in RK3066 and RK3188 SoCs.

Signed-off-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 50 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/net/emac_rockchip.txt b/Documentation/devicetree/bindings/net/emac_rockchip.txt
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+* ARC EMAC 10/100 Ethernet platform driver for Rockchip Rk3066/RK3188 SoCs
+
+Required properties:
+- compatible: Should be "rockchip,rk3066-emac" or "rockchip,rk3188-emac"
+  according to the target SoC.
+- reg: Address and length of the register set for the device
+- interrupts: Should contain the EMAC interrupts
+- rockchip,grf: phandle to the syscon grf used to control speed and mode
+  for emac.
+- phy: see ethernet.txt file in the same directory.
+- phy-mode: see ethernet.txt file in the same directory.
+
+Optional properties:
+- phy-supply: phandle to a regulator if the PHY needs one
+
+Clock handling:
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Shall be "hclk" for the host clock needed to calculate and set
+  polling period of EMAC and "macref" for the reference clock needed to transfer
+  data to and from the phy.
+
+Child nodes of the driver are the individual PHY devices connected to the
+MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
+
+Examples:
+
+ethernet@10204000 {
+        compatible = "rockchip,rk3188-emac";
+        reg = <0xc0fc2000 0x3c>;
+        interrupts = <6>;
+        mac-address = [ 00 11 22 33 44 55 ];
+
+        clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
+        clock-names = "hclk", "macref";
+
+        pinctrl-names = "default";
+        pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+
+        rockchip,grf = <&grf>;
+
+        phy = <&phy0>;
+        phy-mode = "rmii";
+        phy-supply = <&vcc_rmii>;
+
+        #address-cells = <1>;
+        #size-cells = <0>;
+        phy0: ethernet-phy@0 {
+              reg = <1>;
+        };
+};