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authorMarcin Wojtas <mw@semihalf.com>2014-07-10 15:52:13 -0400
committerDavid S. Miller <davem@davemloft.net>2014-07-10 20:18:24 -0400
commit3f518509dedc99f0b755d2ce68d24f610e3a005a (patch)
treedec5c4c2a566e0957f34bec64f5cf2b2a77d141d /Documentation
parentb6428817190c5444294e0cc45bd571bfafbbb537 (diff)
ethernet: Add new driver for Marvell Armada 375 network unit
This commit adds a new network driver for the network controller in Marvell Armada 375 SoC. Given the controller is very different from the ones in the other Marvell SoCs that use the mv643xx_eth (Kirkwood, Orion, Discovery) and mvneta (Armada 370/38x/XP) drivers, a new driver is needed. Signed-off-by: Marcin Wojtas <mw@semihalf.com> [Ezequiel: coding style cleanup] Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/net/marvell-pp2.txt61
1 files changed, 61 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt b/Documentation/devicetree/bindings/net/marvell-pp2.txt
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1* Marvell Armada 375 Ethernet Controller (PPv2)
2
3Required properties:
4
5- compatible: should be "marvell,armada-375-pp2"
6- reg: addresses and length of the register sets for the device.
7 Must contain the following register sets:
8 - common controller registers
9 - LMS registers
10 In addition, at least one port register set is required.
11- clocks: a pointer to the reference clocks for this device, consequently:
12 - main controller clock
13 - GOP clock
14- clock-names: names of used clocks, must be "pp_clk" and "gop_clk".
15
16The ethernet ports are represented by subnodes. At least one port is
17required.
18
19Required properties (port):
20
21- interrupts: interrupt for the port
22- port-id: should be '0' or '1' for ethernet ports, and '2' for the
23 loopback port
24- phy-mode: See ethernet.txt file in the same directory
25
26Optional properties (port):
27
28- marvell,loopback: port is loopback mode
29- phy: a phandle to a phy node defining the PHY address (as the reg
30 property, a single integer). Note: if this property isn't present,
31 then fixed link is assumed, and the 'fixed-link' property is
32 mandatory.
33
34Example:
35
36ethernet@f0000 {
37 compatible = "marvell,armada-375-pp2";
38 reg = <0xf0000 0xa000>,
39 <0xc0000 0x3060>,
40 <0xc4000 0x100>,
41 <0xc5000 0x100>;
42 clocks = <&gateclk 3>, <&gateclk 19>;
43 clock-names = "pp_clk", "gop_clk";
44 status = "okay";
45
46 eth0: eth0@c4000 {
47 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
48 port-id = <0>;
49 status = "okay";
50 phy = <&phy0>;
51 phy-mode = "gmii";
52 };
53
54 eth1: eth1@c5000 {
55 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
56 port-id = <1>;
57 status = "okay";
58 phy = <&phy3>;
59 phy-mode = "gmii";
60 };
61};