Revert "powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file"

This reverts commit 894116bd0e9b7749a0c4b6c62dec13c2a0ccef68.

I applied the wrong version of this patch, correct
version coming up.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 1 insertions, 15 deletions

diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index eb06059f3cf3..2c6be0377f55 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -86,7 +86,6 @@ General Properties:
 
 Clock Properties:
 
-  - fsl,cksel        Timer reference clock source.
   - fsl,tclk-period  Timer reference clock period in nanoseconds.
   - fsl,tmr-prsc     Prescaler, divides the output clock.
   - fsl,tmr-add      Frequency compensation value.
@@ -98,7 +97,7 @@ Clock Properties:
   clock. You must choose these carefully for the clock to work right.
   Here is how to figure good values:
 
-  TimerOsc     = selected reference clock   MHz
+  TimerOsc     = system clock               MHz
   tclk_period  = desired clock period       nanoseconds
   NominalFreq  = 1000 / tclk_period         MHz
   FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
@@ -115,18 +114,6 @@ Clock Properties:
   Pulse Per Second (PPS) signal, since this will be offered to the PPS
   subsystem to synchronize the Linux clock.
 
-  "fsl,cksel" property allows to select different reference clock
-  sources:
-
-  <0> - external high precision timer reference clock (TSEC_TMR_CLK
-        input is used for this purpose);
-  <1> - eTSEC system clock;
-  <2> - eTSEC1 transmit clock;
-  <3> - RTC clock input.
-
-  When this attribute is not used, eTSEC system clock will serve as
-  IEEE 1588 timer reference clock.
-
 Example:
 
         ptp_clock@24E00 {
@@ -134,7 +121,6 @@ Example:
                 reg = <0x24E00 0xB0>;
                 interrupts = <12 0x8 13 0x8>;
                 interrupt-parent = < &ipic >;
-                fsl,cksel       = <1>;
                 fsl,tclk-period = <10>;
                 fsl,tmr-prsc    = <100>;
                 fsl,tmr-add     = <0x999999A4>;