clk: sunxi: Add support for A80 basic bus clocks

The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
new "GT" bus, which I assume is some kind of data bus connecting
the processor cores, memory and various busses. Also there is a
bus clock for a ARM CCI400 module.

As far as I can tell, the GT bus and CCI400 bus clock must be
protected.

This patch adds driver support for peripheral related PLLs and
bus clocks on the A80. The GT and CCI400 clocks are added as well
as these 2 along with the PLLs they are clocked from must not be
disabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index ed116df9c3e7..7f1c486691e0 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -10,14 +10,17 @@ Required properties:
         "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
         "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+        "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
         "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
         "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
+        "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
         "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
         "allwinner,sun4i-a10-axi-clk" - for the AXI clock
         "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
         "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
         "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
+        "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
         "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
@@ -29,6 +32,7 @@ Required properties:
         "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
         "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
         "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
+        "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
         "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
@@ -36,6 +40,7 @@ Required properties:
         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
         "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
         "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
+        "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
         "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
         "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13