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authorMaxime Ripard <maxime.ripard@free-electrons.com>2013-07-16 05:21:59 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2013-08-26 04:46:32 -0400
commit2371dd88b80fc847a451d5eff018e165501f560a (patch)
treeb2c0c45cee37bbd2518f23a3dfb9d41c91ada6a2 /Documentation
parentbddbd13453d838a30baf84869c56076c8ce2b211 (diff)
clk: sunxi: Add A10s gates
The Allwinner A10s has a slightly different gates set than the A10 and A13, so add these gates to the clk driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Emilio López <emilio@elopez.com.ar>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt3
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt75
2 files changed, 78 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index d495521a79d2..b24de1003947 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -14,13 +14,16 @@ Required properties:
14 "allwinner,sun4i-ahb-clk" - for the AHB clock 14 "allwinner,sun4i-ahb-clk" - for the AHB clock
15 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10 15 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
16 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 16 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
17 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
17 "allwinner,sun4i-apb0-clk" - for the APB0 clock 18 "allwinner,sun4i-apb0-clk" - for the APB0 clock
18 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 19 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
19 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 20 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
21 "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
20 "allwinner,sun4i-apb1-clk" - for the APB1 clock 22 "allwinner,sun4i-apb1-clk" - for the APB1 clock
21 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing 23 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
22 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10 24 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
23 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 25 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
26 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
24 27
25Required properties for all clocks: 28Required properties for all clocks:
26- reg : shall be the control register address for the clock. 29- reg : shall be the control register address for the clock.
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
new file mode 100644
index 000000000000..d24279fe1429
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
@@ -0,0 +1,75 @@
1Gate clock outputs
2------------------
3
4 * AXI gates ("allwinner,sun4i-axi-gates-clk")
5
6 DRAM 0
7
8 * AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk")
9
10 USB0 0
11 EHCI0 1
12 OHCI0 2
13
14 SS 5
15 DMA 6
16 BIST 7
17 MMC0 8
18 MMC1 9
19 MMC2 10
20
21 NAND 13
22 SDRAM 14
23
24 EMAC 17
25 TS 18
26
27 SPI0 20
28 SPI1 21
29 SPI2 22
30
31 GPS 26
32
33 HSTIMER 28
34
35 VE 32
36
37 TVE 34
38
39 LCD 36
40
41 CSI 40
42
43 HDMI 43
44 DE_BE 44
45
46 DE_FE 46
47
48 IEP 51
49 MALI400 52
50
51 * APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk")
52
53 CODEC 0
54
55 IIS 3
56
57 PIO 5
58 IR 6
59
60 KEYPAD 10
61
62 * APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk")
63
64 I2C0 0
65 I2C1 1
66 I2C2 2
67
68 UART0 16
69 UART1 17
70 UART2 18
71 UART3 19
72
73Notation:
74 [*]: The datasheet didn't mention these, but they are present on AW code
75 [**]: The datasheet had this marked as "NC" but they are used on AW code