diff options
author | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
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committer | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
commit | c71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch) | |
tree | ecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /Documentation/hwmon/jc42 | |
parent | ea53c912f8a86a8567697115b6a0d8152beee5c8 (diff) | |
parent | 6a00f206debf8a5c8899055726ad127dbeeed098 (diff) |
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts:
litmus/sched_cedf.c
Diffstat (limited to 'Documentation/hwmon/jc42')
-rw-r--r-- | Documentation/hwmon/jc42 | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/Documentation/hwmon/jc42 b/Documentation/hwmon/jc42 index 0e76ef12e4c6..a22ecf48f255 100644 --- a/Documentation/hwmon/jc42 +++ b/Documentation/hwmon/jc42 | |||
@@ -51,7 +51,8 @@ Supported chips: | |||
51 | * JEDEC JC 42.4 compliant temperature sensor chips | 51 | * JEDEC JC 42.4 compliant temperature sensor chips |
52 | Prefix: 'jc42' | 52 | Prefix: 'jc42' |
53 | Addresses scanned: I2C 0x18 - 0x1f | 53 | Addresses scanned: I2C 0x18 - 0x1f |
54 | Datasheet: - | 54 | Datasheet: |
55 | http://www.jedec.org/sites/default/files/docs/4_01_04R19.pdf | ||
55 | 56 | ||
56 | Author: | 57 | Author: |
57 | Guenter Roeck <guenter.roeck@ericsson.com> | 58 | Guenter Roeck <guenter.roeck@ericsson.com> |
@@ -60,7 +61,11 @@ Author: | |||
60 | Description | 61 | Description |
61 | ----------- | 62 | ----------- |
62 | 63 | ||
63 | This driver implements support for JEDEC JC 42.4 compliant temperature sensors. | 64 | This driver implements support for JEDEC JC 42.4 compliant temperature sensors, |
65 | which are used on many DDR3 memory modules for mobile devices and servers. Some | ||
66 | systems use the sensor to prevent memory overheating by automatically throttling | ||
67 | the memory controller. | ||
68 | |||
64 | The driver auto-detects the chips listed above, but can be manually instantiated | 69 | The driver auto-detects the chips listed above, but can be manually instantiated |
65 | to support other JC 42.4 compliant chips. | 70 | to support other JC 42.4 compliant chips. |
66 | 71 | ||
@@ -81,15 +86,19 @@ limits. The chip supports only a single register to configure the hysteresis, | |||
81 | which applies to all limits. This register can be written by writing into | 86 | which applies to all limits. This register can be written by writing into |
82 | temp1_crit_hyst. Other hysteresis attributes are read-only. | 87 | temp1_crit_hyst. Other hysteresis attributes are read-only. |
83 | 88 | ||
89 | If the BIOS has configured the sensor for automatic temperature management, it | ||
90 | is likely that it has locked the registers, i.e., that the temperature limits | ||
91 | cannot be changed. | ||
92 | |||
84 | Sysfs entries | 93 | Sysfs entries |
85 | ------------- | 94 | ------------- |
86 | 95 | ||
87 | temp1_input Temperature (RO) | 96 | temp1_input Temperature (RO) |
88 | temp1_min Minimum temperature (RW) | 97 | temp1_min Minimum temperature (RO or RW) |
89 | temp1_max Maximum temperature (RW) | 98 | temp1_max Maximum temperature (RO or RW) |
90 | temp1_crit Critical high temperature (RW) | 99 | temp1_crit Critical high temperature (RO or RW) |
91 | 100 | ||
92 | temp1_crit_hyst Critical hysteresis temperature (RW) | 101 | temp1_crit_hyst Critical hysteresis temperature (RO or RW) |
93 | temp1_max_hyst Maximum hysteresis temperature (RO) | 102 | temp1_max_hyst Maximum hysteresis temperature (RO) |
94 | 103 | ||
95 | temp1_min_alarm Temperature low alarm | 104 | temp1_min_alarm Temperature low alarm |