diff options
author | H. Peter Anvin <hpa@zytor.com> | 2012-05-30 15:11:26 -0400 |
---|---|---|
committer | H. Peter Anvin <hpa@zytor.com> | 2012-05-30 15:11:32 -0400 |
commit | bbd771474ec44b516107685d77e1c80bbe09f141 (patch) | |
tree | 0cb15781539a68f27b4ea6c89f827282630cbce6 /Documentation/devicetree | |
parent | 403e1c5b7495d7b80fae9fc4d0a7a6f5abdc3307 (diff) | |
parent | 319b6ffc6df892e4ccffff823cc5521a4a5d2dca (diff) |
Merge branch 'x86/trampoline' into x86/urgent
x86/trampoline contains an urgent commit which is necessarily on a
newer baseline.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'Documentation/devicetree')
33 files changed, 870 insertions, 19 deletions
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index bfbc771a65f8..ac9e7516756e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt | |||
@@ -1,6 +1,14 @@ | |||
1 | Freescale i.MX Platforms Device Tree Bindings | 1 | Freescale i.MX Platforms Device Tree Bindings |
2 | ----------------------------------------------- | 2 | ----------------------------------------------- |
3 | 3 | ||
4 | i.MX23 Evaluation Kit | ||
5 | Required root node properties: | ||
6 | - compatible = "fsl,imx23-evk", "fsl,imx23"; | ||
7 | |||
8 | i.MX28 Evaluation Kit | ||
9 | Required root node properties: | ||
10 | - compatible = "fsl,imx28-evk", "fsl,imx28"; | ||
11 | |||
4 | i.MX51 Babbage Board | 12 | i.MX51 Babbage Board |
5 | Required root node properties: | 13 | Required root node properties: |
6 | - compatible = "fsl,imx51-babbage", "fsl,imx51"; | 14 | - compatible = "fsl,imx51-babbage", "fsl,imx51"; |
@@ -29,6 +37,10 @@ i.MX6 Quad SABRE Lite Board | |||
29 | Required root node properties: | 37 | Required root node properties: |
30 | - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; | 38 | - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q"; |
31 | 39 | ||
40 | i.MX6 Quad SABRE Smart Device Board | ||
41 | Required root node properties: | ||
42 | - compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; | ||
43 | |||
32 | Generic i.MX boards | 44 | Generic i.MX boards |
33 | ------------------- | 45 | ------------------- |
34 | 46 | ||
diff --git a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt new file mode 100644 index 000000000000..f2f2171e530e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt | |||
@@ -0,0 +1,52 @@ | |||
1 | * Samsung Exynos Interrupt Combiner Controller | ||
2 | |||
3 | Samsung's Exynos4 architecture includes a interrupt combiner controller which | ||
4 | can combine interrupt sources as a group and provide a single interrupt request | ||
5 | for the group. The interrupt request from each group are connected to a parent | ||
6 | interrupt controller, such as GIC in case of Exynos4210. | ||
7 | |||
8 | The interrupt combiner controller consists of multiple combiners. Upto eight | ||
9 | interrupt sources can be connected to a combiner. The combiner outputs one | ||
10 | combined interrupt for its eight interrupt sources. The combined interrupt | ||
11 | is usually connected to a parent interrupt controller. | ||
12 | |||
13 | A single node in the device tree is used to describe the interrupt combiner | ||
14 | controller module (which includes multiple combiners). A combiner in the | ||
15 | interrupt controller module shares config/control registers with other | ||
16 | combiners. For example, a 32-bit interrupt enable/disable config register | ||
17 | can accommodate upto 4 interrupt combiners (with each combiner supporting | ||
18 | upto 8 interrupt sources). | ||
19 | |||
20 | Required properties: | ||
21 | - compatible: should be "samsung,exynos4210-combiner". | ||
22 | - interrupt-controller: Identifies the node as an interrupt controller. | ||
23 | - #interrupt-cells: should be <2>. The meaning of the cells are | ||
24 | * First Cell: Combiner Group Number. | ||
25 | * Second Cell: Interrupt number within the group. | ||
26 | - reg: Base address and size of interrupt combiner registers. | ||
27 | - interrupts: The list of interrupts generated by the combiners which are then | ||
28 | connected to a parent interrupt controller. The format of the interrupt | ||
29 | specifier depends in the interrupt parent controller. | ||
30 | |||
31 | Optional properties: | ||
32 | - samsung,combiner-nr: The number of interrupt combiners supported. If this | ||
33 | property is not specified, the default number of combiners is assumed | ||
34 | to be 16. | ||
35 | - interrupt-parent: pHandle of the parent interrupt controller, if not | ||
36 | inherited from the parent node. | ||
37 | |||
38 | |||
39 | Example: | ||
40 | |||
41 | The following is a an example from the Exynos4210 SoC dtsi file. | ||
42 | |||
43 | combiner:interrupt-controller@10440000 { | ||
44 | compatible = "samsung,exynos4210-combiner"; | ||
45 | interrupt-controller; | ||
46 | #interrupt-cells = <2>; | ||
47 | reg = <0x10440000 0x1000>; | ||
48 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | ||
49 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | ||
50 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | ||
51 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; | ||
52 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/spear-timer.txt b/Documentation/devicetree/bindings/arm/spear-timer.txt new file mode 100644 index 000000000000..c0017221cf55 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/spear-timer.txt | |||
@@ -0,0 +1,18 @@ | |||
1 | * SPEAr ARM Timer | ||
2 | |||
3 | ** Timer node required properties: | ||
4 | |||
5 | - compatible : Should be: | ||
6 | "st,spear-timer" | ||
7 | - reg: Address range of the timer registers | ||
8 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
9 | that services interrupts for this device | ||
10 | - interrupt: Should contain the timer interrupt number | ||
11 | |||
12 | Example: | ||
13 | |||
14 | timer@f0000000 { | ||
15 | compatible = "st,spear-timer"; | ||
16 | reg = <0xf0000000 0x400>; | ||
17 | interrupts = <2>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/spear.txt b/Documentation/devicetree/bindings/arm/spear.txt index aa5f355cc947..0d42949df6c2 100644 --- a/Documentation/devicetree/bindings/arm/spear.txt +++ b/Documentation/devicetree/bindings/arm/spear.txt | |||
@@ -2,25 +2,25 @@ ST SPEAr Platforms Device Tree Bindings | |||
2 | --------------------------------------- | 2 | --------------------------------------- |
3 | 3 | ||
4 | Boards with the ST SPEAr600 SoC shall have the following properties: | 4 | Boards with the ST SPEAr600 SoC shall have the following properties: |
5 | |||
6 | Required root node property: | 5 | Required root node property: |
7 | |||
8 | compatible = "st,spear600"; | 6 | compatible = "st,spear600"; |
9 | 7 | ||
10 | Boards with the ST SPEAr300 SoC shall have the following properties: | 8 | Boards with the ST SPEAr300 SoC shall have the following properties: |
11 | |||
12 | Required root node property: | 9 | Required root node property: |
13 | |||
14 | compatible = "st,spear300"; | 10 | compatible = "st,spear300"; |
15 | 11 | ||
16 | Boards with the ST SPEAr310 SoC shall have the following properties: | 12 | Boards with the ST SPEAr310 SoC shall have the following properties: |
17 | |||
18 | Required root node property: | 13 | Required root node property: |
19 | |||
20 | compatible = "st,spear310"; | 14 | compatible = "st,spear310"; |
21 | 15 | ||
22 | Boards with the ST SPEAr320 SoC shall have the following properties: | 16 | Boards with the ST SPEAr320 SoC shall have the following properties: |
17 | Required root node property: | ||
18 | compatible = "st,spear320"; | ||
23 | 19 | ||
20 | Boards with the ST SPEAr1310 SoC shall have the following properties: | ||
24 | Required root node property: | 21 | Required root node property: |
22 | compatible = "st,spear1310"; | ||
25 | 23 | ||
26 | compatible = "st,spear320"; | 24 | Boards with the ST SPEAr1340 SoC shall have the following properties: |
25 | Required root node property: | ||
26 | compatible = "st,spear1340"; | ||
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt new file mode 100644 index 000000000000..234406d41c12 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt | |||
@@ -0,0 +1,11 @@ | |||
1 | NVIDIA Tegra AHB | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb" | ||
5 | - reg : Should contain 1 register ranges(address and length) | ||
6 | |||
7 | Example: | ||
8 | ahb: ahb@6000c004 { | ||
9 | compatible = "nvidia,tegra20-ahb"; | ||
10 | reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ | ||
11 | }; | ||
diff --git a/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt new file mode 100644 index 000000000000..ded0398d3bdc --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt | |||
@@ -0,0 +1,19 @@ | |||
1 | * Freescale MXS DMA | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx" | ||
5 | - reg : Should contain registers location and length | ||
6 | |||
7 | Supported chips: | ||
8 | imx23, imx28. | ||
9 | |||
10 | Examples: | ||
11 | dma-apbh@80004000 { | ||
12 | compatible = "fsl,imx28-dma-apbh"; | ||
13 | reg = <0x80004000 2000>; | ||
14 | }; | ||
15 | |||
16 | dma-apbx@80024000 { | ||
17 | compatible = "fsl,imx28-dma-apbx"; | ||
18 | reg = <0x80024000 2000>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt new file mode 100644 index 000000000000..c0d85dbcada5 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/snps-dma.txt | |||
@@ -0,0 +1,17 @@ | |||
1 | * Synopsys Designware DMA Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "snps,dma-spear1340" | ||
5 | - reg: Address range of the DMAC registers | ||
6 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
7 | that services interrupts for this device | ||
8 | - interrupt: Should contain the DMAC interrupt number | ||
9 | |||
10 | Example: | ||
11 | |||
12 | dma@fc000000 { | ||
13 | compatible = "snps,dma-spear1340"; | ||
14 | reg = <0xfc000000 0x1000>; | ||
15 | interrupt-parent = <&vic1>; | ||
16 | interrupts = <12>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt b/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt new file mode 100644 index 000000000000..f93d51478d5a --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt | |||
@@ -0,0 +1,38 @@ | |||
1 | Lantiq SoC External Bus memory mapped GPIO controller | ||
2 | |||
3 | By attaching hardware latches to the EBU it is possible to create output | ||
4 | only gpios. This driver configures a special memory address, which when | ||
5 | written to outputs 16 bit to the latches. | ||
6 | |||
7 | The node describing the memory mapped GPIOs needs to be a child of the node | ||
8 | describing the "lantiq,localbus". | ||
9 | |||
10 | Required properties: | ||
11 | - compatible : Should be "lantiq,gpio-mm-lantiq" | ||
12 | - reg : Address and length of the register set for the device | ||
13 | - #gpio-cells : Should be two. The first cell is the pin number and | ||
14 | the second cell is used to specify optional parameters (currently | ||
15 | unused). | ||
16 | - gpio-controller : Marks the device node as a gpio controller. | ||
17 | |||
18 | Optional properties: | ||
19 | - lantiq,shadow : The default value that we shall assume as already set on the | ||
20 | shift register cascade. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | localbus@0 { | ||
25 | #address-cells = <2>; | ||
26 | #size-cells = <1>; | ||
27 | ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ | ||
28 | 1 0 0x4000000 0x4000010>; /* addsel1 */ | ||
29 | compatible = "lantiq,localbus", "simple-bus"; | ||
30 | |||
31 | gpio_mm0: gpio@4000000 { | ||
32 | compatible = "lantiq,gpio-mm"; | ||
33 | reg = <1 0x0 0x10>; | ||
34 | gpio-controller; | ||
35 | #gpio-cells = <2>; | ||
36 | lantiq,shadow = <0x77f> | ||
37 | }; | ||
38 | } | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt b/Documentation/devicetree/bindings/gpio/gpio-mxs.txt new file mode 100644 index 000000000000..0c35673f7a3e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-mxs.txt | |||
@@ -0,0 +1,87 @@ | |||
1 | * Freescale MXS GPIO controller | ||
2 | |||
3 | The Freescale MXS GPIO controller is part of MXS PIN controller. The | ||
4 | GPIOs are organized in port/bank. Each port consists of 32 GPIOs. | ||
5 | |||
6 | As the GPIO controller is embedded in the PIN controller and all the | ||
7 | GPIO ports share the same IO space with PIN controller, the GPIO node | ||
8 | will be represented as sub-nodes of MXS pinctrl node. | ||
9 | |||
10 | Required properties for GPIO node: | ||
11 | - compatible : Should be "fsl,<soc>-gpio". The supported SoCs include | ||
12 | imx23 and imx28. | ||
13 | - interrupts : Should be the port interrupt shared by all 32 pins. | ||
14 | - gpio-controller : Marks the device node as a gpio controller. | ||
15 | - #gpio-cells : Should be two. The first cell is the pin number and | ||
16 | the second cell is used to specify optional parameters (currently | ||
17 | unused). | ||
18 | - interrupt-controller: Marks the device node as an interrupt controller. | ||
19 | - #interrupt-cells : Should be 2. The first cell is the GPIO number. | ||
20 | The second cell bits[3:0] is used to specify trigger type and level flags: | ||
21 | 1 = low-to-high edge triggered. | ||
22 | 2 = high-to-low edge triggered. | ||
23 | 4 = active high level-sensitive. | ||
24 | 8 = active low level-sensitive. | ||
25 | |||
26 | Note: Each GPIO port should have an alias correctly numbered in "aliases" | ||
27 | node. | ||
28 | |||
29 | Examples: | ||
30 | |||
31 | aliases { | ||
32 | gpio0 = &gpio0; | ||
33 | gpio1 = &gpio1; | ||
34 | gpio2 = &gpio2; | ||
35 | gpio3 = &gpio3; | ||
36 | gpio4 = &gpio4; | ||
37 | }; | ||
38 | |||
39 | pinctrl@80018000 { | ||
40 | compatible = "fsl,imx28-pinctrl", "simple-bus"; | ||
41 | reg = <0x80018000 2000>; | ||
42 | |||
43 | gpio0: gpio@0 { | ||
44 | compatible = "fsl,imx28-gpio"; | ||
45 | interrupts = <127>; | ||
46 | gpio-controller; | ||
47 | #gpio-cells = <2>; | ||
48 | interrupt-controller; | ||
49 | #interrupt-cells = <2>; | ||
50 | }; | ||
51 | |||
52 | gpio1: gpio@1 { | ||
53 | compatible = "fsl,imx28-gpio"; | ||
54 | interrupts = <126>; | ||
55 | gpio-controller; | ||
56 | #gpio-cells = <2>; | ||
57 | interrupt-controller; | ||
58 | #interrupt-cells = <2>; | ||
59 | }; | ||
60 | |||
61 | gpio2: gpio@2 { | ||
62 | compatible = "fsl,imx28-gpio"; | ||
63 | interrupts = <125>; | ||
64 | gpio-controller; | ||
65 | #gpio-cells = <2>; | ||
66 | interrupt-controller; | ||
67 | #interrupt-cells = <2>; | ||
68 | }; | ||
69 | |||
70 | gpio3: gpio@3 { | ||
71 | compatible = "fsl,imx28-gpio"; | ||
72 | interrupts = <124>; | ||
73 | gpio-controller; | ||
74 | #gpio-cells = <2>; | ||
75 | interrupt-controller; | ||
76 | #interrupt-cells = <2>; | ||
77 | }; | ||
78 | |||
79 | gpio4: gpio@4 { | ||
80 | compatible = "fsl,imx28-gpio"; | ||
81 | interrupts = <123>; | ||
82 | gpio-controller; | ||
83 | #gpio-cells = <2>; | ||
84 | interrupt-controller; | ||
85 | #interrupt-cells = <2>; | ||
86 | }; | ||
87 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt new file mode 100644 index 000000000000..854de130a971 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt | |||
@@ -0,0 +1,42 @@ | |||
1 | Lantiq SoC Serial To Parallel (STP) GPIO controller | ||
2 | |||
3 | The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a | ||
4 | peripheral controller used to drive external shift register cascades. At most | ||
5 | 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem | ||
6 | to drive the 2 LSBs of the cascade automatically. | ||
7 | |||
8 | |||
9 | Required properties: | ||
10 | - compatible : Should be "lantiq,gpio-stp-xway" | ||
11 | - reg : Address and length of the register set for the device | ||
12 | - #gpio-cells : Should be two. The first cell is the pin number and | ||
13 | the second cell is used to specify optional parameters (currently | ||
14 | unused). | ||
15 | - gpio-controller : Marks the device node as a gpio controller. | ||
16 | |||
17 | Optional properties: | ||
18 | - lantiq,shadow : The default value that we shall assume as already set on the | ||
19 | shift register cascade. | ||
20 | - lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled | ||
21 | in the shift register cascade. | ||
22 | - lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit | ||
23 | property can enable this feature. | ||
24 | - lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade. | ||
25 | - lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade. | ||
26 | - lantiq,rising : use rising instead of falling edge for the shift register | ||
27 | |||
28 | Example: | ||
29 | |||
30 | gpio1: stp@E100BB0 { | ||
31 | compatible = "lantiq,gpio-stp-xway"; | ||
32 | reg = <0xE100BB0 0x40>; | ||
33 | #gpio-cells = <2>; | ||
34 | gpio-controller; | ||
35 | |||
36 | lantiq,shadow = <0xffff>; | ||
37 | lantiq,groups = <0x7>; | ||
38 | lantiq,dsl = <0x3>; | ||
39 | lantiq,phy1 = <0x7>; | ||
40 | lantiq,phy2 = <0x7>; | ||
41 | /* lantiq,rising; */ | ||
42 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mxs.txt b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt new file mode 100644 index 000000000000..1bfc02de1b0c --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-mxs.txt | |||
@@ -0,0 +1,16 @@ | |||
1 | * Freescale MXS Inter IC (I2C) Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "fsl,<chip>-i2c" | ||
5 | - reg: Should contain registers location and length | ||
6 | - interrupts: Should contain ERROR and DMA interrupts | ||
7 | |||
8 | Examples: | ||
9 | |||
10 | i2c0: i2c@80058000 { | ||
11 | #address-cells = <1>; | ||
12 | #size-cells = <0>; | ||
13 | compatible = "fsl,imx28-i2c"; | ||
14 | reg = <0x80058000 2000>; | ||
15 | interrupts = <111 68>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/mux.txt b/Documentation/devicetree/bindings/i2c/mux.txt new file mode 100644 index 000000000000..af84cce5cd7b --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/mux.txt | |||
@@ -0,0 +1,60 @@ | |||
1 | Common i2c bus multiplexer/switch properties. | ||
2 | |||
3 | An i2c bus multiplexer/switch will have several child busses that are | ||
4 | numbered uniquely in a device dependent manner. The nodes for an i2c bus | ||
5 | multiplexer/switch will have one child node for each child | ||
6 | bus. | ||
7 | |||
8 | Required properties: | ||
9 | - #address-cells = <1>; | ||
10 | - #size-cells = <0>; | ||
11 | |||
12 | Required properties for child nodes: | ||
13 | - #address-cells = <1>; | ||
14 | - #size-cells = <0>; | ||
15 | - reg : The sub-bus number. | ||
16 | |||
17 | Optional properties for child nodes: | ||
18 | - Other properties specific to the multiplexer/switch hardware. | ||
19 | - Child nodes conforming to i2c bus binding | ||
20 | |||
21 | |||
22 | Example : | ||
23 | |||
24 | /* | ||
25 | An NXP pca9548 8 channel I2C multiplexer at address 0x70 | ||
26 | with two NXP pca8574 GPIO expanders attached, one each to | ||
27 | ports 3 and 4. | ||
28 | */ | ||
29 | |||
30 | mux@70 { | ||
31 | compatible = "nxp,pca9548"; | ||
32 | reg = <0x70>; | ||
33 | #address-cells = <1>; | ||
34 | #size-cells = <0>; | ||
35 | |||
36 | i2c@3 { | ||
37 | #address-cells = <1>; | ||
38 | #size-cells = <0>; | ||
39 | reg = <3>; | ||
40 | |||
41 | gpio1: gpio@38 { | ||
42 | compatible = "nxp,pca8574"; | ||
43 | reg = <0x38>; | ||
44 | #gpio-cells = <2>; | ||
45 | gpio-controller; | ||
46 | }; | ||
47 | }; | ||
48 | i2c@4 { | ||
49 | #address-cells = <1>; | ||
50 | #size-cells = <0>; | ||
51 | reg = <4>; | ||
52 | |||
53 | gpio2: gpio@38 { | ||
54 | compatible = "nxp,pca8574"; | ||
55 | reg = <0x38>; | ||
56 | #gpio-cells = <2>; | ||
57 | gpio-controller; | ||
58 | }; | ||
59 | }; | ||
60 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/samsung-i2c.txt b/Documentation/devicetree/bindings/i2c/samsung-i2c.txt index 38832c712919..b6cb5a12c672 100644 --- a/Documentation/devicetree/bindings/i2c/samsung-i2c.txt +++ b/Documentation/devicetree/bindings/i2c/samsung-i2c.txt | |||
@@ -6,14 +6,18 @@ Required properties: | |||
6 | - compatible: value should be either of the following. | 6 | - compatible: value should be either of the following. |
7 | (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c. | 7 | (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c. |
8 | (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c. | 8 | (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c. |
9 | (c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used | ||
10 | inside HDMIPHY block found on several samsung SoCs | ||
9 | - reg: physical base address of the controller and length of memory mapped | 11 | - reg: physical base address of the controller and length of memory mapped |
10 | region. | 12 | region. |
11 | - interrupts: interrupt number to the cpu. | 13 | - interrupts: interrupt number to the cpu. |
12 | - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges. | 14 | - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges. |
13 | - gpios: The order of the gpios should be the following: <SDA, SCL>. | ||
14 | The gpio specifier depends on the gpio controller. | ||
15 | 15 | ||
16 | Optional properties: | 16 | Optional properties: |
17 | - gpios: The order of the gpios should be the following: <SDA, SCL>. | ||
18 | The gpio specifier depends on the gpio controller. Required in all | ||
19 | cases except for "samsung,s3c2440-hdmiphy-i2c" whose input/output | ||
20 | lines are permanently wired to the respective client | ||
17 | - samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not | 21 | - samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not |
18 | specified, default value is 0. | 22 | specified, default value is 0. |
19 | - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not | 23 | - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not |
diff --git a/Documentation/devicetree/bindings/i2c/xiic.txt b/Documentation/devicetree/bindings/i2c/xiic.txt new file mode 100644 index 000000000000..ceabbe91ae44 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/xiic.txt | |||
@@ -0,0 +1,22 @@ | |||
1 | Xilinx IIC controller: | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Must be "xlnx,xps-iic-2.00.a" | ||
5 | - reg : IIC register location and length | ||
6 | - interrupts : IIC controller unterrupt | ||
7 | - #address-cells = <1> | ||
8 | - #size-cells = <0> | ||
9 | |||
10 | Optional properties: | ||
11 | - Child nodes conforming to i2c bus binding | ||
12 | |||
13 | Example: | ||
14 | |||
15 | axi_iic_0: i2c@40800000 { | ||
16 | compatible = "xlnx,xps-iic-2.00.a"; | ||
17 | interrupts = < 1 2 >; | ||
18 | reg = < 0x40800000 0x10000 >; | ||
19 | |||
20 | #size-cells = <0>; | ||
21 | #address-cells = <1>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/da9052-i2c.txt b/Documentation/devicetree/bindings/mfd/da9052-i2c.txt new file mode 100644 index 000000000000..1857f4a6b9a9 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/da9052-i2c.txt | |||
@@ -0,0 +1,60 @@ | |||
1 | * Dialog DA9052/53 Power Management Integrated Circuit (PMIC) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "dlg,da9052", "dlg,da9053-aa", | ||
5 | "dlg,da9053-ab", or "dlg,da9053-bb" | ||
6 | |||
7 | Sub-nodes: | ||
8 | - regulators : Contain the regulator nodes. The DA9052/53 regulators are | ||
9 | bound using their names as listed below: | ||
10 | |||
11 | buck0 : regulator BUCK0 | ||
12 | buck1 : regulator BUCK1 | ||
13 | buck2 : regulator BUCK2 | ||
14 | buck3 : regulator BUCK3 | ||
15 | ldo4 : regulator LDO4 | ||
16 | ldo5 : regulator LDO5 | ||
17 | ldo6 : regulator LDO6 | ||
18 | ldo7 : regulator LDO7 | ||
19 | ldo8 : regulator LDO8 | ||
20 | ldo9 : regulator LDO9 | ||
21 | ldo10 : regulator LDO10 | ||
22 | ldo11 : regulator LDO11 | ||
23 | ldo12 : regulator LDO12 | ||
24 | ldo13 : regulator LDO13 | ||
25 | |||
26 | The bindings details of individual regulator device can be found in: | ||
27 | Documentation/devicetree/bindings/regulator/regulator.txt | ||
28 | |||
29 | Examples: | ||
30 | |||
31 | i2c@63fc8000 { /* I2C1 */ | ||
32 | status = "okay"; | ||
33 | |||
34 | pmic: dialog@48 { | ||
35 | compatible = "dlg,da9053-aa"; | ||
36 | reg = <0x48>; | ||
37 | |||
38 | regulators { | ||
39 | buck0 { | ||
40 | regulator-min-microvolt = <500000>; | ||
41 | regulator-max-microvolt = <2075000>; | ||
42 | }; | ||
43 | |||
44 | buck1 { | ||
45 | regulator-min-microvolt = <500000>; | ||
46 | regulator-max-microvolt = <2075000>; | ||
47 | }; | ||
48 | |||
49 | buck2 { | ||
50 | regulator-min-microvolt = <925000>; | ||
51 | regulator-max-microvolt = <2500000>; | ||
52 | }; | ||
53 | |||
54 | buck3 { | ||
55 | regulator-min-microvolt = <925000>; | ||
56 | regulator-max-microvolt = <2500000>; | ||
57 | }; | ||
58 | }; | ||
59 | }; | ||
60 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/tps65910.txt b/Documentation/devicetree/bindings/mfd/tps65910.txt new file mode 100644 index 000000000000..645f5eaadb3f --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/tps65910.txt | |||
@@ -0,0 +1,133 @@ | |||
1 | TPS65910 Power Management Integrated Circuit | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,tps65910" or "ti,tps65911" | ||
5 | - reg: I2C slave address | ||
6 | - interrupts: the interrupt outputs of the controller | ||
7 | - #gpio-cells: number of cells to describe a GPIO, this should be 2. | ||
8 | The first cell is the GPIO number. | ||
9 | The second cell is used to specify additional options <unused>. | ||
10 | - gpio-controller: mark the device as a GPIO controller | ||
11 | - #interrupt-cells: the number of cells to describe an IRQ, this should be 2. | ||
12 | The first cell is the IRQ number. | ||
13 | The second cell is the flags, encoded as the trigger masks from | ||
14 | Documentation/devicetree/bindings/interrupts.txt | ||
15 | - regulators: This is the list of child nodes that specify the regulator | ||
16 | initialization data for defined regulators. Not all regulators for the given | ||
17 | device need to be present. The definition for each of these nodes is defined | ||
18 | using the standard binding for regulators found at | ||
19 | Documentation/devicetree/bindings/regulator/regulator.txt. | ||
20 | |||
21 | The valid names for regulators are: | ||
22 | tps65910: vrtc, vio, vdd1, vdd2, vdd3, vdig1, vdig2, vpll, vdac, vaux1, | ||
23 | vaux2, vaux33, vmmc | ||
24 | tps65911: vrtc, vio, vdd1, vdd3, vddctrl, ldo1, ldo2, ldo3, ldo4, ldo5, | ||
25 | ldo6, ldo7, ldo8 | ||
26 | |||
27 | Optional properties: | ||
28 | - ti,vmbch-threshold: (tps65911) main battery charged threshold | ||
29 | comparator. (see VMBCH_VSEL in TPS65910 datasheet) | ||
30 | - ti,vmbch2-threshold: (tps65911) main battery discharged threshold | ||
31 | comparator. (see VMBCH_VSEL in TPS65910 datasheet) | ||
32 | - ti,en-gpio-sleep: enable sleep control for gpios | ||
33 | There should be 9 entries here, one for each gpio. | ||
34 | |||
35 | Regulator Optional properties: | ||
36 | - ti,regulator-ext-sleep-control: enable external sleep | ||
37 | control through external inputs [0 (not enabled), 1 (EN1), 2 (EN2) or 4(EN3)] | ||
38 | If this property is not defined, it defaults to 0 (not enabled). | ||
39 | |||
40 | Example: | ||
41 | |||
42 | pmu: tps65910@d2 { | ||
43 | compatible = "ti,tps65910"; | ||
44 | reg = <0xd2>; | ||
45 | interrupt-parent = <&intc>; | ||
46 | interrupts = < 0 118 0x04 >; | ||
47 | |||
48 | #gpio-cells = <2>; | ||
49 | gpio-controller; | ||
50 | |||
51 | #interrupt-cells = <2>; | ||
52 | interrupt-controller; | ||
53 | |||
54 | ti,vmbch-threshold = 0; | ||
55 | ti,vmbch2-threshold = 0; | ||
56 | |||
57 | ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>; | ||
58 | |||
59 | regulators { | ||
60 | vdd1_reg: vdd1 { | ||
61 | regulator-min-microvolt = < 600000>; | ||
62 | regulator-max-microvolt = <1500000>; | ||
63 | regulator-always-on; | ||
64 | regulator-boot-on; | ||
65 | ti,regulator-ext-sleep-control = <0>; | ||
66 | }; | ||
67 | vdd2_reg: vdd2 { | ||
68 | regulator-min-microvolt = < 600000>; | ||
69 | regulator-max-microvolt = <1500000>; | ||
70 | regulator-always-on; | ||
71 | regulator-boot-on; | ||
72 | ti,regulator-ext-sleep-control = <4>; | ||
73 | }; | ||
74 | vddctrl_reg: vddctrl { | ||
75 | regulator-min-microvolt = < 600000>; | ||
76 | regulator-max-microvolt = <1400000>; | ||
77 | regulator-always-on; | ||
78 | regulator-boot-on; | ||
79 | ti,regulator-ext-sleep-control = <0>; | ||
80 | }; | ||
81 | vio_reg: vio { | ||
82 | regulator-min-microvolt = <1500000>; | ||
83 | regulator-max-microvolt = <1800000>; | ||
84 | regulator-always-on; | ||
85 | regulator-boot-on; | ||
86 | ti,regulator-ext-sleep-control = <1>; | ||
87 | }; | ||
88 | ldo1_reg: ldo1 { | ||
89 | regulator-min-microvolt = <1000000>; | ||
90 | regulator-max-microvolt = <3300000>; | ||
91 | ti,regulator-ext-sleep-control = <0>; | ||
92 | }; | ||
93 | ldo2_reg: ldo2 { | ||
94 | regulator-min-microvolt = <1050000>; | ||
95 | regulator-max-microvolt = <1050000>; | ||
96 | ti,regulator-ext-sleep-control = <0>; | ||
97 | }; | ||
98 | ldo3_reg: ldo3 { | ||
99 | regulator-min-microvolt = <1000000>; | ||
100 | regulator-max-microvolt = <3300000>; | ||
101 | ti,regulator-ext-sleep-control = <0>; | ||
102 | }; | ||
103 | ldo4_reg: ldo4 { | ||
104 | regulator-min-microvolt = <1000000>; | ||
105 | regulator-max-microvolt = <3300000>; | ||
106 | regulator-always-on; | ||
107 | ti,regulator-ext-sleep-control = <0>; | ||
108 | }; | ||
109 | ldo5_reg: ldo5 { | ||
110 | regulator-min-microvolt = <1000000>; | ||
111 | regulator-max-microvolt = <3300000>; | ||
112 | ti,regulator-ext-sleep-control = <0>; | ||
113 | }; | ||
114 | ldo6_reg: ldo6 { | ||
115 | regulator-min-microvolt = <1200000>; | ||
116 | regulator-max-microvolt = <1200000>; | ||
117 | ti,regulator-ext-sleep-control = <0>; | ||
118 | }; | ||
119 | ldo7_reg: ldo7 { | ||
120 | regulator-min-microvolt = <1200000>; | ||
121 | regulator-max-microvolt = <1200000>; | ||
122 | regulator-always-on; | ||
123 | regulator-boot-on; | ||
124 | ti,regulator-ext-sleep-control = <1>; | ||
125 | }; | ||
126 | ldo8_reg: ldo8 { | ||
127 | regulator-min-microvolt = <1000000>; | ||
128 | regulator-max-microvolt = <3300000>; | ||
129 | regulator-always-on; | ||
130 | ti,regulator-ext-sleep-control = <1>; | ||
131 | }; | ||
132 | }; | ||
133 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/twl6040.txt b/Documentation/devicetree/bindings/mfd/twl6040.txt new file mode 100644 index 000000000000..bc67c6f424aa --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/twl6040.txt | |||
@@ -0,0 +1,62 @@ | |||
1 | Texas Instruments TWL6040 family | ||
2 | |||
3 | The TWL6040s are 8-channel high quality low-power audio codecs providing audio | ||
4 | and vibra functionality on OMAP4+ platforms. | ||
5 | They are connected ot the host processor via i2c for commands, McPDM for audio | ||
6 | data and commands. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible : Must be "ti,twl6040"; | ||
10 | - reg: must be 0x4b for i2c address | ||
11 | - interrupts: twl6040 has one interrupt line connecteded to the main SoC | ||
12 | - interrupt-parent: The parent interrupt controller | ||
13 | - twl6040,audpwron-gpio: Power on GPIO line for the twl6040 | ||
14 | |||
15 | - vio-supply: Regulator for the twl6040 VIO supply | ||
16 | - v2v1-supply: Regulator for the twl6040 V2V1 supply | ||
17 | |||
18 | Optional properties, nodes: | ||
19 | - enable-active-high: To power on the twl6040 during boot. | ||
20 | |||
21 | Vibra functionality | ||
22 | Required properties: | ||
23 | - vddvibl-supply: Regulator for the left vibra motor | ||
24 | - vddvibr-supply: Regulator for the right vibra motor | ||
25 | - vibra { }: Configuration section for vibra parameters containing the following | ||
26 | properties: | ||
27 | - ti,vibldrv-res: Resistance parameter for left driver | ||
28 | - ti,vibrdrv-res: Resistance parameter for right driver | ||
29 | - ti,viblmotor-res: Resistance parameter for left motor | ||
30 | - ti,viblmotor-res: Resistance parameter for right motor | ||
31 | |||
32 | Optional properties within vibra { } section: | ||
33 | - vddvibl_uV: If the vddvibl default voltage need to be changed | ||
34 | - vddvibr_uV: If the vddvibr default voltage need to be changed | ||
35 | |||
36 | Example: | ||
37 | &i2c1 { | ||
38 | twl6040: twl@4b { | ||
39 | compatible = "ti,twl6040"; | ||
40 | reg = <0x4b>; | ||
41 | |||
42 | interrupts = <0 119 4>; | ||
43 | interrupt-parent = <&gic>; | ||
44 | twl6040,audpwron-gpio = <&gpio4 31 0>; | ||
45 | |||
46 | vio-supply = <&v1v8>; | ||
47 | v2v1-supply = <&v2v1>; | ||
48 | enable-active-high; | ||
49 | |||
50 | /* regulators for vibra motor */ | ||
51 | vddvibl-supply = <&vbat>; | ||
52 | vddvibr-supply = <&vbat>; | ||
53 | |||
54 | vibra { | ||
55 | /* Vibra driver, motor resistance parameters */ | ||
56 | ti,vibldrv-res = <8>; | ||
57 | ti,vibrdrv-res = <3>; | ||
58 | ti,viblmotor-res = <10>; | ||
59 | ti,vibrmotor-res = <10>; | ||
60 | }; | ||
61 | }; | ||
62 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt index 64bcb8be973c..0d93b4b0e0e3 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt | |||
@@ -11,9 +11,11 @@ Required properties: | |||
11 | - interrupt-parent : interrupt source phandle. | 11 | - interrupt-parent : interrupt source phandle. |
12 | - clock-frequency : specifies eSDHC base clock frequency. | 12 | - clock-frequency : specifies eSDHC base clock frequency. |
13 | - sdhci,wp-inverted : (optional) specifies that eSDHC controller | 13 | - sdhci,wp-inverted : (optional) specifies that eSDHC controller |
14 | reports inverted write-protect state; | 14 | reports inverted write-protect state; New devices should use |
15 | the generic "wp-inverted" property. | ||
15 | - sdhci,1-bit-only : (optional) specifies that a controller can | 16 | - sdhci,1-bit-only : (optional) specifies that a controller can |
16 | only handle 1-bit data transfers. | 17 | only handle 1-bit data transfers. New devices should use the |
18 | generic "bus-width = <1>" property. | ||
17 | - sdhci,auto-cmd12: (optional) specifies that a controller can | 19 | - sdhci,auto-cmd12: (optional) specifies that a controller can |
18 | only handle auto CMD12. | 20 | only handle auto CMD12. |
19 | 21 | ||
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index ab22fe6e73ab..c7e404b3ef05 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | |||
@@ -9,7 +9,7 @@ Required properties: | |||
9 | - interrupts : Should contain eSDHC interrupt | 9 | - interrupts : Should contain eSDHC interrupt |
10 | 10 | ||
11 | Optional properties: | 11 | Optional properties: |
12 | - fsl,card-wired : Indicate the card is wired to host permanently | 12 | - non-removable : Indicate the card is wired to host permanently |
13 | - fsl,cd-internal : Indicate to use controller internal card detection | 13 | - fsl,cd-internal : Indicate to use controller internal card detection |
14 | - fsl,wp-internal : Indicate to use controller internal write protection | 14 | - fsl,wp-internal : Indicate to use controller internal write protection |
15 | - cd-gpios : Specify GPIOs for card detection | 15 | - cd-gpios : Specify GPIOs for card detection |
diff --git a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt index 89a0084df2f7..d64aea5a4203 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt +++ b/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt | |||
@@ -10,7 +10,8 @@ Required properties: | |||
10 | 10 | ||
11 | Optional properties: | 11 | Optional properties: |
12 | - gpios : may specify GPIOs in this order: Card-Detect GPIO, | 12 | - gpios : may specify GPIOs in this order: Card-Detect GPIO, |
13 | Write-Protect GPIO. | 13 | Write-Protect GPIO. Note that this does not follow the |
14 | binding from mmc.txt, for historic reasons. | ||
14 | - interrupts : the interrupt of a card detect interrupt. | 15 | - interrupts : the interrupt of a card detect interrupt. |
15 | - interrupt-parent : the phandle for the interrupt controller that | 16 | - interrupt-parent : the phandle for the interrupt controller that |
16 | services interrupts for this device. | 17 | services interrupts for this device. |
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt new file mode 100644 index 000000000000..6e70dcde0a71 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc.txt | |||
@@ -0,0 +1,27 @@ | |||
1 | These properties are common to multiple MMC host controllers. Any host | ||
2 | that requires the respective functionality should implement them using | ||
3 | these definitions. | ||
4 | |||
5 | Required properties: | ||
6 | - bus-width: Number of data lines, can be <1>, <4>, or <8> | ||
7 | |||
8 | Optional properties: | ||
9 | - cd-gpios : Specify GPIOs for card detection, see gpio binding | ||
10 | - wp-gpios : Specify GPIOs for write protection, see gpio binding | ||
11 | - cd-inverted: when present, polarity on the wp gpio line is inverted | ||
12 | - wp-inverted: when present, polarity on the wp gpio line is inverted | ||
13 | - non-removable: non-removable slot (like eMMC) | ||
14 | - max-frequency: maximum operating clock frequency | ||
15 | |||
16 | Example: | ||
17 | |||
18 | sdhci@ab000000 { | ||
19 | compatible = "sdhci"; | ||
20 | reg = <0xab000000 0x200>; | ||
21 | interrupts = <23>; | ||
22 | bus-width = <4>; | ||
23 | cd-gpios = <&gpio 69 0>; | ||
24 | cd-inverted; | ||
25 | wp-gpios = <&gpio 70 0>; | ||
26 | max-frequency = <50000000>; | ||
27 | } | ||
diff --git a/Documentation/devicetree/bindings/mmc/mmci.txt b/Documentation/devicetree/bindings/mmc/mmci.txt new file mode 100644 index 000000000000..14a81d526118 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmci.txt | |||
@@ -0,0 +1,19 @@ | |||
1 | * ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1 | ||
2 | |||
3 | The ARM PrimeCell MMCI PL180 and PL181 provides and interface for | ||
4 | reading and writing to MultiMedia and SD cards alike. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : contains "arm,pl18x", "arm,primecell". | ||
8 | - reg : contains pl18x registers and length. | ||
9 | - interrupts : contains the device IRQ(s). | ||
10 | - arm,primecell-periphid : contains the PrimeCell Peripheral ID. | ||
11 | |||
12 | Optional properties: | ||
13 | - wp-gpios : contains any write protect (ro) gpios | ||
14 | - cd-gpios : contains any card detection gpios | ||
15 | - cd-inverted : indicates whether the cd gpio is inverted | ||
16 | - max-frequency : contains the maximum operating frequency | ||
17 | - bus-width : number of data lines, can be <1>, <4>, or <8> | ||
18 | - mmc-cap-mmc-highspeed : indicates whether MMC is high speed capable | ||
19 | - mmc-cap-sd-highspeed : indicates whether SD is high speed capable | ||
diff --git a/Documentation/devicetree/bindings/mmc/mxs-mmc.txt b/Documentation/devicetree/bindings/mmc/mxs-mmc.txt new file mode 100644 index 000000000000..14d870a9e3db --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mxs-mmc.txt | |||
@@ -0,0 +1,25 @@ | |||
1 | * Freescale MXS MMC controller | ||
2 | |||
3 | The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller | ||
4 | to support MMC, SD, and SDIO types of memory cards. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: Should be "fsl,<chip>-mmc". The supported chips include | ||
8 | imx23 and imx28. | ||
9 | - reg: Should contain registers location and length | ||
10 | - interrupts: Should contain ERROR and DMA interrupts | ||
11 | - fsl,ssp-dma-channel: APBH DMA channel for the SSP | ||
12 | - bus-width: Number of data lines, can be <1>, <4>, or <8> | ||
13 | |||
14 | Optional properties: | ||
15 | - wp-gpios: Specify GPIOs for write protection | ||
16 | |||
17 | Examples: | ||
18 | |||
19 | ssp0: ssp@80010000 { | ||
20 | compatible = "fsl,imx28-mmc"; | ||
21 | reg = <0x80010000 2000>; | ||
22 | interrupts = <96 82>; | ||
23 | fsl,ssp-dma-channel = <0>; | ||
24 | bus-width = <8>; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt index 7e51154679a6..f77c3031607f 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt | |||
@@ -7,12 +7,12 @@ Required properties: | |||
7 | - compatible : Should be "nvidia,<chip>-sdhci" | 7 | - compatible : Should be "nvidia,<chip>-sdhci" |
8 | - reg : Should contain SD/MMC registers location and length | 8 | - reg : Should contain SD/MMC registers location and length |
9 | - interrupts : Should contain SD/MMC interrupt | 9 | - interrupts : Should contain SD/MMC interrupt |
10 | - bus-width : Number of data lines, can be <1>, <4>, or <8> | ||
10 | 11 | ||
11 | Optional properties: | 12 | Optional properties: |
12 | - cd-gpios : Specify GPIOs for card detection | 13 | - cd-gpios : Specify GPIOs for card detection |
13 | - wp-gpios : Specify GPIOs for write protection | 14 | - wp-gpios : Specify GPIOs for write protection |
14 | - power-gpios : Specify GPIOs for power control | 15 | - power-gpios : Specify GPIOs for power control |
15 | - support-8bit : Boolean, indicates if 8-bit mode should be used. | ||
16 | 16 | ||
17 | Example: | 17 | Example: |
18 | 18 | ||
@@ -23,5 +23,5 @@ sdhci@c8000200 { | |||
23 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ | 23 | cd-gpios = <&gpio 69 0>; /* gpio PI5 */ |
24 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ | 24 | wp-gpios = <&gpio 57 0>; /* gpio PH1 */ |
25 | power-gpios = <&gpio 155 0>; /* gpio PT3 */ | 25 | power-gpios = <&gpio 155 0>; /* gpio PT3 */ |
26 | support-8bit; | 26 | bus-width = <8>; |
27 | }; | 27 | }; |
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt index dbd4368ab8cc..8a53958c9a9f 100644 --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt | |||
@@ -15,7 +15,7 @@ Optional properties: | |||
15 | ti,dual-volt: boolean, supports dual voltage cards | 15 | ti,dual-volt: boolean, supports dual voltage cards |
16 | <supply-name>-supply: phandle to the regulator device tree node | 16 | <supply-name>-supply: phandle to the regulator device tree node |
17 | "supply-name" examples are "vmmc", "vmmc_aux" etc | 17 | "supply-name" examples are "vmmc", "vmmc_aux" etc |
18 | ti,bus-width: Number of data lines, default assumed is 1 if the property is missing. | 18 | bus-width: Number of data lines, default assumed is 1 if the property is missing. |
19 | cd-gpios: GPIOs for card detection | 19 | cd-gpios: GPIOs for card detection |
20 | wp-gpios: GPIOs for write protection | 20 | wp-gpios: GPIOs for write protection |
21 | ti,non-removable: non-removable slot (like eMMC) | 21 | ti,non-removable: non-removable slot (like eMMC) |
@@ -27,7 +27,7 @@ Example: | |||
27 | reg = <0x4809c000 0x400>; | 27 | reg = <0x4809c000 0x400>; |
28 | ti,hwmods = "mmc1"; | 28 | ti,hwmods = "mmc1"; |
29 | ti,dual-volt; | 29 | ti,dual-volt; |
30 | ti,bus-width = <4>; | 30 | bus-width = <4>; |
31 | vmmc-supply = <&vmmc>; /* phandle to regulator node */ | 31 | vmmc-supply = <&vmmc>; /* phandle to regulator node */ |
32 | ti,non-removable; | 32 | ti,non-removable; |
33 | }; | 33 | }; |
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index de439517dff0..7ab9e1a2d8be 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt | |||
@@ -14,7 +14,7 @@ Optional properties: | |||
14 | 14 | ||
15 | Example: | 15 | Example: |
16 | 16 | ||
17 | fec@83fec000 { | 17 | ethernet@83fec000 { |
18 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; | 18 | compatible = "fsl,imx51-fec", "fsl,imx27-fec"; |
19 | reg = <0x83fec000 0x4000>; | 19 | reg = <0x83fec000 0x4000>; |
20 | interrupts = <87>; | 20 | interrupts = <87>; |
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt index 3664d37e6799..b4480d5c3aca 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt | |||
@@ -4,6 +4,8 @@ Required properties: | |||
4 | - compatible : "st,spear300-pinmux" | 4 | - compatible : "st,spear300-pinmux" |
5 | : "st,spear310-pinmux" | 5 | : "st,spear310-pinmux" |
6 | : "st,spear320-pinmux" | 6 | : "st,spear320-pinmux" |
7 | : "st,spear1310-pinmux" | ||
8 | : "st,spear1340-pinmux" | ||
7 | - reg : Address range of the pinctrl registers | 9 | - reg : Address range of the pinctrl registers |
8 | - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others. | 10 | - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others. |
9 | - Its values for SPEAr300: | 11 | - Its values for SPEAr300: |
@@ -89,6 +91,37 @@ For SPEAr320 machines: | |||
89 | "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp", | 91 | "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp", |
90 | "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" | 92 | "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" |
91 | 93 | ||
94 | For SPEAr1310 machines: | ||
95 | "i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp", | ||
96 | "i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp", | ||
97 | "smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp", | ||
98 | "smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp", | ||
99 | "nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp", | ||
100 | "keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp", | ||
101 | "gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp", | ||
102 | "sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp", | ||
103 | "uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp", | ||
104 | "uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp", | ||
105 | "i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp", | ||
106 | "i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp", | ||
107 | "i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp", | ||
108 | "can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp", | ||
109 | "pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp", | ||
110 | "ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp" | ||
111 | |||
112 | For SPEAr1340 machines: | ||
113 | "pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp", | ||
114 | "keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp", | ||
115 | "spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp", | ||
116 | "pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp", | ||
117 | "vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp", | ||
118 | "cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp", | ||
119 | "ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp", | ||
120 | "uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp", | ||
121 | "rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp", | ||
122 | "sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp", | ||
123 | "miphy_dbg_grp", "pcie_grp", "sata_grp" | ||
124 | |||
92 | Valid values for function names are: | 125 | Valid values for function names are: |
93 | For All SPEAr3xx machines: | 126 | For All SPEAr3xx machines: |
94 | "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext", | 127 | "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext", |
@@ -106,3 +139,17 @@ For SPEAr320 machines: | |||
106 | "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen", | 139 | "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen", |
107 | "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2", | 140 | "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2", |
108 | "mii0_1", "i2c1", "i2c2" | 141 | "mii0_1", "i2c1", "i2c2" |
142 | |||
143 | |||
144 | For SPEAr1310 machines: | ||
145 | "i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii", | ||
146 | "rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0", | ||
147 | "gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3", | ||
148 | "uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1", | ||
149 | "i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64" | ||
150 | |||
151 | For SPEAr1340 machines: | ||
152 | "pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1", | ||
153 | "pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0", | ||
154 | "uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf", | ||
155 | "xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata" | ||
diff --git a/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt b/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt new file mode 100644 index 000000000000..a87a1e9bc060 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/lpc32xx-rtc.txt | |||
@@ -0,0 +1,15 @@ | |||
1 | * NXP LPC32xx SoC Real Time Clock controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "nxp,lpc3220-rtc" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: The RTC interrupt | ||
8 | |||
9 | Example: | ||
10 | |||
11 | rtc@40024000 { | ||
12 | compatible = "nxp,lpc3220-rtc"; | ||
13 | reg = <0x40024000 0x1000>; | ||
14 | interrupts = <52 0>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/spear-rtc.txt b/Documentation/devicetree/bindings/rtc/spear-rtc.txt new file mode 100644 index 000000000000..ca67ac62108e --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/spear-rtc.txt | |||
@@ -0,0 +1,17 @@ | |||
1 | * SPEAr RTC | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "st,spear600-rtc" | ||
5 | - reg : Address range of the rtc registers | ||
6 | - interrupt-parent: Should be the phandle for the interrupt controller | ||
7 | that services interrupts for this device | ||
8 | - interrupt: Should contain the rtc interrupt number | ||
9 | |||
10 | Example: | ||
11 | |||
12 | rtc@fc000000 { | ||
13 | compatible = "st,spear600-rtc"; | ||
14 | reg = <0xfc000000 0x1000>; | ||
15 | interrupt-parent = <&vic1>; | ||
16 | interrupts = <12>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/omap-dmic.txt b/Documentation/devicetree/bindings/sound/omap-dmic.txt new file mode 100644 index 000000000000..fd8105f18978 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/omap-dmic.txt | |||
@@ -0,0 +1,21 @@ | |||
1 | * Texas Instruments OMAP4+ Digital Microphone Module | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,omap4-dmic" | ||
5 | - reg: Register location and size as an array: | ||
6 | <MPU access base address, size>, | ||
7 | <L3 interconnect address, size>; | ||
8 | - interrupts: Interrupt number for DMIC | ||
9 | - interrupt-parent: The parent interrupt controller | ||
10 | - ti,hwmods: Name of the hwmod associated with OMAP dmic IP | ||
11 | |||
12 | Example: | ||
13 | |||
14 | dmic: dmic@4012e000 { | ||
15 | compatible = "ti,omap4-dmic"; | ||
16 | reg = <0x4012e000 0x7f>, /* MPU private access */ | ||
17 | <0x4902e000 0x7f>; /* L3 Interconnect */ | ||
18 | interrupts = <0 114 0x4>; | ||
19 | interrupt-parent = <&gic>; | ||
20 | ti,hwmods = "dmic"; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/omap-mcpdm.txt b/Documentation/devicetree/bindings/sound/omap-mcpdm.txt new file mode 100644 index 000000000000..0741dff048dd --- /dev/null +++ b/Documentation/devicetree/bindings/sound/omap-mcpdm.txt | |||
@@ -0,0 +1,21 @@ | |||
1 | * Texas Instruments OMAP4+ McPDM | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "ti,omap4-mcpdm" | ||
5 | - reg: Register location and size as an array: | ||
6 | <MPU access base address, size>, | ||
7 | <L3 interconnect address, size>; | ||
8 | - interrupts: Interrupt number for McPDM | ||
9 | - interrupt-parent: The parent interrupt controller | ||
10 | - ti,hwmods: Name of the hwmod associated to the McPDM | ||
11 | |||
12 | Example: | ||
13 | |||
14 | mcpdm: mcpdm@40132000 { | ||
15 | compatible = "ti,omap4-mcpdm"; | ||
16 | reg = <0x40132000 0x7f>, /* MPU private access */ | ||
17 | <0x49032000 0x7f>; /* L3 Interconnect */ | ||
18 | interrupts = <0 112 0x4>; | ||
19 | interrupt-parent = <&gic>; | ||
20 | ti,hwmods = "mcpdm"; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt index a9c0406280e8..b462d0c54823 100644 --- a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt +++ b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt | |||
@@ -11,7 +11,7 @@ Optional properties: | |||
11 | 11 | ||
12 | Example: | 12 | Example: |
13 | 13 | ||
14 | uart@73fbc000 { | 14 | serial@73fbc000 { |
15 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; | 15 | compatible = "fsl,imx51-uart", "fsl,imx21-uart"; |
16 | reg = <0x73fbc000 0x4000>; | 16 | reg = <0x73fbc000 0x4000>; |
17 | interrupts = <31>; | 17 | interrupts = <31>; |
diff --git a/Documentation/devicetree/bindings/usb/tegra-usb.txt b/Documentation/devicetree/bindings/usb/tegra-usb.txt index 007005ddbe12..e9b005dc7625 100644 --- a/Documentation/devicetree/bindings/usb/tegra-usb.txt +++ b/Documentation/devicetree/bindings/usb/tegra-usb.txt | |||
@@ -12,6 +12,9 @@ Required properties : | |||
12 | - nvidia,vbus-gpio : If present, specifies a gpio that needs to be | 12 | - nvidia,vbus-gpio : If present, specifies a gpio that needs to be |
13 | activated for the bus to be powered. | 13 | activated for the bus to be powered. |
14 | 14 | ||
15 | Required properties for phy_type == ulpi: | ||
16 | - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. | ||
17 | |||
15 | Optional properties: | 18 | Optional properties: |
16 | - dr_mode : dual role mode. Indicates the working mode for | 19 | - dr_mode : dual role mode. Indicates the working mode for |
17 | nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", | 20 | nvidia,tegra20-ehci compatible controllers. Can be "host", "peripheral", |