Merge branch 'timers/clockevents' of git://git.linaro.org/people/dlezcano/clockevents into timers/urgent

* New clocksource drivers for ARM SoCs to share

2 files changed, 41 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/arm/global_timer.txt b/Documentation/devicetree/bindings/arm/global_timer.txt
new file mode 100644
index 000000000000..1e548981eda4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/global_timer.txt
@@ -0,0 +1,24 @@
+
+* ARM Global Timer
+        Cortex-A9 are often associated with a per-core Global timer.
+
+** Timer node required properties:
+
+- compatible : Should be "arm,cortex-a9-global-timer"
+                Driver supports versions r2p0 and above.
+
+- interrupts : One interrupt to each core
+
+- reg : Specify the base address and the size of the GT timer
+        register window.
+
+- clocks : Should be phandle to a clock.
+
+Example:
+
+        timer@2c000600 {
+                compatible = "arm,cortex-a9-global-timer";
+                reg = <0x2c000600 0x20>;
+                interrupts = <1 13 0xf01>;
+                clocks = <&arm_periph_clk>;
+        };
diff --git a/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt b/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt
new file mode 100644
index 000000000000..62bb8260cf6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/marvell,orion-timer.txt
@@ -0,0 +1,17 @@
+Marvell Orion SoC timer
+
+Required properties:
+- compatible: shall be "marvell,orion-timer"
+- reg: base address of the timer register starting with TIMERS CONTROL register
+- interrupt-parent: phandle of the bridge interrupt controller
+- interrupts: should contain the interrupts for Timer0 and Timer1
+- clocks: phandle of timer reference clock (tclk)
+
+Example:
+        timer: timer {
+                compatible = "marvell,orion-timer";
+                reg = <0x20300 0x20>;
+                interrupt-parent = <&bridge_intc>;
+                interrupts = <1>, <2>;
+                clocks = <&core_clk 0>;
+        };