diff options
author | Mike Turquette <mturquette@linaro.org> | 2014-05-13 19:04:19 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2014-05-13 19:04:19 -0400 |
commit | 8a5f93faa56b09fed0a7cfbd7a20b7d75d169b27 (patch) | |
tree | 146425de40ccfbcce9152ff8c3d8f6a9489681b4 /Documentation/devicetree | |
parent | 5483bf698f42a6f0467463b064084eb888298232 (diff) | |
parent | 66ecbfea762ad28bd108db76775483b491068b92 (diff) |
Merge tag 'clk-mvebu-3.16' of git://git.infradead.org/linux-mvebu into clk-next-mvebu
clk mvebu changes for v3.16
- orion5x: brand new driver
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/clock/mvebu-core-clock.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt index 307a503c5db8..dc5ea5b22da9 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt | |||
@@ -29,6 +29,11 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove: | |||
29 | 2 = l2clk (L2 Cache clock derived from CPU0 clock) | 29 | 2 = l2clk (L2 Cache clock derived from CPU0 clock) |
30 | 3 = ddrclk (DDR controller clock derived from CPU0 clock) | 30 | 3 = ddrclk (DDR controller clock derived from CPU0 clock) |
31 | 31 | ||
32 | The following is a list of provided IDs and clock names on Orion5x: | ||
33 | 0 = tclk (Internal Bus clock) | ||
34 | 1 = cpuclk (CPU0 clock) | ||
35 | 2 = ddrclk (DDR controller clock derived from CPU0 clock) | ||
36 | |||
32 | Required properties: | 37 | Required properties: |
33 | - compatible : shall be one of the following: | 38 | - compatible : shall be one of the following: |
34 | "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks | 39 | "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks |
@@ -38,6 +43,9 @@ Required properties: | |||
38 | "marvell,dove-core-clock" - for Dove SoC core clocks | 43 | "marvell,dove-core-clock" - for Dove SoC core clocks |
39 | "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) | 44 | "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180) |
40 | "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC | 45 | "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC |
46 | "marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC | ||
47 | "marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC | ||
48 | "marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC | ||
41 | - reg : shall be the register address of the Sample-At-Reset (SAR) register | 49 | - reg : shall be the register address of the Sample-At-Reset (SAR) register |
42 | - #clock-cells : from common clock binding; shall be set to 1 | 50 | - #clock-cells : from common clock binding; shall be set to 1 |
43 | 51 | ||