diff options
author | Mike Turquette <mturquette@linaro.org> | 2014-06-10 19:53:25 -0400 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2014-06-10 19:53:25 -0400 |
commit | 3f6eec9969d24f91a3909d51e86e007ca5efd4c4 (patch) | |
tree | bff0f51bab78b18d52cfd57ad7cd8b78ac6a882c /Documentation/devicetree | |
parent | 963649d735c8b6eb0f97e82c54f02426ff3f1f45 (diff) | |
parent | 7e148070001ae82df08966199580a29b934e3bf3 (diff) |
Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into clk-next
Diffstat (limited to 'Documentation/devicetree')
5 files changed, 152 insertions, 9 deletions
diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt index 7faf5a68b3be..ade4dd4c30f0 100644 --- a/Documentation/devicetree/bindings/clock/ti/apll.txt +++ b/Documentation/devicetree/bindings/clock/ti/apll.txt | |||
@@ -14,18 +14,32 @@ a subtype of a DPLL [2], although a simplified one at that. | |||
14 | [2] Documentation/devicetree/bindings/clock/ti/dpll.txt | 14 | [2] Documentation/devicetree/bindings/clock/ti/dpll.txt |
15 | 15 | ||
16 | Required properties: | 16 | Required properties: |
17 | - compatible : shall be "ti,dra7-apll-clock" | 17 | - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock" |
18 | - #clock-cells : from common clock binding; shall be set to 0. | 18 | - #clock-cells : from common clock binding; shall be set to 0. |
19 | - clocks : link phandles of parent clocks (clk-ref and clk-bypass) | 19 | - clocks : link phandles of parent clocks (clk-ref and clk-bypass) |
20 | - reg : address and length of the register set for controlling the APLL. | 20 | - reg : address and length of the register set for controlling the APLL. |
21 | It contains the information of registers in the following order: | 21 | It contains the information of registers in the following order: |
22 | "control" - contains the control register base address | 22 | "control" - contains the control register offset |
23 | "idlest" - contains the idlest register base address | 23 | "idlest" - contains the idlest register offset |
24 | "autoidle" - contains the autoidle register offset (OMAP2 only) | ||
25 | - ti,clock-frequency : static clock frequency for the clock (OMAP2 only) | ||
26 | - ti,idlest-shift : bit-shift for the idlest field (OMAP2 only) | ||
27 | - ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only) | ||
24 | 28 | ||
25 | Examples: | 29 | Examples: |
26 | apll_pcie_ck: apll_pcie_ck@4a008200 { | 30 | apll_pcie_ck: apll_pcie_ck { |
27 | #clock-cells = <0>; | 31 | #clock-cells = <0>; |
28 | clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; | 32 | clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; |
29 | reg = <0x4a00821c 0x4>, <0x4a008220 0x4>; | 33 | reg = <0x021c>, <0x0220>; |
30 | compatible = "ti,dra7-apll-clock"; | 34 | compatible = "ti,dra7-apll-clock"; |
31 | }; | 35 | }; |
36 | |||
37 | apll96_ck: apll96_ck { | ||
38 | #clock-cells = <0>; | ||
39 | compatible = "ti,omap2-apll-clock"; | ||
40 | clocks = <&sys_ck>; | ||
41 | ti,bit-shift = <2>; | ||
42 | ti,idlest-shift = <8>; | ||
43 | ti,clock-frequency = <96000000>; | ||
44 | reg = <0x0500>, <0x0530>, <0x0520>; | ||
45 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt index 30bfdb7c9f18..df57009ff8e7 100644 --- a/Documentation/devicetree/bindings/clock/ti/dpll.txt +++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt | |||
@@ -24,12 +24,14 @@ Required properties: | |||
24 | "ti,omap4-dpll-core-clock", | 24 | "ti,omap4-dpll-core-clock", |
25 | "ti,omap4-dpll-m4xen-clock", | 25 | "ti,omap4-dpll-m4xen-clock", |
26 | "ti,omap4-dpll-j-type-clock", | 26 | "ti,omap4-dpll-j-type-clock", |
27 | "ti,omap5-mpu-dpll-clock", | ||
27 | "ti,am3-dpll-no-gate-clock", | 28 | "ti,am3-dpll-no-gate-clock", |
28 | "ti,am3-dpll-j-type-clock", | 29 | "ti,am3-dpll-j-type-clock", |
29 | "ti,am3-dpll-no-gate-j-type-clock", | 30 | "ti,am3-dpll-no-gate-j-type-clock", |
30 | "ti,am3-dpll-clock", | 31 | "ti,am3-dpll-clock", |
31 | "ti,am3-dpll-core-clock", | 32 | "ti,am3-dpll-core-clock", |
32 | "ti,am3-dpll-x2-clock", | 33 | "ti,am3-dpll-x2-clock", |
34 | "ti,omap2-dpll-core-clock", | ||
33 | 35 | ||
34 | - #clock-cells : from common clock binding; shall be set to 0. | 36 | - #clock-cells : from common clock binding; shall be set to 0. |
35 | - clocks : link phandles of parent clocks, first entry lists reference clock | 37 | - clocks : link phandles of parent clocks, first entry lists reference clock |
@@ -41,6 +43,7 @@ Required properties: | |||
41 | "mult-div1" - contains the multiplier / divider register base address | 43 | "mult-div1" - contains the multiplier / divider register base address |
42 | "autoidle" - contains the autoidle register base address (optional) | 44 | "autoidle" - contains the autoidle register base address (optional) |
43 | ti,am3-* dpll types do not have autoidle register | 45 | ti,am3-* dpll types do not have autoidle register |
46 | ti,omap2-* dpll type does not support idlest / autoidle registers | ||
44 | 47 | ||
45 | Optional properties: | 48 | Optional properties: |
46 | - DPLL mode setting - defining any one or more of the following overrides | 49 | - DPLL mode setting - defining any one or more of the following overrides |
@@ -73,3 +76,10 @@ Examples: | |||
73 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; | 76 | clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; |
74 | reg = <0x90>, <0x5c>, <0x68>; | 77 | reg = <0x90>, <0x5c>, <0x68>; |
75 | }; | 78 | }; |
79 | |||
80 | dpll_ck: dpll_ck { | ||
81 | #clock-cells = <0>; | ||
82 | compatible = "ti,omap2-dpll-core-clock"; | ||
83 | clocks = <&sys_ck>, <&sys_ck>; | ||
84 | reg = <0x0500>, <0x0540>; | ||
85 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt b/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt new file mode 100644 index 000000000000..585e8c191f50 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/dra7-atl.txt | |||
@@ -0,0 +1,96 @@ | |||
1 | Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC. | ||
2 | |||
3 | The ATL IP is used to generate clock to be used to synchronize baseband and | ||
4 | audio codec. A single ATL IP provides four ATL clock instances sharing the same | ||
5 | functional clock but can be configured to provide different clocks. | ||
6 | ATL can maintain a clock averages to some desired frequency based on the bws/aws | ||
7 | signals - can compensate the drift between the two ws signal. | ||
8 | |||
9 | In order to provide the support for ATL and it's output clocks (which can be used | ||
10 | internally within the SoC or external components) two sets of bindings is needed: | ||
11 | |||
12 | Clock tree binding: | ||
13 | This binding uses the common clock binding[1]. | ||
14 | To be able to integrate the ATL clocks with DT clock tree. | ||
15 | Provides ccf level representation of the ATL clocks to be used by drivers. | ||
16 | Since the clock instances are part of a single IP this binding is used as a node | ||
17 | for the DT clock tree, the IP driver is needed to handle the actual configuration | ||
18 | of the IP. | ||
19 | |||
20 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
21 | |||
22 | Required properties: | ||
23 | - compatible : shall be "ti,dra7-atl-clock" | ||
24 | - #clock-cells : from common clock binding; shall be set to 0. | ||
25 | - clocks : link phandles to functional clock of ATL | ||
26 | |||
27 | Binding for the IP driver: | ||
28 | This binding is used to configure the IP driver which is going to handle the | ||
29 | configuration of the IP for the ATL clock instances. | ||
30 | |||
31 | Required properties: | ||
32 | - compatible : shall be "ti,dra7-atl" | ||
33 | - reg : base address for the ATL IP | ||
34 | - ti,provided-clocks : List of phandles to the clocks associated with the ATL | ||
35 | - clocks : link phandles to functional clock of ATL | ||
36 | - clock-names : Shall be set to "fck" | ||
37 | - ti,hwmods : Shall be set to "atl" | ||
38 | |||
39 | Optional properties: | ||
40 | Configuration of ATL instances: | ||
41 | - atl{0/1/2/3} { | ||
42 | - bws : Baseband word select signal selection | ||
43 | - aws : Audio word select signal selection | ||
44 | }; | ||
45 | |||
46 | For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include | ||
47 | file. | ||
48 | |||
49 | Examples: | ||
50 | /* clock bindings for atl provided clocks */ | ||
51 | atl_clkin0_ck: atl_clkin0_ck { | ||
52 | #clock-cells = <0>; | ||
53 | compatible = "ti,dra7-atl-clock"; | ||
54 | clocks = <&atl_gfclk_mux>; | ||
55 | }; | ||
56 | |||
57 | atl_clkin1_ck: atl_clkin1_ck { | ||
58 | #clock-cells = <0>; | ||
59 | compatible = "ti,dra7-atl-clock"; | ||
60 | clocks = <&atl_gfclk_mux>; | ||
61 | }; | ||
62 | |||
63 | atl_clkin2_ck: atl_clkin2_ck { | ||
64 | #clock-cells = <0>; | ||
65 | compatible = "ti,dra7-atl-clock"; | ||
66 | clocks = <&atl_gfclk_mux>; | ||
67 | }; | ||
68 | |||
69 | atl_clkin3_ck: atl_clkin3_ck { | ||
70 | #clock-cells = <0>; | ||
71 | compatible = "ti,dra7-atl-clock"; | ||
72 | clocks = <&atl_gfclk_mux>; | ||
73 | }; | ||
74 | |||
75 | /* binding for the IP */ | ||
76 | atl: atl@4843c000 { | ||
77 | compatible = "ti,dra7-atl"; | ||
78 | reg = <0x4843c000 0x3ff>; | ||
79 | ti,hwmods = "atl"; | ||
80 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, | ||
81 | <&atl_clkin2_ck>, <&atl_clkin3_ck>; | ||
82 | clocks = <&atl_gfclk_mux>; | ||
83 | clock-names = "fck"; | ||
84 | status = "disabled"; | ||
85 | }; | ||
86 | |||
87 | #include <dt-bindings/clk/ti-dra7-atl.h> | ||
88 | |||
89 | &atl { | ||
90 | status = "okay"; | ||
91 | |||
92 | atl2 { | ||
93 | bws = <DRA7_ATL_WS_MCASP2_FSX>; | ||
94 | aws = <DRA7_ATL_WS_MCASP3_FSX>; | ||
95 | }; | ||
96 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/ti/gate.txt b/Documentation/devicetree/bindings/clock/ti/gate.txt index 125281aaa4ca..03f8fdee62a7 100644 --- a/Documentation/devicetree/bindings/clock/ti/gate.txt +++ b/Documentation/devicetree/bindings/clock/ti/gate.txt | |||
@@ -25,6 +25,11 @@ Required properties: | |||
25 | to map clockdomains properly | 25 | to map clockdomains properly |
26 | "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling, | 26 | "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling, |
27 | required for a hardware errata | 27 | required for a hardware errata |
28 | "ti,composite-gate-clock" - composite gate clock, to be part of composite | ||
29 | clock | ||
30 | "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait | ||
31 | for clock to be active before returning | ||
32 | from clk_enable() | ||
28 | - #clock-cells : from common clock binding; shall be set to 0 | 33 | - #clock-cells : from common clock binding; shall be set to 0 |
29 | - clocks : link to phandle of parent clock | 34 | - clocks : link to phandle of parent clock |
30 | - reg : offset for register controlling adjustable gate, not needed for | 35 | - reg : offset for register controlling adjustable gate, not needed for |
@@ -41,7 +46,7 @@ Examples: | |||
41 | #clock-cells = <0>; | 46 | #clock-cells = <0>; |
42 | compatible = "ti,gate-clock"; | 47 | compatible = "ti,gate-clock"; |
43 | clocks = <&core_96m_fck>; | 48 | clocks = <&core_96m_fck>; |
44 | reg = <0x48004a00 0x4>; | 49 | reg = <0x0a00>; |
45 | ti,bit-shift = <25>; | 50 | ti,bit-shift = <25>; |
46 | }; | 51 | }; |
47 | 52 | ||
@@ -57,7 +62,7 @@ Examples: | |||
57 | #clock-cells = <0>; | 62 | #clock-cells = <0>; |
58 | compatible = "ti,dss-gate-clock"; | 63 | compatible = "ti,dss-gate-clock"; |
59 | clocks = <&dpll4_m4x2_ck>; | 64 | clocks = <&dpll4_m4x2_ck>; |
60 | reg = <0x48004e00 0x4>; | 65 | reg = <0x0e00>; |
61 | ti,bit-shift = <0>; | 66 | ti,bit-shift = <0>; |
62 | }; | 67 | }; |
63 | 68 | ||
@@ -65,7 +70,7 @@ Examples: | |||
65 | #clock-cells = <0>; | 70 | #clock-cells = <0>; |
66 | compatible = "ti,am35xx-gate-clock"; | 71 | compatible = "ti,am35xx-gate-clock"; |
67 | clocks = <&ipss_ick>; | 72 | clocks = <&ipss_ick>; |
68 | reg = <0x4800259c 0x4>; | 73 | reg = <0x059c>; |
69 | ti,bit-shift = <1>; | 74 | ti,bit-shift = <1>; |
70 | }; | 75 | }; |
71 | 76 | ||
@@ -80,6 +85,22 @@ Examples: | |||
80 | compatible = "ti,hsdiv-gate-clock"; | 85 | compatible = "ti,hsdiv-gate-clock"; |
81 | clocks = <&dpll4_m2x2_mul_ck>; | 86 | clocks = <&dpll4_m2x2_mul_ck>; |
82 | ti,bit-shift = <0x1b>; | 87 | ti,bit-shift = <0x1b>; |
83 | reg = <0x48004d00 0x4>; | 88 | reg = <0x0d00>; |
84 | ti,set-bit-to-disable; | 89 | ti,set-bit-to-disable; |
85 | }; | 90 | }; |
91 | |||
92 | vlynq_gate_fck: vlynq_gate_fck { | ||
93 | #clock-cells = <0>; | ||
94 | compatible = "ti,composite-gate-clock"; | ||
95 | clocks = <&core_ck>; | ||
96 | ti,bit-shift = <3>; | ||
97 | reg = <0x0200>; | ||
98 | }; | ||
99 | |||
100 | sys_clkout2_src_gate: sys_clkout2_src_gate { | ||
101 | #clock-cells = <0>; | ||
102 | compatible = "ti,composite-no-wait-gate-clock"; | ||
103 | clocks = <&core_ck>; | ||
104 | ti,bit-shift = <15>; | ||
105 | reg = <0x0070>; | ||
106 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/ti/interface.txt b/Documentation/devicetree/bindings/clock/ti/interface.txt index 064e8caccac3..3111a409fea6 100644 --- a/Documentation/devicetree/bindings/clock/ti/interface.txt +++ b/Documentation/devicetree/bindings/clock/ti/interface.txt | |||
@@ -21,6 +21,8 @@ Required properties: | |||
21 | "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling | 21 | "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling |
22 | "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling | 22 | "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling |
23 | "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling | 23 | "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling |
24 | "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW | ||
25 | handling | ||
24 | - #clock-cells : from common clock binding; shall be set to 0 | 26 | - #clock-cells : from common clock binding; shall be set to 0 |
25 | - clocks : link to phandle of parent clock | 27 | - clocks : link to phandle of parent clock |
26 | - reg : base address for the control register | 28 | - reg : base address for the control register |