diff options
author | Chen-Yu Tsai <wens@csie.org> | 2014-10-20 10:10:28 -0400 |
---|---|---|
committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-10-21 15:47:34 -0400 |
commit | 0b0f08028e4e2d69edbe4bb073af26cd17505a04 (patch) | |
tree | 17aef4828848ef4c2e971e4482db5367664f2211 /Documentation/devicetree | |
parent | 3b2bd70f03c75d37de791b65d574a31d1e2507b0 (diff) |
clk: sunxi: Add support for bus clock gates on Allwinner A80 SoC
This adds the gate clocks for AHB/APB busses on the A80 SoC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/clock/sunxi.txt | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 7f1c486691e0..0455cb9caa97 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt | |||
@@ -29,6 +29,9 @@ Required properties: | |||
29 | "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 | 29 | "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 |
30 | "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 | 30 | "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 |
31 | "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 | 31 | "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 |
32 | "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 | ||
33 | "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80 | ||
34 | "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80 | ||
32 | "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock | 35 | "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock |
33 | "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 | 36 | "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 |
34 | "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 | 37 | "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 |
@@ -39,6 +42,7 @@ Required properties: | |||
39 | "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 | 42 | "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 |
40 | "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 | 43 | "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 |
41 | "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 | 44 | "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 |
45 | "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 | ||
42 | "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock | 46 | "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock |
43 | "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 | 47 | "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 |
44 | "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing | 48 | "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing |
@@ -48,6 +52,7 @@ Required properties: | |||
48 | "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 | 52 | "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 |
49 | "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 | 53 | "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 |
50 | "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 | 54 | "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 |
55 | "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 | ||
51 | "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31 | 56 | "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31 |
52 | "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 | 57 | "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 |
53 | "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 | 58 | "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 |