diff options
author | Arnd Bergmann <arnd@arndb.de> | 2011-11-01 21:46:10 -0400 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2011-11-01 21:46:10 -0400 |
commit | 884897e6a10a86de0e611a76f4bf3fd0068a672c (patch) | |
tree | 019689fb9d129404af1efba4df10975bc9e0a57a /Documentation/devicetree | |
parent | c72dbae971400e466ad9ff16c920cd6d9d8c55a1 (diff) | |
parent | 8b61f37440388ebbd2a894178fe098f2e70ab392 (diff) |
Merge branch 'highbank/soc' into next/soc
Conflicts:
arch/arm/mach-mxs/include/mach/gpio.h
arch/arm/mach-omap2/board-generic.c
arch/arm/plat-mxc/include/mach/gpio.h
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/arm/calxeda.txt | 8 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/arm/l2cc.txt | 44 |
2 files changed, 52 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt new file mode 100644 index 000000000000..4755caaccba6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/calxeda.txt | |||
@@ -0,0 +1,8 @@ | |||
1 | Calxeda Highbank Platforms Device Tree Bindings | ||
2 | ----------------------------------------------- | ||
3 | |||
4 | Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following | ||
5 | properties. | ||
6 | |||
7 | Required root node properties: | ||
8 | - compatible = "calxeda,highbank"; | ||
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt new file mode 100644 index 000000000000..7ca52161e7ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/l2cc.txt | |||
@@ -0,0 +1,44 @@ | |||
1 | * ARM L2 Cache Controller | ||
2 | |||
3 | ARM cores often have a separate level 2 cache controller. There are various | ||
4 | implementations of the L2 cache controller with compatible programming models. | ||
5 | The ARM L2 cache representation in the device tree should be done as follows: | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible : should be one of: | ||
10 | "arm,pl310-cache" | ||
11 | "arm,l220-cache" | ||
12 | "arm,l210-cache" | ||
13 | - cache-unified : Specifies the cache is a unified cache. | ||
14 | - cache-level : Should be set to 2 for a level 2 cache. | ||
15 | - reg : Physical base address and size of cache controller's memory mapped | ||
16 | registers. | ||
17 | |||
18 | Optional properties: | ||
19 | |||
20 | - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of | ||
21 | read, write and setup latencies. Minimum valid values are 1. Controllers | ||
22 | without setup latency control should use a value of 0. | ||
23 | - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of | ||
24 | read, write and setup latencies. Controllers without setup latency control | ||
25 | should use 0. Controllers without separate read and write Tag RAM latency | ||
26 | values should only use the first cell. | ||
27 | - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. | ||
28 | - arm,filter-ranges : <start length> Starting address and length of window to | ||
29 | filter. Addresses in the filter window are directed to the M1 port. Other | ||
30 | addresses will go to the M0 port. | ||
31 | - interrupts : 1 combined interrupt. | ||
32 | |||
33 | Example: | ||
34 | |||
35 | L2: cache-controller { | ||
36 | compatible = "arm,pl310-cache"; | ||
37 | reg = <0xfff12000 0x1000>; | ||
38 | arm,data-latency = <1 1 1>; | ||
39 | arm,tag-latency = <2 2 2>; | ||
40 | arm,filter-latency = <0x80000000 0x8000000>; | ||
41 | cache-unified; | ||
42 | cache-level = <2>; | ||
43 | interrupts = <45>; | ||
44 | }; | ||