Merge tag 'usb-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Pull USB updates from Greg KH:
 "Here's the big set of USB and PHY patches for 3.19-rc1.

  The normal churn in the USB gadget area is in here, as well as xhci
  and other individual USB driver updates.  The PHY tree is also in
  here, as there were dependancies on the USB tree.

  All of these have been in linux-next"

* tag 'usb-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (351 commits)
  arm: omap3: twl: remove usb phy init data
  usbip: fix error handling in stub_probe()
  usb: gadget: udc: missing curly braces
  USB: mos7720: delete some unneeded code
  wusb: replace memset by memzero_explicit
  usbip: remove unneeded structure
  usb: xhci: fix comment for PORT_DEV_REMOVE
  xhci: don't use the same variable for stopped and halted rings current TD
  xhci: clear extra bits from slot context when setting max exit latency
  xhci: cleanup finish_td function
  USB: adutux: NULL dereferences on disconnect
  usb: chipidea: fix platform_no_drv_owner.cocci warnings
  usb: chipidea: Fixed a few typos in comments
  Documentation: bindings: add doc for the USB2 ChipIdea USB driver
  usb: chipidea: add a usb2 driver for ci13xxx
  usb: chipidea: fix phy handling
  usb: chipidea: remove duplicate dev_set_drvdata for host_start
  usb: chipidea: parameter 'mode' isn't needed for hw_device_reset
  usb: chipidea: add controller reset API
  usb: chipidea: remove flag CI_HDRC_REQUIRE_TRANSCEIVER
  ...

11 files changed, 277 insertions, 3 deletions

diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt
index 1c8351604d38..b460edd12766 100644
--- a/Documentation/devicetree/bindings/ata/marvell.txt
+++ b/Documentation/devicetree/bindings/ata/marvell.txt
@@ -6,11 +6,17 @@ Required Properties:
 - interrupts    : Interrupt controller is using
 - nr-ports      : Number of SATA ports in use.
 
+Optional Properties:
+- phys          : List of phandles to sata phys
+- phy-names     : Should be "0", "1", etc, one number per phandle
+
 Example:
 
         sata@80000 {
                 compatible = "marvell,orion-sata";
                 reg = <0x80000 0x5000>;
                 interrupts = <21>;
+                phys = <&sata_phy0>, <&sata_phy1>;
+                phy-names = "0", "1";
                 nr-ports = <2>;
         }
diff --git a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
index 88f8c23384c0..c0155f842f62 100644
--- a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
+++ b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
@@ -2,7 +2,9 @@ Berlin SATA PHY
 ---------------
 
 Required properties:
-- compatible: should be "marvell,berlin2q-sata-phy"
+- compatible: should be one of
+    "marvell,berlin2-sata-phy"
+    "marvell,berlin2q-sata-phy"
 - address-cells: should be 1
 - size-cells: should be 0
 - phy-cells: from the generic PHY bindings, must be 1
diff --git a/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
new file mode 100644
index 000000000000..be33780f668e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
@@ -0,0 +1,16 @@
+* Marvell Berlin USB PHY
+
+Required properties:
+- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"
+- reg: base address and length of the registers
+- #phys-cells: should be 0
+- resets: reference to the reset controller
+
+Example:
+
+        usb-phy@f774000 {
+                compatible = "marvell,berlin2-usb-phy";
+                reg = <0xf774000 0x128>;
+                #phy-cells = <0>;
+                resets = <&chip 0x104 14>;
+        };
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
new file mode 100644
index 000000000000..46a135dae6b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -0,0 +1,128 @@
+STMicroelectronics STi MIPHY28LP PHY binding
+============================================
+
+This binding describes a miphy device that is used to control PHY hardware
+for SATA, PCIe or USB3.
+
+Required properties (controller (parent) node):
+- compatible    : Should be "st,miphy28lp-phy".
+- st,syscfg     : Should be a phandle of the system configuration register group
+                  which contain the SATA, PCIe or USB3 mode setting bits.
+
+Required nodes  :  A sub-node is required for each channel the controller
+                   provides. Address range information including the usual
+                   'reg' and 'reg-names' properties are used inside these
+                   nodes to describe the controller's topology. These nodes
+                   are translated by the driver's .xlate() function.
+
+Required properties (port (child) node):
+- #phy-cells    : Should be 1 (See second example)
+                  Cell after port phandle is device type from:
+                        - PHY_TYPE_SATA
+                        - PHY_TYPE_PCI
+                        - PHY_TYPE_USB3
+- reg           : Address and length of the register set for the device.
+- reg-names     : The names of the register addresses corresponding to the registers
+                  filled in "reg". It can also contain the offset of the system configuration
+                  registers used as glue-logic to setup the device for SATA/PCIe or USB3
+                  devices.
+- resets        : phandle to the parent reset controller.
+- reset-names   : Associated name must be "miphy-sw-rst".
+
+Optional properties (port (child) node):
+- st,osc-rdy            : to check the MIPHY0_OSC_RDY status in the glue-logic. This
+                          is not available in all the MiPHY. For example, for STiH407, only the
+                          MiPHY0 has this bit.
+- st,osc-force-ext      : to select the external oscillator. This can change from
+                          different MiPHY inside the same SoC.
+- st,sata_gen           : to select which SATA_SPDMODE has to be set in the SATA system config
+                          register.
+- st,px_rx_pol_inv      : to invert polarity of RXn/RXp (respectively negative line and positive
+                          line).
+- st,scc-on             : enable ssc to reduce effects of EMI (only for sata or PCIe).
+- st,tx-impedance-comp  : to compensate tx impedance avoiding out of range values.
+
+example:
+
+                miphy28lp_phy: miphy28lp@9b22000 {
+                        compatible = "st,miphy28lp-phy";
+                        st,syscfg = <&syscfg_core>;
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        ranges;
+
+                        phy_port0: port@9b22000 {
+                                reg = <0x9b22000 0xff>,
+                                      <0x9b09000 0xff>,
+                                      <0x9b04000 0xff>,
+                                      <0x114 0x4>, /* sysctrl MiPHY cntrl */
+                                      <0x818 0x4>, /* sysctrl MiPHY status*/
+                                      <0xe0  0x4>, /* sysctrl PCIe */
+                                      <0xec  0x4>; /* sysctrl SATA */
+                                reg-names = "sata-up",
+                                            "pcie-up",
+                                            "pipew",
+                                            "miphy-ctrl-glue",
+                                            "miphy-status-glue",
+                                            "pcie-glue",
+                                            "sata-glue";
+                                #phy-cells = <1>;
+                                st,osc-rdy;
+                                reset-names = "miphy-sw-rst";
+                                resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
+                        };
+
+                        phy_port1: port@9b2a000 {
+                                reg = <0x9b2a000 0xff>,
+                                      <0x9b19000 0xff>,
+                                      <0x9b14000 0xff>,
+                                      <0x118 0x4>,
+                                      <0x81c 0x4>,
+                                      <0xe4  0x4>,
+                                      <0xf0  0x4>;
+                                reg-names = "sata-up",
+                                            "pcie-up",
+                                            "pipew",
+                                            "miphy-ctrl-glue",
+                                            "miphy-status-glue",
+                                            "pcie-glue",
+                                            "sata-glue";
+                                #phy-cells = <1>;
+                                st,osc-force-ext;
+                                reset-names = "miphy-sw-rst";
+                                resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
+                        };
+
+                        phy_port2: port@8f95000 {
+                                reg = <0x8f95000 0xff>,
+                                      <0x8f90000 0xff>,
+                                      <0x11c 0x4>,
+                                      <0x820 0x4>;
+                                reg-names = "pipew",
+                                    "usb3-up",
+                                    "miphy-ctrl-glue",
+                                    "miphy-status-glue";
+                                #phy-cells = <1>;
+                                reset-names = "miphy-sw-rst";
+                                resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
+                        };
+                };
+
+
+Specifying phy control of devices
+=================================
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the miphy device node and an index
+specifying which configuration to use, as described in phy-bindings.txt.
+
+example:
+                sata0: sata@9b20000  {
+                        ...
+                        phys            = <&phy_port0 PHY_TYPE_SATA>;
+                        ...
+                };
+
+Macro definitions for the supported miphy configuration can be found in:
+
+include/dt-bindings/phy/phy-miphy28lp.h
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu.txt b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
new file mode 100644
index 000000000000..f95b6260a3b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
@@ -0,0 +1,43 @@
+* Marvell MVEBU SATA PHY
+
+Power control for the SATA phy found on Marvell MVEBU SoCs.
+
+This document extends the binding described in phy-bindings.txt
+
+Required properties :
+
+ - reg             : Offset and length of the register set for the SATA device
+ - compatible      : Should be "marvell,mvebu-sata-phy"
+ - clocks          : phandle of clock and specifier that supplies the device
+ - clock-names     : Should be "sata"
+
+Example:
+                sata-phy@84000 {
+                        compatible = "marvell,mvebu-sata-phy";
+                        reg = <0x84000 0x0334>;
+                        clocks = <&gate_clk 15>;
+                        clock-names = "sata";
+                        #phy-cells = <0>;
+                        status = "ok";
+                };
+
+Armada 375 USB cluster
+----------------------
+
+Armada 375 comes with an USB2 host and device controller and an USB3
+controller. The USB cluster control register allows to manage common
+features of both USB controllers.
+
+Required properties:
+
+- compatible: "marvell,armada-375-usb-cluster"
+- reg: Should contain usb cluster register location and length.
+- #phy-cells : from the generic phy bindings, must be 1. Possible
+values are 1 (USB2), 2 (USB3).
+
+Example:
+                usbcluster: usb-cluster@18400 {
+                        compatible = "marvell,armada-375-usb-cluster";
+                        reg = <0x18400 0x4>;
+                        #phy-cells = <1>
+                };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 15e0f2c7130f..d5bad920827f 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -128,6 +128,7 @@ Required properties:
 - compatible : Should be set to one of the following supported values:
         - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
         - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
+        - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
 - reg : Register offset and length of USB DRD PHY register set;
 - clocks: Clock IDs array as required by the controller
 - clock-names: names of clocks correseponding to IDs in the clock property;
@@ -138,6 +139,11 @@ Required properties:
                PHY operations, associated by phy name. It is used to
                determine bit values for clock settings register.
                For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
+        - optional clocks: Exynos7 SoC has now following additional
+                           gate clocks available:
+                           - phy_pipe: for PIPE3 phy
+                           - phy_utmi: for UTMI+ phy
+                           - itp: for ITP generation
 - samsung,pmu-syscon: phandle for PMU system controller interface, used to
                       control pmu registers for power isolation.
 - #phy-cells : from the generic PHY bindings, must be 1;
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
new file mode 100644
index 000000000000..27f8b1e5ee46
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
@@ -0,0 +1,24 @@
+* USB2 ChipIdea USB controller for ci13xxx
+
+Required properties:
+- compatible: should be "chipidea,usb2"
+- reg: base address and length of the registers
+- interrupts: interrupt for the USB controller
+
+Optional properties:
+- clocks: reference to the USB clock
+- phys: reference to the USB PHY
+- phy-names: should be "usb-phy"
+- vbus-supply: reference to the VBUS regulator
+
+Example:
+
+        usb@f7ed0000 {
+                compatible = "chipidea,usb2";
+                reg = <0xf7ed0000 0x10000>;
+                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&chip CLKID_USB0>;
+                phys = <&usb_phy0>;
+                phy-names = "usb-phy";
+                vbus-supply = <&reg_usb0_vbus>;
+        };
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 471366d6a129..cd7f0454e13a 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -14,6 +14,29 @@ Optional properties:
  - phys: from the *Generic PHY* bindings
  - phy-names: from the *Generic PHY* bindings
  - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
+ - snps,disable_scramble_quirk: true when SW should disable data scrambling.
+        Only really useful for FPGA builds.
+ - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
+ - snps,lpm-nyet-threshold: LPM NYET threshold
+ - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
+ - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
+ - snps,req_p1p2p3_quirk: when set, the core will always request for
+                        P1/P2/P3 transition sequence.
+ - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain
+                        amount of 8B10B errors occur.
+ - snps,del_phy_power_chg_quirk: when set core will delay PHY power change
+                        from P0 to P1/P2/P3.
+ - snps,lfps_filter_quirk: when set core will filter LFPS reception.
+ - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start
+                        Polling LFPS after RX.Detect.
+ - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value.
+ - snps,tx_de_emphasis: the value driven to the PHY is controlled by the
+                        LTSSM during USB3 Compliance mode.
+ - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
+ - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
+ - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
+                        utmi_l1_suspend_n, false when asserts utmi_sleep_n
+ - snps,hird-threshold: HIRD threshold
 
 This is usually a subnode to DWC3 glue to which it is connected.
 
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index a3b5990d0f2c..9b4dbe3b2acc 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -82,8 +82,10 @@ Example:
 
 DWC3
 Required properties:
- - compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3
-               controller.
+ - compatible: should be one of the following -
+               "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
+                                            Exynos5250/5420.
+               "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
  - #address-cells, #size-cells : should be '1' if the device has sub-nodes
                                  with 'reg' property.
  - ranges: allows valid 1:1 translation between child's address space and
diff --git a/Documentation/devicetree/bindings/usb/pxa-usb.txt b/Documentation/devicetree/bindings/usb/pxa-usb.txt
index 79729a948d5a..9c331799b87c 100644
--- a/Documentation/devicetree/bindings/usb/pxa-usb.txt
+++ b/Documentation/devicetree/bindings/usb/pxa-usb.txt
@@ -29,3 +29,25 @@ Example:
                 marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */
         };
 
+UDC
+
+Required properties:
+ - compatible: Should be "marvell,pxa270-udc" for USB controllers
+   used in device mode.
+ - reg: usb device MMIO address space
+ - interrupts: single interrupt generated by the UDC IP
+ - clocks: input clock of the UDC IP (see clock-bindings.txt)
+
+Optional properties:
+ - gpios:
+   - gpio activated to control the USB D+ pullup (see gpio.txt)
+
+Example:
+
+                pxa27x_udc: udc@40600000 {
+                        compatible = "marvell,pxa270-udc";
+                        reg = <0x40600000 0x10000>;
+                        interrupts = <11>;
+                        clocks = <&pxa2xx_clks 11>;
+                        gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+                };
diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt
index b968a1aea995..19233b7365e1 100644
--- a/Documentation/devicetree/bindings/usb/usb-ohci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt
@@ -9,6 +9,8 @@ Optional properties:
 - big-endian-regs : boolean, set this for hcds with big-endian registers
 - big-endian-desc : boolean, set this for hcds with big-endian descriptors
 - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
+- no-big-frame-no : boolean, set if frame_no lives in bits [15:0] of HCCA
+- num-ports : u32, to override the detected port count
 - clocks : a list of phandle + clock specifier pairs
 - phys : phandle + phy specifier pair
 - phy-names : "usb"