clk: sunxi: Add driver for A80 MMC config clocks/resets

On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.

This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

1 files changed, 24 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 0dfd018ba47b..60b44285250d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -57,6 +57,7 @@ Required properties:
         "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
         "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
         "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
+        "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
         "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
         "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
         "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
@@ -75,7 +76,8 @@ Required properties for all clocks:
         the following compatibles where it shall be set to 1:
         "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
         "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
-        "allwinner,*-usb-clk", "allwinner,*-mmc-clk"
+        "allwinner,*-usb-clk", "allwinner,*-mmc-clk",
+        "allwinner,*-mmc-config-clk"
 - clock-output-names : shall be the corresponding names of the outputs.
         If the clock module only has one output, the name shall be the
         module name.
@@ -83,6 +85,10 @@ Required properties for all clocks:
 And "allwinner,*-usb-clk" clocks also require:
 - reset-cells : shall be set to 1
 
+The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
+- #reset-cells : shall be set to 1
+- resets : shall be the reset control phandle for the mmc block.
+
 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
 dummy clocks at 25 MHz and 125 MHz, respectively. See example.
 
@@ -101,6 +107,10 @@ The "allwinner,*-mmc-clk" clocks have three different outputs: the
 main clock, with the ID 0, and the output and sample clocks, with the
 IDs 1 and 2, respectively.
 
+The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
+per mmc controller. The number of outputs is determined by the size of
+the address block, which is related to the overall mmc block.
+
 For example:
 
 osc24M: clk@01c20050 {
@@ -176,3 +186,16 @@ gmac_clk: clk@01c20164 {
         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
         clock-output-names = "gmac";
 };
+
+mmc_config_clk: clk@01c13000 {
+        compatible = "allwinner,sun9i-a80-mmc-config-clk";
+        reg = <0x01c13000 0x10>;
+        clocks = <&ahb0_gates 8>;
+        clock-names = "ahb";
+        resets = <&ahb0_resets 8>;
+        reset-names = "ahb";
+        #clock-cells = <1>;
+        #reset-cells = <1>;
+        clock-output-names = "mmc0_config", "mmc1_config",
+                             "mmc2_config", "mmc3_config";
+};