Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (106 commits)
  powerpc/p3060qds: Add support for P3060QDS board
  powerpc/83xx: Add shutdown request support to MCU handling on MPC8349 MITX
  powerpc/85xx: Make kexec to interate over online cpus
  powerpc/fsl_booke: Fix comment in head_fsl_booke.S
  powerpc/85xx: issue 15 EOI after core reset for FSL CoreNet devices
  powerpc/8xxx: Fix interrupt handling in MPC8xxx GPIO driver
  powerpc/85xx: Add 'fsl,pq3-gpio' compatiable for GPIO driver
  powerpc/86xx: Correct Gianfar support for GE boards
  powerpc/cpm: Clear muram before it is in use.
  drivers/virt: add ioctl for 32-bit compat on 64-bit to fsl-hv-manager
  powerpc/fsl_msi: add support for "msi-address-64" property
  powerpc/85xx: Setup secondary cores PIR with hard SMP id
  powerpc/fsl-booke: Fix settlbcam for 64-bit
  powerpc/85xx: Adding DCSR node to dtsi device trees
  powerpc/85xx: clean up FPGA device tree nodes for Freecsale QorIQ boards
  powerpc/85xx: fix PHYS_64BIT selection for P1022DS
  powerpc/fsl-booke: Fix setup_initial_memory_limit to not blindly map
  powerpc: respect mem= setting for early memory limit setup
  powerpc: Update corenet64_smp_defconfig
  powerpc: Update mpc85xx/corenet 32-bit defconfigs
  ...

Fix up trivial conflicts in:
 - arch/powerpc/configs/40x/hcu4_defconfig
	removed stale file, edited elsewhere
 - arch/powerpc/include/asm/udbg.h, arch/powerpc/kernel/udbg.c:
	added opal and gelic drivers vs added ePAPR driver
 - drivers/tty/serial/8250.c
	moved UPIO_TSI to powerpc vs removed UPIO_DWAPB support

3 files changed, 455 insertions, 12 deletions

diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
index 39e941515a36..380914e965e0 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
@@ -1,3 +1,8 @@
+Freescale Reference Board Bindings
+
+This document describes device tree bindings for various devices that
+exist on some Freescale reference boards.
+
 * Board Control and Status (BCSR)
 
 Required properties:
@@ -12,25 +17,26 @@ Example:
                 reg = <f8000000 8000>;
         };
 
-* Freescale on board FPGA
+* Freescale on-board FPGA
 
 This is the memory-mapped registers for on board FPGA.
 
 Required properities:
-- compatible : should be "fsl,fpga-pixis".
-- reg : should contain the address and the length of the FPPGA register
-  set.
+- compatible: should be a board-specific string followed by a string
+  indicating the type of FPGA.  Example:
+        "fsl,<board>-fpga", "fsl,fpga-pixis"
+- reg: should contain the address and the length of the FPGA register set.
 - interrupt-parent: should specify phandle for the interrupt controller.
-- interrupts : should specify event (wakeup) IRQ.
+- interrupts: should specify event (wakeup) IRQ.
 
-Example (MPC8610HPCD):
+Example (P1022DS):
 
-        board-control@e8000000 {
-                compatible = "fsl,fpga-pixis";
-                reg = <0xe8000000 32>;
-                interrupt-parent = <&mpic>;
-                interrupts = <8 8>;
-        };
+         board-control@3,0 {
+                 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
+                 reg = <3 0 0x30>;
+                 interrupt-parent = <&mpic>;
+                 interrupts = <8 8 0 0>;
+         };
 
 * Freescale BCSR GPIO banks
 
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt b/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
new file mode 100644
index 000000000000..9d54eb5a295f
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
@@ -0,0 +1,395 @@
+===================================================================
+Debug Control and Status Register (DCSR) Binding
+Copyright 2011 Freescale Semiconductor Inc.
+
+NOTE: The bindings described in this document are preliminary and subject
+to change.  Some of the compatible strings that contain only generic names
+may turn out to be inappropriate, or need additional properties to describe
+the integration of the block with the rest of the chip.
+
+=====================================================================
+Debug Control and Status Register Memory Map
+
+Description
+
+This node defines the base address and range for the
+defined DCSR Memory Map. Child nodes will describe the individual
+debug blocks defined within this memory space.
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr" and "simple-bus".
+        The DCSR space exists in the memory-mapped bus.
+
+        - #address-cells
+        Usage: required
+        Value type: <u32>
+        Definition: A standard property.  Defines the number of cells
+        or representing physical addresses in child nodes.
+
+        - #size-cells
+        Usage: required
+        Value type: <u32>
+        Definition: A standard property.  Defines the number of cells
+        or representing the size of physical addresses in
+        child nodes.
+
+        - ranges
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property. Specifies the physical address
+        range of the DCSR space.
+
+EXAMPLE
+        dcsr: dcsr@f00000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,dcsr", "simple-bus";
+                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
+        };
+
+=====================================================================
+Event Processing Unit
+
+This node represents the region of DCSR space allocated to the EPU
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr-epu"
+
+        - interrupts
+        Usage: required
+        Value type: <prop_encoded-array>
+        Definition:  Specifies the interrupts generated by the EPU.
+        The value of the interrupts property consists of three
+        interrupt specifiers. The format of the specifier is defined
+        by the binding document describing the node's interrupt parent.
+
+        The EPU counters can be configured to assert the performance
+        monitor interrupt signal based on either counter overflow or value
+        match. Which counter asserted the interrupt is captured in an EPU
+        Counter Interrupt Status Register (EPCPUISR).
+
+        The EPU unit can also be configured to assert either or both of
+        two interrupt signals based on debug event sources within the SoC.
+        The interrupt signals are epu_xt_int0 and epu_xt_int1.
+        Which event source asserted the interrupt is captured in an EPU
+        Interrupt Status Register (EPISR0,EPISR1).
+
+        Interrupt numbers are lised in order (perfmon, event0, event1).
+
+        - interrupt-parent
+        Usage: required
+        Value type: <phandle>
+        Definition: A single <phandle> value that points
+        to the interrupt parent to which the child domain
+        is being mapped. Value must be "&mpic"
+
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+
+EXAMPLE
+        dcsr-epu@0 {
+                compatible = "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0>;
+                interrupt-parent = <&mpic>;
+                reg = <0x0 0x1000>;
+        };
+
+=======================================================================
+Nexus Port Controller
+
+This node represents the region of DCSR space allocated to the NPC
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr-npc"
+
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+        The Nexus Port controller occupies two regions in the DCSR space
+        with distinct functionality.
+
+        The first register range describes the Nexus Port Controller
+        control and status registers.
+
+        The second register range describes the Nexus Port Controller
+        internal trace buffer. The NPC trace buffer is a small memory buffer
+        which stages the nexus trace data for transmission via the Aurora port
+        or to a DDR based trace buffer. In some configurations the NPC trace
+        buffer can be the only trace buffer used.
+
+
+EXAMPLE
+                dcsr-npc {
+                        compatible = "fsl,dcsr-npc";
+                        reg = <0x1000 0x1000 0x1000000 0x8000>;
+                };
+
+=======================================================================
+Nexus Concentrator
+
+This node represents the region of DCSR space allocated to the NXC
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr-nxc"
+
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+
+EXAMPLE
+                dcsr-nxc@2000 {
+                        compatible = "fsl,dcsr-nxc";
+                        reg = <0x2000 0x1000>;
+                };
+=======================================================================
+CoreNet Debug Controller
+
+This node represents the region of DCSR space allocated to
+the CoreNet Debug controller.
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr-corenet"
+
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+        The CoreNet Debug controller occupies two regions in the DCSR space
+        with distinct functionality.
+
+        The first register range describes the CoreNet Debug Controller
+        functionalty to perform transaction and transaction attribute matches.
+
+        The second register range describes the CoreNet Debug Controller
+        functionalty to trigger event notifications and debug traces.
+
+EXAMPLE
+                dcsr-corenet {
+                        compatible = "fsl,dcsr-corenet";
+                        reg = <0x8000 0x1000 0xB0000 0x1000>;
+                };
+
+=======================================================================
+Data Path Debug controller
+
+This node represents the region of DCSR space allocated to
+the DPAA Debug Controller. This controller controls debug configuration
+for the QMAN and FMAN blocks.
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include both an identifier specific to the SoC
+        or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
+        generic compatible string "fsl,dcsr-dpaa".
+
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+
+EXAMPLE
+                dcsr-dpaa@9000 {
+                        compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
+                        reg = <0x9000 0x1000>;
+                };
+
+=======================================================================
+OCeaN Debug controller
+
+This node represents the region of DCSR space allocated to
+the OCN Debug Controller.
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include both an identifier specific to the SoC
+        or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
+        generic compatible string "fsl,dcsr-ocn".
+
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+
+EXAMPLE
+                dcsr-ocn@11000 {
+                        compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
+                        reg = <0x11000 0x1000>;
+                };
+
+=======================================================================
+DDR Controller Debug controller
+
+This node represents the region of DCSR space allocated to
+the OCN Debug Controller.
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr-ddr"
+
+        - dev-handle
+        Usage: required
+        Definition: A phandle to associate this debug node with its
+        component controller.
+
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+
+EXAMPLE
+                dcsr-ddr@12000 {
+                        compatible = "fsl,dcsr-ddr";
+                        dev-handle = <&ddr1>;
+                        reg = <0x12000 0x1000>;
+                };
+
+=======================================================================
+Nexus Aurora Link Controller
+
+This node represents the region of DCSR space allocated to
+the NAL Controller.
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include both an identifier specific to the SoC
+        or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
+        generic compatible string "fsl,dcsr-nal".
+
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+
+EXAMPLE
+                dcsr-nal@18000 {
+                        compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
+                        reg = <0x18000 0x1000>;
+                };
+
+
+=======================================================================
+Run Control and Power Management
+
+This node represents the region of DCSR space allocated to
+the RCPM Debug Controller. This functionlity is limited to the
+control the debug operations of the SoC and cores.
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include both an identifier specific to the SoC
+        or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
+        generic compatible string "fsl,dcsr-rcpm".
+
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+
+EXAMPLE
+                dcsr-rcpm@22000 {
+                        compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
+                        reg = <0x22000 0x1000>;
+                };
+
+=======================================================================
+Core Service Bridge Proxy
+
+This node represents the region of DCSR space allocated to
+the Core Service Bridge Proxies.
+There is one Core Service Bridge Proxy device for each CPU in the system.
+This functionlity provides access to the debug operations of the CPU.
+
+PROPERTIES
+
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include both an identifier specific to the cpu
+        of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
+        generic compatible string "fsl,dcsr-cpu-sb-proxy".
+
+        - cpu-handle
+        Usage: required
+        Definition: A phandle to associate this debug node with its cpu.
+
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+
+EXAMPLE
+                dcsr-cpu-sb-proxy@40000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy",
+                                     "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu0>;
+                        reg = <0x40000 0x1000>;
+                };
+                dcsr-cpu-sb-proxy@41000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy",
+                                     "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu1>;
+                        reg = <0x41000 0x1000>;
+                };
+
+=======================================================================
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 70558c3f3682..5d586e1ccaf5 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -25,6 +25,16 @@ Required properties:
   are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
   to MPIC.
 
+Optional properties:
+- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
+  is used for MSI messaging.  The address of MSIIR in PCI address space is
+  the MSI message address.
+
+  This property may be used in virtualized environments where the hypervisor
+  has created an alternate mapping for the MSIR block.  See below for an
+  explanation.
+
+
 Example:
         msi@41600 {
                 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
@@ -41,3 +51,35 @@ Example:
                         0xe7 0>;
                 interrupt-parent = <&mpic>;
         };
+
+The Freescale hypervisor and msi-address-64
+-------------------------------------------
+Normally, PCI devices have access to all of CCSR via an ATMU mapping.  The
+Freescale MSI driver calculates the address of MSIIR (in the MSI register
+block) and sets that address as the MSI message address.
+
+In a virtualized environment, the hypervisor may need to create an IOMMU
+mapping for MSIIR.  The Freescale ePAPR hypervisor has this requirement
+because of hardware limitations of the Peripheral Access Management Unit
+(PAMU), which is currently the only IOMMU that the hypervisor supports.
+The ATMU is programmed with the guest physical address, and the PAMU
+intercepts transactions and reroutes them to the true physical address.
+
+In the PAMU, each PCI controller is given only one primary window.  The
+PAMU restricts DMA operations so that they can only occur within a window.
+Because PCI devices must be able to DMA to memory, the primary window must
+be used to cover all of the guest's memory space.
+
+PAMU primary windows can be divided into 256 subwindows, and each
+subwindow can have its own address mapping ("guest physical" to "true
+physical").  However, each subwindow has to have the same alignment, which
+means they cannot be located at just any address.  Because of these
+restrictions, it is usually impossible to create a 4KB subwindow that
+covers MSIIR where it's normally located.
+
+Therefore, the hypervisor has to create a subwindow inside the same
+primary window used for memory, but mapped to the MSIR block (where MSIIR
+lives).  The first subwindow after the end of guest memory is used for
+this.  The address specified in the msi-address-64 property is the PCI
+address of MSIIR.  The hypervisor configures the PAMU to map that address to
+the true physical address of MSIIR.