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authorMark Brown <broonie@kernel.org>2015-02-09 02:10:02 -0500
committerMark Brown <broonie@kernel.org>2015-02-09 02:10:02 -0500
commit103004749235915190b81108f6bf4dbf53f220b9 (patch)
treed15f43ad6a9ecb7e4815e86d4aceef671d1d1df7 /Documentation/devicetree/bindings
parent1d03ab06d7337497f369350ec6f22a7172d30a2c (diff)
parent9c7da1a57bb5938f1d874c8cd5e50d2494830d08 (diff)
Merge remote-tracking branch 'asoc/topic/pcm512x' into asoc-next
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r--Documentation/devicetree/bindings/sound/pcm512x.txt25
1 files changed, 23 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/sound/pcm512x.txt b/Documentation/devicetree/bindings/sound/pcm512x.txt
index 98e0d34915e8..3aae3b41bd8e 100644
--- a/Documentation/devicetree/bindings/sound/pcm512x.txt
+++ b/Documentation/devicetree/bindings/sound/pcm512x.txt
@@ -17,9 +17,16 @@ Required properties:
17Optional properties: 17Optional properties:
18 18
19 - clocks : A clock specifier for the clock connected as SCLK. If this 19 - clocks : A clock specifier for the clock connected as SCLK. If this
20 is absent the device will be configured to clock from BCLK. 20 is absent the device will be configured to clock from BCLK. If pll-in
21 and pll-out are specified in addition to a clock, the device is
22 configured to accept clock input on a specified gpio pin.
21 23
22Example: 24 - pll-in, pll-out : gpio pins used to connect the pll using <1>
25 through <6>. The device will be configured for clock input on the
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
28
29Examples:
23 30
24 pcm5122: pcm5122@4c { 31 pcm5122: pcm5122@4c {
25 compatible = "ti,pcm5122"; 32 compatible = "ti,pcm5122";
@@ -29,3 +36,17 @@ Example:
29 DVDD-supply = <&reg_1v8>; 36 DVDD-supply = <&reg_1v8>;
30 CPVDD-supply = <&reg_3v3>; 37 CPVDD-supply = <&reg_3v3>;
31 }; 38 };
39
40
41 pcm5142: pcm5142@4c {
42 compatible = "ti,pcm5142";
43 reg = <0x4c>;
44
45 AVDD-supply = <&reg_3v3_analog>;
46 DVDD-supply = <&reg_1v8>;
47 CPVDD-supply = <&reg_3v3>;
48
49 clocks = <&sck>;
50 pll-in = <3>;
51 pll-out = <6>;
52 };