diff options
| author | Soren Brinkmann <soren.brinkmann@xilinx.com> | 2014-04-04 20:23:44 -0400 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2014-07-18 05:54:24 -0400 |
| commit | db34d2b32fa5edaf15f8aee6680be3722161d27a (patch) | |
| tree | 900fcd8ffcd85dace6ae6bc454f88ca94f8cd1d1 /Documentation/devicetree/bindings/serial | |
| parent | 1795cd9b3a91d4b5473c97f491d63892442212ab (diff) | |
tty: cadence: Document DT binding
Add binding documentation for the Cadence UART.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'Documentation/devicetree/bindings/serial')
| -rw-r--r-- | Documentation/devicetree/bindings/serial/cdns,uart.txt | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.txt b/Documentation/devicetree/bindings/serial/cdns,uart.txt new file mode 100644 index 000000000000..a3eb154c32ca --- /dev/null +++ b/Documentation/devicetree/bindings/serial/cdns,uart.txt | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | Binding for Cadence UART Controller | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible : should be "cdns,uart-r1p8", or "xlnx,xuartps" | ||
| 5 | - reg: Should contain UART controller registers location and length. | ||
| 6 | - interrupts: Should contain UART controller interrupts. | ||
| 7 | - clocks: Must contain phandles to the UART clocks | ||
| 8 | See ../clocks/clock-bindings.txt for details. | ||
| 9 | - clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk" | ||
| 10 | See ../clocks/clock-bindings.txt for details. | ||
| 11 | |||
| 12 | |||
| 13 | Example: | ||
| 14 | uart@e0000000 { | ||
| 15 | compatible = "cdns,uart-r1p8"; | ||
| 16 | clocks = <&clkc 23>, <&clkc 40>; | ||
| 17 | clock-names = "uart_clk", "pclk"; | ||
| 18 | reg = <0xE0000000 0x1000>; | ||
| 19 | interrupts = <0 27 4>; | ||
| 20 | }; | ||
