diff options
author | Thomas Abraham <thomas.ab@samsung.com> | 2012-09-17 14:16:43 -0400 |
---|---|---|
committer | Chris Ball <cjb@laptop.org> | 2012-10-03 10:05:20 -0400 |
commit | c3665006eccd7d2326b7dc2c1d5ff2f545dee6c5 (patch) | |
tree | 9bee54383377917f9999d3d7ed0bef58d8c51d08 /Documentation/devicetree/bindings/mmc | |
parent | 800d78bfccb3d38116abfda2a5b9c8afdbd5ea21 (diff) |
mmc: dw_mmc: add support for exynos specific implementation of dw-mshc
Samsung Exynos SoC's extend the dw-mshc controller for additional clock
and bus control. Add support for these extensions and include provide
device tree based discovery suppory as well.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Will Newton <will.newton@imgtec.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mmc')
-rw-r--r-- | Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt new file mode 100644 index 000000000000..792768953330 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | |||
@@ -0,0 +1,87 @@ | |||
1 | * Samsung Exynos specific extensions to the Synopsis Designware Mobile | ||
2 | Storage Host Controller | ||
3 | |||
4 | The Synopsis designware mobile storage host controller is used to interface | ||
5 | a SoC with storage medium such as eMMC or SD/MMC cards. This file documents | ||
6 | differences between the core Synopsis dw mshc controller properties described | ||
7 | by synposis-dw-mshc.txt and the properties used by the Samsung Exynos specific | ||
8 | extensions to the Synopsis Designware Mobile Storage Host Controller. | ||
9 | |||
10 | Required Properties: | ||
11 | |||
12 | * compatible: should be | ||
13 | - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210 | ||
14 | specific extentions. | ||
15 | - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412 | ||
16 | specific extentions. | ||
17 | - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 | ||
18 | specific extentions. | ||
19 | |||
20 | * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface | ||
21 | unit (ciu) clock. This property is applicable only for Exynos5 SoC's and | ||
22 | ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. | ||
23 | |||
24 | * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value | ||
25 | in transmit mode and CIU clock phase shift value in receive mode for single | ||
26 | data rate mode operation. Refer notes below for the order of the cells and the | ||
27 | valid values. | ||
28 | |||
29 | * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value | ||
30 | in transmit mode and CIU clock phase shift value in receive mode for double | ||
31 | data rate mode operation. Refer notes below for the order of the cells and the | ||
32 | valid values. | ||
33 | |||
34 | Notes for the sdr-timing and ddr-timing values: | ||
35 | |||
36 | The order of the cells should be | ||
37 | - First Cell: CIU clock phase shift value for tx mode. | ||
38 | - Second Cell: CIU clock phase shift value for rx mode. | ||
39 | |||
40 | Valid values for SDR and DDR CIU clock timing for Exynos5250: | ||
41 | - valid value for tx phase shift and rx phase shift is 0 to 7. | ||
42 | - when CIU clock divider value is set to 3, all possible 8 phase shift | ||
43 | values can be used. | ||
44 | - if CIU clock divider value is 0 (that is divide by 1), both tx and rx | ||
45 | phase shift clocks should be 0. | ||
46 | |||
47 | Required properties for a slot: | ||
48 | |||
49 | * gpios: specifies a list of gpios used for command, clock and data bus. The | ||
50 | first gpio is the command line and the second gpio is the clock line. The | ||
51 | rest of the gpios (depending on the bus-width property) are the data lines in | ||
52 | no particular order. The format of the gpio specifier depends on the gpio | ||
53 | controller. | ||
54 | |||
55 | Example: | ||
56 | |||
57 | The MSHC controller node can be split into two portions, SoC specific and | ||
58 | board specific portions as listed below. | ||
59 | |||
60 | dwmmc0@12200000 { | ||
61 | compatible = "samsung,exynos5250-dw-mshc"; | ||
62 | reg = <0x12200000 0x1000>; | ||
63 | interrupts = <0 75 0>; | ||
64 | #address-cells = <1>; | ||
65 | #size-cells = <0>; | ||
66 | }; | ||
67 | |||
68 | dwmmc0@12200000 { | ||
69 | num-slots = <1>; | ||
70 | supports-highspeed; | ||
71 | broken-cd; | ||
72 | fifo-depth = <0x80>; | ||
73 | card-detect-delay = <200>; | ||
74 | samsung,dw-mshc-ciu-div = <3>; | ||
75 | samsung,dw-mshc-sdr-timing = <2 3>; | ||
76 | samsung,dw-mshc-ddr-timing = <1 2>; | ||
77 | |||
78 | slot@0 { | ||
79 | reg = <0>; | ||
80 | bus-width = <8>; | ||
81 | gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>, | ||
82 | <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>, | ||
83 | <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>, | ||
84 | <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>, | ||
85 | <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>; | ||
86 | }; | ||
87 | }; | ||