diff options
author | Cho KyongHo <pullip.cho@samsung.com> | 2014-05-12 02:15:01 -0400 |
---|---|---|
committer | Joerg Roedel <jroedel@suse.de> | 2014-05-13 13:12:59 -0400 |
commit | 93e268dca82eafb59157bfb7eb70e97fe3564412 (patch) | |
tree | a85e7ef61b4c6f2dcc9e3f8a96230746017bdb61 /Documentation/devicetree/bindings/iommu | |
parent | 0bf4e54dbebff8aa4b69057e88431ba8b48d3d19 (diff) |
documentation: iommu: Add binding document of Exynos System MMU
This patch adds a description of the device tree binding for the
Samsung Exynos System MMU.
Signed-off-by: Cho KyongHo <pullip.cho@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'Documentation/devicetree/bindings/iommu')
-rw-r--r-- | Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt new file mode 100644 index 000000000000..15b2a2baa22a --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt | |||
@@ -0,0 +1,65 @@ | |||
1 | Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) | ||
2 | |||
3 | Samsung's Exynos architecture contains System MMUs that enables scattered | ||
4 | physical memory chunks visible as a contiguous region to DMA-capable peripheral | ||
5 | devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. | ||
6 | |||
7 | System MMU is an IOMMU and supports identical translation table format to | ||
8 | ARMv7 translation tables with minimum set of page properties including access | ||
9 | permissions, shareability and security protection. In addition, System MMU has | ||
10 | another capabilities like L2 TLB or block-fetch buffers to minimize translation | ||
11 | latency. | ||
12 | |||
13 | System MMUs are in many to one relation with peripheral devices, i.e. single | ||
14 | peripheral device might have multiple System MMUs (usually one for each bus | ||
15 | master), but one System MMU can handle transactions from only one peripheral | ||
16 | device. The relation between a System MMU and the peripheral device needs to be | ||
17 | defined in device node of the peripheral device. | ||
18 | |||
19 | MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System | ||
20 | MMUs. | ||
21 | * MFC has one System MMU on its left and right bus. | ||
22 | * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU | ||
23 | for window 1, 2 and 3. | ||
24 | * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and | ||
25 | the other System MMU on the write channel. | ||
26 | The drivers must consider how to handle those System MMUs. One of the idea is | ||
27 | to implement child devices or sub-devices which are the client devices of the | ||
28 | System MMU. | ||
29 | |||
30 | Required properties: | ||
31 | - compatible: Should be "samsung,exynos-sysmmu" | ||
32 | - reg: A tuple of base address and size of System MMU registers. | ||
33 | - interrupt-parent: The phandle of the interrupt controller of System MMU | ||
34 | - interrupts: An interrupt specifier for interrupt signal of System MMU, | ||
35 | according to the format defined by a particular interrupt | ||
36 | controller. | ||
37 | - clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock. | ||
38 | Optional "master" if the clock to the System MMU is gated by | ||
39 | another gate clock other than "sysmmu". | ||
40 | Exynos4 SoCs, there needs no "master" clock. | ||
41 | Exynos5 SoCs, some System MMUs must have "master" clocks. | ||
42 | - clocks: Required if the System MMU is needed to gate its clock. | ||
43 | - samsung,power-domain: Required if the System MMU is needed to gate its power. | ||
44 | Please refer to the following document: | ||
45 | Documentation/devicetree/bindings/arm/exynos/power_domain.txt | ||
46 | |||
47 | Examples: | ||
48 | gsc_0: gsc@13e00000 { | ||
49 | compatible = "samsung,exynos5-gsc"; | ||
50 | reg = <0x13e00000 0x1000>; | ||
51 | interrupts = <0 85 0>; | ||
52 | samsung,power-domain = <&pd_gsc>; | ||
53 | clocks = <&clock CLK_GSCL0>; | ||
54 | clock-names = "gscl"; | ||
55 | }; | ||
56 | |||
57 | sysmmu_gsc0: sysmmu@13E80000 { | ||
58 | compatible = "samsung,exynos-sysmmu"; | ||
59 | reg = <0x13E80000 0x1000>; | ||
60 | interrupt-parent = <&combiner>; | ||
61 | interrupts = <2 0>; | ||
62 | clock-names = "sysmmu", "master"; | ||
63 | clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>; | ||
64 | samsung,power-domain = <&pd_gsc>; | ||
65 | }; | ||