diff options
author | Philipp Zabel <p.zabel@pengutronix.de> | 2014-11-24 10:33:34 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2014-11-25 18:40:39 -0500 |
commit | 6556f7f82b9c401950d703072c0d8137b6f9f516 (patch) | |
tree | 7432c41c5e01cb975a5a8f8aaf5fbf88021af145 /Documentation/devicetree/bindings/drm | |
parent | 0364d4fef4d19bdddca9a649ea83bc4bf458324f (diff) |
drm: imx: Move imx-drm driver out of staging
The imx-drm driver was put into staging mostly for the following reasons,
all of which have been addressed or superseded:
- convert the irq driver to use linear irq domains
- work out the device tree bindings, this lead to the common of_graph
bindings being used
- factor out common helper functions, this mostly resulted in the
component framework and drm of_graph helpers.
Before adding new fixes, and certainly before adding new features,
move it into its proper place below drivers/gpu/drm.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'Documentation/devicetree/bindings/drm')
-rw-r--r-- | Documentation/devicetree/bindings/drm/imx/fsl-imx-drm.txt | 83 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/drm/imx/hdmi.txt | 58 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/drm/imx/ldb.txt | 122 |
3 files changed, 263 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/drm/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/drm/imx/fsl-imx-drm.txt new file mode 100644 index 000000000000..e75f0e549fff --- /dev/null +++ b/Documentation/devicetree/bindings/drm/imx/fsl-imx-drm.txt | |||
@@ -0,0 +1,83 @@ | |||
1 | Freescale i.MX DRM master device | ||
2 | ================================ | ||
3 | |||
4 | The freescale i.MX DRM master device is a virtual device needed to list all | ||
5 | IPU or other display interface nodes that comprise the graphics subsystem. | ||
6 | |||
7 | Required properties: | ||
8 | - compatible: Should be "fsl,imx-display-subsystem" | ||
9 | - ports: Should contain a list of phandles pointing to display interface ports | ||
10 | of IPU devices | ||
11 | |||
12 | example: | ||
13 | |||
14 | display-subsystem { | ||
15 | compatible = "fsl,display-subsystem"; | ||
16 | ports = <&ipu_di0>; | ||
17 | }; | ||
18 | |||
19 | |||
20 | Freescale i.MX IPUv3 | ||
21 | ==================== | ||
22 | |||
23 | Required properties: | ||
24 | - compatible: Should be "fsl,<chip>-ipu" | ||
25 | - reg: should be register base and length as documented in the | ||
26 | datasheet | ||
27 | - interrupts: Should contain sync interrupt and error interrupt, | ||
28 | in this order. | ||
29 | - resets: phandle pointing to the system reset controller and | ||
30 | reset line index, see reset/fsl,imx-src.txt for details | ||
31 | Optional properties: | ||
32 | - port@[0-3]: Port nodes with endpoint definitions as defined in | ||
33 | Documentation/devicetree/bindings/media/video-interfaces.txt. | ||
34 | Ports 0 and 1 should correspond to CSI0 and CSI1, | ||
35 | ports 2 and 3 should correspond to DI0 and DI1, respectively. | ||
36 | |||
37 | example: | ||
38 | |||
39 | ipu: ipu@18000000 { | ||
40 | #address-cells = <1>; | ||
41 | #size-cells = <0>; | ||
42 | compatible = "fsl,imx53-ipu"; | ||
43 | reg = <0x18000000 0x080000000>; | ||
44 | interrupts = <11 10>; | ||
45 | resets = <&src 2>; | ||
46 | |||
47 | ipu_di0: port@2 { | ||
48 | reg = <2>; | ||
49 | |||
50 | ipu_di0_disp0: endpoint { | ||
51 | remote-endpoint = <&display_in>; | ||
52 | }; | ||
53 | }; | ||
54 | }; | ||
55 | |||
56 | Parallel display support | ||
57 | ======================== | ||
58 | |||
59 | Required properties: | ||
60 | - compatible: Should be "fsl,imx-parallel-display" | ||
61 | Optional properties: | ||
62 | - interface_pix_fmt: How this display is connected to the | ||
63 | display interface. Currently supported types: "rgb24", "rgb565", "bgr666" | ||
64 | and "lvds666". | ||
65 | - edid: verbatim EDID data block describing attached display. | ||
66 | - ddc: phandle describing the i2c bus handling the display data | ||
67 | channel | ||
68 | - port: A port node with endpoint definitions as defined in | ||
69 | Documentation/devicetree/bindings/media/video-interfaces.txt. | ||
70 | |||
71 | example: | ||
72 | |||
73 | display@di0 { | ||
74 | compatible = "fsl,imx-parallel-display"; | ||
75 | edid = [edid-data]; | ||
76 | interface-pix-fmt = "rgb24"; | ||
77 | |||
78 | port { | ||
79 | display_in: endpoint { | ||
80 | remote-endpoint = <&ipu_di0_disp0>; | ||
81 | }; | ||
82 | }; | ||
83 | }; | ||
diff --git a/Documentation/devicetree/bindings/drm/imx/hdmi.txt b/Documentation/devicetree/bindings/drm/imx/hdmi.txt new file mode 100644 index 000000000000..1b756cf9afb0 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/imx/hdmi.txt | |||
@@ -0,0 +1,58 @@ | |||
1 | Device-Tree bindings for HDMI Transmitter | ||
2 | |||
3 | HDMI Transmitter | ||
4 | ================ | ||
5 | |||
6 | The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP | ||
7 | with accompanying PHY IP. | ||
8 | |||
9 | Required properties: | ||
10 | - #address-cells : should be <1> | ||
11 | - #size-cells : should be <0> | ||
12 | - compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi". | ||
13 | - gpr : should be <&gpr>. | ||
14 | The phandle points to the iomuxc-gpr region containing the HDMI | ||
15 | multiplexer control register. | ||
16 | - clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described | ||
17 | in Documentation/devicetree/bindings/clock/clock-bindings.txt and | ||
18 | Documentation/devicetree/bindings/clock/imx6q-clock.txt. | ||
19 | - port@[0-4]: Up to four port nodes with endpoint definitions as defined in | ||
20 | Documentation/devicetree/bindings/media/video-interfaces.txt, | ||
21 | corresponding to the four inputs to the HDMI multiplexer. | ||
22 | |||
23 | Optional properties: | ||
24 | - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing | ||
25 | |||
26 | example: | ||
27 | |||
28 | gpr: iomuxc-gpr@020e0000 { | ||
29 | /* ... */ | ||
30 | }; | ||
31 | |||
32 | hdmi: hdmi@0120000 { | ||
33 | #address-cells = <1>; | ||
34 | #size-cells = <0>; | ||
35 | compatible = "fsl,imx6q-hdmi"; | ||
36 | reg = <0x00120000 0x9000>; | ||
37 | interrupts = <0 115 0x04>; | ||
38 | gpr = <&gpr>; | ||
39 | clocks = <&clks 123>, <&clks 124>; | ||
40 | clock-names = "iahb", "isfr"; | ||
41 | ddc-i2c-bus = <&i2c2>; | ||
42 | |||
43 | port@0 { | ||
44 | reg = <0>; | ||
45 | |||
46 | hdmi_mux_0: endpoint { | ||
47 | remote-endpoint = <&ipu1_di0_hdmi>; | ||
48 | }; | ||
49 | }; | ||
50 | |||
51 | port@1 { | ||
52 | reg = <1>; | ||
53 | |||
54 | hdmi_mux_1: endpoint { | ||
55 | remote-endpoint = <&ipu1_di1_hdmi>; | ||
56 | }; | ||
57 | }; | ||
58 | }; | ||
diff --git a/Documentation/devicetree/bindings/drm/imx/ldb.txt b/Documentation/devicetree/bindings/drm/imx/ldb.txt new file mode 100644 index 000000000000..443bcb6134d5 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/imx/ldb.txt | |||
@@ -0,0 +1,122 @@ | |||
1 | Device-Tree bindings for LVDS Display Bridge (ldb) | ||
2 | |||
3 | LVDS Display Bridge | ||
4 | =================== | ||
5 | |||
6 | The LVDS Display Bridge device tree node contains up to two lvds-channel | ||
7 | nodes describing each of the two LVDS encoder channels of the bridge. | ||
8 | |||
9 | Required properties: | ||
10 | - #address-cells : should be <1> | ||
11 | - #size-cells : should be <0> | ||
12 | - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". | ||
13 | Both LDB versions are similar, but i.MX6 has an additional | ||
14 | multiplexer in the front to select any of the four IPU display | ||
15 | interfaces as input for each LVDS channel. | ||
16 | - gpr : should be <&gpr> on i.MX53 and i.MX6q. | ||
17 | The phandle points to the iomuxc-gpr region containing the LVDS | ||
18 | control register. | ||
19 | - clocks, clock-names : phandles to the LDB divider and selector clocks and to | ||
20 | the display interface selector clocks, as described in | ||
21 | Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
22 | The following clocks are expected on i.MX53: | ||
23 | "di0_pll" - LDB LVDS channel 0 mux | ||
24 | "di1_pll" - LDB LVDS channel 1 mux | ||
25 | "di0" - LDB LVDS channel 0 gate | ||
26 | "di1" - LDB LVDS channel 1 gate | ||
27 | "di0_sel" - IPU1 DI0 mux | ||
28 | "di1_sel" - IPU1 DI1 mux | ||
29 | On i.MX6q the following additional clocks are needed: | ||
30 | "di2_sel" - IPU2 DI0 mux | ||
31 | "di3_sel" - IPU2 DI1 mux | ||
32 | The needed clock numbers for each are documented in | ||
33 | Documentation/devicetree/bindings/clock/imx5-clock.txt, and in | ||
34 | Documentation/devicetree/bindings/clock/imx6q-clock.txt. | ||
35 | |||
36 | Optional properties: | ||
37 | - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q | ||
38 | - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, | ||
39 | not used on i.MX6q | ||
40 | - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should | ||
41 | be configured - one input will be distributed on both outputs in dual | ||
42 | channel mode | ||
43 | |||
44 | LVDS Channel | ||
45 | ============ | ||
46 | |||
47 | Each LVDS Channel has to contain a display-timings node that describes the | ||
48 | video timings for the connected LVDS display. For detailed information, also | ||
49 | have a look at Documentation/devicetree/bindings/video/display-timing.txt. | ||
50 | |||
51 | Required properties: | ||
52 | - reg : should be <0> or <1> | ||
53 | - fsl,data-mapping : should be "spwg" or "jeida" | ||
54 | This describes how the color bits are laid out in the | ||
55 | serialized LVDS signal. | ||
56 | - fsl,data-width : should be <18> or <24> | ||
57 | - port: A port node with endpoint definitions as defined in | ||
58 | Documentation/devicetree/bindings/media/video-interfaces.txt. | ||
59 | On i.MX5, the internal two-input-multiplexer is used. | ||
60 | Due to hardware limitations, only one port (port@[0,1]) | ||
61 | can be used for each channel (lvds-channel@[0,1], respectively) | ||
62 | On i.MX6, there should be four ports (port@[0-3]) that correspond | ||
63 | to the four LVDS multiplexer inputs. | ||
64 | |||
65 | example: | ||
66 | |||
67 | gpr: iomuxc-gpr@53fa8000 { | ||
68 | /* ... */ | ||
69 | }; | ||
70 | |||
71 | ldb: ldb@53fa8008 { | ||
72 | #address-cells = <1>; | ||
73 | #size-cells = <0>; | ||
74 | compatible = "fsl,imx53-ldb"; | ||
75 | gpr = <&gpr>; | ||
76 | clocks = <&clks 122>, <&clks 120>, | ||
77 | <&clks 115>, <&clks 116>, | ||
78 | <&clks 123>, <&clks 85>; | ||
79 | clock-names = "di0_pll", "di1_pll", | ||
80 | "di0_sel", "di1_sel", | ||
81 | "di0", "di1"; | ||
82 | |||
83 | lvds-channel@0 { | ||
84 | #address-cells = <1>; | ||
85 | #size-cells = <0>; | ||
86 | reg = <0>; | ||
87 | fsl,data-mapping = "spwg"; | ||
88 | fsl,data-width = <24>; | ||
89 | |||
90 | display-timings { | ||
91 | /* ... */ | ||
92 | }; | ||
93 | |||
94 | port@0 { | ||
95 | reg = <0>; | ||
96 | |||
97 | lvds0_in: endpoint { | ||
98 | remote-endpoint = <&ipu_di0_lvds0>; | ||
99 | }; | ||
100 | }; | ||
101 | }; | ||
102 | |||
103 | lvds-channel@1 { | ||
104 | #address-cells = <1>; | ||
105 | #size-cells = <0>; | ||
106 | reg = <1>; | ||
107 | fsl,data-mapping = "spwg"; | ||
108 | fsl,data-width = <24>; | ||
109 | |||
110 | display-timings { | ||
111 | /* ... */ | ||
112 | }; | ||
113 | |||
114 | port@1 { | ||
115 | reg = <1>; | ||
116 | |||
117 | lvds1_in: endpoint { | ||
118 | remote-endpoint = <&ipu_di1_lvds1>; | ||
119 | }; | ||
120 | }; | ||
121 | }; | ||
122 | }; | ||