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authorZhangfei Gao <zhangfei.gao@linaro.org>2013-08-26 22:20:10 -0400
committerVinod Koul <vinod.koul@intel.com>2013-08-28 01:53:40 -0400
commit8e6152bc660e69f526c6bf163ff0ebfdab90f6cf (patch)
tree18d27ff4cedae2a166ee0b780da0960b0696d533 /Documentation/devicetree/bindings/dma/k3dma.txt
parent0429936697321612e3c2edbfa2161856e737ac09 (diff)
dmaengine: Add hisilicon k3 DMA engine driver
Add dmaengine driver for hisilicon k3 platform based on virt_dma Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Kai Yang <jean.yangkai@huawei.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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1* Hisilicon K3 DMA controller
2
3See dma.txt first
4
5Required properties:
6- compatible: Should be "hisilicon,k3-dma-1.0"
7- reg: Should contain DMA registers location and length.
8- interrupts: Should contain one interrupt shared by all channel
9- #dma-cells: see dma.txt, should be 1, para number
10- dma-channels: physical channels supported
11- dma-requests: virtual channels supported, each virtual channel
12 have specific request line
13- clocks: clock required
14
15Example:
16
17Controller:
18 dma0: dma@fcd02000 {
19 compatible = "hisilicon,k3-dma-1.0";
20 reg = <0xfcd02000 0x1000>;
21 #dma-cells = <1>;
22 dma-channels = <16>;
23 dma-requests = <27>;
24 interrupts = <0 12 4>;
25 clocks = <&pclk>;
26 status = "disable";
27 };
28
29Client:
30Use specific request line passing from dmax
31For example, i2c0 read channel request line is 18, while write channel use 19
32
33 i2c0: i2c@fcb08000 {
34 compatible = "snps,designware-i2c";
35 dmas = <&dma0 18 /* read channel */
36 &dma0 19>; /* write channel */
37 dma-names = "rx", "tx";
38 };
39
40 i2c1: i2c@fcb09000 {
41 compatible = "snps,designware-i2c";
42 dmas = <&dma0 20 /* read channel */
43 &dma0 21>; /* write channel */
44 dma-names = "rx", "tx";
45 };
46