clk: st: Adds divmux and prediv clock binding

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

1 files changed, 83 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
new file mode 100644
index 000000000000..49ec5ae18b5b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -0,0 +1,83 @@
+Binding for a Clockgen hardware block found on
+certain STMicroelectronics consumer electronics SoC devices.
+
+A Clockgen node can contain pll, diviser or multiplexer nodes.
+
+We will find only the base address of the Clockgen, this base
+address is common of all subnode.
+
+        clockgen_node {
+                reg = <>;
+
+                pll_node {
+                        ...
+                };
+
+                prediv_node {
+                        ...
+                };
+
+                divmux_node {
+                        ...
+                };
+
+                quadfs_node {
+                        ...
+                };
+                ...
+        };
+
+This binding uses the common clock binding[1].
+Each subnode should use the binding discribe in [2]..[4]
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
+
+Required properties:
+- reg : A Base address and length of the register set.
+
+Example:
+
+        clockgenA@fee62000 {
+
+                reg = <0xfee62000 0xb48>;
+
+                CLK_S_A0_PLL: CLK_S_A0_PLL {
+                        #clock-cells = <1>;
+                        compatible = "st,clkgena-plls-c65";
+
+                        clocks = <&CLK_SYSIN>;
+
+                        clock-output-names = "CLK_S_A0_PLL0_HS",
+                                             "CLK_S_A0_PLL0_LS",
+                                             "CLK_S_A0_PLL1";
+                };
+
+                CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
+                        #clock-cells = <0>;
+                        compatible = "st,clkgena-prediv-c65",
+                                     "st,clkgena-prediv";
+
+                        clocks = <&CLK_SYSIN>;
+
+                        clock-output-names = "CLK_S_A0_OSC_PREDIV";
+                };
+
+                CLK_S_A0_HS: CLK_S_A0_HS {
+                        #clock-cells = <1>;
+                        compatible = "st,clkgena-divmux-c65-hs",
+                                     "st,clkgena-divmux";
+
+                        clocks = <&CLK_S_A0_OSC_PREDIV>,
+                                 <&CLK_S_A0_PLL 0>, /* PLL0 HS */
+                                 <&CLK_S_A0_PLL 2>; /* PLL1 */
+
+                        clock-output-names = "CLK_S_FDMA_0",
+                                             "CLK_S_FDMA_1",
+                                             ""; /* CLK_S_JIT_SENSE */
+                                             /* Fourth output unused */
+                };
+        };
+