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authorMathieu Olivari <mathieu@codeaurora.org>2015-02-20 21:19:36 -0500
committerWim Van Sebroeck <wim@iguana.be>2015-04-22 09:28:16 -0400
commitcf79fb14d09f8a9aaadfce59d01cfedf4f96d99d (patch)
treed22d927a8d48a08a07f1c42e2f71155c5c00383b /Documentation/devicetree/bindings/arm
parent4ba1c98b552c58b1a29bd943aef51b1788465b2d (diff)
ARM: msm: add watchdog entries to DT timer binding doc
The watchdog has been reworked to use the same DT node as the timer. This change is updating the device tree doc accordingly. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
-rw-r--r--Documentation/devicetree/bindings/arm/msm/timer.txt16
1 files changed, 13 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt
index 74607b6c1117..5e10c345548f 100644
--- a/Documentation/devicetree/bindings/arm/msm/timer.txt
+++ b/Documentation/devicetree/bindings/arm/msm/timer.txt
@@ -9,11 +9,17 @@ Properties:
9 "qcom,scss-timer" - scorpion subsystem 9 "qcom,scss-timer" - scorpion subsystem
10 10
11- interrupts : Interrupts for the debug timer, the first general purpose 11- interrupts : Interrupts for the debug timer, the first general purpose
12 timer, and optionally a second general purpose timer in that 12 timer, and optionally a second general purpose timer, and
13 order. 13 optionally as well, 2 watchdog interrupts, in that order.
14 14
15- reg : Specifies the base address of the timer registers. 15- reg : Specifies the base address of the timer registers.
16 16
17- clocks: Reference to the parent clocks, one per output clock. The parents
18 must appear in the same order as the clock names.
19
20- clock-names: The name of the clocks as free-form strings. They should be in
21 the same order as the clocks.
22
17- clock-frequency : The frequency of the debug timer and the general purpose 23- clock-frequency : The frequency of the debug timer and the general purpose
18 timer(s) in Hz in that order. 24 timer(s) in Hz in that order.
19 25
@@ -29,9 +35,13 @@ Example:
29 compatible = "qcom,scss-timer", "qcom,msm-timer"; 35 compatible = "qcom,scss-timer", "qcom,msm-timer";
30 interrupts = <1 1 0x301>, 36 interrupts = <1 1 0x301>,
31 <1 2 0x301>, 37 <1 2 0x301>,
32 <1 3 0x301>; 38 <1 3 0x301>,
39 <1 4 0x301>,
40 <1 5 0x301>;
33 reg = <0x0200a000 0x100>; 41 reg = <0x0200a000 0x100>;
34 clock-frequency = <19200000>, 42 clock-frequency = <19200000>,
35 <32768>; 43 <32768>;
44 clocks = <&sleep_clk>;
45 clock-names = "sleep";
36 cpu-offset = <0x40000>; 46 cpu-offset = <0x40000>;
37 }; 47 };