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authorMatt LaPlante <kernel1@cyberdogtech.com>2007-10-19 19:34:40 -0400
committerAdrian Bunk <bunk@kernel.org>2007-10-19 19:34:40 -0400
commit01dd2fbf0da4019c380b6ca22a074538fb31db5a (patch)
tree210291bd341c4450c8c51d8db890af0978f4035d /Documentation/arm
parent0f035b8e8491f4ff87f6eec3e3f754d36b39d7a2 (diff)
typo fixes
Most of these fixes were already submitted for old kernel versions, and were approved, but for some reason they never made it into the releases. Because this is a consolidation of a couple old missed patches, it touches both Kconfigs and documentation texts. Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com> Acked-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
Diffstat (limited to 'Documentation/arm')
-rw-r--r--Documentation/arm/Samsung-S3C24XX/DMA.txt18
1 files changed, 9 insertions, 9 deletions
diff --git a/Documentation/arm/Samsung-S3C24XX/DMA.txt b/Documentation/arm/Samsung-S3C24XX/DMA.txt
index 37f4edcc5d87..3ed82383efea 100644
--- a/Documentation/arm/Samsung-S3C24XX/DMA.txt
+++ b/Documentation/arm/Samsung-S3C24XX/DMA.txt
@@ -5,7 +5,7 @@ Introduction
5------------ 5------------
6 6
7 The kernel provides an interface to manage DMA transfers 7 The kernel provides an interface to manage DMA transfers
8 using the DMA channels in the cpu, so that the central 8 using the DMA channels in the CPU, so that the central
9 duty of managing channel mappings, and programming the 9 duty of managing channel mappings, and programming the
10 channel generators is in one place. 10 channel generators is in one place.
11 11
@@ -17,24 +17,24 @@ DMA Channel Ordering
17 channels to all sources, which means that some devices 17 channels to all sources, which means that some devices
18 have a restricted number of channels that can be used. 18 have a restricted number of channels that can be used.
19 19
20 To allow flexibilty for each cpu type and board, the 20 To allow flexibility for each CPU type and board, the
21 dma code can be given an dma ordering structure which 21 DMA code can be given a DMA ordering structure which
22 allows the order of channel search to be specified, as 22 allows the order of channel search to be specified, as
23 well as allowing the prohibition of certain claims. 23 well as allowing the prohibition of certain claims.
24 24
25 struct s3c24xx_dma_order has a list of channels, and 25 struct s3c24xx_dma_order has a list of channels, and
26 each channel within has a slot for a list of dma 26 each channel within has a slot for a list of DMA
27 channel numbers. The slots are searched in order, for 27 channel numbers. The slots are searched in order for
28 the presence of a dma channel number with DMA_CH_VALID 28 the presence of a DMA channel number with DMA_CH_VALID
29 orred in. 29 or-ed in.
30 30
31 If the order has the flag DMA_CH_NEVER set, then after 31 If the order has the flag DMA_CH_NEVER set, then after
32 checking the channel list, the system will return no 32 checking the channel list, the system will return no
33 found channel, thus denying the request. 33 found channel, thus denying the request.
34 34
35 A board support file can call s3c24xx_dma_order_set() 35 A board support file can call s3c24xx_dma_order_set()
36 to register an complete ordering set. The routine will 36 to register a complete ordering set. The routine will
37 copy the data, so the original can be discared with 37 copy the data, so the original can be discarded with
38 __initdata. 38 __initdata.
39 39
40 40