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authorMark A. Greer <mgreer@animalcreek.com>2012-12-21 11:28:13 -0500
committerPaul Walmsley <paul@pwsan.com>2013-03-30 17:52:05 -0400
commitff2acd7d5da9c78ad6ffb7663c5d72d2a839f6df (patch)
treed321e369e04bbbe39b51cb33dba8dfdb0be583ba
parent53335acc444fdb8cf3479e4c45a3165281a592dd (diff)
ARM: AM33XX: Add aes0 crypto clock data
Add clock data for for the SHA0 crypto module on the am33xx SoC. CC: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mark A. Greer <mgreer@animalcreek.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ef0267ca2417..c8dcc523c31a 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -417,6 +417,10 @@ static struct clk sha0_fck;
417DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL); 417DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
418DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null); 418DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
419 419
420static struct clk aes0_fck;
421DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
422DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
423
420/* 424/*
421 * Modules clock nodes 425 * Modules clock nodes
422 * 426 *
@@ -883,6 +887,7 @@ static struct omap_clk am33xx_clks[] = {
883 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck), 887 CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
884 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), 888 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
885 CLK(NULL, "sha0_fck", &sha0_fck), 889 CLK(NULL, "sha0_fck", &sha0_fck),
890 CLK(NULL, "aes0_fck", &aes0_fck),
886 CLK(NULL, "timer1_fck", &timer1_fck), 891 CLK(NULL, "timer1_fck", &timer1_fck),
887 CLK(NULL, "timer2_fck", &timer2_fck), 892 CLK(NULL, "timer2_fck", &timer2_fck),
888 CLK(NULL, "timer3_fck", &timer3_fck), 893 CLK(NULL, "timer3_fck", &timer3_fck),