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authorHaojian Zhuang <haojian.zhuang@gmail.com>2012-04-19 06:44:50 -0400
committerHaojian Zhuang <haojian.zhuang@gmail.com>2012-05-05 04:39:29 -0400
commitff290fc3ed7c4f451ea029190624cff692f028a5 (patch)
tree43b0b2588cd2602186a58e696cebab538ce69b2b
parent641f4d562cf69e1839c84c9415169644025ec247 (diff)
ARM: dts: refresh dts file for arch mmp
Append mmp2 and pxa910 dts files. Update PXA168 dts files for irq, timer, gpio components. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/boot/dts/mmp2-brownstone.dts38
-rw-r--r--arch/arm/boot/dts/mmp2.dtsi220
-rw-r--r--arch/arm/boot/dts/pxa168.dtsi67
-rw-r--r--arch/arm/boot/dts/pxa910-dkb.dts38
-rw-r--r--arch/arm/boot/dts/pxa910.dtsi140
5 files changed, 487 insertions, 16 deletions
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
new file mode 100644
index 000000000000..153a4b2d12b5
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11/include/ "mmp2.dtsi"
12
13/ {
14 model = "Marvell MMP2 Aspenite Development Board";
15 compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
16
17 chosen {
18 bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
19 };
20
21 memory {
22 reg = <0x00000000 0x04000000>;
23 };
24
25 soc {
26 apb@d4000000 {
27 uart3: uart@d4018000 {
28 status = "okay";
29 };
30 twsi1: i2c@d4011000 {
31 status = "okay";
32 };
33 rtc: rtc@d4010000 {
34 status = "okay";
35 };
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
new file mode 100644
index 000000000000..80f74e256408
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -0,0 +1,220 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 aliases {
14 serial0 = &uart1;
15 serial1 = &uart2;
16 serial2 = &uart3;
17 serial3 = &uart4;
18 i2c0 = &twsi1;
19 i2c1 = &twsi2;
20 };
21
22 soc {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "simple-bus";
26 interrupt-parent = <&intc>;
27 ranges;
28
29 axi@d4200000 { /* AXI */
30 compatible = "mrvl,axi-bus", "simple-bus";
31 #address-cells = <1>;
32 #size-cells = <1>;
33 reg = <0xd4200000 0x00200000>;
34 ranges;
35
36 intc: interrupt-controller@d4282000 {
37 compatible = "mrvl,mmp2-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
40 reg = <0xd4282000 0x1000>;
41 mrvl,intc-nr-irqs = <64>;
42 };
43
44 intcmux4@d4282150 {
45 compatible = "mrvl,mmp2-mux-intc";
46 interrupts = <4>;
47 interrupt-controller;
48 #interrupt-cells = <1>;
49 reg = <0x150 0x4>, <0x168 0x4>;
50 reg-names = "mux status", "mux mask";
51 mrvl,intc-nr-irqs = <2>;
52 };
53
54 intcmux5: interrupt-controller@d4282154 {
55 compatible = "mrvl,mmp2-mux-intc";
56 interrupts = <5>;
57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x154 0x4>, <0x16c 0x4>;
60 reg-names = "mux status", "mux mask";
61 mrvl,intc-nr-irqs = <2>;
62 mrvl,clr-mfp-irq = <1>;
63 };
64
65 intcmux9: interrupt-controller@d4282180 {
66 compatible = "mrvl,mmp2-mux-intc";
67 interrupts = <9>;
68 interrupt-controller;
69 #interrupt-cells = <1>;
70 reg = <0x180 0x4>, <0x17c 0x4>;
71 reg-names = "mux status", "mux mask";
72 mrvl,intc-nr-irqs = <3>;
73 };
74
75 intcmux17: interrupt-controller@d4282158 {
76 compatible = "mrvl,mmp2-mux-intc";
77 interrupts = <17>;
78 interrupt-controller;
79 #interrupt-cells = <1>;
80 reg = <0x158 0x4>, <0x170 0x4>;
81 reg-names = "mux status", "mux mask";
82 mrvl,intc-nr-irqs = <5>;
83 };
84
85 intcmux35: interrupt-controller@d428215c {
86 compatible = "mrvl,mmp2-mux-intc";
87 interrupts = <35>;
88 interrupt-controller;
89 #interrupt-cells = <1>;
90 reg = <0x15c 0x4>, <0x174 0x4>;
91 reg-names = "mux status", "mux mask";
92 mrvl,intc-nr-irqs = <15>;
93 };
94
95 intcmux51: interrupt-controller@d4282160 {
96 compatible = "mrvl,mmp2-mux-intc";
97 interrupts = <51>;
98 interrupt-controller;
99 #interrupt-cells = <1>;
100 reg = <0x160 0x4>, <0x178 0x4>;
101 reg-names = "mux status", "mux mask";
102 mrvl,intc-nr-irqs = <2>;
103 };
104
105 intcmux55: interrupt-controller@d4282188 {
106 compatible = "mrvl,mmp2-mux-intc";
107 interrupts = <55>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
110 reg = <0x188 0x4>, <0x184 0x4>;
111 reg-names = "mux status", "mux mask";
112 mrvl,intc-nr-irqs = <2>;
113 };
114 };
115
116 apb@d4000000 { /* APB */
117 compatible = "mrvl,apb-bus", "simple-bus";
118 #address-cells = <1>;
119 #size-cells = <1>;
120 reg = <0xd4000000 0x00200000>;
121 ranges;
122
123 timer0: timer@d4014000 {
124 compatible = "mrvl,mmp-timer";
125 reg = <0xd4014000 0x100>;
126 interrupts = <13>;
127 };
128
129 uart1: uart@d4030000 {
130 compatible = "mrvl,mmp-uart";
131 reg = <0xd4030000 0x1000>;
132 interrupts = <27>;
133 status = "disabled";
134 };
135
136 uart2: uart@d4017000 {
137 compatible = "mrvl,mmp-uart";
138 reg = <0xd4017000 0x1000>;
139 interrupts = <28>;
140 status = "disabled";
141 };
142
143 uart3: uart@d4018000 {
144 compatible = "mrvl,mmp-uart";
145 reg = <0xd4018000 0x1000>;
146 interrupts = <24>;
147 status = "disabled";
148 };
149
150 uart4: uart@d4016000 {
151 compatible = "mrvl,mmp-uart";
152 reg = <0xd4016000 0x1000>;
153 interrupts = <46>;
154 status = "disabled";
155 };
156
157 gpio@d4019000 {
158 compatible = "mrvl,mmp-gpio";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 reg = <0xd4019000 0x1000>;
162 gpio-controller;
163 #gpio-cells = <2>;
164 interrupts = <49>;
165 interrupt-names = "gpio_mux";
166 interrupt-controller;
167 #interrupt-cells = <1>;
168 ranges;
169
170 gcb0: gpio@d4019000 {
171 reg = <0xd4019000 0x4>;
172 };
173
174 gcb1: gpio@d4019004 {
175 reg = <0xd4019004 0x4>;
176 };
177
178 gcb2: gpio@d4019008 {
179 reg = <0xd4019008 0x4>;
180 };
181
182 gcb3: gpio@d4019100 {
183 reg = <0xd4019100 0x4>;
184 };
185
186 gcb4: gpio@d4019104 {
187 reg = <0xd4019104 0x4>;
188 };
189
190 gcb5: gpio@d4019108 {
191 reg = <0xd4019108 0x4>;
192 };
193 };
194
195 twsi1: i2c@d4011000 {
196 compatible = "mrvl,mmp-twsi";
197 reg = <0xd4011000 0x1000>;
198 interrupts = <7>;
199 mrvl,i2c-fast-mode;
200 status = "disabled";
201 };
202
203 twsi2: i2c@d4025000 {
204 compatible = "mrvl,mmp-twsi";
205 reg = <0xd4025000 0x1000>;
206 interrupts = <58>;
207 status = "disabled";
208 };
209
210 rtc: rtc@d4010000 {
211 compatible = "mrvl,mmp-rtc";
212 reg = <0xd4010000 0x1000>;
213 interrupts = <1 0>;
214 interrupt-names = "rtc 1Hz", "rtc alarm";
215 interrupt-parent = <&intcmux5>;
216 status = "disabled";
217 };
218 };
219 };
220};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index d32d5128f225..31a718696080 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -18,13 +18,6 @@
18 i2c1 = &twsi2; 18 i2c1 = &twsi2;
19 }; 19 };
20 20
21 intc: intc-interrupt-controller@d4282000 {
22 compatible = "mrvl,mmp-intc", "mrvl,intc";
23 interrupt-controller;
24 #interrupt-cells = <1>;
25 reg = <0xd4282000 0x1000>;
26 };
27
28 soc { 21 soc {
29 #address-cells = <1>; 22 #address-cells = <1>;
30 #size-cells = <1>; 23 #size-cells = <1>;
@@ -32,6 +25,23 @@
32 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
33 ranges; 26 ranges;
34 27
28 axi@d4200000 { /* AXI */
29 compatible = "mrvl,axi-bus", "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 reg = <0xd4200000 0x00200000>;
33 ranges;
34
35 intc: interrupt-controller@d4282000 {
36 compatible = "mrvl,mmp-intc";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0xd4282000 0x1000>;
40 mrvl,intc-nr-irqs = <64>;
41 };
42
43 };
44
35 apb@d4000000 { /* APB */ 45 apb@d4000000 { /* APB */
36 compatible = "mrvl,apb-bus", "simple-bus"; 46 compatible = "mrvl,apb-bus", "simple-bus";
37 #address-cells = <1>; 47 #address-cells = <1>;
@@ -39,40 +49,65 @@
39 reg = <0xd4000000 0x00200000>; 49 reg = <0xd4000000 0x00200000>;
40 ranges; 50 ranges;
41 51
52 timer0: timer@d4014000 {
53 compatible = "mrvl,mmp-timer";
54 reg = <0xd4014000 0x100>;
55 interrupts = <13>;
56 };
57
42 uart1: uart@d4017000 { 58 uart1: uart@d4017000 {
43 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; 59 compatible = "mrvl,mmp-uart";
44 reg = <0xd4017000 0x1000>; 60 reg = <0xd4017000 0x1000>;
45 interrupts = <27>; 61 interrupts = <27>;
46 status = "disabled"; 62 status = "disabled";
47 }; 63 };
48 64
49 uart2: uart@d4018000 { 65 uart2: uart@d4018000 {
50 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; 66 compatible = "mrvl,mmp-uart";
51 reg = <0xd4018000 0x1000>; 67 reg = <0xd4018000 0x1000>;
52 interrupts = <28>; 68 interrupts = <28>;
53 status = "disabled"; 69 status = "disabled";
54 }; 70 };
55 71
56 uart3: uart@d4026000 { 72 uart3: uart@d4026000 {
57 compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; 73 compatible = "mrvl,mmp-uart";
58 reg = <0xd4026000 0x1000>; 74 reg = <0xd4026000 0x1000>;
59 interrupts = <29>; 75 interrupts = <29>;
60 status = "disabled"; 76 status = "disabled";
61 }; 77 };
62 78
63 gpio: gpio@d4019000 { 79 gpio@d4019000 {
64 compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio"; 80 compatible = "mrvl,mmp-gpio";
81 #address-cells = <1>;
82 #size-cells = <1>;
65 reg = <0xd4019000 0x1000>; 83 reg = <0xd4019000 0x1000>;
84 gpio-controller;
85 #gpio-cells = <2>;
66 interrupts = <49>; 86 interrupts = <49>;
67 interrupt-names = "gpio_mux"; 87 interrupt-names = "gpio_mux";
68 gpio-controller;
69 #gpio-cells = <1>;
70 interrupt-controller; 88 interrupt-controller;
71 #interrupt-cells = <1>; 89 #interrupt-cells = <1>;
90 ranges;
91
92 gcb0: gpio@d4019000 {
93 reg = <0xd4019000 0x4>;
94 };
95
96 gcb1: gpio@d4019004 {
97 reg = <0xd4019004 0x4>;
98 };
99
100 gcb2: gpio@d4019008 {
101 reg = <0xd4019008 0x4>;
102 };
103
104 gcb3: gpio@d4019100 {
105 reg = <0xd4019100 0x4>;
106 };
72 }; 107 };
73 108
74 twsi1: i2c@d4011000 { 109 twsi1: i2c@d4011000 {
75 compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; 110 compatible = "mrvl,mmp-twsi";
76 reg = <0xd4011000 0x1000>; 111 reg = <0xd4011000 0x1000>;
77 interrupts = <7>; 112 interrupts = <7>;
78 mrvl,i2c-fast-mode; 113 mrvl,i2c-fast-mode;
@@ -80,7 +115,7 @@
80 }; 115 };
81 116
82 twsi2: i2c@d4025000 { 117 twsi2: i2c@d4025000 {
83 compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; 118 compatible = "mrvl,mmp-twsi";
84 reg = <0xd4025000 0x1000>; 119 reg = <0xd4025000 0x1000>;
85 interrupts = <58>; 120 interrupts = <58>;
86 status = "disabled"; 121 status = "disabled";
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
new file mode 100644
index 000000000000..e92be5a474e7
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/dts-v1/;
11/include/ "pxa910.dtsi"
12
13/ {
14 model = "Marvell PXA910 DKB Development Board";
15 compatible = "mrvl,pxa910-dkb", "mrvl,pxa910";
16
17 chosen {
18 bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
19 };
20
21 memory {
22 reg = <0x00000000 0x10000000>;
23 };
24
25 soc {
26 apb@d4000000 {
27 uart1: uart@d4017000 {
28 status = "okay";
29 };
30 twsi1: i2c@d4011000 {
31 status = "okay";
32 };
33 rtc: rtc@d4010000 {
34 status = "okay";
35 };
36 };
37 };
38};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
new file mode 100644
index 000000000000..aebf32de73b4
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -0,0 +1,140 @@
1/*
2 * Copyright (C) 2012 Marvell Technology Group Ltd.
3 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9
10/include/ "skeleton.dtsi"
11
12/ {
13 aliases {
14 serial0 = &uart1;
15 serial1 = &uart2;
16 serial2 = &uart3;
17 i2c0 = &twsi1;
18 i2c1 = &twsi2;
19 };
20
21 soc {
22 #address-cells = <1>;
23 #size-cells = <1>;
24 compatible = "simple-bus";
25 interrupt-parent = <&intc>;
26 ranges;
27
28 axi@d4200000 { /* AXI */
29 compatible = "mrvl,axi-bus", "simple-bus";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 reg = <0xd4200000 0x00200000>;
33 ranges;
34
35 intc: interrupt-controller@d4282000 {
36 compatible = "mrvl,mmp-intc";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0xd4282000 0x1000>;
40 mrvl,intc-nr-irqs = <64>;
41 };
42
43 };
44
45 apb@d4000000 { /* APB */
46 compatible = "mrvl,apb-bus", "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 reg = <0xd4000000 0x00200000>;
50 ranges;
51
52 timer0: timer@d4014000 {
53 compatible = "mrvl,mmp-timer";
54 reg = <0xd4014000 0x100>;
55 interrupts = <13>;
56 };
57
58 timer1: timer@d4016000 {
59 compatible = "mrvl,mmp-timer";
60 reg = <0xd4016000 0x100>;
61 interrupts = <29>;
62 status = "disabled";
63 };
64
65 uart1: uart@d4017000 {
66 compatible = "mrvl,mmp-uart";
67 reg = <0xd4017000 0x1000>;
68 interrupts = <27>;
69 status = "disabled";
70 };
71
72 uart2: uart@d4018000 {
73 compatible = "mrvl,mmp-uart";
74 reg = <0xd4018000 0x1000>;
75 interrupts = <28>;
76 status = "disabled";
77 };
78
79 uart3: uart@d4036000 {
80 compatible = "mrvl,mmp-uart";
81 reg = <0xd4036000 0x1000>;
82 interrupts = <59>;
83 status = "disabled";
84 };
85
86 gpio@d4019000 {
87 compatible = "mrvl,mmp-gpio";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 reg = <0xd4019000 0x1000>;
91 gpio-controller;
92 #gpio-cells = <2>;
93 interrupts = <49>;
94 interrupt-names = "gpio_mux";
95 interrupt-controller;
96 #interrupt-cells = <1>;
97 ranges;
98
99 gcb0: gpio@d4019000 {
100 reg = <0xd4019000 0x4>;
101 };
102
103 gcb1: gpio@d4019004 {
104 reg = <0xd4019004 0x4>;
105 };
106
107 gcb2: gpio@d4019008 {
108 reg = <0xd4019008 0x4>;
109 };
110
111 gcb3: gpio@d4019100 {
112 reg = <0xd4019100 0x4>;
113 };
114 };
115
116 twsi1: i2c@d4011000 {
117 compatible = "mrvl,mmp-twsi";
118 reg = <0xd4011000 0x1000>;
119 interrupts = <7>;
120 mrvl,i2c-fast-mode;
121 status = "disabled";
122 };
123
124 twsi2: i2c@d4037000 {
125 compatible = "mrvl,mmp-twsi";
126 reg = <0xd4037000 0x1000>;
127 interrupts = <54>;
128 status = "disabled";
129 };
130
131 rtc: rtc@d4010000 {
132 compatible = "mrvl,mmp-rtc";
133 reg = <0xd4010000 0x1000>;
134 interrupts = <5 6>;
135 interrupt-names = "rtc 1Hz", "rtc alarm";
136 status = "disabled";
137 };
138 };
139 };
140};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-12 23:40:17 -0400