aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2014-02-01 13:29:59 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-02-01 13:29:59 -0500
commitfea8893da7c52906caa1a8dc3199f4b2ed3b8dbd (patch)
tree56e3482be95e2f1bd1386ecb3bc104a55f68f5e7
parent04480094de7242d08bb62088e713fd7fe00443b4 (diff)
parentd7216f8f02da54f8f235c5cca562a55b7f52210d (diff)
Merge tag 'staging-3.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull rtl8812ae staging wireless driver from Greg KH: "Here's a single staging driver for a wireless chipset that has shown up in the SteamBox hardware. It is merged separately from the "main" staging pull request to sync up with the wireless api changes that came in from the networking tree. It's self-contained and works for me and others. Larry will be replacing it with a "real" driver for 3.15, but for now this one is needed" * tag 'staging-3.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: staging: r8821ae: Enable build by reverting BROKEN marking staging: r8821ae: Fix build problems Staging: rtl8812ae: disable due to build errors Staging: rtl8821ae: add TODO file Staging: rtl8821ae: removed unused functions and variables Staging: rtl8821ae: rc.c: fix up function prototypes Staging: rtl8812ae: Add Realtek 8821 PCI WIFI driver
Diffstat
-rw-r--r--drivers/staging/Kconfig2
-rw-r--r--drivers/staging/Makefile1
-rw-r--r--drivers/staging/rtl8821ae/Kconfig11
-rw-r--r--drivers/staging/rtl8821ae/Makefile35
-rw-r--r--drivers/staging/rtl8821ae/TODO10
-rw-r--r--drivers/staging/rtl8821ae/base.c1873
-rw-r--r--drivers/staging/rtl8821ae/base.h159
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/HalBtc8812a1Ant.c3976
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/HalBtc8812a1Ant.h205
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/habtc8723a1ant.c1614
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/habtc8723a1ant.h176
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbt_precomp.h99
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtc8192e1ant.c3891
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtc8192e1ant.h226
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtc8192e2ant.c4242
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtc8192e2ant.h162
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtc8723a2ant.c3780
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtc8723a2ant.h179
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtc8723b1ant.c4104
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtc8723b1ant.h175
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtc8723b2ant.c4185
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtc8723b2ant.h145
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtcoutsrc.c1181
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/halbtcoutsrc.h549
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/rtl_btc.c236
-rw-r--r--drivers/staging/rtl8821ae/btcoexist/rtl_btc.h66
-rw-r--r--drivers/staging/rtl8821ae/cam.c354
-rw-r--r--drivers/staging/rtl8821ae/cam.h56
-rw-r--r--drivers/staging/rtl8821ae/compat.h125
-rw-r--r--drivers/staging/rtl8821ae/core.c1464
-rw-r--r--drivers/staging/rtl8821ae/core.h43
-rw-r--r--drivers/staging/rtl8821ae/debug.c988
-rw-r--r--drivers/staging/rtl8821ae/debug.h227
-rw-r--r--drivers/staging/rtl8821ae/efuse.c1285
-rw-r--r--drivers/staging/rtl8821ae/efuse.h130
-rw-r--r--drivers/staging/rtl8821ae/pci.c2549
-rw-r--r--drivers/staging/rtl8821ae/pci.h353
-rw-r--r--drivers/staging/rtl8821ae/ps.c1025
-rw-r--r--drivers/staging/rtl8821ae/ps.h55
-rw-r--r--drivers/staging/rtl8821ae/rc.c309
-rw-r--r--drivers/staging/rtl8821ae/rc.h47
-rw-r--r--drivers/staging/rtl8821ae/regd.c503
-rw-r--r--drivers/staging/rtl8821ae/regd.h75
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/btc.h87
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/def.h442
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/dm.c3045
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/dm.h426
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/fw.c1349
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/fw.h321
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/hal_bt_coexist.c519
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/hal_bt_coexist.h169
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/hal_btc.c2069
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/hal_btc.h160
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/hw.c3346
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/hw.h75
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/led.c239
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/led.h40
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/phy.c5525
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/phy.h258
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/pwrseq.c199
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/pwrseq.h413
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/pwrseqcmd.c140
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/pwrseqcmd.h71
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/reg.h2427
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/rf.c464
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/rf.h46
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/sw.c499
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/sw.h39
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/table.c4002
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/table.h62
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/trx.c1050
-rw-r--r--drivers/staging/rtl8821ae/rtl8821ae/trx.h641
-rw-r--r--drivers/staging/rtl8821ae/stats.c283
-rw-r--r--drivers/staging/rtl8821ae/stats.h46
-rw-r--r--drivers/staging/rtl8821ae/wifi.h2532
75 files changed, 71854 insertions, 0 deletions
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 040a51525b42..99375f0a9440 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -52,6 +52,8 @@ source "drivers/staging/rtl8712/Kconfig"
52 52
53source "drivers/staging/rtl8188eu/Kconfig" 53source "drivers/staging/rtl8188eu/Kconfig"
54 54
55source "drivers/staging/rtl8821ae/Kconfig"
56
55source "drivers/staging/rts5139/Kconfig" 57source "drivers/staging/rts5139/Kconfig"
56 58
57source "drivers/staging/rts5208/Kconfig" 59source "drivers/staging/rts5208/Kconfig"
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index dea056bf7ff2..ddc3c4a5d39d 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_RTL8192U) += rtl8192u/
18obj-$(CONFIG_RTL8192E) += rtl8192e/ 18obj-$(CONFIG_RTL8192E) += rtl8192e/
19obj-$(CONFIG_R8712U) += rtl8712/ 19obj-$(CONFIG_R8712U) += rtl8712/
20obj-$(CONFIG_R8188EU) += rtl8188eu/ 20obj-$(CONFIG_R8188EU) += rtl8188eu/
21obj-$(CONFIG_R8821AE) += rtl8821ae/
21obj-$(CONFIG_RTS5139) += rts5139/ 22obj-$(CONFIG_RTS5139) += rts5139/
22obj-$(CONFIG_RTS5208) += rts5208/ 23obj-$(CONFIG_RTS5208) += rts5208/
23obj-$(CONFIG_TRANZPORT) += frontier/ 24obj-$(CONFIG_TRANZPORT) += frontier/
diff --git a/drivers/staging/rtl8821ae/Kconfig b/drivers/staging/rtl8821ae/Kconfig
new file mode 100644
index 000000000000..2aa5dac2f1df
--- /dev/null
+++ b/drivers/staging/rtl8821ae/Kconfig
@@ -0,0 +1,11 @@
1config R8821AE
2 tristate "RealTek RTL8821AE Wireless LAN NIC driver"
3 depends on PCI && WLAN
4 depends on m
5 select WIRELESS_EXT
6 select WEXT_PRIV
7 select EEPROM_93CX6
8 select CRYPTO
9 default N
10 ---help---
11 If built as a module, it will be called r8821ae.ko.
diff --git a/drivers/staging/rtl8821ae/Makefile b/drivers/staging/rtl8821ae/Makefile
new file mode 100644
index 000000000000..8a23bd7e8842
--- /dev/null
+++ b/drivers/staging/rtl8821ae/Makefile
@@ -0,0 +1,35 @@
1PCI_MAIN_OBJS := base.o \
2 rc.o \
3 debug.o \
4 regd.o \
5 efuse.o \
6 cam.o \
7 ps.o \
8 core.o \
9 stats.o \
10 pci.o \
11
12BT_COEXIST_OBJS:= btcoexist/halbtc8192e2ant.o\
13 btcoexist/halbtc8723b1ant.o\
14 btcoexist/halbtc8723b2ant.o\
15 btcoexist/halbtcoutsrc.o\
16 btcoexist/rtl_btc.o \
17
18PCI_8821AE_HAL_OBJS:= \
19 rtl8821ae/hw.o \
20 rtl8821ae/table.o \
21 rtl8821ae/sw.o \
22 rtl8821ae/trx.o \
23 rtl8821ae/led.o \
24 rtl8821ae/fw.o \
25 rtl8821ae/phy.o \
26 rtl8821ae/rf.o \
27 rtl8821ae/dm.o \
28 rtl8821ae/pwrseq.o \
29 rtl8821ae/pwrseqcmd.o \
30 rtl8821ae/hal_btc.o \
31 rtl8821ae/hal_bt_coexist.o \
32
33rtl8821ae-objs += $(BT_COEXIST_OBJS) $(PCI_MAIN_OBJS) $(PCI_8821AE_HAL_OBJS)
34
35obj-$(CONFIG_R8821AE) += rtl8821ae.o
diff --git a/drivers/staging/rtl8821ae/TODO b/drivers/staging/rtl8821ae/TODO
new file mode 100644
index 000000000000..3ee7529d4ed5
--- /dev/null
+++ b/drivers/staging/rtl8821ae/TODO
@@ -0,0 +1,10 @@
1Realtek 8821AE PCI wifi driver TODO:
2 - remove built-in btcoexist module when the "real" one gets upstream
3 - remove built-in rtlwifi code by porting driver to use the "real" one
4 in the drivers/net/ directory.
5 - fix up coding style issues
6
7Please send any patches for this driver to:
8 Greg Kroah-Hartman <gregkh@linuxfoundation.org>
9and the <devel@driverdev.osuosl.org> mailing list.
10
diff --git a/drivers/staging/rtl8821ae/base.c b/drivers/staging/rtl8821ae/base.c
new file mode 100644
index 000000000000..18c936fbdf1e
--- /dev/null
+++ b/drivers/staging/rtl8821ae/base.c
@@ -0,0 +1,1873 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include <linux/ip.h>
31#include <linux/module.h>
32#include "wifi.h"
33#include "rc.h"
34#include "base.h"
35#include "efuse.h"
36#include "cam.h"
37#include "ps.h"
38#include "regd.h"
39#include "pci.h"
40
41/*
42 *NOTICE!!!: This file will be very big, we hsould
43 *keep it clear under follwing roles:
44 *
45 *This file include follwing part, so, if you add new
46 *functions into this file, please check which part it
47 *should includes. or check if you should add new part
48 *for this file:
49 *
50 *1) mac80211 init functions
51 *2) tx information functions
52 *3) functions called by core.c
53 *4) wq & timer callback functions
54 *5) frame process functions
55 *6) IOT functions
56 *7) sysfs functions
57 *8) vif functions
58 *9) ...
59 */
60
61/*********************************************************
62 *
63 * mac80211 init functions
64 *
65 *********************************************************/
66static struct ieee80211_channel rtl_channeltable_2g[] = {
67 {.center_freq = 2412,.hw_value = 1,},
68 {.center_freq = 2417,.hw_value = 2,},
69 {.center_freq = 2422,.hw_value = 3,},
70 {.center_freq = 2427,.hw_value = 4,},
71 {.center_freq = 2432,.hw_value = 5,},
72 {.center_freq = 2437,.hw_value = 6,},
73 {.center_freq = 2442,.hw_value = 7,},
74 {.center_freq = 2447,.hw_value = 8,},
75 {.center_freq = 2452,.hw_value = 9,},
76 {.center_freq = 2457,.hw_value = 10,},
77 {.center_freq = 2462,.hw_value = 11,},
78 {.center_freq = 2467,.hw_value = 12,},
79 {.center_freq = 2472,.hw_value = 13,},
80 {.center_freq = 2484,.hw_value = 14,},
81};
82
83static struct ieee80211_channel rtl_channeltable_5g[] = {
84 {.center_freq = 5180,.hw_value = 36,},
85 {.center_freq = 5200,.hw_value = 40,},
86 {.center_freq = 5220,.hw_value = 44,},
87 {.center_freq = 5240,.hw_value = 48,},
88 {.center_freq = 5260,.hw_value = 52,},
89 {.center_freq = 5280,.hw_value = 56,},
90 {.center_freq = 5300,.hw_value = 60,},
91 {.center_freq = 5320,.hw_value = 64,},
92 {.center_freq = 5500,.hw_value = 100,},
93 {.center_freq = 5520,.hw_value = 104,},
94 {.center_freq = 5540,.hw_value = 108,},
95 {.center_freq = 5560,.hw_value = 112,},
96 {.center_freq = 5580,.hw_value = 116,},
97 {.center_freq = 5600,.hw_value = 120,},
98 {.center_freq = 5620,.hw_value = 124,},
99 {.center_freq = 5640,.hw_value = 128,},
100 {.center_freq = 5660,.hw_value = 132,},
101 {.center_freq = 5680,.hw_value = 136,},
102 {.center_freq = 5700,.hw_value = 140,},
103 {.center_freq = 5745,.hw_value = 149,},
104 {.center_freq = 5765,.hw_value = 153,},
105 {.center_freq = 5785,.hw_value = 157,},
106 {.center_freq = 5805,.hw_value = 161,},
107 {.center_freq = 5825,.hw_value = 165,},
108};
109
110static struct ieee80211_rate rtl_ratetable_2g[] = {
111 {.bitrate = 10,.hw_value = 0x00,},
112 {.bitrate = 20,.hw_value = 0x01,},
113 {.bitrate = 55,.hw_value = 0x02,},
114 {.bitrate = 110,.hw_value = 0x03,},
115 {.bitrate = 60,.hw_value = 0x04,},
116 {.bitrate = 90,.hw_value = 0x05,},
117 {.bitrate = 120,.hw_value = 0x06,},
118 {.bitrate = 180,.hw_value = 0x07,},
119 {.bitrate = 240,.hw_value = 0x08,},
120 {.bitrate = 360,.hw_value = 0x09,},
121 {.bitrate = 480,.hw_value = 0x0a,},
122 {.bitrate = 540,.hw_value = 0x0b,},
123};
124
125static struct ieee80211_rate rtl_ratetable_5g[] = {
126 {.bitrate = 60,.hw_value = 0x04,},
127 {.bitrate = 90,.hw_value = 0x05,},
128 {.bitrate = 120,.hw_value = 0x06,},
129 {.bitrate = 180,.hw_value = 0x07,},
130 {.bitrate = 240,.hw_value = 0x08,},
131 {.bitrate = 360,.hw_value = 0x09,},
132 {.bitrate = 480,.hw_value = 0x0a,},
133 {.bitrate = 540,.hw_value = 0x0b,},
134};
135
136static const struct ieee80211_supported_band rtl_band_2ghz = {
137 .band = IEEE80211_BAND_2GHZ,
138
139 .channels = rtl_channeltable_2g,
140 .n_channels = ARRAY_SIZE(rtl_channeltable_2g),
141
142 .bitrates = rtl_ratetable_2g,
143 .n_bitrates = ARRAY_SIZE(rtl_ratetable_2g),
144
145 .ht_cap = {0},
146};
147
148static struct ieee80211_supported_band rtl_band_5ghz = {
149 .band = IEEE80211_BAND_5GHZ,
150
151 .channels = rtl_channeltable_5g,
152 .n_channels = ARRAY_SIZE(rtl_channeltable_5g),
153
154 .bitrates = rtl_ratetable_5g,
155 .n_bitrates = ARRAY_SIZE(rtl_ratetable_5g),
156
157 .ht_cap = {0},
158};
159
160static const u8 tid_to_ac[] = {
161 2, /* IEEE80211_AC_BE */
162 3, /* IEEE80211_AC_BK */
163 3, /* IEEE80211_AC_BK */
164 2, /* IEEE80211_AC_BE */
165 1, /* IEEE80211_AC_VI */
166 1, /* IEEE80211_AC_VI */
167 0, /* IEEE80211_AC_VO */
168 0, /* IEEE80211_AC_VO */
169};
170
171u8 rtl_tid_to_ac(struct ieee80211_hw *hw, u8 tid)
172{
173 return tid_to_ac[tid];
174}
175
176static void _rtl_init_hw_ht_capab(struct ieee80211_hw *hw,
177 struct ieee80211_sta_ht_cap *ht_cap)
178{
179 struct rtl_priv *rtlpriv = rtl_priv(hw);
180 struct rtl_phy *rtlphy = &(rtlpriv->phy);
181
182 ht_cap->ht_supported = true;
183 ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
184 IEEE80211_HT_CAP_SGI_40 |
185 IEEE80211_HT_CAP_SGI_20 |
186 IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU;
187
188 if (rtlpriv->rtlhal.disable_amsdu_8k)
189 ht_cap->cap &= ~IEEE80211_HT_CAP_MAX_AMSDU;
190
191 /*
192 *Maximum length of AMPDU that the STA can receive.
193 *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets)
194 */
195 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
196
197 /*Minimum MPDU start spacing , */
198 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
199
200 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
201
202 /*
203 *hw->wiphy->bands[IEEE80211_BAND_2GHZ]
204 *base on ant_num
205 *rx_mask: RX mask
206 *if rx_ant =1 rx_mask[0]=0xff;==>MCS0-MCS7
207 *if rx_ant =2 rx_mask[1]=0xff;==>MCS8-MCS15
208 *if rx_ant >=3 rx_mask[2]=0xff;
209 *if BW_40 rx_mask[4]=0x01;
210 *highest supported RX rate
211 */
212 if (rtlpriv->dm.supp_phymode_switch) {
213 RT_TRACE(COMP_INIT, DBG_EMERG, ("Support phy mode switch\n"));
214
215 ht_cap->mcs.rx_mask[0] = 0xFF;
216 ht_cap->mcs.rx_mask[1] = 0xFF;
217 ht_cap->mcs.rx_mask[4] = 0x01;
218
219 ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS15;
220 } else {
221 if (get_rf_type(rtlphy) == RF_1T2R ||
222 get_rf_type(rtlphy) == RF_2T2R) {
223
224 RT_TRACE(COMP_INIT, DBG_DMESG, ("1T2R or 2T2R\n"));
225
226 ht_cap->mcs.rx_mask[0] = 0xFF;
227 ht_cap->mcs.rx_mask[1] = 0xFF;
228 ht_cap->mcs.rx_mask[4] = 0x01;
229
230 ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS15;
231 } else if (get_rf_type(rtlphy) == RF_1T1R) {
232
233 RT_TRACE(COMP_INIT, DBG_DMESG, ("1T1R\n"));
234
235 ht_cap->mcs.rx_mask[0] = 0xFF;
236 ht_cap->mcs.rx_mask[1] = 0x00;
237 ht_cap->mcs.rx_mask[4] = 0x01;
238
239 ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS7;
240 }
241 }
242}
243
244static void _rtl_init_mac80211(struct ieee80211_hw *hw)
245{
246 struct rtl_priv *rtlpriv = rtl_priv(hw);
247 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
248 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
249 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
250 struct ieee80211_supported_band *sband;
251
252
253 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
254 rtlhal->bandset == BAND_ON_BOTH) {
255 /* 1: 2.4 G bands */
256 /* <1> use mac->bands as mem for hw->wiphy->bands */
257 sband = &(rtlmac->bands[IEEE80211_BAND_2GHZ]);
258
259 /* <2> set hw->wiphy->bands[IEEE80211_BAND_2GHZ]
260 * to default value(1T1R) */
261 memcpy(&(rtlmac->bands[IEEE80211_BAND_2GHZ]), &rtl_band_2ghz,
262 sizeof(struct ieee80211_supported_band));
263
264 /* <3> init ht cap base on ant_num */
265 _rtl_init_hw_ht_capab(hw, &sband->ht_cap);
266
267 /* <4> set mac->sband to wiphy->sband */
268 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
269
270 /* 2: 5 G bands */
271 /* <1> use mac->bands as mem for hw->wiphy->bands */
272 sband = &(rtlmac->bands[IEEE80211_BAND_5GHZ]);
273
274 /* <2> set hw->wiphy->bands[IEEE80211_BAND_5GHZ]
275 * to default value(1T1R) */
276 memcpy(&(rtlmac->bands[IEEE80211_BAND_5GHZ]), &rtl_band_5ghz,
277 sizeof(struct ieee80211_supported_band));
278
279 /* <3> init ht cap base on ant_num */
280 _rtl_init_hw_ht_capab(hw, &sband->ht_cap);
281
282 /* <4> set mac->sband to wiphy->sband */
283 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
284 } else {
285 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
286 /* <1> use mac->bands as mem for hw->wiphy->bands */
287 sband = &(rtlmac->bands[IEEE80211_BAND_2GHZ]);
288
289 /* <2> set hw->wiphy->bands[IEEE80211_BAND_2GHZ]
290 * to default value(1T1R) */
291 memcpy(&(rtlmac->bands[IEEE80211_BAND_2GHZ]),
292 &rtl_band_2ghz,
293 sizeof(struct ieee80211_supported_band));
294
295 /* <3> init ht cap base on ant_num */
296 _rtl_init_hw_ht_capab(hw, &sband->ht_cap);
297
298 /* <4> set mac->sband to wiphy->sband */
299 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
300 } else if (rtlhal->current_bandtype == BAND_ON_5G) {
301 /* <1> use mac->bands as mem for hw->wiphy->bands */
302 sband = &(rtlmac->bands[IEEE80211_BAND_5GHZ]);
303
304 /* <2> set hw->wiphy->bands[IEEE80211_BAND_5GHZ]
305 * to default value(1T1R) */
306 memcpy(&(rtlmac->bands[IEEE80211_BAND_5GHZ]),
307 &rtl_band_5ghz,
308 sizeof(struct ieee80211_supported_band));
309
310 /* <3> init ht cap base on ant_num */
311 _rtl_init_hw_ht_capab(hw, &sband->ht_cap);
312
313 /* <4> set mac->sband to wiphy->sband */
314 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
315 } else {
316 RT_TRACE(COMP_INIT, DBG_EMERG, ("Err BAND %d\n",
317 rtlhal->current_bandtype));
318 }
319 }
320 /* <5> set hw caps */
321 hw->flags = IEEE80211_HW_SIGNAL_DBM |
322 IEEE80211_HW_RX_INCLUDES_FCS |
323#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0))
324 IEEE80211_HW_BEACON_FILTER |
325#endif
326 IEEE80211_HW_AMPDU_AGGREGATION |
327 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
328 IEEE80211_HW_CONNECTION_MONITOR |
329 /* IEEE80211_HW_SUPPORTS_CQM_RSSI | */
330 IEEE80211_HW_MFP_CAPABLE | 0;
331
332 /* swlps or hwlps has been set in diff chip in init_sw_vars */
333 if (rtlpriv->psc.b_swctrl_lps)
334 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
335 IEEE80211_HW_PS_NULLFUNC_STACK |
336 /* IEEE80211_HW_SUPPORTS_DYNAMIC_PS | */
337 0;
338/*<delete in kernel start>*/
339#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
340 hw->wiphy->interface_modes =
341 BIT(NL80211_IFTYPE_AP) |
342 BIT(NL80211_IFTYPE_STATION) |
343 BIT(NL80211_IFTYPE_ADHOC) |
344 BIT(NL80211_IFTYPE_MESH_POINT) |
345 BIT(NL80211_IFTYPE_P2P_CLIENT) |
346 BIT(NL80211_IFTYPE_P2P_GO);
347#else
348/*<delete in kernel end>*/
349 hw->wiphy->interface_modes =
350 BIT(NL80211_IFTYPE_AP) |
351 BIT(NL80211_IFTYPE_STATION) |
352 BIT(NL80211_IFTYPE_ADHOC) |
353 BIT(NL80211_IFTYPE_MESH_POINT) ;
354/*<delete in kernel start>*/
355#endif
356/*<delete in kernel end>*/
357#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,39))
358 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
359#endif
360
361#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0))
362 hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
363#endif
364
365 hw->wiphy->rts_threshold = 2347;
366
367 hw->queues = AC_MAX;
368 hw->extra_tx_headroom = RTL_TX_HEADER_SIZE;
369
370 /* TODO: Correct this value for our hw */
371 /* TODO: define these hard code value */
372 hw->max_listen_interval = 10;
373 hw->max_rate_tries = 4;
374 /* hw->max_rates = 1; */
375 hw->sta_data_size = sizeof(struct rtl_sta_info);
376#ifdef VIF_TODO
377 hw->vif_data_size = sizeof(struct rtl_vif_info);
378#endif
379
380 /* <6> mac address */
381 if (is_valid_ether_addr(rtlefuse->dev_addr)) {
382 SET_IEEE80211_PERM_ADDR(hw, rtlefuse->dev_addr);
383 } else {
384 u8 rtlmac[] = { 0x00, 0xe0, 0x4c, 0x81, 0x92, 0x00 };
385 get_random_bytes((rtlmac + (ETH_ALEN - 1)), 1);
386 SET_IEEE80211_PERM_ADDR(hw, rtlmac);
387 }
388
389}
390
391static void _rtl_init_deferred_work(struct ieee80211_hw *hw)
392{
393 struct rtl_priv *rtlpriv = rtl_priv(hw);
394
395 /* <1> timer */
396 init_timer(&rtlpriv->works.watchdog_timer);
397 setup_timer(&rtlpriv->works.watchdog_timer,
398 rtl_watch_dog_timer_callback, (unsigned long)hw);
399 init_timer(&rtlpriv->works.dualmac_easyconcurrent_retrytimer);
400 setup_timer(&rtlpriv->works.dualmac_easyconcurrent_retrytimer,
401 rtl_easy_concurrent_retrytimer_callback, (unsigned long)hw);
402 /* <2> work queue */
403 rtlpriv->works.hw = hw;
404/*<delete in kernel start>*/
405#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
406/*<delete in kernel end>*/
407 rtlpriv->works.rtl_wq = alloc_workqueue(rtlpriv->cfg->name, 0, 0);
408/*<delete in kernel start>*/
409#else
410 rtlpriv->works.rtl_wq = create_workqueue(rtlpriv->cfg->name);
411#endif
412/*<delete in kernel end>*/
413 INIT_DELAYED_WORK(&rtlpriv->works.watchdog_wq,
414 (void *)rtl_watchdog_wq_callback);
415 INIT_DELAYED_WORK(&rtlpriv->works.ips_nic_off_wq,
416 (void *)rtl_ips_nic_off_wq_callback);
417 INIT_DELAYED_WORK(&rtlpriv->works.ps_work,
418 (void *)rtl_swlps_wq_callback);
419 INIT_DELAYED_WORK(&rtlpriv->works.ps_rfon_wq,
420 (void *)rtl_swlps_rfon_wq_callback);
421 INIT_DELAYED_WORK(&rtlpriv->works.fwevt_wq,
422 (void *)rtl_fwevt_wq_callback);
423
424}
425
426void rtl_deinit_deferred_work(struct ieee80211_hw *hw)
427{
428 struct rtl_priv *rtlpriv = rtl_priv(hw);
429
430 del_timer_sync(&rtlpriv->works.watchdog_timer);
431
432 cancel_delayed_work(&rtlpriv->works.watchdog_wq);
433 cancel_delayed_work(&rtlpriv->works.ips_nic_off_wq);
434 cancel_delayed_work(&rtlpriv->works.ps_work);
435 cancel_delayed_work(&rtlpriv->works.ps_rfon_wq);
436 cancel_delayed_work(&rtlpriv->works.fwevt_wq);
437}
438
439void rtl_init_rfkill(struct ieee80211_hw *hw)
440{
441 struct rtl_priv *rtlpriv = rtl_priv(hw);
442
443 bool radio_state;
444 bool blocked;
445 u8 valid = 0;
446
447 /*set init state to on */
448 rtlpriv->rfkill.rfkill_state = 1;
449 wiphy_rfkill_set_hw_state(hw->wiphy, 0);
450
451 radio_state = rtlpriv->cfg->ops->radio_onoff_checking(hw, &valid);
452
453 if (valid) {
454 printk(KERN_INFO "rtlwifi: wireless switch is %s\n",
455 rtlpriv->rfkill.rfkill_state ? "on" : "off");
456
457 rtlpriv->rfkill.rfkill_state = radio_state;
458
459 blocked = (rtlpriv->rfkill.rfkill_state == 1) ? 0 : 1;
460 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
461 }
462
463 wiphy_rfkill_start_polling(hw->wiphy);
464}
465
466void rtl_deinit_rfkill(struct ieee80211_hw *hw)
467{
468 wiphy_rfkill_stop_polling(hw->wiphy);
469}
470
471#ifdef VIF_TODO
472static void rtl_init_vif(struct ieee80211_hw *hw)
473{
474 struct rtl_priv *rtlpriv = rtl_priv(hw);
475
476 INIT_LIST_HEAD(&rtlpriv->vif_priv.vif_list);
477
478 rtlpriv->vif_priv.vifs = 0;
479}
480#endif
481
482int rtl_init_core(struct ieee80211_hw *hw)
483{
484 struct rtl_priv *rtlpriv = rtl_priv(hw);
485 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
486
487 /* <1> init mac80211 */
488 _rtl_init_mac80211(hw);
489 rtlmac->hw = hw;
490 rtlmac->link_state = MAC80211_NOLINK;
491
492 /* <2> rate control register */
493 hw->rate_control_algorithm = "rtl_rc";
494
495 /*
496 * <3> init CRDA must come after init
497 * mac80211 hw in _rtl_init_mac80211.
498 */
499 if (rtl_regd_init(hw, rtl_reg_notifier)) {
500 RT_TRACE(COMP_ERR, DBG_EMERG, ("REGD init failed\n"));
501 return 1;
502 }
503
504 /* <4> locks */
505 mutex_init(&rtlpriv->locks.conf_mutex);
506 spin_lock_init(&rtlpriv->locks.ips_lock);
507 spin_lock_init(&rtlpriv->locks.irq_th_lock);
508 spin_lock_init(&rtlpriv->locks.h2c_lock);
509 spin_lock_init(&rtlpriv->locks.rf_ps_lock);
510 spin_lock_init(&rtlpriv->locks.rf_lock);
511 spin_lock_init(&rtlpriv->locks.lps_lock);
512 spin_lock_init(&rtlpriv->locks.waitq_lock);
513 spin_lock_init(&rtlpriv->locks.entry_list_lock);
514 spin_lock_init(&rtlpriv->locks.cck_and_rw_pagea_lock);
515 spin_lock_init(&rtlpriv->locks.check_sendpkt_lock);
516 spin_lock_init(&rtlpriv->locks.fw_ps_lock);
517 spin_lock_init(&rtlpriv->locks.iqk_lock);
518 /* <5> init list */
519 INIT_LIST_HEAD(&rtlpriv->entry_list);
520
521 /* <6> init deferred work */
522 _rtl_init_deferred_work(hw);
523
524 /* <7> */
525#ifdef VIF_TODO
526 rtl_init_vif(hw);
527#endif
528
529 return 0;
530}
531
532void rtl_deinit_core(struct ieee80211_hw *hw)
533{
534}
535
536void rtl_init_rx_config(struct ieee80211_hw *hw)
537{
538 struct rtl_priv *rtlpriv = rtl_priv(hw);
539 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
540
541 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *) (&mac->rx_conf));
542}
543
544/*********************************************************
545 *
546 * tx information functions
547 *
548 *********************************************************/
549static void _rtl_qurey_shortpreamble_mode(struct ieee80211_hw *hw,
550 struct rtl_tcb_desc *tcb_desc,
551 struct ieee80211_tx_info *info)
552{
553 struct rtl_priv *rtlpriv = rtl_priv(hw);
554 u8 rate_flag = info->control.rates[0].flags;
555
556 tcb_desc->use_shortpreamble = false;
557
558 /* 1M can only use Long Preamble. 11B spec */
559 if (tcb_desc->hw_rate == rtlpriv->cfg->maps[RTL_RC_CCK_RATE1M])
560 return;
561 else if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
562 tcb_desc->use_shortpreamble = true;
563
564 return;
565}
566
567static void _rtl_query_shortgi(struct ieee80211_hw *hw,
568 struct ieee80211_sta *sta,
569 struct rtl_tcb_desc *tcb_desc,
570 struct ieee80211_tx_info *info)
571{
572 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
573 u8 rate_flag = info->control.rates[0].flags;
574 u8 sgi_40 = 0, sgi_20 = 0, bw_40 = 0;
575 tcb_desc->use_shortgi = false;
576
577 if (sta == NULL)
578 return;
579
580 sgi_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40;
581 sgi_20 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20;
582
583 if (!(sta->ht_cap.ht_supported))
584 return;
585
586 if (!sgi_40 && !sgi_20)
587 return;
588
589 if (mac->opmode == NL80211_IFTYPE_STATION)
590 bw_40 = mac->bw_40;
591 else if (mac->opmode == NL80211_IFTYPE_AP ||
592 mac->opmode == NL80211_IFTYPE_ADHOC ||
593 mac->opmode == NL80211_IFTYPE_MESH_POINT)
594 bw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
595
596 if ((bw_40 == true) && sgi_40)
597 tcb_desc->use_shortgi = true;
598 else if ((bw_40 == false) && sgi_20)
599 tcb_desc->use_shortgi = true;
600
601 if (!(rate_flag & IEEE80211_TX_RC_SHORT_GI))
602 tcb_desc->use_shortgi = false;
603}
604
605static void _rtl_query_protection_mode(struct ieee80211_hw *hw,
606 struct rtl_tcb_desc *tcb_desc,
607 struct ieee80211_tx_info *info)
608{
609 struct rtl_priv *rtlpriv = rtl_priv(hw);
610 u8 rate_flag = info->control.rates[0].flags;
611
612 /* Common Settings */
613 tcb_desc->b_rts_stbc = false;
614 tcb_desc->b_cts_enable = false;
615 tcb_desc->rts_sc = 0;
616 tcb_desc->b_rts_bw = false;
617 tcb_desc->b_rts_use_shortpreamble = false;
618 tcb_desc->b_rts_use_shortgi = false;
619
620 if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT) {
621 /* Use CTS-to-SELF in protection mode. */
622 tcb_desc->b_rts_enable = true;
623 tcb_desc->b_cts_enable = true;
624 tcb_desc->rts_rate = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE24M];
625 } else if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
626 /* Use RTS-CTS in protection mode. */
627 tcb_desc->b_rts_enable = true;
628 tcb_desc->rts_rate = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE24M];
629 }
630}
631
632static void _rtl_txrate_selectmode(struct ieee80211_hw *hw,
633 struct ieee80211_sta *sta,
634 struct rtl_tcb_desc *tcb_desc)
635{
636 struct rtl_priv *rtlpriv = rtl_priv(hw);
637 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
638 struct rtl_sta_info *sta_entry = NULL;
639 u8 ratr_index = 7;
640
641 if (sta) {
642 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
643 ratr_index = sta_entry->ratr_index;
644 }
645 if (!tcb_desc->disable_ratefallback || !tcb_desc->use_driver_rate) {
646 if (mac->opmode == NL80211_IFTYPE_STATION) {
647 tcb_desc->ratr_index = 0;
648 } else if (mac->opmode == NL80211_IFTYPE_ADHOC ||
649 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
650 if (tcb_desc->b_multicast || tcb_desc->b_broadcast) {
651 tcb_desc->hw_rate =
652 rtlpriv->cfg->maps[RTL_RC_CCK_RATE2M];
653 tcb_desc->use_driver_rate = 1;
654 tcb_desc->ratr_index = RATR_INX_WIRELESS_MC;
655 } else {
656 tcb_desc->ratr_index = ratr_index;
657 }
658 } else if (mac->opmode == NL80211_IFTYPE_AP) {
659 tcb_desc->ratr_index = ratr_index;
660 }
661 }
662
663 if (rtlpriv->dm.b_useramask) {
664 tcb_desc->ratr_index = ratr_index;
665 /* TODO we will differentiate adhoc and station futrue */
666 if (mac->opmode == NL80211_IFTYPE_STATION ||
667 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
668 tcb_desc->mac_id = 0;
669
670 if (mac->mode == WIRELESS_MODE_N_24G) {
671 tcb_desc->ratr_index = RATR_INX_WIRELESS_NGB;
672 } else if (mac->mode == WIRELESS_MODE_N_5G) {
673 tcb_desc->ratr_index = RATR_INX_WIRELESS_NG;
674 } else if (mac->mode & WIRELESS_MODE_G) {
675 tcb_desc->ratr_index = RATR_INX_WIRELESS_GB;
676 } else if (mac->mode & WIRELESS_MODE_B) {
677 tcb_desc->ratr_index = RATR_INX_WIRELESS_B;
678 } else if (mac->mode & WIRELESS_MODE_A) {
679 tcb_desc->ratr_index = RATR_INX_WIRELESS_G;
680 }
681 } else if (mac->opmode == NL80211_IFTYPE_AP ||
682 mac->opmode == NL80211_IFTYPE_ADHOC) {
683 if (NULL != sta) {
684 if (sta->aid > 0) {
685 tcb_desc->mac_id = sta->aid + 1;
686 } else {
687 tcb_desc->mac_id = 1;
688 }
689 } else {
690 tcb_desc->mac_id = 0;
691 }
692 }
693 }
694}
695
696static void _rtl_query_bandwidth_mode(struct ieee80211_hw *hw,
697 struct ieee80211_sta *sta,
698 struct rtl_tcb_desc *tcb_desc)
699{
700 struct rtl_priv *rtlpriv = rtl_priv(hw);
701 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
702
703 tcb_desc->b_packet_bw = false;
704 if (!sta)
705 return;
706 if (mac->opmode == NL80211_IFTYPE_AP ||
707 mac->opmode == NL80211_IFTYPE_ADHOC ||
708 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
709 if (!(sta->ht_cap.ht_supported) ||
710 !(sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40))
711 return;
712 } else if (mac->opmode == NL80211_IFTYPE_STATION) {
713 if (!mac->bw_40 || !(sta->ht_cap.ht_supported))
714 return;
715 }
716 if (tcb_desc->b_multicast || tcb_desc->b_broadcast)
717 return;
718
719 /*use legency rate, shall use 20MHz */
720 if (tcb_desc->hw_rate <= rtlpriv->cfg->maps[RTL_RC_OFDM_RATE54M])
721 return;
722
723 tcb_desc->b_packet_bw = true;
724}
725
726static u8 _rtl_get_highest_n_rate(struct ieee80211_hw *hw,
727 struct ieee80211_sta *sta)
728{
729 struct rtl_priv *rtlpriv = rtl_priv(hw);
730 struct rtl_phy *rtlphy = &(rtlpriv->phy);
731 u8 hw_rate;
732
733 if ((get_rf_type(rtlphy) == RF_2T2R) && (sta->ht_cap.mcs.rx_mask[1]!=0))
734 hw_rate = rtlpriv->cfg->maps[RTL_RC_HT_RATEMCS15];
735 else
736 hw_rate = rtlpriv->cfg->maps[RTL_RC_HT_RATEMCS7];
737
738 return hw_rate;
739}
740
741void rtl_get_tcb_desc(struct ieee80211_hw *hw,
742 struct ieee80211_tx_info *info,
743 struct ieee80211_sta *sta,
744 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc)
745{
746 struct rtl_priv *rtlpriv = rtl_priv(hw);
747 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
748 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
749 struct ieee80211_rate *txrate;
750 u16 fc = rtl_get_fc(skb);
751
752 txrate = ieee80211_get_tx_rate(hw, info);
753 if (txrate != NULL)
754 tcb_desc->hw_rate = txrate->hw_value;
755
756 if (ieee80211_is_data(fc)) {
757 /*
758 *we set data rate INX 0
759 *in rtl_rc.c if skb is special data or
760 *mgt which need low data rate.
761 */
762
763 /*
764 *So tcb_desc->hw_rate is just used for
765 *special data and mgt frames
766 */
767 if (info->control.rates[0].idx == 0 ||
768 ieee80211_is_nullfunc(fc)) {
769 tcb_desc->use_driver_rate = true;
770 tcb_desc->ratr_index = RATR_INX_WIRELESS_MC;
771
772 tcb_desc->disable_ratefallback = 1;
773 } else {
774 /*
775 *because hw will nerver use hw_rate
776 *when tcb_desc->use_driver_rate = false
777 *so we never set highest N rate here,
778 *and N rate will all be controled by FW
779 *when tcb_desc->use_driver_rate = false
780 */
781 if (sta && (sta->ht_cap.ht_supported)) {
782 tcb_desc->hw_rate = _rtl_get_highest_n_rate(hw, sta);
783 } else {
784 if(rtlmac->mode == WIRELESS_MODE_B) {
785 tcb_desc->hw_rate =
786 rtlpriv->cfg->maps[RTL_RC_CCK_RATE11M];
787 } else {
788 tcb_desc->hw_rate =
789 rtlpriv->cfg->maps[RTL_RC_OFDM_RATE54M];
790 }
791 }
792 }
793
794 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)))
795 tcb_desc->b_multicast = 1;
796 else if (is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
797 tcb_desc->b_broadcast = 1;
798
799 _rtl_txrate_selectmode(hw, sta, tcb_desc);
800 _rtl_query_bandwidth_mode(hw, sta, tcb_desc);
801 _rtl_qurey_shortpreamble_mode(hw, tcb_desc, info);
802 _rtl_query_shortgi(hw, sta, tcb_desc, info);
803 _rtl_query_protection_mode(hw, tcb_desc, info);
804 } else {
805 tcb_desc->use_driver_rate = true;
806 tcb_desc->ratr_index = RATR_INX_WIRELESS_MC;
807 tcb_desc->disable_ratefallback = 1;
808 tcb_desc->mac_id = 0;
809 tcb_desc->b_packet_bw = false;
810 }
811}
812//EXPORT_SYMBOL(rtl_get_tcb_desc);
813
814bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb)
815{
816 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
817 struct rtl_priv *rtlpriv = rtl_priv(hw);
818 u16 fc = rtl_get_fc(skb);
819
820 if (rtlpriv->dm.supp_phymode_switch &&
821 mac->link_state < MAC80211_LINKED &&
822 (ieee80211_is_auth(fc) || ieee80211_is_probe_req(fc))) {
823 if (rtlpriv->cfg->ops->check_switch_to_dmdp)
824 rtlpriv->cfg->ops->check_switch_to_dmdp(hw);
825 }
826 if (ieee80211_is_auth(fc)) {
827 RT_TRACE(COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
828 rtl_ips_nic_on(hw);
829
830 mac->link_state = MAC80211_LINKING;
831 /* Dul mac */
832 rtlpriv->phy.b_need_iqk = true;
833
834 }
835
836 return true;
837}
838
839struct sk_buff *rtl_make_del_ba(struct ieee80211_hw *hw, u8 *sa,
840 u8 *bssid, u16 tid);
841bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
842{
843 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
844 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
845 struct rtl_priv *rtlpriv = rtl_priv(hw);
846 u16 fc = rtl_get_fc(skb);
847 u8 *act = (u8 *) (((u8 *) skb->data + MAC80211_3ADDR_LEN));
848 u8 category;
849
850 if (!ieee80211_is_action(fc))
851 return true;
852
853 category = *act;
854 act++;
855 switch (category) {
856 case ACT_CAT_BA:
857 switch (*act) {
858 case ACT_ADDBAREQ:
859 if (mac->act_scanning)
860 return false;
861
862 RT_TRACE((COMP_SEND | COMP_RECV), DBG_DMESG,
863 ("%s ACT_ADDBAREQ From :%pM\n",
864 is_tx ? "Tx" : "Rx", hdr->addr2));
865 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("req \n"),
866 skb->data, skb->len);
867 if (!is_tx) {
868 struct ieee80211_sta *sta = NULL;
869 struct rtl_sta_info *sta_entry = NULL;
870 struct ieee80211_mgmt *mgmt = (void *)skb->data;
871 u16 capab = 0, tid = 0;
872 struct rtl_tid_data *tid_data;
873 struct sk_buff *skb_delba = NULL;
874 struct ieee80211_rx_status rx_status = { 0 };
875
876 rcu_read_lock();
877 sta = rtl_find_sta(hw, hdr->addr3);
878 if (sta == NULL) {
879 RT_TRACE((COMP_SEND | COMP_RECV),
880 DBG_EMERG, ("sta is NULL\n"));
881 rcu_read_unlock();
882 return true;
883 }
884
885 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
886 if (!sta_entry) {
887 rcu_read_unlock();
888 return true;
889 }
890 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
891 tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2;
892 tid_data = &sta_entry->tids[tid];
893 if (tid_data->agg.rx_agg_state ==
894 RTL_RX_AGG_START) {
895 skb_delba = rtl_make_del_ba(hw,
896 hdr->addr2,
897 hdr->addr3,
898 tid);
899 if (skb_delba) {
900#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
901 rx_status.freq = hw->conf.chandef.chan->center_freq;
902 rx_status.band = hw->conf.chandef.chan->band;
903#else
904 rx_status.freq = hw->conf.channel->center_freq;
905 rx_status.band = hw->conf.channel->band;
906#endif
907 rx_status.flag |= RX_FLAG_DECRYPTED;
908 rx_status.flag |= RX_FLAG_MACTIME_MPDU;
909 rx_status.rate_idx = 0;
910 rx_status.signal = 50 + 10;
911 memcpy(IEEE80211_SKB_RXCB(skb_delba), &rx_status,
912 sizeof(rx_status));
913 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG,
914 ("fake del\n"), skb_delba->data,
915 skb_delba->len);
916 ieee80211_rx_irqsafe(hw, skb_delba);
917 }
918 }
919 rcu_read_unlock();
920 }
921 break;
922 case ACT_ADDBARSP:
923 RT_TRACE((COMP_SEND | COMP_RECV), DBG_DMESG,
924 ("%s ACT_ADDBARSP From :%pM\n",
925 is_tx ? "Tx" : "Rx", hdr->addr2));
926 break;
927 case ACT_DELBA:
928 RT_TRACE((COMP_SEND | COMP_RECV), DBG_DMESG,
929 ("ACT_ADDBADEL From :%pM\n", hdr->addr2));
930 break;
931 }
932 break;
933 default:
934 break;
935 }
936
937 return true;
938}
939
940/*should call before software enc*/
941u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
942{
943 struct rtl_priv *rtlpriv = rtl_priv(hw);
944 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
945 u16 fc = rtl_get_fc(skb);
946 u16 ether_type;
947 u8 mac_hdr_len = ieee80211_get_hdrlen_from_skb(skb);
948 const struct iphdr *ip;
949
950 if (!ieee80211_is_data(fc))
951 goto end;
952
953
954 ip = (struct iphdr *)((u8 *) skb->data + mac_hdr_len +
955 SNAP_SIZE + PROTOC_TYPE_SIZE);
956 ether_type = *(u16 *) ((u8 *) skb->data + mac_hdr_len + SNAP_SIZE);
957 ether_type = ntohs(ether_type);
958
959 if (ETH_P_IP == ether_type) {
960 if (IPPROTO_UDP == ip->protocol) {
961 struct udphdr *udp = (struct udphdr *)((u8 *) ip +
962 (ip->ihl << 2));
963 if (((((u8 *) udp)[1] == 68) &&
964 (((u8 *) udp)[3] == 67)) ||
965 ((((u8 *) udp)[1] == 67) &&
966 (((u8 *) udp)[3] == 68))) {
967 /*
968 * 68 : UDP BOOTP client
969 * 67 : UDP BOOTP server
970 */
971 RT_TRACE((COMP_SEND | COMP_RECV),
972 DBG_DMESG, ("dhcp %s !!\n",
973 (is_tx) ? "Tx" : "Rx"));
974
975 if (is_tx) {
976 rtlpriv->ra.is_special_data = true;
977 rtl_lps_leave(hw);
978 ppsc->last_delaylps_stamp_jiffies =
979 jiffies;
980 }
981
982 return true;
983 }
984 }
985 } else if (ETH_P_ARP == ether_type) {
986 if (is_tx) {
987 rtlpriv->ra.is_special_data = true;
988 rtl_lps_leave(hw);
989 ppsc->last_delaylps_stamp_jiffies = jiffies;
990 }
991
992 return true;
993 } else if (ETH_P_PAE == ether_type) {
994 RT_TRACE((COMP_SEND | COMP_RECV), DBG_DMESG,
995 ("802.1X %s EAPOL pkt!!\n", (is_tx) ? "Tx" : "Rx"));
996
997 if (is_tx) {
998 rtlpriv->ra.is_special_data = true;
999 rtl_lps_leave(hw);
1000 ppsc->last_delaylps_stamp_jiffies = jiffies;
1001 }
1002
1003 return true;
1004 } else if (0x86DD == ether_type) {
1005 return true;
1006 }
1007
1008end:
1009 rtlpriv->ra.is_special_data = false;
1010 return false;
1011}
1012
1013/*********************************************************
1014 *
1015 * functions called by core.c
1016 *
1017 *********************************************************/
1018int rtl_tx_agg_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1019 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1020{
1021 struct rtl_priv *rtlpriv = rtl_priv(hw);
1022 struct rtl_tid_data *tid_data;
1023 struct rtl_sta_info *sta_entry = NULL;
1024
1025 if (sta == NULL)
1026 return -EINVAL;
1027
1028 if (unlikely(tid >= MAX_TID_COUNT))
1029 return -EINVAL;
1030
1031 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1032 if (!sta_entry)
1033 return -ENXIO;
1034 tid_data = &sta_entry->tids[tid];
1035
1036 RT_TRACE(COMP_SEND, DBG_DMESG,
1037 ("on ra = %pM tid = %d seq:%d\n", sta->addr, tid,
1038 tid_data->seq_number));
1039
1040 *ssn = tid_data->seq_number;
1041 tid_data->agg.agg_state = RTL_AGG_START;
1042
1043 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1044 return 0;
1045}
1046
1047int rtl_tx_agg_stop(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1048 struct ieee80211_sta *sta, u16 tid)
1049{
1050 struct rtl_priv *rtlpriv = rtl_priv(hw);
1051 struct rtl_tid_data *tid_data;
1052 struct rtl_sta_info *sta_entry = NULL;
1053
1054 if (sta == NULL)
1055 return -EINVAL;
1056
1057 if (!sta->addr) {
1058 RT_TRACE(COMP_ERR, DBG_EMERG, ("ra = NULL\n"));
1059 return -EINVAL;
1060 }
1061
1062 RT_TRACE(COMP_SEND, DBG_DMESG,
1063 ("on ra = %pM tid = %d\n", sta->addr, tid));
1064
1065 if (unlikely(tid >= MAX_TID_COUNT))
1066 return -EINVAL;
1067
1068 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1069 tid_data = &sta_entry->tids[tid];
1070 sta_entry->tids[tid].agg.agg_state = RTL_AGG_STOP;
1071
1072 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1073 return 0;
1074}
1075
1076int rtl_rx_agg_start(struct ieee80211_hw *hw,
1077 struct ieee80211_sta *sta, u16 tid)
1078{
1079 struct rtl_priv *rtlpriv = rtl_priv(hw);
1080 struct rtl_tid_data *tid_data;
1081 struct rtl_sta_info *sta_entry = NULL;
1082
1083 if (sta == NULL)
1084 return -EINVAL;
1085
1086 if (unlikely(tid >= MAX_TID_COUNT))
1087 return -EINVAL;
1088
1089 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1090 if (!sta_entry)
1091 return -ENXIO;
1092 tid_data = &sta_entry->tids[tid];
1093
1094 RT_TRACE(COMP_RECV, DBG_DMESG,
1095 ("on ra = %pM tid = %d seq:%d\n", sta->addr, tid,
1096 tid_data->seq_number));
1097
1098 tid_data->agg.rx_agg_state = RTL_RX_AGG_START;
1099 return 0;
1100}
1101
1102int rtl_rx_agg_stop(struct ieee80211_hw *hw,
1103 struct ieee80211_sta *sta, u16 tid)
1104{
1105 struct rtl_priv *rtlpriv = rtl_priv(hw);
1106 struct rtl_tid_data *tid_data;
1107 struct rtl_sta_info *sta_entry = NULL;
1108
1109 if (sta == NULL)
1110 return -EINVAL;
1111
1112 if (!sta->addr) {
1113 RT_TRACE(COMP_ERR, DBG_EMERG, ("ra = NULL\n"));
1114 return -EINVAL;
1115 }
1116
1117 RT_TRACE(COMP_SEND, DBG_DMESG,
1118 ("on ra = %pM tid = %d\n", sta->addr, tid));
1119
1120 if (unlikely(tid >= MAX_TID_COUNT))
1121 return -EINVAL;
1122
1123 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1124 tid_data = &sta_entry->tids[tid];
1125 sta_entry->tids[tid].agg.rx_agg_state = RTL_RX_AGG_STOP;
1126
1127 return 0;
1128}
1129int rtl_tx_agg_oper(struct ieee80211_hw *hw,
1130 struct ieee80211_sta *sta, u16 tid)
1131{
1132 struct rtl_priv *rtlpriv = rtl_priv(hw);
1133 struct rtl_tid_data *tid_data;
1134 struct rtl_sta_info *sta_entry = NULL;
1135
1136 if (sta == NULL)
1137 return -EINVAL;
1138
1139 if (!sta->addr) {
1140 RT_TRACE(COMP_ERR, DBG_EMERG, ("ra = NULL\n"));
1141 return -EINVAL;
1142 }
1143
1144 RT_TRACE(COMP_SEND, DBG_DMESG,
1145 ("on ra = %pM tid = %d\n", sta->addr, tid));
1146
1147 if (unlikely(tid >= MAX_TID_COUNT))
1148 return -EINVAL;
1149
1150 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1151 tid_data = &sta_entry->tids[tid];
1152 sta_entry->tids[tid].agg.agg_state = RTL_AGG_OPERATIONAL;
1153
1154 return 0;
1155}
1156
1157/*********************************************************
1158 *
1159 * wq & timer callback functions
1160 *
1161 *********************************************************/
1162/* this function is used for roaming */
1163void rtl_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb)
1164{
1165 struct rtl_priv *rtlpriv = rtl_priv(hw);
1166 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1167
1168 if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
1169 return;
1170
1171 if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
1172 return;
1173
1174 /* check if this really is a beacon */
1175 if (!ieee80211_is_beacon(hdr->frame_control) &&
1176 !ieee80211_is_probe_resp(hdr->frame_control))
1177 return;
1178
1179 /* min. beacon length + FCS_LEN */
1180 if (skb->len <= 40 + FCS_LEN)
1181 return;
1182
1183 /* and only beacons from the associated BSSID, please */
1184 if (ether_addr_equal(hdr->addr3, rtlpriv->mac80211.bssid))
1185 return;
1186
1187 rtlpriv->link_info.bcn_rx_inperiod ++;
1188}
1189
1190void rtl_watchdog_wq_callback(void *data)
1191{
1192 struct rtl_works *rtlworks = container_of_dwork_rtl(data,
1193 struct rtl_works,
1194 watchdog_wq);
1195 struct ieee80211_hw *hw = rtlworks->hw;
1196 struct rtl_priv *rtlpriv = rtl_priv(hw);
1197 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1198 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1199 bool b_busytraffic = false;
1200 bool b_tx_busy_traffic = false;
1201 bool b_rx_busy_traffic = false;
1202 bool b_higher_busytraffic = false;
1203 bool b_higher_busyrxtraffic = false;
1204 u8 idx, tid;
1205 u32 rx_cnt_inp4eriod = 0;
1206 u32 tx_cnt_inp4eriod = 0;
1207 u32 aver_rx_cnt_inperiod = 0;
1208 u32 aver_tx_cnt_inperiod = 0;
1209 u32 aver_tidtx_inperiod[MAX_TID_COUNT] = {0};
1210 u32 tidtx_inp4eriod[MAX_TID_COUNT] = {0};
1211 bool benter_ps = false;
1212
1213 if (is_hal_stop(rtlhal))
1214 return;
1215
1216 /* <1> Determine if action frame is allowed */
1217 if (mac->link_state > MAC80211_NOLINK) {
1218 if (mac->cnt_after_linked < 20)
1219 mac->cnt_after_linked++;
1220 } else {
1221 mac->cnt_after_linked = 0;
1222 }
1223
1224 /* <2> to check if traffic busy, if
1225 * busytraffic we don't change channel */
1226 if (mac->link_state >= MAC80211_LINKED) {
1227
1228 /* (1) get aver_rx_cnt_inperiod & aver_tx_cnt_inperiod */
1229 for (idx = 0; idx <= 2; idx++) {
1230 rtlpriv->link_info.num_rx_in4period[idx] =
1231 rtlpriv->link_info.num_rx_in4period[idx + 1];
1232 rtlpriv->link_info.num_tx_in4period[idx] =
1233 rtlpriv->link_info.num_tx_in4period[idx + 1];
1234 }
1235 rtlpriv->link_info.num_rx_in4period[3] =
1236 rtlpriv->link_info.num_rx_inperiod;
1237 rtlpriv->link_info.num_tx_in4period[3] =
1238 rtlpriv->link_info.num_tx_inperiod;
1239 for (idx = 0; idx <= 3; idx++) {
1240 rx_cnt_inp4eriod +=
1241 rtlpriv->link_info.num_rx_in4period[idx];
1242 tx_cnt_inp4eriod +=
1243 rtlpriv->link_info.num_tx_in4period[idx];
1244 }
1245 aver_rx_cnt_inperiod = rx_cnt_inp4eriod / 4;
1246 aver_tx_cnt_inperiod = tx_cnt_inp4eriod / 4;
1247
1248 /* (2) check traffic busy */
1249 if (aver_rx_cnt_inperiod > 100 || aver_tx_cnt_inperiod > 100) {
1250 b_busytraffic = true;
1251 if (aver_rx_cnt_inperiod > aver_tx_cnt_inperiod)
1252 b_rx_busy_traffic = true;
1253 else
1254 b_tx_busy_traffic = false;
1255 }
1256
1257 /* Higher Tx/Rx data. */
1258 if (aver_rx_cnt_inperiod > 4000 ||
1259 aver_tx_cnt_inperiod > 4000) {
1260 b_higher_busytraffic = true;
1261
1262 /* Extremely high Rx data. */
1263 if (aver_rx_cnt_inperiod > 5000)
1264 b_higher_busyrxtraffic = true;
1265 }
1266
1267 /* check every tid's tx traffic */
1268 for (tid = 0; tid <= 7; tid++) {
1269 for (idx = 0; idx <= 2; idx++)
1270 rtlpriv->link_info.tidtx_in4period[tid][idx] =
1271 rtlpriv->link_info.tidtx_in4period[tid]
1272 [idx + 1];
1273 rtlpriv->link_info.tidtx_in4period[tid][3] =
1274 rtlpriv->link_info.tidtx_inperiod[tid];
1275
1276 for (idx = 0; idx <= 3; idx++)
1277 tidtx_inp4eriod[tid] +=
1278 rtlpriv->link_info.tidtx_in4period[tid][idx];
1279 aver_tidtx_inperiod[tid] = tidtx_inp4eriod[tid] / 4;
1280 if (aver_tidtx_inperiod[tid] > 5000)
1281 rtlpriv->link_info.higher_busytxtraffic[tid] =
1282 true;
1283 else
1284 rtlpriv->link_info.higher_busytxtraffic[tid] =
1285 false;
1286 }
1287
1288 if (((rtlpriv->link_info.num_rx_inperiod +
1289 rtlpriv->link_info.num_tx_inperiod) > 8) ||
1290 (rtlpriv->link_info.num_rx_inperiod > 2))
1291 benter_ps = false;
1292 else
1293 benter_ps = true;
1294
1295 /* LeisurePS only work in infra mode. */
1296 if (benter_ps)
1297 rtl_lps_enter(hw);
1298 else
1299 rtl_lps_leave(hw);
1300 }
1301
1302 rtlpriv->link_info.num_rx_inperiod = 0;
1303 rtlpriv->link_info.num_tx_inperiod = 0;
1304 for (tid = 0; tid <= 7; tid++)
1305 rtlpriv->link_info.tidtx_inperiod[tid] = 0;
1306
1307 rtlpriv->link_info.b_busytraffic = b_busytraffic;
1308 rtlpriv->link_info.b_rx_busy_traffic = b_rx_busy_traffic;
1309 rtlpriv->link_info.b_tx_busy_traffic = b_tx_busy_traffic;
1310 rtlpriv->link_info.b_higher_busytraffic = b_higher_busytraffic;
1311 rtlpriv->link_info.b_higher_busyrxtraffic = b_higher_busyrxtraffic;
1312
1313 /* <3> DM */
1314 rtlpriv->cfg->ops->dm_watchdog(hw);
1315
1316 /* <4> roaming */
1317 if (mac->link_state == MAC80211_LINKED &&
1318 mac->opmode == NL80211_IFTYPE_STATION) {
1319 if ((rtlpriv->link_info.bcn_rx_inperiod +
1320 rtlpriv->link_info.num_rx_inperiod) == 0) {
1321 rtlpriv->link_info.roam_times++;
1322 RT_TRACE(COMP_ERR, DBG_DMESG, ("AP off for %d s\n",
1323 (rtlpriv->link_info.roam_times * 2)));
1324
1325 /* if we can't recv beacon for 10s,
1326 * we should reconnect this AP */
1327 if (rtlpriv->link_info.roam_times >= 5) {
1328 RT_TRACE(COMP_ERR, DBG_EMERG,
1329 ("AP off, try to reconnect now\n"));
1330 rtlpriv->link_info.roam_times = 0;
1331 ieee80211_connection_loss(rtlpriv->mac80211.vif);
1332 }
1333 } else {
1334 rtlpriv->link_info.roam_times = 0;
1335 }
1336 }
1337 rtlpriv->link_info.bcn_rx_inperiod = 0;
1338}
1339
1340void rtl_watch_dog_timer_callback(unsigned long data)
1341{
1342 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
1343 struct rtl_priv *rtlpriv = rtl_priv(hw);
1344
1345 queue_delayed_work(rtlpriv->works.rtl_wq,
1346 &rtlpriv->works.watchdog_wq, 0);
1347
1348 mod_timer(&rtlpriv->works.watchdog_timer,
1349 jiffies + MSECS(RTL_WATCH_DOG_TIME));
1350}
1351void rtl_fwevt_wq_callback(void *data)
1352{
1353 struct rtl_works *rtlworks =
1354 container_of_dwork_rtl(data, struct rtl_works, fwevt_wq);
1355 struct ieee80211_hw *hw = rtlworks->hw;
1356 struct rtl_priv *rtlpriv = rtl_priv(hw);
1357
1358 rtlpriv->cfg->ops->c2h_command_handle(hw);
1359}
1360void rtl_easy_concurrent_retrytimer_callback(unsigned long data)
1361{
1362 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
1363 struct rtl_priv *rtlpriv = rtl_priv(hw);
1364 struct rtl_priv *buddy_priv = rtlpriv->buddy_priv;
1365
1366 if(buddy_priv == NULL)
1367 return;
1368
1369 rtlpriv->cfg->ops->dualmac_easy_concurrent(hw);
1370}
1371/*********************************************************
1372 *
1373 * frame process functions
1374 *
1375 *********************************************************/
1376u8 *rtl_find_ie(u8 *data, unsigned int len, u8 ie)
1377{
1378 struct ieee80211_mgmt *mgmt = (void *)data;
1379 u8 *pos, *end;
1380
1381 pos = (u8 *)mgmt->u.beacon.variable;
1382 end = data + len;
1383 while (pos < end) {
1384 if (pos + 2 + pos[1] > end)
1385 return NULL;
1386
1387 if (pos[0] == ie)
1388 return pos;
1389
1390 pos += 2 + pos[1];
1391 }
1392 return NULL;
1393}
1394
1395/* when we use 2 rx ants we send IEEE80211_SMPS_OFF */
1396/* when we use 1 rx ant we send IEEE80211_SMPS_STATIC */
1397struct sk_buff *rtl_make_smps_action(struct ieee80211_hw *hw,
1398 enum ieee80211_smps_mode smps,
1399 u8 *da, u8 *bssid)
1400{
1401 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1402 struct sk_buff *skb;
1403 struct ieee80211_mgmt_compat *action_frame;
1404
1405 /* 27 = header + category + action + smps mode */
1406 skb = dev_alloc_skb(27 + hw->extra_tx_headroom);
1407 if (!skb)
1408 return NULL;
1409
1410 skb_reserve(skb, hw->extra_tx_headroom);
1411 action_frame = (void *)skb_put(skb, 27);
1412 memset(action_frame, 0, 27);
1413 memcpy(action_frame->da, da, ETH_ALEN);
1414 memcpy(action_frame->sa, rtlefuse->dev_addr, ETH_ALEN);
1415 memcpy(action_frame->bssid, bssid, ETH_ALEN);
1416 action_frame->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1417 IEEE80211_STYPE_ACTION);
1418 action_frame->u.action.category = WLAN_CATEGORY_HT;
1419 action_frame->u.action.u.ht_smps.action = WLAN_HT_ACTION_SMPS;
1420 switch (smps) {
1421 case IEEE80211_SMPS_AUTOMATIC:/* 0 */
1422 case IEEE80211_SMPS_NUM_MODES:/* 4 */
1423 WARN_ON(1);
1424 case IEEE80211_SMPS_OFF:/* 1 */ /*MIMO_PS_NOLIMIT*/
1425 action_frame->u.action.u.ht_smps.smps_control =
1426 WLAN_HT_SMPS_CONTROL_DISABLED;/* 0 */
1427 break;
1428 case IEEE80211_SMPS_STATIC:/* 2 */ /*MIMO_PS_STATIC*/
1429 action_frame->u.action.u.ht_smps.smps_control =
1430 WLAN_HT_SMPS_CONTROL_STATIC;/* 1 */
1431 break;
1432 case IEEE80211_SMPS_DYNAMIC:/* 3 */ /*MIMO_PS_DYNAMIC*/
1433 action_frame->u.action.u.ht_smps.smps_control =
1434 WLAN_HT_SMPS_CONTROL_DYNAMIC;/* 3 */
1435 break;
1436 }
1437
1438 return skb;
1439}
1440
1441int rtl_send_smps_action(struct ieee80211_hw *hw,
1442 struct ieee80211_sta *sta,
1443 enum ieee80211_smps_mode smps)
1444{
1445 struct rtl_priv *rtlpriv = rtl_priv(hw);
1446 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1447 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1448 struct sk_buff *skb = NULL;
1449 struct rtl_tcb_desc tcb_desc;
1450 u8 bssid[ETH_ALEN] = {0};
1451
1452 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1453
1454 if (rtlpriv->mac80211.act_scanning)
1455 goto err_free;
1456
1457 if (!sta)
1458 goto err_free;
1459
1460 if (unlikely(is_hal_stop(rtlhal) || ppsc->rfpwr_state != ERFON))
1461 goto err_free;
1462
1463 if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
1464 goto err_free;
1465
1466 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP)
1467 memcpy(bssid, rtlpriv->efuse.dev_addr, ETH_ALEN);
1468 else
1469 memcpy(bssid, rtlpriv->mac80211.bssid, ETH_ALEN);
1470
1471 skb = rtl_make_smps_action(hw, smps, sta->addr, bssid);
1472 /* this is a type = mgmt * stype = action frame */
1473 if (skb) {
1474 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1475 struct rtl_sta_info *sta_entry =
1476 (struct rtl_sta_info *) sta->drv_priv;
1477 sta_entry->mimo_ps = smps;
1478 /* rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 0); */
1479
1480 info->control.rates[0].idx = 0;
1481#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
1482 info->band = hw->conf.chandef.chan->band;
1483#else
1484 info->band = hw->conf.channel->band;
1485#endif
1486/*<delete in kernel start>*/
1487#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1488 info->control.sta = sta;
1489 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
1490#else
1491/*<delete in kernel end>*/
1492 rtlpriv->intf_ops->adapter_tx(hw, sta, skb, &tcb_desc);
1493/*<delete in kernel start>*/
1494#endif
1495/*<delete in kernel end>*/
1496 }
1497 return 1;
1498
1499err_free:
1500 return 0;
1501}
1502//EXPORT_SYMBOL(rtl_send_smps_action);
1503
1504/* because mac80211 have issues when can receive del ba
1505 * so here we just make a fake del_ba if we receive a ba_req
1506 * but rx_agg was opened to let mac80211 release some ba
1507 * related resources, so please this del_ba for tx */
1508struct sk_buff *rtl_make_del_ba(struct ieee80211_hw *hw,
1509 u8 *sa, u8 *bssid, u16 tid)
1510{
1511 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1512 struct sk_buff *skb;
1513 struct ieee80211_mgmt *action_frame;
1514 u16 params;
1515
1516 /* 27 = header + category + action + smps mode */
1517 skb = dev_alloc_skb(34 + hw->extra_tx_headroom);
1518 if (!skb)
1519 return NULL;
1520
1521 skb_reserve(skb, hw->extra_tx_headroom);
1522 action_frame = (void *)skb_put(skb, 34);
1523 memset(action_frame, 0, 34);
1524 memcpy(action_frame->sa, sa, ETH_ALEN);
1525 memcpy(action_frame->da, rtlefuse->dev_addr, ETH_ALEN);
1526 memcpy(action_frame->bssid, bssid, ETH_ALEN);
1527 action_frame->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1528 IEEE80211_STYPE_ACTION);
1529 action_frame->u.action.category = WLAN_CATEGORY_BACK;
1530 action_frame->u.action.u.delba.action_code = WLAN_ACTION_DELBA;
1531 params = (u16)(1 << 11); /* bit 11 initiator */
1532 params |= (u16)(tid << 12); /* bit 15:12 TID number */
1533
1534 action_frame->u.action.u.delba.params = cpu_to_le16(params);
1535 action_frame->u.action.u.delba.reason_code =
1536 cpu_to_le16(WLAN_REASON_QSTA_TIMEOUT);
1537
1538 return skb;
1539}
1540
1541/*********************************************************
1542 *
1543 * IOT functions
1544 *
1545 *********************************************************/
1546static bool rtl_chk_vendor_ouisub(struct ieee80211_hw *hw,
1547 struct octet_string vendor_ie)
1548{
1549 struct rtl_priv *rtlpriv = rtl_priv(hw);
1550 bool matched = false;
1551 static u8 athcap_1[] = { 0x00, 0x03, 0x7F };
1552 static u8 athcap_2[] = { 0x00, 0x13, 0x74 };
1553 static u8 broadcap_1[] = { 0x00, 0x10, 0x18 };
1554 static u8 broadcap_2[] = { 0x00, 0x0a, 0xf7 };
1555 static u8 broadcap_3[] = { 0x00, 0x05, 0xb5 };
1556 static u8 racap[] = { 0x00, 0x0c, 0x43 };
1557 static u8 ciscocap[] = { 0x00, 0x40, 0x96 };
1558 static u8 marvcap[] = { 0x00, 0x50, 0x43 };
1559
1560 if (memcmp(vendor_ie.octet, athcap_1, 3) == 0 ||
1561 memcmp(vendor_ie.octet, athcap_2, 3) == 0) {
1562 rtlpriv->mac80211.vendor = PEER_ATH;
1563 matched = true;
1564 } else if (memcmp(vendor_ie.octet, broadcap_1, 3) == 0 ||
1565 memcmp(vendor_ie.octet, broadcap_2, 3) == 0 ||
1566 memcmp(vendor_ie.octet, broadcap_3, 3) == 0) {
1567 rtlpriv->mac80211.vendor = PEER_BROAD;
1568 matched = true;
1569 } else if (memcmp(vendor_ie.octet, racap, 3) == 0) {
1570 rtlpriv->mac80211.vendor = PEER_RAL;
1571 matched = true;
1572 } else if (memcmp(vendor_ie.octet, ciscocap, 3) == 0) {
1573 rtlpriv->mac80211.vendor = PEER_CISCO;
1574 matched = true;
1575 } else if (memcmp(vendor_ie.octet, marvcap, 3) == 0) {
1576 rtlpriv->mac80211.vendor = PEER_MARV;
1577 matched = true;
1578 }
1579
1580 return matched;
1581}
1582
1583bool rtl_find_221_ie(struct ieee80211_hw *hw, u8 *data,
1584 unsigned int len)
1585{
1586 struct ieee80211_mgmt *mgmt = (void *)data;
1587 struct octet_string vendor_ie;
1588 u8 *pos, *end;
1589
1590 pos = (u8 *)mgmt->u.beacon.variable;
1591 end = data + len;
1592 while (pos < end) {
1593 if (pos[0] == 221) {
1594 vendor_ie.length = pos[1];
1595 vendor_ie.octet = &pos[2];
1596 if (rtl_chk_vendor_ouisub(hw, vendor_ie))
1597 return true;
1598 }
1599
1600 if (pos + 2 + pos[1] > end)
1601 return false;
1602
1603 pos += 2 + pos[1];
1604 }
1605 return false;
1606}
1607
1608void rtl_recognize_peer(struct ieee80211_hw *hw, u8 *data, unsigned int len)
1609{
1610 struct rtl_priv *rtlpriv = rtl_priv(hw);
1611 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1612 struct ieee80211_hdr *hdr = (void *)data;
1613 u32 vendor = PEER_UNKNOWN;
1614
1615 static u8 ap3_1[3] = { 0x00, 0x14, 0xbf };
1616 static u8 ap3_2[3] = { 0x00, 0x1a, 0x70 };
1617 static u8 ap3_3[3] = { 0x00, 0x1d, 0x7e };
1618 static u8 ap4_1[3] = { 0x00, 0x90, 0xcc };
1619 static u8 ap4_2[3] = { 0x00, 0x0e, 0x2e };
1620 static u8 ap4_3[3] = { 0x00, 0x18, 0x02 };
1621 static u8 ap4_4[3] = { 0x00, 0x17, 0x3f };
1622 static u8 ap4_5[3] = { 0x00, 0x1c, 0xdf };
1623 static u8 ap5_1[3] = { 0x00, 0x1c, 0xf0 };
1624 static u8 ap5_2[3] = { 0x00, 0x21, 0x91 };
1625 static u8 ap5_3[3] = { 0x00, 0x24, 0x01 };
1626 static u8 ap5_4[3] = { 0x00, 0x15, 0xe9 };
1627 static u8 ap5_5[3] = { 0x00, 0x17, 0x9A };
1628 static u8 ap5_6[3] = { 0x00, 0x18, 0xE7 };
1629 static u8 ap6_1[3] = { 0x00, 0x17, 0x94 };
1630 static u8 ap7_1[3] = { 0x00, 0x14, 0xa4 };
1631
1632 if (mac->opmode != NL80211_IFTYPE_STATION)
1633 return;
1634
1635 if (mac->link_state == MAC80211_NOLINK) {
1636 mac->vendor = PEER_UNKNOWN;
1637 return;
1638 }
1639
1640 if (mac->cnt_after_linked > 2)
1641 return;
1642
1643 /* check if this really is a beacon */
1644 if (!ieee80211_is_beacon(hdr->frame_control))
1645 return;
1646
1647 /* min. beacon length + FCS_LEN */
1648 if (len <= 40 + FCS_LEN)
1649 return;
1650
1651 /* and only beacons from the associated BSSID, please */
1652 if (ether_addr_equal(hdr->addr3, rtlpriv->mac80211.bssid))
1653 return;
1654
1655 if (rtl_find_221_ie(hw, data, len)) {
1656 vendor = mac->vendor;
1657 }
1658
1659 if ((memcmp(mac->bssid, ap5_1, 3) == 0) ||
1660 (memcmp(mac->bssid, ap5_2, 3) == 0) ||
1661 (memcmp(mac->bssid, ap5_3, 3) == 0) ||
1662 (memcmp(mac->bssid, ap5_4, 3) == 0) ||
1663 (memcmp(mac->bssid, ap5_5, 3) == 0) ||
1664 (memcmp(mac->bssid, ap5_6, 3) == 0) ||
1665 vendor == PEER_ATH) {
1666 vendor = PEER_ATH;
1667 RT_TRACE(COMP_MAC80211, DBG_LOUD, ("=>ath find\n"));
1668 } else if ((memcmp(mac->bssid, ap4_4, 3) == 0) ||
1669 (memcmp(mac->bssid, ap4_5, 3) == 0) ||
1670 (memcmp(mac->bssid, ap4_1, 3) == 0) ||
1671 (memcmp(mac->bssid, ap4_2, 3) == 0) ||
1672 (memcmp(mac->bssid, ap4_3, 3) == 0) ||
1673 vendor == PEER_RAL) {
1674 RT_TRACE(COMP_MAC80211, DBG_LOUD, ("=>ral findn\n"));
1675 vendor = PEER_RAL;
1676 } else if (memcmp(mac->bssid, ap6_1, 3) == 0 ||
1677 vendor == PEER_CISCO) {
1678 vendor = PEER_CISCO;
1679 RT_TRACE(COMP_MAC80211, DBG_LOUD, ("=>cisco find\n"));
1680 } else if ((memcmp(mac->bssid, ap3_1, 3) == 0) ||
1681 (memcmp(mac->bssid, ap3_2, 3) == 0) ||
1682 (memcmp(mac->bssid, ap3_3, 3) == 0) ||
1683 vendor == PEER_BROAD) {
1684 RT_TRACE(COMP_MAC80211, DBG_LOUD, ("=>broad find\n"));
1685 vendor = PEER_BROAD;
1686 } else if (memcmp(mac->bssid, ap7_1, 3) == 0 ||
1687 vendor == PEER_MARV) {
1688 vendor = PEER_MARV;
1689 RT_TRACE(COMP_MAC80211, DBG_LOUD, ("=>marv find\n"));
1690 }
1691
1692 mac->vendor = vendor;
1693}
1694
1695/*********************************************************
1696 *
1697 * sysfs functions
1698 *
1699 *********************************************************/
1700static ssize_t rtl_show_debug_level(struct device *d,
1701 struct device_attribute *attr, char *buf)
1702{
1703 struct ieee80211_hw *hw = dev_get_drvdata(d);
1704 struct rtl_priv *rtlpriv = rtl_priv(hw);
1705
1706 return sprintf(buf, "0x%08X\n", rtlpriv->dbg.global_debuglevel);
1707}
1708
1709static ssize_t rtl_store_debug_level(struct device *d,
1710 struct device_attribute *attr,
1711 const char *buf, size_t count)
1712{
1713 struct ieee80211_hw *hw = dev_get_drvdata(d);
1714 struct rtl_priv *rtlpriv = rtl_priv(hw);
1715 unsigned long val;
1716 int ret;
1717
1718 ret = strict_strtoul(buf, 0, &val);
1719 if (ret) {
1720 printk(KERN_DEBUG "%s is not in hex or decimal form.\n", buf);
1721 } else {
1722 rtlpriv->dbg.global_debuglevel = val;
1723 printk(KERN_DEBUG "debuglevel:%x\n",
1724 rtlpriv->dbg.global_debuglevel);
1725 }
1726
1727 return strnlen(buf, count);
1728}
1729
1730static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1731 rtl_show_debug_level, rtl_store_debug_level);
1732
1733static struct attribute *rtl_sysfs_entries[] = {
1734
1735 &dev_attr_debug_level.attr,
1736
1737 NULL
1738};
1739
1740/*
1741 * "name" is folder name witch will be
1742 * put in device directory like :
1743 * sys/devices/pci0000:00/0000:00:1c.4/
1744 * 0000:06:00.0/rtl_sysfs
1745 */
1746struct attribute_group rtl_attribute_group = {
1747 .name = "rtlsysfs",
1748 .attrs = rtl_sysfs_entries,
1749};
1750
1751#ifdef VIF_TODO
1752/*********************************************************
1753 *
1754 * vif functions
1755 *
1756 *********************************************************/
1757static inline struct ieee80211_vif *
1758rtl_get_vif(struct rtl_vif_info *vif_priv)
1759{
1760 return container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
1761}
1762
1763/* Protected by ar->mutex or RCU */
1764struct ieee80211_vif *rtl_get_main_vif(struct ieee80211_hw *hw)
1765{
1766 struct rtl_priv *rtlpriv = rtl_priv(hw);
1767 struct rtl_vif_info *cvif;
1768
1769 list_for_each_entry_rcu(cvif, &rtlpriv->vif_priv.vif_list, list) {
1770 if (cvif->active)
1771 return rtl_get_vif(cvif);
1772 }
1773
1774 return NULL;
1775}
1776
1777static inline bool is_main_vif(struct ieee80211_hw *hw,
1778 struct ieee80211_vif *vif)
1779{
1780 bool ret;
1781
1782 rcu_read_lock();
1783 ret = (rtl_get_main_vif(hw) == vif);
1784 rcu_read_unlock();
1785 return ret;
1786}
1787
1788bool rtl_set_vif_info(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1789{
1790 struct rtl_vif_info *vif_info = (void *) vif->drv_priv;
1791 struct rtl_priv *rtlpriv = rtl_priv(hw);
1792 int vif_id = -1;
1793
1794 if (rtlpriv->vif_priv.vifs >= MAX_VIRTUAL_MAC) {
1795 RT_TRACE(COMP_ERR, DBG_WARNING,
1796 ("vif number can not bigger than %d, now vifs is:%d\n",
1797 MAX_VIRTUAL_MAC, rtlpriv->vif_priv.vifs));
1798 return false;
1799 }
1800
1801 rcu_read_lock();
1802 vif_id = bitmap_find_free_region(&rtlpriv->vif_priv.vif_bitmap,
1803 MAX_VIRTUAL_MAC, 0);
1804 RT_TRACE(COMP_MAC80211, DBG_DMESG,
1805 ("%s vid_id:%d\n", __func__, vif_id));
1806
1807 if (vif_id < 0) {
1808 rcu_read_unlock();
1809 return false;
1810 }
1811
1812 BUG_ON(rtlpriv->vif_priv.vif[vif_id].id != vif_id);
1813 vif_info->active = true;
1814 vif_info->id = vif_id;
1815 vif_info->enable_beacon = false;
1816 rtlpriv->vif_priv.vifs++;
1817 if (rtlpriv->vif_priv.vifs > 1) {
1818 rtlpriv->psc.b_inactiveps = false;
1819 rtlpriv->psc.b_swctrl_lps = false;
1820 rtlpriv->psc.b_fwctrl_lps = false;
1821 }
1822
1823 list_add_tail_rcu(&vif_info->list, &rtlpriv->vif_priv.vif_list);
1824 rcu_assign_pointer(rtlpriv->vif_priv.vif[vif_id].vif, vif);
1825
1826 RT_TRACE(COMP_MAC80211, DBG_DMESG, ("vifaddress:%p %p %p\n",
1827 rtlpriv->vif_priv.vif[vif_id].vif, vif, rtl_get_main_vif(hw)));
1828
1829 rcu_read_unlock();
1830
1831 return true;
1832}
1833#endif
1834
1835
1836#if 0
1837MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
1838MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
1839MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
1840MODULE_LICENSE("GPL");
1841MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
1842#endif
1843struct rtl_global_var global_var = {};
1844
1845int rtl_core_module_init(void)
1846{
1847 if (rtl_rate_control_register())
1848 printk(KERN_DEBUG "rtl: Unable to register rtl_rc,"
1849 "use default RC !!\n");
1850
1851 /* add proc for debug */
1852 rtl_proc_add_topdir();
1853
1854 /* init some global vars */
1855 INIT_LIST_HEAD(&global_var.glb_priv_list);
1856 spin_lock_init(&global_var.glb_list_lock);
1857
1858 return 0;
1859}
1860
1861void rtl_core_module_exit(void)
1862{
1863 /*RC*/
1864 rtl_rate_control_unregister();
1865
1866 /* add proc for debug */
1867 rtl_proc_remove_topdir();
1868}
1869
1870#if 0
1871module_init(rtl_core_module_init);
1872module_exit(rtl_core_module_exit);
1873#endif
diff --git a/drivers/staging/rtl8821ae/base.h b/drivers/staging/rtl8821ae/base.h
new file mode 100644
index 000000000000..629d14f42f0b
--- /dev/null
+++ b/drivers/staging/rtl8821ae/base.h
@@ -0,0 +1,159 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_BASE_H__
31#define __RTL_BASE_H__
32
33#include "compat.h"
34
35enum ap_peer {
36 PEER_UNKNOWN = 0,
37 PEER_RTL = 1,
38 PEER_RTL_92SE = 2,
39 PEER_BROAD = 3,
40 PEER_RAL = 4,
41 PEER_ATH = 5,
42 PEER_CISCO = 6,
43 PEER_MARV = 7,
44 PEER_AIRGO = 9,
45 PEER_MAX = 10,
46} ;
47
48#define RTL_DUMMY_OFFSET 0
49#define RTL_DUMMY_UNIT 8
50#define RTL_TX_DUMMY_SIZE (RTL_DUMMY_OFFSET * RTL_DUMMY_UNIT)
51#define RTL_TX_DESC_SIZE 32
52#define RTL_TX_HEADER_SIZE (RTL_TX_DESC_SIZE + RTL_TX_DUMMY_SIZE)
53
54#define HT_AMSDU_SIZE_4K 3839
55#define HT_AMSDU_SIZE_8K 7935
56
57#define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */
58#define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */
59
60#define RTL_RATE_COUNT_LEGACY 12
61#define RTL_CHANNEL_COUNT 14
62
63#define FRAME_OFFSET_FRAME_CONTROL 0
64#define FRAME_OFFSET_DURATION 2
65#define FRAME_OFFSET_ADDRESS1 4
66#define FRAME_OFFSET_ADDRESS2 10
67#define FRAME_OFFSET_ADDRESS3 16
68#define FRAME_OFFSET_SEQUENCE 22
69#define FRAME_OFFSET_ADDRESS4 24
70
71#define SET_80211_HDR_FRAME_CONTROL(_hdr, _val) \
72 WRITEEF2BYTE(_hdr, _val)
73#define SET_80211_HDR_TYPE_AND_SUBTYPE(_hdr, _val) \
74 WRITEEF1BYTE(_hdr, _val)
75#define SET_80211_HDR_PWR_MGNT(_hdr, _val) \
76 SET_BITS_TO_LE_2BYTE(_hdr, 12, 1, _val)
77#define SET_80211_HDR_TO_DS(_hdr, _val) \
78 SET_BITS_TO_LE_2BYTE(_hdr, 8, 1, _val)
79
80#define SET_80211_PS_POLL_AID(_hdr, _val) \
81 WRITEEF2BYTE(((u8*)(_hdr))+2, _val)
82#define SET_80211_PS_POLL_BSSID(_hdr, _val) \
83 CP_MACADDR(((u8*)(_hdr))+4, (u8*)(_val))
84#define SET_80211_PS_POLL_TA(_hdr, _val) \
85 CP_MACADDR(((u8*)(_hdr))+10, (u8*)(_val))
86
87#define SET_80211_HDR_DURATION(_hdr, _val) \
88 WRITEEF2BYTE((u8*)(_hdr)+FRAME_OFFSET_DURATION, _val)
89#define SET_80211_HDR_ADDRESS1(_hdr, _val) \
90 CP_MACADDR((u8*)(_hdr)+FRAME_OFFSET_ADDRESS1, (u8*)(_val))
91#define SET_80211_HDR_ADDRESS2(_hdr, _val) \
92 CP_MACADDR((u8*)(_hdr)+FRAME_OFFSET_ADDRESS2, (u8*)(_val))
93#define SET_80211_HDR_ADDRESS3(_hdr, _val) \
94 CP_MACADDR((u8*)(_hdr)+FRAME_OFFSET_ADDRESS3, (u8*)(_val))
95#define SET_80211_HDR_FRAGMENT_SEQUENCE(_hdr, _val) \
96 WRITEEF2BYTE((u8*)(_hdr)+FRAME_OFFSET_SEQUENCE, _val)
97
98#define SET_BEACON_PROBE_RSP_TIME_STAMP_LOW(__phdr, __val) \
99 WRITEEF4BYTE(((u8*)(__phdr)) + 24, __val)
100#define SET_BEACON_PROBE_RSP_TIME_STAMP_HIGH(__phdr, __val) \
101 WRITEEF4BYTE(((u8*)(__phdr)) + 28, __val)
102#define SET_BEACON_PROBE_RSP_BEACON_INTERVAL(__phdr, __val) \
103 WRITEEF2BYTE(((u8*)(__phdr)) + 32, __val)
104#define GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) \
105 READEF2BYTE(((u8*)(__phdr)) + 34)
106#define SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
107 WRITEEF2BYTE(((u8*)(__phdr)) + 34, __val)
108#define MASK_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
109 SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, \
110 (GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) & (~(__val))))
111
112int rtl_init_core(struct ieee80211_hw *hw);
113void rtl_deinit_core(struct ieee80211_hw *hw);
114void rtl_init_rx_config(struct ieee80211_hw *hw);
115void rtl_init_rfkill(struct ieee80211_hw *hw);
116void rtl_deinit_rfkill(struct ieee80211_hw *hw);
117
118void rtl_watch_dog_timer_callback(unsigned long data);
119void rtl_deinit_deferred_work(struct ieee80211_hw *hw);
120
121bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);
122bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb);
123u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);
124
125void rtl_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb);
126void rtl_watch_dog_timer_callback(unsigned long data);
127int rtl_tx_agg_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
128 struct ieee80211_sta *sta, u16 tid, u16 * ssn);
129int rtl_tx_agg_stop(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
130 struct ieee80211_sta *sta, u16 tid);
131int rtl_tx_agg_oper(struct ieee80211_hw *hw,
132 struct ieee80211_sta *sta, u16 tid);
133int rtl_rx_agg_start(struct ieee80211_hw *hw,
134 struct ieee80211_sta *sta, u16 tid);
135int rtl_rx_agg_stop(struct ieee80211_hw *hw,
136 struct ieee80211_sta *sta, u16 tid);
137void rtl_watchdog_wq_callback(void *data);
138void rtl_fwevt_wq_callback(void *data);
139
140void rtl_get_tcb_desc(struct ieee80211_hw *hw,
141 struct ieee80211_tx_info *info,
142 struct ieee80211_sta *sta,
143 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc);
144
145int rtl_send_smps_action(struct ieee80211_hw *hw,
146 struct ieee80211_sta *sta,
147 enum ieee80211_smps_mode smps);
148u8 *rtl_find_ie(u8 *data, unsigned int len, u8 ie);
149void rtl_recognize_peer(struct ieee80211_hw *hw, u8 *data, unsigned int len);
150u8 rtl_tid_to_ac(struct ieee80211_hw *hw, u8 tid);
151extern struct attribute_group rtl_attribute_group;
152void rtl_easy_concurrent_retrytimer_callback(unsigned long data);
153extern struct rtl_global_var global_var;
154
155#ifdef VIF_TODO
156struct ieee80211_vif *rtl_get_main_vif(struct ieee80211_hw *hw);
157bool rtl_set_vif_info(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
158#endif
159#endif
diff --git a/drivers/staging/rtl8821ae/btcoexist/HalBtc8812a1Ant.c b/drivers/staging/rtl8821ae/btcoexist/HalBtc8812a1Ant.c
new file mode 100644
index 000000000000..b30f17ae0215
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/HalBtc8812a1Ant.c
@@ -0,0 +1,3976 @@
1//============================================================
2// Description:
3//
4// This file is for 8812a1ant Co-exist mechanism
5//
6// History
7// 2012/11/15 Cosa first check in.
8//
9//============================================================
10
11//============================================================
12// include files
13//============================================================
14#include "halbt_precomp.h"
15#if 1
16//============================================================
17// Global variables, these are static variables
18//============================================================
19static COEX_DM_8812A_1ANT GLCoexDm8812a1Ant;
20static PCOEX_DM_8812A_1ANT coex_dm=&GLCoexDm8812a1Ant;
21static COEX_STA_8812A_1ANT GLCoexSta8812a1Ant;
22static PCOEX_STA_8812A_1ANT coex_sta=&GLCoexSta8812a1Ant;
23
24const char *const GLBtInfoSrc8812a1Ant[]={
25 "BT Info[wifi fw]",
26 "BT Info[bt rsp]",
27 "BT Info[bt auto report]",
28};
29
30//============================================================
31// local function proto type if needed
32//============================================================
33//============================================================
34// local function start with halbtc8812a1ant_
35//============================================================
36#if 0
37void
38halbtc8812a1ant_Reg0x550Bit3(
39 PBTC_COEXIST btcoexist,
40 BOOLEAN bSet
41 )
42{
43 u1Byte u1tmp=0;
44
45 u1tmp = btcoexist->btc_read_1byte(btcoexist, 0x550);
46 if(bSet)
47 {
48 u1tmp |= BIT3;
49 }
50 else
51 {
52 u1tmp &= ~BIT3;
53 }
54 btcoexist->btc_write_1byte(btcoexist, 0x550, u1tmp);
55 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], set 0x550[3]=%d\n", (bSet? 1:0)));
56}
57#endif
58u1Byte
59halbtc8812a1ant_BtRssiState(
60 u1Byte level_num,
61 u1Byte rssi_thresh,
62 u1Byte rssi_thresh1
63 )
64{
65 s4Byte bt_rssi=0;
66 u1Byte bt_rssi_state;
67
68 bt_rssi = coex_sta->bt_rssi;
69
70 if(level_num == 2)
71 {
72 if( (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
73 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW))
74 {
75 if(bt_rssi >= (rssi_thresh+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
76 {
77 bt_rssi_state = BTC_RSSI_STATE_HIGH;
78 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to High\n"));
79 }
80 else
81 {
82 bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
83 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at Low\n"));
84 }
85 }
86 else
87 {
88 if(bt_rssi < rssi_thresh)
89 {
90 bt_rssi_state = BTC_RSSI_STATE_LOW;
91 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Low\n"));
92 }
93 else
94 {
95 bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
96 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at High\n"));
97 }
98 }
99 }
100 else if(level_num == 3)
101 {
102 if(rssi_thresh > rssi_thresh1)
103 {
104 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi thresh error!!\n"));
105 return coex_sta->pre_bt_rssi_state;
106 }
107
108 if( (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
109 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW))
110 {
111 if(bt_rssi >= (rssi_thresh+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
112 {
113 bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
114 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Medium\n"));
115 }
116 else
117 {
118 bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
119 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at Low\n"));
120 }
121 }
122 else if( (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
123 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM))
124 {
125 if(bt_rssi >= (rssi_thresh1+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
126 {
127 bt_rssi_state = BTC_RSSI_STATE_HIGH;
128 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to High\n"));
129 }
130 else if(bt_rssi < rssi_thresh)
131 {
132 bt_rssi_state = BTC_RSSI_STATE_LOW;
133 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Low\n"));
134 }
135 else
136 {
137 bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
138 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at Medium\n"));
139 }
140 }
141 else
142 {
143 if(bt_rssi < rssi_thresh1)
144 {
145 bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
146 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Medium\n"));
147 }
148 else
149 {
150 bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
151 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at High\n"));
152 }
153 }
154 }
155
156 coex_sta->pre_bt_rssi_state = bt_rssi_state;
157
158 return bt_rssi_state;
159}
160
161u1Byte
162halbtc8812a1ant_WifiRssiState(
163 PBTC_COEXIST btcoexist,
164 u1Byte index,
165 u1Byte level_num,
166 u1Byte rssi_thresh,
167 u1Byte rssi_thresh1
168 )
169{
170 s4Byte wifi_rssi=0;
171 u1Byte wifi_rssi_state;
172
173 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
174
175 if(level_num == 2)
176 {
177 if( (coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) ||
178 (coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_STAY_LOW))
179 {
180 if(wifi_rssi >= (rssi_thresh+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
181 {
182 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
183 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to High\n"));
184 }
185 else
186 {
187 wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
188 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at Low\n"));
189 }
190 }
191 else
192 {
193 if(wifi_rssi < rssi_thresh)
194 {
195 wifi_rssi_state = BTC_RSSI_STATE_LOW;
196 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Low\n"));
197 }
198 else
199 {
200 wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
201 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at High\n"));
202 }
203 }
204 }
205 else if(level_num == 3)
206 {
207 if(rssi_thresh > rssi_thresh1)
208 {
209 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI thresh error!!\n"));
210 return coex_sta->pre_wifi_rssi_state[index];
211 }
212
213 if( (coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) ||
214 (coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_STAY_LOW))
215 {
216 if(wifi_rssi >= (rssi_thresh+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
217 {
218 wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
219 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Medium\n"));
220 }
221 else
222 {
223 wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
224 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at Low\n"));
225 }
226 }
227 else if( (coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_MEDIUM) ||
228 (coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_STAY_MEDIUM))
229 {
230 if(wifi_rssi >= (rssi_thresh1+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT))
231 {
232 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
233 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to High\n"));
234 }
235 else if(wifi_rssi < rssi_thresh)
236 {
237 wifi_rssi_state = BTC_RSSI_STATE_LOW;
238 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Low\n"));
239 }
240 else
241 {
242 wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
243 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at Medium\n"));
244 }
245 }
246 else
247 {
248 if(wifi_rssi < rssi_thresh1)
249 {
250 wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
251 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Medium\n"));
252 }
253 else
254 {
255 wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
256 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at High\n"));
257 }
258 }
259 }
260
261 coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
262
263 return wifi_rssi_state;
264}
265
266void
267halbtc8812a1ant_MonitorBtEnableDisable(
268 PBTC_COEXIST btcoexist
269 )
270{
271 static BOOLEAN pre_bt_disabled=false;
272 static u4Byte bt_disable_cnt=0;
273 BOOLEAN bt_active=true, bt_disable_by68=false, bt_disabled=false;
274 u4Byte u4_tmp=0;
275
276 // This function check if bt is disabled
277
278 if( coex_sta->high_priority_tx == 0 &&
279 coex_sta->high_priority_rx == 0 &&
280 coex_sta->low_priority_tx == 0 &&
281 coex_sta->low_priority_rx == 0)
282 {
283 bt_active = false;
284 }
285 if( coex_sta->high_priority_tx == 0xffff &&
286 coex_sta->high_priority_rx == 0xffff &&
287 coex_sta->low_priority_tx == 0xffff &&
288 coex_sta->low_priority_rx == 0xffff)
289 {
290 bt_active = false;
291 }
292 if(bt_active)
293 {
294 bt_disable_cnt = 0;
295 bt_disabled = false;
296 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, &bt_disabled);
297 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is enabled !!\n"));
298 }
299 else
300 {
301 bt_disable_cnt++;
302 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], bt all counters=0, %d times!!\n",
303 bt_disable_cnt));
304 if(bt_disable_cnt >= 2 ||bt_disable_by68)
305 {
306 bt_disabled = true;
307 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, &bt_disabled);
308 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is disabled !!\n"));
309 }
310 }
311 if(pre_bt_disabled != bt_disabled)
312 {
313 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is from %s to %s!!\n",
314 (pre_bt_disabled ? "disabled":"enabled"),
315 (bt_disabled ? "disabled":"enabled")));
316 pre_bt_disabled = bt_disabled;
317 if(!bt_disabled)
318 {
319 }
320 else
321 {
322 }
323 }
324}
325
326void
327halbtc8812a1ant_MonitorBtCtr(
328 PBTC_COEXIST btcoexist
329 )
330{
331 u4Byte reg_hp_tx_rx, reg_lp_tx_rx, u4_tmp;
332 u4Byte reg_hp_tx=0, reg_hp_rx=0, reg_lp_tx=0, reg_lp_rx=0;
333 u1Byte u1_tmp;
334
335 reg_hp_tx_rx = 0x770;
336 reg_lp_tx_rx = 0x774;
337
338 u4_tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_tx_rx);
339 reg_hp_tx = u4_tmp & bMaskLWord;
340 reg_hp_rx = (u4_tmp & bMaskHWord)>>16;
341
342 u4_tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_tx_rx);
343 reg_lp_tx = u4_tmp & bMaskLWord;
344 reg_lp_rx = (u4_tmp & bMaskHWord)>>16;
345
346 coex_sta->high_priority_tx = reg_hp_tx;
347 coex_sta->high_priority_rx = reg_hp_rx;
348 coex_sta->low_priority_tx = reg_lp_tx;
349 coex_sta->low_priority_rx = reg_lp_rx;
350
351 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=%x(%d)/%x(%d)\n",
352 reg_hp_tx_rx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx));
353 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=%x(%d)/%x(%d)\n",
354 reg_lp_tx_rx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx));
355
356 // reset counter
357 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
358}
359
360void
361halbtc8812a1ant_QueryBtInfo(
362 PBTC_COEXIST btcoexist
363 )
364{
365 u1Byte dataLen=3;
366 u1Byte buf[5] = {0};
367 static u4Byte btInfoCnt=0;
368
369 if(!btInfoCnt ||
370 (coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_BT_RSP]-btInfoCnt)>2)
371 {
372 buf[0] = dataLen;
373 buf[1] = 0x1; // polling enable, 1=enable, 0=disable
374 buf[2] = 0x2; // polling time in seconds
375 buf[3] = 0x1; // auto report enable, 1=enable, 0=disable
376
377 btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_INFO, (PVOID)&buf[0]);
378 }
379 btInfoCnt = coex_sta->bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_BT_RSP];
380}
381u1Byte
382halbtc8812a1ant_ActionAlgorithm(
383 PBTC_COEXIST btcoexist
384 )
385{
386 PBTC_STACK_INFO stack_info=&btcoexist->stack_info;
387 BOOLEAN bt_hs_on=false;
388 u1Byte algorithm=BT_8812A_1ANT_COEX_ALGO_UNDEFINED;
389 u1Byte num_of_diff_profile=0;
390
391 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
392
393 if(!stack_info->bt_link_exist)
394 {
395 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], No profile exists!!!\n"));
396 return algorithm;
397 }
398
399 if(stack_info->sco_exist)
400 num_of_diff_profile++;
401 if(stack_info->hid_exist)
402 num_of_diff_profile++;
403 if(stack_info->pan_exist)
404 num_of_diff_profile++;
405 if(stack_info->a2dp_exist)
406 num_of_diff_profile++;
407
408 if(num_of_diff_profile == 1)
409 {
410 if(stack_info->sco_exist)
411 {
412 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO only\n"));
413 algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
414 }
415 else
416 {
417 if(stack_info->hid_exist)
418 {
419 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID only\n"));
420 algorithm = BT_8812A_1ANT_COEX_ALGO_HID;
421 }
422 else if(stack_info->a2dp_exist)
423 {
424 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP only\n"));
425 algorithm = BT_8812A_1ANT_COEX_ALGO_A2DP;
426 }
427 else if(stack_info->pan_exist)
428 {
429 if(bt_hs_on)
430 {
431 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN(HS) only\n"));
432 algorithm = BT_8812A_1ANT_COEX_ALGO_PANHS;
433 }
434 else
435 {
436 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN(EDR) only\n"));
437 algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR;
438 }
439 }
440 }
441 }
442 else if(num_of_diff_profile == 2)
443 {
444 if(stack_info->sco_exist)
445 {
446 if(stack_info->hid_exist)
447 {
448 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID\n"));
449 algorithm = BT_8812A_1ANT_COEX_ALGO_HID;
450 }
451 else if(stack_info->a2dp_exist)
452 {
453 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + A2DP ==> SCO\n"));
454 algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
455 }
456 else if(stack_info->pan_exist)
457 {
458 if(bt_hs_on)
459 {
460 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + PAN(HS)\n"));
461 algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
462 }
463 else
464 {
465 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + PAN(EDR)\n"));
466 algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
467 }
468 }
469 }
470 else
471 {
472 if( stack_info->hid_exist &&
473 stack_info->a2dp_exist )
474 {
475 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + A2DP\n"));
476 algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
477 }
478 else if( stack_info->hid_exist &&
479 stack_info->pan_exist )
480 {
481 if(bt_hs_on)
482 {
483 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + PAN(HS)\n"));
484 algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
485 }
486 else
487 {
488 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + PAN(EDR)\n"));
489 algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
490 }
491 }
492 else if( stack_info->pan_exist &&
493 stack_info->a2dp_exist )
494 {
495 if(bt_hs_on)
496 {
497 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP + PAN(HS)\n"));
498 algorithm = BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS;
499 }
500 else
501 {
502 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP + PAN(EDR)\n"));
503 algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP;
504 }
505 }
506 }
507 }
508 else if(num_of_diff_profile == 3)
509 {
510 if(stack_info->sco_exist)
511 {
512 if( stack_info->hid_exist &&
513 stack_info->a2dp_exist )
514 {
515 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + A2DP ==> HID\n"));
516 algorithm = BT_8812A_1ANT_COEX_ALGO_HID;
517 }
518 else if( stack_info->hid_exist &&
519 stack_info->pan_exist )
520 {
521 if(bt_hs_on)
522 {
523 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + PAN(HS)\n"));
524 algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
525 }
526 else
527 {
528 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + PAN(EDR)\n"));
529 algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
530 }
531 }
532 else if( stack_info->pan_exist &&
533 stack_info->a2dp_exist )
534 {
535 if(bt_hs_on)
536 {
537 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + A2DP + PAN(HS)\n"));
538 algorithm = BT_8812A_1ANT_COEX_ALGO_SCO;
539 }
540 else
541 {
542 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"));
543 algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
544 }
545 }
546 }
547 else
548 {
549 if( stack_info->hid_exist &&
550 stack_info->pan_exist &&
551 stack_info->a2dp_exist )
552 {
553 if(bt_hs_on)
554 {
555 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + A2DP + PAN(HS)\n"));
556 algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP;
557 }
558 else
559 {
560 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + A2DP + PAN(EDR)\n"));
561 algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
562 }
563 }
564 }
565 }
566 else if(num_of_diff_profile >= 3)
567 {
568 if(stack_info->sco_exist)
569 {
570 if( stack_info->hid_exist &&
571 stack_info->pan_exist &&
572 stack_info->a2dp_exist )
573 {
574 if(bt_hs_on)
575 {
576 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"));
577
578 }
579 else
580 {
581 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"));
582 algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_HID;
583 }
584 }
585 }
586 }
587
588 return algorithm;
589}
590
591BOOLEAN
592halbtc8812a1ant_NeedToDecBtPwr(
593 PBTC_COEXIST btcoexist
594 )
595{
596 BOOLEAN ret=false;
597 BOOLEAN bt_hs_on=false, wifi_connected=false;
598 s4Byte bt_hs_rssi=0;
599
600 if(!btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on))
601 return false;
602 if(!btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected))
603 return false;
604 if(!btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi))
605 return false;
606
607 if(wifi_connected)
608 {
609 if(bt_hs_on)
610 {
611 if(bt_hs_rssi > 37)
612 {
613 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], Need to decrease bt power for HS mode!!\n"));
614 ret = true;
615 }
616 }
617 else
618 {
619 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], Need to decrease bt power for Wifi is connected!!\n"));
620 ret = true;
621 }
622 }
623
624 return ret;
625}
626
627void
628halbtc8812a1ant_SetFwDacSwingLevel(
629 PBTC_COEXIST btcoexist,
630 u1Byte dac_swing_lvl
631 )
632{
633 u1Byte h2c_parameter[1] ={0};
634
635 // There are several type of dacswing
636 // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6
637 h2c_parameter[0] = dac_swing_lvl;
638
639 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], Set Dac Swing Level=0x%x\n", dac_swing_lvl));
640 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], FW write 0x64=0x%x\n", h2c_parameter[0]));
641
642 btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
643}
644
645void
646halbtc8812a1ant_SetFwDecBtPwr(
647 PBTC_COEXIST btcoexist,
648 BOOLEAN dec_bt_pwr
649 )
650{
651 u1Byte dataLen=3;
652 u1Byte buf[5] = {0};
653
654 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], decrease Bt Power : %s\n",
655 (dec_bt_pwr? "Yes!!":"No!!")));
656
657 buf[0] = dataLen;
658 buf[1] = 0x3; // OP_Code
659 buf[2] = 0x1; // OP_Code_Length
660 if(dec_bt_pwr)
661 buf[3] = 0x1; // OP_Code_Content
662 else
663 buf[3] = 0x0;
664
665 btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]);
666}
667
668void
669halbtc8812a1ant_DecBtPwr(
670 PBTC_COEXIST btcoexist,
671 BOOLEAN force_exec,
672 BOOLEAN dec_bt_pwr
673 )
674{
675 return;
676 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s Dec BT power = %s\n",
677 (force_exec? "force to":""), ((dec_bt_pwr)? "ON":"OFF")));
678 coex_dm->cur_dec_bt_pwr = dec_bt_pwr;
679
680 if(!force_exec)
681 {
682 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], pre_dec_bt_pwr=%d, cur_dec_bt_pwr=%d\n",
683 coex_dm->pre_dec_bt_pwr, coex_dm->cur_dec_bt_pwr));
684
685 if(coex_dm->pre_dec_bt_pwr == coex_dm->cur_dec_bt_pwr)
686 return;
687 }
688 halbtc8812a1ant_SetFwDecBtPwr(btcoexist, coex_dm->cur_dec_bt_pwr);
689
690 coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr;
691}
692
693void
694halbtc8812a1ant_SetFwBtLnaConstrain(
695 PBTC_COEXIST btcoexist,
696 BOOLEAN bt_lna_cons_on
697 )
698{
699 u1Byte dataLen=3;
700 u1Byte buf[5] = {0};
701
702 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], set BT LNA Constrain: %s\n",
703 (bt_lna_cons_on? "ON!!":"OFF!!")));
704
705 buf[0] = dataLen;
706 buf[1] = 0x2; // OP_Code
707 buf[2] = 0x1; // OP_Code_Length
708 if(bt_lna_cons_on)
709 buf[3] = 0x1; // OP_Code_Content
710 else
711 buf[3] = 0x0;
712
713 btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]);
714}
715
716void
717halbtc8812a1ant_SetBtLnaConstrain(
718 PBTC_COEXIST btcoexist,
719 BOOLEAN force_exec,
720 BOOLEAN bt_lna_cons_on
721 )
722{
723 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s BT Constrain = %s\n",
724 (force_exec? "force":""), ((bt_lna_cons_on)? "ON":"OFF")));
725 coex_dm->bCurBtLnaConstrain = bt_lna_cons_on;
726
727 if(!force_exec)
728 {
729 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPreBtLnaConstrain=%d, bCurBtLnaConstrain=%d\n",
730 coex_dm->bPreBtLnaConstrain, coex_dm->bCurBtLnaConstrain));
731
732 if(coex_dm->bPreBtLnaConstrain == coex_dm->bCurBtLnaConstrain)
733 return;
734 }
735 halbtc8812a1ant_SetFwBtLnaConstrain(btcoexist, coex_dm->bCurBtLnaConstrain);
736
737 coex_dm->bPreBtLnaConstrain = coex_dm->bCurBtLnaConstrain;
738}
739
740void
741halbtc8812a1ant_SetFwBtPsdMode(
742 PBTC_COEXIST btcoexist,
743 u1Byte bt_psd_mode
744 )
745{
746 u1Byte dataLen=3;
747 u1Byte buf[5] = {0};
748
749 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], set BT PSD mode=0x%x\n",
750 bt_psd_mode));
751
752 buf[0] = dataLen;
753 buf[1] = 0x4; // OP_Code
754 buf[2] = 0x1; // OP_Code_Length
755 buf[3] = bt_psd_mode; // OP_Code_Content
756
757 btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]);
758}
759
760
761void
762halbtc8812a1ant_SetBtPsdMode(
763 PBTC_COEXIST btcoexist,
764 BOOLEAN force_exec,
765 u1Byte bt_psd_mode
766 )
767{
768 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s BT PSD mode = 0x%x\n",
769 (force_exec? "force":""), bt_psd_mode));
770 coex_dm->bCurBtPsdMode = bt_psd_mode;
771
772 if(!force_exec)
773 {
774 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPreBtPsdMode=0x%x, bCurBtPsdMode=0x%x\n",
775 coex_dm->bPreBtPsdMode, coex_dm->bCurBtPsdMode));
776
777 if(coex_dm->bPreBtPsdMode == coex_dm->bCurBtPsdMode)
778 return;
779 }
780 halbtc8812a1ant_SetFwBtPsdMode(btcoexist, coex_dm->bCurBtPsdMode);
781
782 coex_dm->bPreBtPsdMode = coex_dm->bCurBtPsdMode;
783}
784
785
786void
787halbtc8812a1ant_SetBtAutoReport(
788 PBTC_COEXIST btcoexist,
789 BOOLEAN enable_auto_report
790 )
791{
792#if 0
793 u1Byte h2c_parameter[1] ={0};
794
795 h2c_parameter[0] = 0;
796
797 if(enable_auto_report)
798 {
799 h2c_parameter[0] |= BIT0;
800 }
801
802 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n",
803 (enable_auto_report? "Enabled!!":"Disabled!!"), h2c_parameter[0]));
804
805 btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
806#else
807
808#endif
809}
810
811void
812halbtc8812a1ant_BtAutoReport(
813 PBTC_COEXIST btcoexist,
814 BOOLEAN force_exec,
815 BOOLEAN enable_auto_report
816 )
817{
818 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s BT Auto report = %s\n",
819 (force_exec? "force to":""), ((enable_auto_report)? "Enabled":"Disabled")));
820 coex_dm->cur_bt_auto_report = enable_auto_report;
821
822 if(!force_exec)
823 {
824 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], pre_bt_auto_report=%d, cur_bt_auto_report=%d\n",
825 coex_dm->pre_bt_auto_report, coex_dm->cur_bt_auto_report));
826
827 if(coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
828 return;
829 }
830 halbtc8812a1ant_SetBtAutoReport(btcoexist, coex_dm->cur_bt_auto_report);
831
832 coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
833}
834
835void
836halbtc8812a1ant_FwDacSwingLvl(
837 PBTC_COEXIST btcoexist,
838 BOOLEAN force_exec,
839 u1Byte fw_dac_swing_lvl
840 )
841{
842 return;
843 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s set FW Dac Swing level = %d\n",
844 (force_exec? "force to":""), fw_dac_swing_lvl));
845 coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
846
847 if(!force_exec)
848 {
849 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], pre_fw_dac_swing_lvl=%d, cur_fw_dac_swing_lvl=%d\n",
850 coex_dm->pre_fw_dac_swing_lvl, coex_dm->cur_fw_dac_swing_lvl));
851
852 if(coex_dm->pre_fw_dac_swing_lvl == coex_dm->cur_fw_dac_swing_lvl)
853 return;
854 }
855
856 halbtc8812a1ant_SetFwDacSwingLevel(btcoexist, coex_dm->cur_fw_dac_swing_lvl);
857
858 coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
859}
860
861void
862halbtc8812a1ant_SetSwRfRxLpfCorner(
863 PBTC_COEXIST btcoexist,
864 BOOLEAN rx_rf_shrink_on
865 )
866{
867 if(rx_rf_shrink_on)
868 {
869 //Shrink RF Rx LPF corner
870 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Shrink RF Rx LPF corner!!\n"));
871 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf0ff7);
872 }
873 else
874 {
875 //Resume RF Rx LPF corner
876 // After initialized, we can use coex_dm->bt_rf0x1e_backup
877 if(btcoexist->bInitilized)
878 {
879 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Resume RF Rx LPF corner!!\n"));
880 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff, coex_dm->bt_rf0x1e_backup);
881 }
882 }
883}
884
885void
886halbtc8812a1ant_RfShrink(
887 PBTC_COEXIST btcoexist,
888 BOOLEAN force_exec,
889 BOOLEAN rx_rf_shrink_on
890 )
891{
892 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn Rx RF Shrink = %s\n",
893 (force_exec? "force to":""), ((rx_rf_shrink_on)? "ON":"OFF")));
894 coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
895
896 if(!force_exec)
897 {
898 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], pre_rf_rx_lpf_shrink=%d, cur_rf_rx_lpf_shrink=%d\n",
899 coex_dm->pre_rf_rx_lpf_shrink, coex_dm->cur_rf_rx_lpf_shrink));
900
901 if(coex_dm->pre_rf_rx_lpf_shrink == coex_dm->cur_rf_rx_lpf_shrink)
902 return;
903 }
904 halbtc8812a1ant_SetSwRfRxLpfCorner(btcoexist, coex_dm->cur_rf_rx_lpf_shrink);
905
906 coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
907}
908
909void
910halbtc8812a1ant_SetSwPenaltyTxRateAdaptive(
911 PBTC_COEXIST btcoexist,
912 BOOLEAN low_penalty_ra
913 )
914{
915 u1Byte u1_tmp;
916
917 u1_tmp = btcoexist->btc_read_1byte(btcoexist, 0x4fd);
918 u1_tmp |= BIT0;
919 if(low_penalty_ra)
920 {
921 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Tx rate adaptive, set low penalty!!\n"));
922 u1_tmp &= ~BIT2;
923 }
924 else
925 {
926 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Tx rate adaptive, set normal!!\n"));
927 u1_tmp |= BIT2;
928 }
929
930 btcoexist->btc_write_1byte(btcoexist, 0x4fd, u1_tmp);
931}
932
933void
934halbtc8812a1ant_LowPenaltyRa(
935 PBTC_COEXIST btcoexist,
936 BOOLEAN force_exec,
937 BOOLEAN low_penalty_ra
938 )
939{
940 return;
941 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn LowPenaltyRA = %s\n",
942 (force_exec? "force to":""), ((low_penalty_ra)? "ON":"OFF")));
943 coex_dm->cur_low_penalty_ra = low_penalty_ra;
944
945 if(!force_exec)
946 {
947 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], pre_low_penalty_ra=%d, cur_low_penalty_ra=%d\n",
948 coex_dm->pre_low_penalty_ra, coex_dm->cur_low_penalty_ra));
949
950 if(coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
951 return;
952 }
953 halbtc8812a1ant_SetSwPenaltyTxRateAdaptive(btcoexist, coex_dm->cur_low_penalty_ra);
954
955 coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
956}
957
958void
959halbtc8812a1ant_SetDacSwingReg(
960 PBTC_COEXIST btcoexist,
961 u4Byte level
962 )
963{
964 u1Byte val=(u1Byte)level;
965
966 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Write SwDacSwing = 0x%x\n", level));
967 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc5b, 0x3e, val);
968}
969
970void
971halbtc8812a1ant_SetSwFullTimeDacSwing(
972 PBTC_COEXIST btcoexist,
973 BOOLEAN sw_dac_swing_on,
974 u4Byte sw_dac_swing_lvl
975 )
976{
977 if(sw_dac_swing_on)
978 {
979 halbtc8812a1ant_SetDacSwingReg(btcoexist, sw_dac_swing_lvl);
980 }
981 else
982 {
983 halbtc8812a1ant_SetDacSwingReg(btcoexist, 0x18);
984 }
985}
986
987
988void
989halbtc8812a1ant_DacSwing(
990 PBTC_COEXIST btcoexist,
991 BOOLEAN force_exec,
992 BOOLEAN dac_swing_on,
993 u4Byte dac_swing_lvl
994 )
995{
996 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn DacSwing=%s, dac_swing_lvl=0x%x\n",
997 (force_exec? "force to":""), ((dac_swing_on)? "ON":"OFF"), dac_swing_lvl));
998 coex_dm->cur_dac_swing_on = dac_swing_on;
999 coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
1000
1001 if(!force_exec)
1002 {
1003 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], pre_dac_swing_on=%d, pre_dac_swing_lvl=0x%x, cur_dac_swing_on=%d, cur_dac_swing_lvl=0x%x\n",
1004 coex_dm->pre_dac_swing_on, coex_dm->pre_dac_swing_lvl,
1005 coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl));
1006
1007 if( (coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
1008 (coex_dm->pre_dac_swing_lvl == coex_dm->cur_dac_swing_lvl) )
1009 return;
1010 }
1011 delay_ms(30);
1012 halbtc8812a1ant_SetSwFullTimeDacSwing(btcoexist, dac_swing_on, dac_swing_lvl);
1013
1014 coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
1015 coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
1016}
1017
1018void
1019halbtc8812a1ant_SetAdcBackOff(
1020 PBTC_COEXIST btcoexist,
1021 BOOLEAN adc_back_off
1022 )
1023{
1024 if(adc_back_off)
1025 {
1026 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], BB BackOff Level On!\n"));
1027 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3);
1028 }
1029 else
1030 {
1031 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], BB BackOff Level Off!\n"));
1032 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1);
1033 }
1034}
1035
1036void
1037halbtc8812a1ant_AdcBackOff(
1038 PBTC_COEXIST btcoexist,
1039 BOOLEAN force_exec,
1040 BOOLEAN adc_back_off
1041 )
1042{
1043 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn AdcBackOff = %s\n",
1044 (force_exec? "force to":""), ((adc_back_off)? "ON":"OFF")));
1045 coex_dm->cur_adc_back_off = adc_back_off;
1046
1047 if(!force_exec)
1048 {
1049 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], pre_adc_back_off=%d, cur_adc_back_off=%d\n",
1050 coex_dm->pre_adc_back_off, coex_dm->cur_adc_back_off));
1051
1052 if(coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
1053 return;
1054 }
1055 halbtc8812a1ant_SetAdcBackOff(btcoexist, coex_dm->cur_adc_back_off);
1056
1057 coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
1058}
1059
1060void
1061halbtc8812a1ant_SetAgcTable(
1062 PBTC_COEXIST btcoexist,
1063 BOOLEAN agc_table_en
1064 )
1065{
1066 u1Byte rssi_adjust_val=0;
1067
1068 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000);
1069 if(agc_table_en)
1070 {
1071 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Agc Table On!\n"));
1072 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, 0x3fa58);
1073 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, 0x37a58);
1074 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, 0x2fa58);
1075 rssi_adjust_val = 8;
1076 }
1077 else
1078 {
1079 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Agc Table Off!\n"));
1080 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, 0x39258);
1081 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, 0x31258);
1082 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b, 0xfffff, 0x29258);
1083 }
1084 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
1085
1086 // set rssi_adjust_val for wifi module.
1087 btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssi_adjust_val);
1088}
1089
1090
1091void
1092halbtc8812a1ant_AgcTable(
1093 PBTC_COEXIST btcoexist,
1094 BOOLEAN force_exec,
1095 BOOLEAN agc_table_en
1096 )
1097{
1098 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s %s Agc Table\n",
1099 (force_exec? "force to":""), ((agc_table_en)? "Enable":"Disable")));
1100 coex_dm->cur_agc_table_en = agc_table_en;
1101
1102 if(!force_exec)
1103 {
1104 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], pre_agc_table_en=%d, cur_agc_table_en=%d\n",
1105 coex_dm->pre_agc_table_en, coex_dm->cur_agc_table_en));
1106
1107 if(coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
1108 return;
1109 }
1110 halbtc8812a1ant_SetAgcTable(btcoexist, agc_table_en);
1111
1112 coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
1113}
1114
1115void
1116halbtc8812a1ant_SetCoexTable(
1117 PBTC_COEXIST btcoexist,
1118 u4Byte val0x6c0,
1119 u4Byte val0x6c4,
1120 u4Byte val0x6c8,
1121 u1Byte val0x6cc
1122 )
1123{
1124 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0));
1125 btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
1126
1127 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4));
1128 btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
1129
1130 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8));
1131 btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
1132
1133 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc));
1134 btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
1135}
1136
1137void
1138halbtc8812a1ant_CoexTable(
1139 PBTC_COEXIST btcoexist,
1140 BOOLEAN force_exec,
1141 u4Byte val0x6c0,
1142 u4Byte val0x6c4,
1143 u4Byte val0x6c8,
1144 u1Byte val0x6cc
1145 )
1146{
1147 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
1148 (force_exec? "force to":""), val0x6c0, val0x6c4, val0x6c8, val0x6cc));
1149 coex_dm->cur_val0x6c0 = val0x6c0;
1150 coex_dm->cur_val0x6c4 = val0x6c4;
1151 coex_dm->cur_val0x6c8 = val0x6c8;
1152 coex_dm->cur_val0x6cc = val0x6cc;
1153
1154 if(!force_exec)
1155 {
1156 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], pre_val0x6c0=0x%x, pre_val0x6c4=0x%x, pre_val0x6c8=0x%x, pre_val0x6cc=0x%x !!\n",
1157 coex_dm->pre_val0x6c0, coex_dm->pre_val0x6c4, coex_dm->pre_val0x6c8, coex_dm->pre_val0x6cc));
1158 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], cur_val0x6c0=0x%x, cur_val0x6c4=0x%x, cur_val0x6c8=0x%x, cur_val0x6cc=0x%x !!\n",
1159 coex_dm->cur_val0x6c0, coex_dm->cur_val0x6c4, coex_dm->cur_val0x6c8, coex_dm->cur_val0x6cc));
1160
1161 if( (coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
1162 (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
1163 (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
1164 (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc) )
1165 return;
1166 }
1167 halbtc8812a1ant_SetCoexTable(btcoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc);
1168
1169 coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
1170 coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
1171 coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
1172 coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
1173}
1174
1175void
1176halbtc8812a1ant_SetFwIgnoreWlanAct(
1177 PBTC_COEXIST btcoexist,
1178 BOOLEAN enable
1179 )
1180{
1181 u1Byte dataLen=3;
1182 u1Byte buf[5] = {0};
1183
1184 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], %s BT Ignore Wlan_Act\n",
1185 (enable? "Enable":"Disable")));
1186
1187 buf[0] = dataLen;
1188 buf[1] = 0x1; // OP_Code
1189 buf[2] = 0x1; // OP_Code_Length
1190 if(enable)
1191 buf[3] = 0x1; // OP_Code_Content
1192 else
1193 buf[3] = 0x0;
1194
1195 btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]);
1196}
1197
1198void
1199halbtc8812a1ant_IgnoreWlanAct(
1200 PBTC_COEXIST btcoexist,
1201 BOOLEAN force_exec,
1202 BOOLEAN enable
1203 )
1204{
1205 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s turn Ignore WlanAct %s\n",
1206 (force_exec? "force to":""), (enable? "ON":"OFF")));
1207 coex_dm->cur_ignore_wlan_act = enable;
1208
1209 if(!force_exec)
1210 {
1211 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], pre_ignore_wlan_act = %d, cur_ignore_wlan_act = %d!!\n",
1212 coex_dm->pre_ignore_wlan_act, coex_dm->cur_ignore_wlan_act));
1213
1214 if(coex_dm->pre_ignore_wlan_act == coex_dm->cur_ignore_wlan_act)
1215 return;
1216 }
1217 halbtc8812a1ant_SetFwIgnoreWlanAct(btcoexist, enable);
1218
1219 coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
1220}
1221
1222void
1223halbtc8812a1ant_SetFwPstdma(
1224 PBTC_COEXIST btcoexist,
1225 u1Byte byte1,
1226 u1Byte byte2,
1227 u1Byte byte3,
1228 u1Byte byte4,
1229 u1Byte byte5
1230 )
1231{
1232 u1Byte h2c_parameter[5] ={0};
1233
1234 h2c_parameter[0] = byte1;
1235 h2c_parameter[1] = byte2;
1236 h2c_parameter[2] = byte3;
1237 h2c_parameter[3] = byte4;
1238 h2c_parameter[4] = byte5;
1239
1240 coex_dm->ps_tdma_para[0] = byte1;
1241 coex_dm->ps_tdma_para[1] = byte2;
1242 coex_dm->ps_tdma_para[2] = byte3;
1243 coex_dm->ps_tdma_para[3] = byte4;
1244 coex_dm->ps_tdma_para[4] = byte5;
1245
1246 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], FW write 0x60(5bytes)=0x%x%08x\n",
1247 h2c_parameter[0],
1248 h2c_parameter[1]<<24|h2c_parameter[2]<<16|h2c_parameter[3]<<8|h2c_parameter[4]));
1249
1250 btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
1251}
1252
1253void
1254halbtc8812a1ant_SetLpsRpwm(
1255 PBTC_COEXIST btcoexist,
1256 u1Byte lps_val,
1257 u1Byte rpwm_val
1258 )
1259{
1260 u1Byte lps=lps_val;
1261 u1Byte rpwm=rpwm_val;
1262
1263 btcoexist->btc_set(btcoexist, BTC_SET_U1_1ANT_LPS, &lps);
1264 btcoexist->btc_set(btcoexist, BTC_SET_U1_1ANT_RPWM, &rpwm);
1265
1266 btcoexist->btc_set(btcoexist, BTC_SET_ACT_INC_FORCE_EXEC_PWR_CMD_CNT, NULL);
1267}
1268
1269void
1270halbtc8812a1ant_LpsRpwm(
1271 PBTC_COEXIST btcoexist,
1272 BOOLEAN force_exec,
1273 u1Byte lps_val,
1274 u1Byte rpwm_val
1275 )
1276{
1277 BOOLEAN bForceExecPwrCmd=false;
1278
1279 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n",
1280 (force_exec? "force to":""), lps_val, rpwm_val));
1281 coex_dm->cur_lps = lps_val;
1282 coex_dm->cur_rpwm = rpwm_val;
1283
1284 if(!force_exec)
1285 {
1286 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], pre_lps/cur_lps=0x%x/0x%x, pre_rpwm/cur_rpwm=0x%x/0x%x!!\n",
1287 coex_dm->pre_lps, coex_dm->cur_lps, coex_dm->pre_rpwm, coex_dm->cur_rpwm));
1288
1289 if( (coex_dm->pre_lps == coex_dm->cur_lps) &&
1290 (coex_dm->pre_rpwm == coex_dm->cur_rpwm) )
1291 {
1292 return;
1293 }
1294 }
1295 halbtc8812a1ant_SetLpsRpwm(btcoexist, lps_val, rpwm_val);
1296
1297 coex_dm->pre_lps = coex_dm->cur_lps;
1298 coex_dm->pre_rpwm = coex_dm->cur_rpwm;
1299}
1300
1301void
1302halbtc8812a1ant_SwMechanism1(
1303 PBTC_COEXIST btcoexist,
1304 BOOLEAN shrink_rx_lpf,
1305 BOOLEAN low_penalty_ra,
1306 BOOLEAN limited_dig,
1307 BOOLEAN bt_lna_constrain
1308 )
1309{
1310 //halbtc8812a1ant_RfShrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
1311 //halbtc8812a1ant_LowPenaltyRa(btcoexist, NORMAL_EXEC, low_penalty_ra);
1312
1313 //no limited DIG
1314 //halbtc8812a1ant_SetBtLnaConstrain(btcoexist, NORMAL_EXEC, bt_lna_constrain);
1315}
1316
1317void
1318halbtc8812a1ant_SwMechanism2(
1319 PBTC_COEXIST btcoexist,
1320 BOOLEAN agc_table_shift,
1321 BOOLEAN adc_back_off,
1322 BOOLEAN sw_dac_swing,
1323 u4Byte dac_swing_lvl
1324 )
1325{
1326 //halbtc8812a1ant_AgcTable(btcoexist, NORMAL_EXEC, agc_table_shift);
1327 //halbtc8812a1ant_AdcBackOff(btcoexist, NORMAL_EXEC, adc_back_off);
1328 //halbtc8812a1ant_DacSwing(btcoexist, NORMAL_EXEC, sw_dac_swing, dac_swing_lvl);
1329}
1330
1331void
1332halbtc8812a1ant_PsTdma(
1333 PBTC_COEXIST btcoexist,
1334 BOOLEAN force_exec,
1335 BOOLEAN turn_on,
1336 u1Byte type
1337 )
1338{
1339 BOOLEAN bTurnOnByCnt=false;
1340 u1Byte psTdmaTypeByCnt=0, rssi_adjust_val=0;
1341
1342 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s turn %s PS TDMA, type=%d\n",
1343 (force_exec? "force to":""), (turn_on? "ON":"OFF"), type));
1344 coex_dm->cur_ps_tdma_on = turn_on;
1345 coex_dm->cur_ps_tdma = type;
1346
1347 if(!force_exec)
1348 {
1349 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], pre_ps_tdma_on = %d, cur_ps_tdma_on = %d!!\n",
1350 coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on));
1351 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], pre_ps_tdma = %d, cur_ps_tdma = %d!!\n",
1352 coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma));
1353
1354 if( (coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
1355 (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma) )
1356 return;
1357 }
1358 if(turn_on)
1359 {
1360 switch(type)
1361 {
1362 default:
1363 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xd3, 0x1a, 0x1a, 0x0, 0x58);
1364 break;
1365 case 1:
1366 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xd3, 0x1a, 0x1a, 0x0, 0x48);
1367 rssi_adjust_val = 11;
1368 break;
1369 case 2:
1370 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xd3, 0x12, 0x12, 0x0, 0x48);
1371 rssi_adjust_val = 14;
1372 break;
1373 case 3:
1374 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x93, 0x25, 0x3, 0x10, 0x40);
1375 break;
1376 case 4:
1377 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x93, 0x15, 0x3, 0x14, 0x0);
1378 rssi_adjust_val = 17;
1379 break;
1380 case 5:
1381 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x61, 0x15, 0x3, 0x31, 0x0);
1382 break;
1383 case 6:
1384 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x13, 0xa, 0x3, 0x0, 0x0);
1385 break;
1386 case 7:
1387 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x13, 0xc, 0x5, 0x0, 0x0);
1388 break;
1389 case 8:
1390 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x93, 0x25, 0x3, 0x10, 0x0);
1391 break;
1392 case 9:
1393 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xd3, 0xa, 0xa, 0x0, 0x48);
1394 rssi_adjust_val = 18;
1395 break;
1396 case 10:
1397 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x13, 0xa, 0xa, 0x0, 0x40);
1398 break;
1399 case 11:
1400 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xd3, 0x5, 0x5, 0x0, 0x48);
1401 rssi_adjust_val = 20;
1402 break;
1403 case 12:
1404 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xeb, 0xa, 0x3, 0x31, 0x18);
1405 break;
1406
1407 case 15:
1408 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x13, 0xa, 0x3, 0x8, 0x0);
1409 break;
1410 case 16:
1411 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x93, 0x15, 0x3, 0x10, 0x0);
1412 rssi_adjust_val = 18;
1413 break;
1414
1415 case 18:
1416 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x93, 0x25, 0x3, 0x10, 0x0);
1417 rssi_adjust_val = 14;
1418 break;
1419
1420 case 20:
1421 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x13, 0x25, 0x25, 0x0, 0x0);
1422 break;
1423 case 21:
1424 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x93, 0x20, 0x3, 0x10, 0x40);
1425 break;
1426 case 22:
1427 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x13, 0x8, 0x8, 0x0, 0x40);
1428 break;
1429 case 23:
1430 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xe3, 0x25, 0x3, 0x31, 0x18);
1431 rssi_adjust_val = 22;
1432 break;
1433 case 24:
1434 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xe3, 0x15, 0x3, 0x31, 0x18);
1435 rssi_adjust_val = 22;
1436 break;
1437 case 25:
1438 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xe3, 0xa, 0x3, 0x31, 0x18);
1439 rssi_adjust_val = 22;
1440 break;
1441 case 26:
1442 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xe3, 0xa, 0x3, 0x31, 0x18);
1443 rssi_adjust_val = 22;
1444 break;
1445 case 27:
1446 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xe3, 0x25, 0x3, 0x31, 0x98);
1447 rssi_adjust_val = 22;
1448 break;
1449 case 28:
1450 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x69, 0x25, 0x3, 0x31, 0x0);
1451 break;
1452 case 29:
1453 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xab, 0x1a, 0x1a, 0x1, 0x8);
1454 break;
1455 case 30:
1456 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x93, 0x15, 0x3, 0x14, 0x0);
1457 break;
1458 case 31:
1459 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xd3, 0x1a, 0x1a, 0, 0x58);
1460 break;
1461 case 32:
1462 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xab, 0xa, 0x3, 0x31, 0x88);
1463 break;
1464 case 33:
1465 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xa3, 0x25, 0x3, 0x30, 0x88);
1466 break;
1467 case 34:
1468 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xd3, 0x1a, 0x1a, 0x0, 0x8);
1469 break;
1470 case 35:
1471 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xe3, 0x1a, 0x1a, 0x0, 0x8);
1472 break;
1473 case 36:
1474 halbtc8812a1ant_SetFwPstdma(btcoexist, 0xd3, 0x12, 0x3, 0x14, 0x58);
1475 break;
1476 }
1477 }
1478 else
1479 {
1480 // disable PS tdma
1481 switch(type)
1482 {
1483 case 8:
1484 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x8, 0x0, 0x0, 0x0, 0x0);
1485 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
1486 break;
1487 case 0:
1488 default:
1489 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x0, 0x0, 0x0, 0x0, 0x0);
1490 delay_ms(5);
1491 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
1492 break;
1493 case 9:
1494 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x0, 0x0, 0x0, 0x0, 0x0);
1495 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
1496 break;
1497 case 10:
1498 halbtc8812a1ant_SetFwPstdma(btcoexist, 0x0, 0x0, 0x0, 0x8, 0x0);
1499 delay_ms(5);
1500 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
1501 break;
1502 }
1503 }
1504 rssi_adjust_val =0;
1505 btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssi_adjust_val);
1506
1507 // update pre state
1508 coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
1509 coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
1510}
1511
1512void
1513halbtc8812a1ant_CoexAllOff(
1514 PBTC_COEXIST btcoexist
1515 )
1516{
1517 // fw all off
1518 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
1519 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
1520
1521 // sw all off
1522 halbtc8812a1ant_SwMechanism1(btcoexist,false,false,false,false);
1523 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
1524
1525
1526 // hw all off
1527 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
1528}
1529
1530void
1531halbtc8812a1ant_WifiParaAdjust(
1532 PBTC_COEXIST btcoexist,
1533 BOOLEAN enable
1534 )
1535{
1536 if(enable)
1537 {
1538 halbtc8812a1ant_LowPenaltyRa(btcoexist, NORMAL_EXEC, true);
1539 }
1540 else
1541 {
1542 halbtc8812a1ant_LowPenaltyRa(btcoexist, NORMAL_EXEC, false);
1543 }
1544}
1545
1546BOOLEAN
1547halbtc8812a1ant_IsCommonAction(
1548 PBTC_COEXIST btcoexist
1549 )
1550{
1551 BOOLEAN common=false, wifi_connected=false, wifi_busy=false;
1552
1553 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
1554 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
1555
1556 //halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
1557
1558 if(!wifi_connected &&
1559 BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status)
1560 {
1561 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"));
1562 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
1563 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
1564
1565 halbtc8812a1ant_SwMechanism1(btcoexist,false,false,false,false);
1566 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
1567
1568 common = true;
1569 }
1570 else if(wifi_connected &&
1571 (BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status) )
1572 {
1573 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi connected + BT non connected-idle!!\n"));
1574 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
1575 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
1576
1577 halbtc8812a1ant_SwMechanism1(btcoexist,false,false,false,false);
1578 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
1579
1580 common = true;
1581 }
1582 else if(!wifi_connected &&
1583 (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) )
1584 {
1585 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"));
1586 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
1587 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
1588
1589 halbtc8812a1ant_SwMechanism1(btcoexist,false,false,false,false);
1590 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
1591
1592 common = true;
1593 }
1594 else if(wifi_connected &&
1595 (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) )
1596 {
1597 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi connected + BT connected-idle!!\n"));
1598 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
1599 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
1600
1601 halbtc8812a1ant_SwMechanism1(btcoexist,true,true,true,true);
1602 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
1603
1604 common = true;
1605 }
1606 else if(!wifi_connected &&
1607 (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE != coex_dm->bt_status) )
1608 {
1609 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi non connected-idle + BT Busy!!\n"));
1610 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
1611 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
1612
1613 halbtc8812a1ant_SwMechanism1(btcoexist,false,false,false,false);
1614 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
1615
1616 common = true;
1617 }
1618 else
1619 {
1620 halbtc8812a1ant_SwMechanism1(btcoexist,true,true,true,true);
1621
1622 common = false;
1623 }
1624
1625 return common;
1626}
1627
1628
1629void
1630halbtc8812a1ant_TdmaDurationAdjustForAcl(
1631 PBTC_COEXIST btcoexist
1632 )
1633{
1634 static s4Byte up,dn,m,n,wait_count;
1635 s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration
1636 u1Byte retry_count=0, bt_info_ext;
1637
1638 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], halbtc8812a1ant_TdmaDurationAdjustForAcl()\n"));
1639 if(coex_dm->reset_tdma_adjust)
1640 {
1641 coex_dm->reset_tdma_adjust = false;
1642 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], first run TdmaDurationAdjust()!!\n"));
1643
1644 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
1645 coex_dm->ps_tdma_du_adj_type = 2;
1646 //============
1647 up = 0;
1648 dn = 0;
1649 m = 1;
1650 n= 3;
1651 result = 0;
1652 wait_count = 0;
1653 }
1654 else
1655 {
1656 //accquire the BT TRx retry count from BT_Info byte2
1657 retry_count = coex_sta->bt_retry_cnt;
1658 bt_info_ext = coex_sta->bt_info_ext;
1659 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], retry_count = %d\n", retry_count));
1660 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_count=%d\n",
1661 up, dn, m, n, wait_count));
1662 result = 0;
1663 wait_count++;
1664
1665 if(retry_count == 0) // no retry in the last 2-second duration
1666 {
1667 up++;
1668 dn--;
1669
1670 if (dn <= 0)
1671 dn = 0;
1672
1673 if(up >= n) // if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration
1674 {
1675 wait_count = 0;
1676 n = 3;
1677 up = 0;
1678 dn = 0;
1679 result = 1;
1680 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], Increase wifi duration!!\n"));
1681 }
1682 }
1683 else if (retry_count <= 3) // <=3 retry in the last 2-second duration
1684 {
1685 up--;
1686 dn++;
1687
1688 if (up <= 0)
1689 up = 0;
1690
1691 if (dn == 2) // if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration
1692 {
1693 if (wait_count <= 2)
1694 m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^
1695 else
1696 m = 1;
1697
1698 if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
1699 m = 20;
1700
1701 n = 3*m;
1702 up = 0;
1703 dn = 0;
1704 wait_count = 0;
1705 result = -1;
1706 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n"));
1707 }
1708 }
1709 else //retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration
1710 {
1711 if (wait_count == 1)
1712 m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^
1713 else
1714 m = 1;
1715
1716 if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
1717 m = 20;
1718
1719 n = 3*m;
1720 up = 0;
1721 dn = 0;
1722 wait_count = 0;
1723 result = -1;
1724 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n"));
1725 }
1726
1727 if(result == -1)
1728 {
1729 if( (BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
1730 ((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) )
1731 {
1732 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 9);
1733 coex_dm->ps_tdma_du_adj_type = 9;
1734 }
1735 else if(coex_dm->cur_ps_tdma == 1)
1736 {
1737 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
1738 coex_dm->ps_tdma_du_adj_type = 2;
1739 }
1740 else if(coex_dm->cur_ps_tdma == 2)
1741 {
1742 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 9);
1743 coex_dm->ps_tdma_du_adj_type = 9;
1744 }
1745 else if(coex_dm->cur_ps_tdma == 9)
1746 {
1747 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 11);
1748 coex_dm->ps_tdma_du_adj_type = 11;
1749 }
1750 }
1751 else if(result == 1)
1752 {
1753 if( (BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
1754 ((coex_dm->cur_ps_tdma == 1) ||(coex_dm->cur_ps_tdma == 2)) )
1755 {
1756 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 9);
1757 coex_dm->ps_tdma_du_adj_type = 9;
1758 }
1759 else if(coex_dm->cur_ps_tdma == 11)
1760 {
1761 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 9);
1762 coex_dm->ps_tdma_du_adj_type = 9;
1763 }
1764 else if(coex_dm->cur_ps_tdma == 9)
1765 {
1766 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
1767 coex_dm->ps_tdma_du_adj_type = 2;
1768 }
1769 else if(coex_dm->cur_ps_tdma == 2)
1770 {
1771 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 1);
1772 coex_dm->ps_tdma_du_adj_type = 1;
1773 }
1774 }
1775
1776 if( coex_dm->cur_ps_tdma != 1 &&
1777 coex_dm->cur_ps_tdma != 2 &&
1778 coex_dm->cur_ps_tdma != 9 &&
1779 coex_dm->cur_ps_tdma != 11 )
1780 {
1781 // recover to previous adjust type
1782 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, coex_dm->ps_tdma_du_adj_type);
1783 }
1784 }
1785}
1786
1787u1Byte
1788halbtc8812a1ant_PsTdmaTypeByWifiRssi(
1789 s4Byte wifi_rssi,
1790 s4Byte pre_wifi_rssi,
1791 u1Byte wifi_rssi_thresh
1792 )
1793{
1794 u1Byte ps_tdma_type=0;
1795
1796 if(wifi_rssi > pre_wifi_rssi)
1797 {
1798 if(wifi_rssi > (wifi_rssi_thresh+5))
1799 {
1800 ps_tdma_type = 26;
1801 }
1802 else
1803 {
1804 ps_tdma_type = 25;
1805 }
1806 }
1807 else
1808 {
1809 if(wifi_rssi > wifi_rssi_thresh)
1810 {
1811 ps_tdma_type = 26;
1812 }
1813 else
1814 {
1815 ps_tdma_type = 25;
1816 }
1817 }
1818
1819 return ps_tdma_type;
1820}
1821
1822void
1823halbtc8812a1ant_PsTdmaCheckForPowerSaveState(
1824 PBTC_COEXIST btcoexist,
1825 BOOLEAN new_ps_state
1826 )
1827{
1828 u1Byte lps_mode=0x0;
1829
1830 btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
1831
1832 if(lps_mode) // already under LPS state
1833 {
1834 if(new_ps_state)
1835 {
1836 // keep state under LPS, do nothing.
1837 }
1838 else
1839 {
1840 // will leave LPS state, turn off psTdma first
1841 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 0);
1842 }
1843 }
1844 else // NO PS state
1845 {
1846 if(new_ps_state)
1847 {
1848 // will enter LPS state, turn off psTdma first
1849 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 0);
1850 }
1851 else
1852 {
1853 // keep state under NO PS state, do nothing.
1854 }
1855 }
1856}
1857
1858// SCO only or SCO+PAN(HS)
1859void
1860halbtc8812a1ant_ActionSco(
1861 PBTC_COEXIST btcoexist
1862 )
1863{
1864 u1Byte wifi_rssi_state;
1865 u4Byte wifi_bw;
1866
1867 wifi_rssi_state = halbtc8812a1ant_WifiRssiState(btcoexist, 0, 2, 25, 0);
1868
1869 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 4);
1870
1871 if(halbtc8812a1ant_NeedToDecBtPwr(btcoexist))
1872 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
1873 else
1874 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
1875
1876 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
1877
1878 if(BTC_WIFI_BW_HT40 == wifi_bw)
1879 {
1880 // sw mechanism
1881 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
1882 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
1883 {
1884 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
1885 }
1886 else
1887 {
1888 halbtc8812a1ant_SwMechanism2(btcoexist,false,true,false,0x18);
1889 }
1890 }
1891 else
1892 {
1893 // sw mechanism
1894 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
1895 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
1896 {
1897 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
1898 }
1899 else
1900 {
1901 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
1902 }
1903 }
1904}
1905
1906
1907void
1908halbtc8812a1ant_ActionHid(
1909 PBTC_COEXIST btcoexist
1910 )
1911{
1912 u1Byte wifi_rssi_state, bt_rssi_state;
1913 u4Byte wifi_bw;
1914
1915 wifi_rssi_state = halbtc8812a1ant_WifiRssiState(btcoexist, 0, 2, 25, 0);
1916 bt_rssi_state = halbtc8812a1ant_BtRssiState(2, 50, 0);
1917
1918 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
1919
1920 if(halbtc8812a1ant_NeedToDecBtPwr(btcoexist))
1921 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
1922 else
1923 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
1924
1925 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
1926
1927 if(BTC_WIFI_BW_HT40 == wifi_bw)
1928 {
1929 // sw mechanism
1930 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
1931 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
1932 {
1933 halbtc8812a1ant_SwMechanism2(btcoexist,true,false,false,0x18);
1934 }
1935 else
1936 {
1937 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
1938 }
1939 }
1940 else
1941 {
1942 // sw mechanism
1943 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
1944 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
1945 {
1946 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
1947 }
1948 else
1949 {
1950 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
1951 }
1952 }
1953}
1954
1955//A2DP only / PAN(EDR) only/ A2DP+PAN(HS)
1956void
1957halbtc8812a1ant_ActionA2dp(
1958 PBTC_COEXIST btcoexist
1959 )
1960{
1961 u1Byte wifi_rssi_state, bt_rssi_state;
1962 u4Byte wifi_bw;
1963
1964 wifi_rssi_state = halbtc8812a1ant_WifiRssiState(btcoexist, 0, 2, 25, 0);
1965 bt_rssi_state = halbtc8812a1ant_BtRssiState(2, 50, 0);
1966
1967 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
1968
1969 if(halbtc8812a1ant_NeedToDecBtPwr(btcoexist))
1970 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
1971 else
1972 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
1973
1974 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
1975
1976 if(BTC_WIFI_BW_HT40 == wifi_bw)
1977 {
1978 // sw mechanism
1979 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
1980 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
1981 {
1982 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
1983 }
1984 else
1985 {
1986 halbtc8812a1ant_SwMechanism2(btcoexist,false,true,false,0x18);
1987 }
1988 }
1989 else
1990 {
1991 // sw mechanism
1992 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
1993 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
1994 {
1995 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
1996 }
1997 else
1998 {
1999 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
2000 }
2001 }
2002}
2003
2004void
2005halbtc8812a1ant_ActionA2dpPanHs(
2006 PBTC_COEXIST btcoexist
2007 )
2008{
2009 u1Byte wifi_rssi_state, bt_rssi_state, bt_info_ext;
2010 u4Byte wifi_bw;
2011
2012 bt_info_ext = coex_sta->bt_info_ext;
2013 wifi_rssi_state = halbtc8812a1ant_WifiRssiState(btcoexist, 0, 2, 25, 0);
2014 bt_rssi_state = halbtc8812a1ant_BtRssiState(2, 50, 0);
2015
2016 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
2017
2018 if(halbtc8812a1ant_NeedToDecBtPwr(btcoexist))
2019 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
2020 else
2021 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
2022
2023 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2024
2025 if(BTC_WIFI_BW_HT40 == wifi_bw)
2026 {
2027 // sw mechanism
2028 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2029 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2030 {
2031 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2032 }
2033 else
2034 {
2035 halbtc8812a1ant_SwMechanism2(btcoexist,false,true,false,0x18);
2036 }
2037 }
2038 else
2039 {
2040 // sw mechanism
2041 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2042 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2043 {
2044 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2045 }
2046 else
2047 {
2048 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
2049 }
2050 }
2051}
2052
2053void
2054halbtc8812a1ant_ActionPanEdr(
2055 PBTC_COEXIST btcoexist
2056 )
2057{
2058 u1Byte wifi_rssi_state, bt_rssi_state;
2059 u4Byte wifi_bw;
2060
2061 wifi_rssi_state = halbtc8812a1ant_WifiRssiState(btcoexist, 0, 2, 25, 0);
2062 bt_rssi_state = halbtc8812a1ant_BtRssiState(2, 50, 0);
2063
2064 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
2065
2066 if(halbtc8812a1ant_NeedToDecBtPwr(btcoexist))
2067 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
2068 else
2069 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
2070
2071 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2072
2073 if(BTC_WIFI_BW_HT40 == wifi_bw)
2074 {
2075 // sw mechanism
2076 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2077 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2078 {
2079 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2080 }
2081 else
2082 {
2083 halbtc8812a1ant_SwMechanism2(btcoexist,false,true,false,0x18);
2084 }
2085 }
2086 else
2087 {
2088 // sw mechanism
2089 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2090 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2091 {
2092 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2093 }
2094 else
2095 {
2096 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
2097 }
2098 }
2099}
2100
2101
2102//PAN(HS) only
2103void
2104halbtc8812a1ant_ActionPanHs(
2105 PBTC_COEXIST btcoexist
2106 )
2107{
2108 u1Byte wifi_rssi_state, bt_rssi_state;
2109 u4Byte wifi_bw;
2110
2111 wifi_rssi_state = halbtc8812a1ant_WifiRssiState(btcoexist, 0, 2, 25, 0);
2112 bt_rssi_state = halbtc8812a1ant_BtRssiState(2, 50, 0);
2113
2114 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
2115
2116 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2117
2118 if(BTC_WIFI_BW_HT40 == wifi_bw)
2119 {
2120 // fw mechanism
2121 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2122 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2123 {
2124 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
2125 }
2126 else
2127 {
2128 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
2129 }
2130
2131 // sw mechanism
2132 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2133 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2134 {
2135 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2136 }
2137 else
2138 {
2139 halbtc8812a1ant_SwMechanism2(btcoexist,false,true,false,0x18);
2140 }
2141 }
2142 else
2143 {
2144 // fw mechanism
2145 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2146 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2147 {
2148 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
2149 }
2150 else
2151 {
2152 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
2153 }
2154
2155 // sw mechanism
2156 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2157 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2158 {
2159 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2160 }
2161 else
2162 {
2163 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
2164 }
2165 }
2166}
2167
2168//PAN(EDR)+A2DP
2169void
2170halbtc8812a1ant_ActionPanEdrA2dp(
2171 PBTC_COEXIST btcoexist
2172 )
2173{
2174 u1Byte wifi_rssi_state, bt_rssi_state, bt_info_ext;
2175 u4Byte wifi_bw;
2176
2177 bt_info_ext = coex_sta->bt_info_ext;
2178 wifi_rssi_state = halbtc8812a1ant_WifiRssiState(btcoexist, 0, 2, 25, 0);
2179 bt_rssi_state = halbtc8812a1ant_BtRssiState(2, 50, 0);
2180
2181 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
2182
2183 if(halbtc8812a1ant_NeedToDecBtPwr(btcoexist))
2184 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
2185 else
2186 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
2187
2188 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2189
2190 if(BTC_WIFI_BW_HT40 == wifi_bw)
2191 {
2192 // sw mechanism
2193 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2194 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2195 {
2196 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2197 }
2198 else
2199 {
2200 halbtc8812a1ant_SwMechanism2(btcoexist,false,true,false,0x18);
2201 }
2202 }
2203 else
2204 {
2205 // sw mechanism
2206 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2207 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2208 {
2209 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2210 }
2211 else
2212 {
2213 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
2214 }
2215 }
2216}
2217
2218void
2219halbtc8812a1ant_ActionPanEdrHid(
2220 PBTC_COEXIST btcoexist
2221 )
2222{
2223 u1Byte wifi_rssi_state, bt_rssi_state;
2224 u4Byte wifi_bw;
2225
2226 wifi_rssi_state = halbtc8812a1ant_WifiRssiState(btcoexist, 0, 2, 25, 0);
2227 bt_rssi_state = halbtc8812a1ant_BtRssiState(2, 50, 0);
2228
2229 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
2230
2231 if(halbtc8812a1ant_NeedToDecBtPwr(btcoexist))
2232 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
2233 else
2234 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
2235
2236 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2237
2238 if(BTC_WIFI_BW_HT40 == wifi_bw)
2239 {
2240 // sw mechanism
2241 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2242 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2243 {
2244 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2245 }
2246 else
2247 {
2248 halbtc8812a1ant_SwMechanism2(btcoexist,false,true,false,0x18);
2249 }
2250 }
2251 else
2252 {
2253 // sw mechanism
2254 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2255 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2256 {
2257 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2258 }
2259 else
2260 {
2261 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
2262 }
2263 }
2264}
2265
2266// HID+A2DP+PAN(EDR)
2267void
2268halbtc8812a1ant_ActionHidA2dpPanEdr(
2269 PBTC_COEXIST btcoexist
2270 )
2271{
2272 u1Byte wifi_rssi_state, bt_rssi_state, bt_info_ext;
2273 u4Byte wifi_bw;
2274
2275 bt_info_ext = coex_sta->bt_info_ext;
2276 wifi_rssi_state = halbtc8812a1ant_WifiRssiState(btcoexist, 0, 2, 25, 0);
2277 bt_rssi_state = halbtc8812a1ant_BtRssiState(2, 50, 0);
2278
2279 halbtc8812a1ant_FwDacSwingLvl(btcoexist, NORMAL_EXEC, 6);
2280
2281 if(halbtc8812a1ant_NeedToDecBtPwr(btcoexist))
2282 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
2283 else
2284 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
2285
2286 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2287
2288 if(BTC_WIFI_BW_HT40 == wifi_bw)
2289 {
2290 // sw mechanism
2291 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2292 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2293 {
2294 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2295 }
2296 else
2297 {
2298 halbtc8812a1ant_SwMechanism2(btcoexist,false,true,false,0x18);
2299 }
2300 }
2301 else
2302 {
2303 // sw mechanism
2304 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2305 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2306 {
2307 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2308 }
2309 else
2310 {
2311 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
2312 }
2313 }
2314}
2315
2316void
2317halbtc8812a1ant_ActionHidA2dp(
2318 PBTC_COEXIST btcoexist
2319 )
2320{
2321 u1Byte wifi_rssi_state, bt_rssi_state, bt_info_ext;
2322 u4Byte wifi_bw;
2323
2324 bt_info_ext = coex_sta->bt_info_ext;
2325 wifi_rssi_state = halbtc8812a1ant_WifiRssiState(btcoexist, 0, 2, 25, 0);
2326 bt_rssi_state = halbtc8812a1ant_BtRssiState(2, 50, 0);
2327
2328 if(halbtc8812a1ant_NeedToDecBtPwr(btcoexist))
2329 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, true);
2330 else
2331 halbtc8812a1ant_DecBtPwr(btcoexist, NORMAL_EXEC, false);
2332
2333 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2334
2335 if(BTC_WIFI_BW_HT40 == wifi_bw)
2336 {
2337 // sw mechanism
2338 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2339 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2340 {
2341 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2342 }
2343 else
2344 {
2345 halbtc8812a1ant_SwMechanism2(btcoexist,false,true,false,0x18);
2346 }
2347 }
2348 else
2349 {
2350 // sw mechanism
2351 if( (wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2352 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
2353 {
2354 halbtc8812a1ant_SwMechanism2(btcoexist,true,true,false,0x18);
2355 }
2356 else
2357 {
2358 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
2359 }
2360 }
2361}
2362
2363void
2364halbtc8812a1ant_ActionHs(
2365 PBTC_COEXIST btcoexist,
2366 BOOLEAN hs_connecting
2367 )
2368{
2369 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action for HS, hs_connecting=%d!!!\n", hs_connecting));
2370 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 8);
2371
2372 if(hs_connecting)
2373 {
2374 halbtc8812a1ant_CoexTable(btcoexist, FORCE_EXEC, 0xaaaaaaaa, 0xaaaaaaaa, 0xffff, 0x3);
2375 }
2376 else
2377 {
2378 if((coex_sta->high_priority_tx+coex_sta->high_priority_rx+
2379 coex_sta->low_priority_tx+coex_sta->low_priority_rx)<=1200)
2380 halbtc8812a1ant_CoexTable(btcoexist, FORCE_EXEC, 0xaaaaaaaa, 0xaaaaaaaa, 0xffff, 0x3);
2381 else
2382 halbtc8812a1ant_CoexTable(btcoexist, FORCE_EXEC, 0xffffffff, 0xffffffff, 0xffff, 0x3);
2383 }
2384}
2385
2386
2387void
2388halbtc8812a1ant_ActionWifiNotConnected(
2389 PBTC_COEXIST btcoexist
2390 )
2391{
2392 BOOLEAN hs_connecting=false;
2393
2394 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_CONNECTING, &hs_connecting);
2395
2396 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2397 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2398
2399 if(hs_connecting)
2400 {
2401 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HS is connecting!!!\n"));
2402 halbtc8812a1ant_ActionHs(btcoexist, hs_connecting);
2403 }
2404 else
2405 {
2406 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 8);
2407 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2408 }
2409}
2410
2411void
2412halbtc8812a1ant_ActionWifiNotConnectedAssoAuthScan(
2413 PBTC_COEXIST btcoexist
2414 )
2415{
2416 PBTC_STACK_INFO stack_info=&btcoexist->stack_info;
2417 BOOLEAN hs_connecting=false;
2418
2419 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_CONNECTING, &hs_connecting);
2420 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2421 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2422
2423 if(hs_connecting)
2424 {
2425 halbtc8812a1ant_ActionHs(btcoexist, hs_connecting);
2426 }
2427 else if(btcoexist->bt_info.bt_disabled)
2428 {
2429 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
2430 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2431 }
2432 else if(BT_8812A_1ANT_BT_STATUS_INQ_PAGE == coex_dm->bt_status)
2433{
2434 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 30);
2435 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2436 }
2437 else if( (BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status) ||
2438 (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) )
2439 {
2440 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 28);
2441 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2442 }
2443 else if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status)
2444 {
2445 if(stack_info->hid_exist)
2446 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 35);
2447 else
2448 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 29);
2449 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2450 }
2451 else if( (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
2452 (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status) )
2453 {
2454 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 8);
2455 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x5aea5aea, 0x5aea5aea, 0xffff, 0x3);
2456 }
2457 else
2458 {
2459 //error condition, should not reach here, record error number for debugging.
2460 coex_dm->error_condition = 1;
2461 }
2462}
2463
2464void
2465halbtc8812a1ant_ActionWifiConnectedScan(
2466 PBTC_COEXIST btcoexist
2467 )
2468{
2469 PBTC_STACK_INFO stack_info=&btcoexist->stack_info;
2470
2471 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], ActionConnectedScan()===>\n"));
2472
2473 if(btcoexist->bt_info.bt_disabled)
2474 {
2475 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2476 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2477 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
2478 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2479 }
2480 else
2481 {
2482 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, true);
2483 halbtc8812a1ant_LpsRpwm(btcoexist, NORMAL_EXEC, 0x0, 0x4);
2484 // power save must executed before psTdma.
2485 btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
2486
2487 // psTdma
2488 if(BT_8812A_1ANT_BT_STATUS_INQ_PAGE == coex_dm->bt_status)
2489 {
2490 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], ActionConnectedScan(), bt is under inquiry/page scan\n"));
2491 if(stack_info->sco_exist)
2492 {
2493 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 32);
2494 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2495 }
2496 else
2497 {
2498 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 30);
2499 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2500 }
2501 }
2502 else if( (BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status) ||
2503 (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) )
2504 {
2505 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 5);
2506 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2507 }
2508 else if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status)
2509 {
2510 if(stack_info->hid_exist)
2511 {
2512 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 34);
2513 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2514 }
2515 else
2516 {
2517 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 4);
2518 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2519 }
2520 }
2521 else if( (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
2522 (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status) )
2523 {
2524 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 33);
2525 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2526 }
2527 else
2528 {
2529 //error condition, should not reach here
2530 coex_dm->error_condition = 2;
2531 }
2532 }
2533 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], ActionConnectedScan()<===\n"));
2534}
2535
2536void
2537halbtc8812a1ant_ActionWifiConnectedSpecialPacket(
2538 PBTC_COEXIST btcoexist
2539 )
2540{
2541 PBTC_STACK_INFO stack_info=&btcoexist->stack_info;
2542
2543 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2544 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2545
2546 if(btcoexist->bt_info.bt_disabled)
2547 {
2548 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
2549 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2550 }
2551 else
2552 {
2553 if(BT_8812A_1ANT_BT_STATUS_INQ_PAGE == coex_dm->bt_status)
2554 {
2555 if(stack_info->sco_exist)
2556 {
2557 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 32);
2558 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2559 }
2560 else
2561 {
2562 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 30);
2563 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2564 }
2565 }
2566 else if( (BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status) ||
2567 (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) )
2568 {
2569 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 28);
2570 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2571 }
2572 else if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status)
2573 {
2574 if(stack_info->hid_exist)
2575 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 35);
2576 else
2577 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 29);
2578 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2579 }
2580 else if( (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
2581 (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status) )
2582 {
2583 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 8);
2584 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x5aea5aea, 0x5aea5aea, 0xffff, 0x3);
2585 }
2586 else
2587 {
2588 //error condition, should not reach here
2589 coex_dm->error_condition = 3;
2590 }
2591 }
2592}
2593
2594void
2595halbtc8812a1ant_ActionWifiConnected(
2596 PBTC_COEXIST btcoexist
2597 )
2598{
2599 PBTC_STACK_INFO stack_info=&btcoexist->stack_info;
2600 BOOLEAN wifi_connected=false, wifi_busy=false, bt_hs_on=false;
2601 BOOLEAN scan=false, link=false, roam=false;
2602 BOOLEAN hs_connecting=false, under4way=false;
2603 u4Byte wifi_bw;
2604
2605 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], CoexForWifiConnect()===>\n"));
2606
2607 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
2608 if(!wifi_connected)
2609 {
2610 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], CoexForWifiConnect(), return for wifi not connected<===\n"));
2611 return;
2612 }
2613
2614 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &under4way);
2615 if(under4way)
2616 {
2617 halbtc8812a1ant_ActionWifiConnectedSpecialPacket(btcoexist);
2618 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"));
2619 return;
2620 }
2621
2622 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_CONNECTING, &hs_connecting);
2623 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
2624 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
2625 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
2626 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
2627 if(scan || link || roam)
2628 {
2629 halbtc8812a1ant_ActionWifiConnectedScan(btcoexist);
2630 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"));
2631 return;
2632 }
2633
2634 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
2635 if(!wifi_busy)
2636 {
2637 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], wifi associated-idle!!!\n"));
2638 if(btcoexist->bt_info.bt_disabled)
2639 {
2640 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, true);
2641 halbtc8812a1ant_LpsRpwm(btcoexist, NORMAL_EXEC, 0x0, 0x4);
2642 btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
2643 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
2644 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2645 }
2646 else
2647 {
2648 if(BT_8812A_1ANT_BT_STATUS_INQ_PAGE == coex_dm->bt_status)
2649 {
2650 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], bt is under inquiry/page scan!!!\n"));
2651 if(stack_info->sco_exist)
2652 {
2653 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 32);
2654 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2655 }
2656 else
2657 {
2658 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, true);
2659 halbtc8812a1ant_LpsRpwm(btcoexist, NORMAL_EXEC, 0x0, 0x4);
2660 // power save must executed before psTdma.
2661 btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
2662 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 30);
2663 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2664 }
2665 }
2666 else if(BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status)
2667 {
2668 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, true);
2669 halbtc8812a1ant_LpsRpwm(btcoexist, NORMAL_EXEC, 0x26, 0x0);
2670 // power save must executed before psTdma.
2671 btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
2672 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
2673 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2674 }
2675 else if(BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
2676 {
2677 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, true);
2678 halbtc8812a1ant_LpsRpwm(btcoexist, NORMAL_EXEC, 0x26, 0x0);
2679 // power save must executed before psTdma.
2680 btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
2681 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 0);
2682 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2683 }
2684 else if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status)
2685 {
2686 if(stack_info->hid_exist && stack_info->numOfLink==1)
2687 {
2688 // hid only
2689 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2690 // power save must executed before psTdma.
2691 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2692
2693 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 8);
2694 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x5fff5fff, 0x5fff5fff, 0xffff, 0x3);
2695 coex_dm->reset_tdma_adjust = true;
2696 }
2697 else
2698 {
2699 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, true);
2700 halbtc8812a1ant_LpsRpwm(btcoexist, NORMAL_EXEC, 0x0, 0x4);
2701 // power save must executed before psTdma.
2702 btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
2703
2704 if(stack_info->hid_exist)
2705 {
2706 if(stack_info->a2dp_exist)
2707 {
2708 // hid+a2dp
2709 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
2710 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2711 }
2712 else if(stack_info->pan_exist)
2713 {
2714 if(bt_hs_on)
2715 {
2716 // hid+hs
2717 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
2718 }
2719 else
2720 {
2721 // hid+pan
2722 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
2723 }
2724 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2725 }
2726 else
2727 {
2728 coex_dm->error_condition = 4;
2729 }
2730 coex_dm->reset_tdma_adjust = true;
2731 }
2732 else if(stack_info->a2dp_exist)
2733 {
2734 if(stack_info->pan_exist)
2735 {
2736 if(bt_hs_on)
2737 {
2738 // a2dp+hs
2739 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
2740 }
2741 else
2742 {
2743 // a2dp+pan
2744 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 36);
2745 }
2746 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2747 coex_dm->reset_tdma_adjust = true;
2748 }
2749 else
2750 {
2751 // a2dp only
2752 halbtc8812a1ant_TdmaDurationAdjustForAcl(btcoexist);
2753 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2754 }
2755 }
2756 else if(stack_info->pan_exist)
2757 {
2758 // pan only
2759 if(bt_hs_on)
2760 {
2761 coex_dm->error_condition = 5;
2762 }
2763 else
2764 {
2765 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
2766 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2767 }
2768 coex_dm->reset_tdma_adjust = true;
2769 }
2770 else
2771 {
2772 // temp state, do nothing!!!
2773 //DbgPrint("error 6, coex_dm->bt_status=%d\n", coex_dm->bt_status);
2774 //DbgPrint("error 6, stack_info->numOfLink=%d, stack_info->hid_exist=%d, stack_info->a2dp_exist=%d, stack_info->pan_exist=%d, stack_info->sco_exist=%d\n",
2775 //stack_info->numOfLink, stack_info->hid_exist, stack_info->a2dp_exist, stack_info->pan_exist, stack_info->sco_exist);
2776 //coex_dm->error_condition = 6;
2777 }
2778 }
2779 }
2780 else if( (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
2781 (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status) )
2782 {
2783 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2784 // power save must executed before psTdma.
2785 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2786
2787 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 8);
2788 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x5aea5aea, 0x5aea5aea, 0xffff, 0x3);
2789 }
2790 else
2791 {
2792 //error condition, should not reach here
2793 coex_dm->error_condition = 7;
2794 }
2795 }
2796 }
2797 else
2798 {
2799 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], wifi busy!!!\n"));
2800 if(btcoexist->bt_info.bt_disabled)
2801 {
2802 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2803 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2804 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
2805 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2806 }
2807 else
2808 {
2809 if(bt_hs_on)
2810 {
2811 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HS is under progress!!!\n"));
2812 //DbgPrint("coex_dm->bt_status = 0x%x\n", coex_dm->bt_status);
2813 halbtc8812a1ant_ActionHs(btcoexist, hs_connecting);
2814 }
2815 else if(BT_8812A_1ANT_BT_STATUS_INQ_PAGE == coex_dm->bt_status)
2816 {
2817 if(stack_info->sco_exist)
2818 {
2819 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 32);
2820 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2821 }
2822 else
2823 {
2824 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, true);
2825 halbtc8812a1ant_LpsRpwm(btcoexist, NORMAL_EXEC, 0x0, 0x4);
2826 // power save must executed before psTdma.
2827 btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
2828 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 30);
2829 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
2830 }
2831 }
2832 else if(BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status)
2833 {
2834 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2835 // power save must executed before psTdma.
2836 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2837 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 5);
2838 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x5a5a5a5a, 0x5a5a5a5a, 0xffff, 0x3);
2839 }
2840 else if(BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)
2841 {
2842 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2843 // power save must executed before psTdma.
2844 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2845 if(bt_hs_on)
2846 {
2847 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HS is under progress!!!\n"));
2848 halbtc8812a1ant_ActionHs(btcoexist, hs_connecting);
2849 }
2850 else
2851 {
2852 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 5);
2853 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x5a5a5a5a, 0x5a5a5a5a, 0xffff, 0x3);
2854 }
2855 }
2856 else if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status)
2857 {
2858 if(stack_info->hid_exist && stack_info->numOfLink==1)
2859 {
2860 // hid only
2861 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2862 // power save must executed before psTdma.
2863 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2864
2865 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 8);
2866 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x5fff5fff, 0x5fff5fff, 0xffff, 0x3);
2867 coex_dm->reset_tdma_adjust = true;
2868 }
2869 else
2870 {
2871 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, true);
2872 halbtc8812a1ant_LpsRpwm(btcoexist, NORMAL_EXEC, 0x0, 0x4);
2873 // power save must executed before psTdma.
2874 btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
2875
2876 if(stack_info->hid_exist)
2877 {
2878 if(stack_info->a2dp_exist)
2879 {
2880 // hid+a2dp
2881 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
2882 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2883 }
2884 else if(stack_info->pan_exist)
2885 {
2886 if(bt_hs_on)
2887 {
2888 // hid+hs
2889 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
2890 }
2891 else
2892 {
2893 // hid+pan
2894 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
2895 }
2896 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2897 }
2898 else
2899 {
2900 coex_dm->error_condition = 8;
2901 }
2902 coex_dm->reset_tdma_adjust = true;
2903 }
2904 else if(stack_info->a2dp_exist)
2905 {
2906 if(stack_info->pan_exist)
2907 {
2908 if(bt_hs_on)
2909 {
2910 // a2dp+hs
2911 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
2912 }
2913 else
2914 {
2915 // a2dp+pan
2916 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 36);
2917 }
2918 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2919 coex_dm->reset_tdma_adjust = true;
2920 }
2921 else
2922 {
2923 // a2dp only
2924 halbtc8812a1ant_TdmaDurationAdjustForAcl(btcoexist);
2925 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2926 }
2927 }
2928 else if(stack_info->pan_exist)
2929 {
2930 // pan only
2931 if(bt_hs_on)
2932 {
2933 coex_dm->error_condition = 9;
2934 }
2935 else
2936 {
2937 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, true, 2);
2938 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x5afa5afa, 0xffff, 0x3);
2939 }
2940 coex_dm->reset_tdma_adjust = true;
2941 }
2942 else
2943 {
2944 //DbgPrint("error 10, stack_info->numOfLink=%d, stack_info->hid_exist=%d, stack_info->a2dp_exist=%d, stack_info->pan_exist=%d, stack_info->sco_exist=%d\n",
2945 //stack_info->numOfLink, stack_info->hid_exist, stack_info->a2dp_exist, stack_info->pan_exist, stack_info->sco_exist);
2946 coex_dm->error_condition = 10;
2947 }
2948 }
2949 }
2950 else if( (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
2951 (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status) )
2952 {
2953 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2954 // power save must executed before psTdma.
2955 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2956
2957 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 8);
2958 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x5aea5aea, 0x5aea5aea, 0xffff, 0x3);
2959 }
2960 else
2961 {
2962 //DbgPrint("error 11, coex_dm->bt_status=%d\n", coex_dm->bt_status);
2963 //DbgPrint("error 11, stack_info->numOfLink=%d, stack_info->hid_exist=%d, stack_info->a2dp_exist=%d, stack_info->pan_exist=%d, stack_info->sco_exist=%d\n",
2964 //stack_info->numOfLink, stack_info->hid_exist, stack_info->a2dp_exist, stack_info->pan_exist, stack_info->sco_exist);
2965 //error condition, should not reach here
2966 coex_dm->error_condition = 11;
2967 }
2968 }
2969 }
2970 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], CoexForWifiConnect()<===\n"));
2971}
2972
2973void
2974halbtc8812a1ant_RunSwCoexistMechanism(
2975 PBTC_COEXIST btcoexist
2976 )
2977{
2978 PBTC_STACK_INFO stack_info=&btcoexist->stack_info;
2979 BOOLEAN wifi_under5g=false, wifi_busy=false, wifi_connected=false;
2980 u1Byte bt_info_original=0, bt_retry_cnt=0;
2981 u1Byte algorithm=0;
2982
2983 return;
2984 if(stack_info->bProfileNotified)
2985 {
2986 algorithm = halbtc8812a1ant_ActionAlgorithm(btcoexist);
2987 coex_dm->cur_algorithm = algorithm;
2988 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Algorithm = %d \n", coex_dm->cur_algorithm));
2989
2990 if(halbtc8812a1ant_IsCommonAction(btcoexist))
2991 {
2992 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action common.\n"));
2993 }
2994 else
2995 {
2996 switch(coex_dm->cur_algorithm)
2997 {
2998 case BT_8812A_1ANT_COEX_ALGO_SCO:
2999 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = SCO.\n"));
3000 halbtc8812a1ant_ActionSco(btcoexist);
3001 break;
3002 case BT_8812A_1ANT_COEX_ALGO_HID:
3003 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = HID.\n"));
3004 halbtc8812a1ant_ActionHid(btcoexist);
3005 break;
3006 case BT_8812A_1ANT_COEX_ALGO_A2DP:
3007 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = A2DP.\n"));
3008 halbtc8812a1ant_ActionA2dp(btcoexist);
3009 break;
3010 case BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS:
3011 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = A2DP+PAN(HS).\n"));
3012 halbtc8812a1ant_ActionA2dpPanHs(btcoexist);
3013 break;
3014 case BT_8812A_1ANT_COEX_ALGO_PANEDR:
3015 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = PAN(EDR).\n"));
3016 halbtc8812a1ant_ActionPanEdr(btcoexist);
3017 break;
3018 case BT_8812A_1ANT_COEX_ALGO_PANHS:
3019 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = HS mode.\n"));
3020 halbtc8812a1ant_ActionPanHs(btcoexist);
3021 break;
3022 case BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP:
3023 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = PAN+A2DP.\n"));
3024 halbtc8812a1ant_ActionPanEdrA2dp(btcoexist);
3025 break;
3026 case BT_8812A_1ANT_COEX_ALGO_PANEDR_HID:
3027 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = PAN(EDR)+HID.\n"));
3028 halbtc8812a1ant_ActionPanEdrHid(btcoexist);
3029 break;
3030 case BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
3031 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = HID+A2DP+PAN.\n"));
3032 halbtc8812a1ant_ActionHidA2dpPanEdr(btcoexist);
3033 break;
3034 case BT_8812A_1ANT_COEX_ALGO_HID_A2DP:
3035 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = HID+A2DP.\n"));
3036 halbtc8812a1ant_ActionHidA2dp(btcoexist);
3037 break;
3038 default:
3039 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = coexist All Off!!\n"));
3040 halbtc8812a1ant_CoexAllOff(btcoexist);
3041 break;
3042 }
3043 coex_dm->pre_algorithm = coex_dm->cur_algorithm;
3044 }
3045 }
3046}
3047
3048void
3049halbtc8812a1ant_RunCoexistMechanism(
3050 PBTC_COEXIST btcoexist
3051 )
3052{
3053 PBTC_STACK_INFO stack_info=&btcoexist->stack_info;
3054 BOOLEAN wifi_under5g=false, wifi_busy=false, wifi_connected=false;
3055
3056 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], RunCoexistMechanism()===>\n"));
3057
3058 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under5g);
3059
3060 if(wifi_under5g)
3061 {
3062 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], RunCoexistMechanism(), return for 5G <===\n"));
3063 return;
3064 }
3065
3066 if(btcoexist->manual_control)
3067 {
3068 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"));
3069 return;
3070 }
3071
3072 if(btcoexist->stop_coex_dm)
3073 {
3074 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"));
3075 return;
3076 }
3077
3078 halbtc8812a1ant_RunSwCoexistMechanism(btcoexist);
3079
3080 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
3081 if(btcoexist->bt_info.bt_disabled)
3082 {
3083 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], bt is disabled!!!\n"));
3084 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
3085 if(wifi_busy)
3086 {
3087 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
3088 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
3089 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
3090 }
3091 else
3092 {
3093 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, true);
3094 halbtc8812a1ant_LpsRpwm(btcoexist, NORMAL_EXEC, 0x0, 0x4);
3095 // power save must executed before psTdma.
3096 btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
3097 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
3098 }
3099 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
3100 }
3101 else if(coex_sta->under_ips)
3102 {
3103 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], wifi is under IPS !!!\n"));
3104 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 0);
3105 halbtc8812a1ant_CoexTable(btcoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
3106 halbtc8812a1ant_WifiParaAdjust(btcoexist, false);
3107 }
3108 else if(!wifi_connected)
3109 {
3110 BOOLEAN scan=false, link=false, roam=false;
3111
3112 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], wifi is non connected-idle !!!\n"));
3113
3114 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
3115 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
3116 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
3117
3118 if(scan || link || roam)
3119 halbtc8812a1ant_ActionWifiNotConnectedAssoAuthScan(btcoexist);
3120 else
3121 halbtc8812a1ant_ActionWifiNotConnected(btcoexist);
3122 }
3123 else // wifi LPS/Busy
3124 {
3125 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], wifi is NOT under IPS!!!\n"));
3126 halbtc8812a1ant_WifiParaAdjust(btcoexist, true);
3127 halbtc8812a1ant_ActionWifiConnected(btcoexist);
3128 }
3129 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], RunCoexistMechanism()<===\n"));
3130}
3131
3132void
3133halbtc8812a1ant_InitCoexDm(
3134 PBTC_COEXIST btcoexist
3135 )
3136{
3137 BOOLEAN wifi_connected=false;
3138 // force to reset coex mechanism
3139
3140 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
3141 if(!wifi_connected) // non-connected scan
3142 {
3143 halbtc8812a1ant_ActionWifiNotConnected(btcoexist);
3144 }
3145 else // wifi is connected
3146 {
3147 halbtc8812a1ant_ActionWifiConnected(btcoexist);
3148 }
3149
3150 halbtc8812a1ant_FwDacSwingLvl(btcoexist, FORCE_EXEC, 6);
3151 halbtc8812a1ant_DecBtPwr(btcoexist, FORCE_EXEC, false);
3152
3153 // sw all off
3154 halbtc8812a1ant_SwMechanism1(btcoexist,false,false,false,false);
3155 halbtc8812a1ant_SwMechanism2(btcoexist,false,false,false,0x18);
3156
3157 halbtc8812a1ant_CoexTable(btcoexist, FORCE_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3);
3158}
3159
3160//============================================================
3161// work around function start with wa_halbtc8812a1ant_
3162//============================================================
3163//============================================================
3164// extern function start with EXhalbtc8812a1ant_
3165//============================================================
3166void
3167EXhalbtc8812a1ant_InitHwConfig(
3168 PBTC_COEXIST btcoexist
3169 )
3170{
3171 u4Byte u4_tmp=0;
3172 u2Byte u2Tmp=0;
3173 u1Byte u1_tmp=0;
3174
3175 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], 1Ant Init HW Config!!\n"));
3176
3177 // backup rf 0x1e value
3178 coex_dm->bt_rf0x1e_backup =
3179 btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff);
3180
3181 //ant sw control to BT
3182 btcoexist->btc_write_4byte(btcoexist, 0x900, 0x00000400);
3183 btcoexist->btc_write_1byte(btcoexist, 0x76d, 0x1);
3184 btcoexist->btc_write_1byte(btcoexist, 0xcb3, 0x77);
3185 btcoexist->btc_write_1byte(btcoexist, 0xcb7, 0x40);
3186
3187 // 0x790[5:0]=0x5
3188 u1_tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
3189 u1_tmp &= 0xc0;
3190 u1_tmp |= 0x5;
3191 btcoexist->btc_write_1byte(btcoexist, 0x790, u1_tmp);
3192
3193 // PTA parameter
3194 btcoexist->btc_write_1byte(btcoexist, 0x6cc, 0x0);
3195 btcoexist->btc_write_4byte(btcoexist, 0x6c8, 0xffff);
3196 btcoexist->btc_write_4byte(btcoexist, 0x6c4, 0x55555555);
3197 btcoexist->btc_write_4byte(btcoexist, 0x6c0, 0x55555555);
3198
3199 // coex parameters
3200 btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
3201
3202 // enable counter statistics
3203 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
3204
3205 // enable PTA
3206 btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
3207
3208 // bt clock related
3209 u1_tmp = btcoexist->btc_read_1byte(btcoexist, 0x4);
3210 u1_tmp |= BIT7;
3211 btcoexist->btc_write_1byte(btcoexist, 0x4, u1_tmp);
3212
3213 // bt clock related
3214 u1_tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
3215 u1_tmp |= BIT1;
3216 btcoexist->btc_write_1byte(btcoexist, 0x7, u1_tmp);
3217}
3218
3219void
3220EXhalbtc8812a1ant_InitCoexDm(
3221 PBTC_COEXIST btcoexist
3222 )
3223{
3224 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], Coex Mechanism Init!!\n"));
3225
3226 btcoexist->stop_coex_dm = false;
3227
3228 halbtc8812a1ant_InitCoexDm(btcoexist);
3229}
3230
3231void
3232EXhalbtc8812a1ant_DisplayCoexInfo(
3233 PBTC_COEXIST btcoexist
3234 )
3235{
3236 PBTC_BOARD_INFO board_info=&btcoexist->boardInfo;
3237 PBTC_STACK_INFO stack_info=&btcoexist->stack_info;
3238 pu1Byte cli_buf=btcoexist->cli_buf;
3239 u1Byte u1_tmp[4], i, bt_info_ext, psTdmaCase=0;
3240 u4Byte u4_tmp[4];
3241 BOOLEAN roam=false, scan=false, link=false, wifi_under5g=false;
3242 BOOLEAN bt_hs_on=false, wifi_busy=false;
3243 s4Byte wifi_rssi=0, bt_hs_rssi=0;
3244 u4Byte wifi_bw, wifiTrafficDir;
3245 u1Byte wifiDot11Chnl, wifiHsChnl;
3246
3247 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============");
3248 CL_PRINTF(cli_buf);
3249
3250 if(btcoexist->manual_control)
3251 {
3252 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============");
3253 CL_PRINTF(cli_buf);
3254 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n ==========================================");
3255 CL_PRINTF(cli_buf);
3256 }
3257 if(btcoexist->stop_coex_dm)
3258 {
3259 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n ============[Coex is STOPPED]============");
3260 CL_PRINTF(cli_buf);
3261 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n ==========================================");
3262 CL_PRINTF(cli_buf);
3263 }
3264
3265 if(!board_info->bBtExist)
3266 {
3267 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n BT not exists !!!");
3268 CL_PRINTF(cli_buf);
3269 return;
3270 }
3271
3272 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \
3273 board_info->pgAntNum, board_info->btdmAntNum);
3274 CL_PRINTF(cli_buf);
3275
3276 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \
3277 ((stack_info->bProfileNotified)? "Yes":"No"), stack_info->hciVersion);
3278 CL_PRINTF(cli_buf);
3279 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_FW_VER);
3280
3281 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
3282 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiDot11Chnl);
3283 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifiHsChnl);
3284 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d(%d)", "Dot11 channel / HsChnl(HsMode)", \
3285 wifiDot11Chnl, wifiHsChnl, bt_hs_on);
3286 CL_PRINTF(cli_buf);
3287
3288 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "H2C Wifi inform bt chnl Info", \
3289 coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
3290 coex_dm->wifi_chnl_info[2]);
3291 CL_PRINTF(cli_buf);
3292
3293 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
3294 btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi);
3295 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "Wifi rssi/ HS rssi", \
3296 wifi_rssi, bt_hs_rssi);
3297 CL_PRINTF(cli_buf);
3298
3299 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
3300 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
3301 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
3302 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Wifi link/ roam/ scan", \
3303 link, roam, scan);
3304 CL_PRINTF(cli_buf);
3305
3306 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under5g);
3307 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3308 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
3309 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
3310 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s ", "Wifi status", \
3311 (wifi_under5g? "5G":"2.4G"),
3312 ((BTC_WIFI_BW_LEGACY==wifi_bw)? "Legacy": (((BTC_WIFI_BW_HT40==wifi_bw)? "HT40":"HT20"))),
3313 ((!wifi_busy)? "idle": ((BTC_WIFI_TRAFFIC_TX==wifiTrafficDir)? "uplink":"downlink")));
3314 CL_PRINTF(cli_buf);
3315 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \
3316 ((coex_sta->c2h_bt_inquiry_page)?("inquiry/page scan"):((BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status)? "non-connected idle":
3317 ( (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)? "connected-idle":"busy"))),
3318 coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
3319 CL_PRINTF(cli_buf);
3320
3321 if(stack_info->bProfileNotified)
3322 {
3323 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \
3324 stack_info->sco_exist, stack_info->hid_exist, stack_info->pan_exist, stack_info->a2dp_exist);
3325 CL_PRINTF(cli_buf);
3326
3327 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
3328 }
3329
3330 bt_info_ext = coex_sta->bt_info_ext;
3331 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \
3332 (bt_info_ext&BIT0)? "Basic rate":"EDR rate");
3333 CL_PRINTF(cli_buf);
3334
3335 for(i=0; i<BT_INFO_SRC_8812A_1ANT_MAX; i++)
3336 {
3337 if(coex_sta->bt_info_c2h_cnt[i])
3338 {
3339 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8812a1Ant[i], \
3340 coex_sta->bt_info_c2h[i][0], coex_sta->bt_info_c2h[i][1],
3341 coex_sta->bt_info_c2h[i][2], coex_sta->bt_info_c2h[i][3],
3342 coex_sta->bt_info_c2h[i][4], coex_sta->bt_info_c2h[i][5],
3343 coex_sta->bt_info_c2h[i][6], coex_sta->bt_info_c2h_cnt[i]);
3344 CL_PRINTF(cli_buf);
3345 }
3346 }
3347 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/%s, (0x%x/0x%x)", "PS state, IPS/LPS, (lps/rpwm)", \
3348 ((coex_sta->under_ips? "IPS ON":"IPS OFF")),
3349 ((coex_sta->under_lps? "LPS ON":"LPS OFF")),
3350 btcoexist->bt_info.lps1Ant,
3351 btcoexist->bt_info.rpwm1Ant);
3352 CL_PRINTF(cli_buf);
3353 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD);
3354
3355 if(!btcoexist->manual_control)
3356 {
3357 // Sw mechanism
3358 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============");
3359 CL_PRINTF(cli_buf);
3360
3361 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d ", "SM1[ShRf/ LpRA/ LimDig/ btLna]", \
3362 coex_dm->cur_rf_rx_lpf_shrink, coex_dm->cur_low_penalty_ra, coex_dm->limited_dig, coex_dm->bCurBtLnaConstrain);
3363 CL_PRINTF(cli_buf);
3364 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \
3365 coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off, coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
3366 CL_PRINTF(cli_buf);
3367
3368 // Fw mechanism
3369 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============");
3370 CL_PRINTF(cli_buf);
3371
3372 psTdmaCase = coex_dm->cur_ps_tdma;
3373 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \
3374 coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1],
3375 coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3],
3376 coex_dm->ps_tdma_para[4], psTdmaCase);
3377 CL_PRINTF(cli_buf);
3378
3379 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)", \
3380 coex_dm->error_condition);
3381 CL_PRINTF(cli_buf);
3382
3383 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \
3384 coex_dm->cur_dec_bt_pwr, coex_dm->cur_ignore_wlan_act);
3385 CL_PRINTF(cli_buf);
3386 }
3387
3388 // Hw setting
3389 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============");
3390 CL_PRINTF(cli_buf);
3391
3392 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \
3393 coex_dm->bt_rf0x1e_backup);
3394 CL_PRINTF(cli_buf);
3395
3396 u1_tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
3397 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", \
3398 u1_tmp[0]);
3399 CL_PRINTF(cli_buf);
3400
3401 u1_tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c);
3402 u4_tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930);
3403 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x92c/ 0x930", \
3404 (u1_tmp[0]), u4_tmp[0]);
3405 CL_PRINTF(cli_buf);
3406
3407 u1_tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
3408 u1_tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f);
3409 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x40/ 0x4f", \
3410 u1_tmp[0], u1_tmp[1]);
3411 CL_PRINTF(cli_buf);
3412
3413 u4_tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
3414 u1_tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
3415 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \
3416 u4_tmp[0], u1_tmp[0]);
3417 CL_PRINTF(cli_buf);
3418
3419 u4_tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
3420 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \
3421 u4_tmp[0]);
3422 CL_PRINTF(cli_buf);
3423
3424#if 0
3425 u4_tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xf48);
3426 u4_tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xf4c);
3427 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xf48/ 0xf4c (FA cnt)", \
3428 u4_tmp[0], u4_tmp[1]);
3429 CL_PRINTF(cli_buf);
3430#endif
3431
3432 u4_tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
3433 u4_tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
3434 u4_tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
3435 u1_tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
3436 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \
3437 u4_tmp[0], u4_tmp[1], u4_tmp[2], u1_tmp[0]);
3438 CL_PRINTF(cli_buf);
3439
3440 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(hp rx[31:16]/tx[15:0])", \
3441 coex_sta->high_priority_rx, coex_sta->high_priority_tx);
3442 CL_PRINTF(cli_buf);
3443 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \
3444 coex_sta->low_priority_rx, coex_sta->low_priority_tx);
3445 CL_PRINTF(cli_buf);
3446
3447 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
3448}
3449
3450
3451void
3452EXhalbtc8812a1ant_IpsNotify(
3453 PBTC_COEXIST btcoexist,
3454 u1Byte type
3455 )
3456{
3457 u4Byte u4_tmp=0;
3458
3459 if(btcoexist->manual_control || btcoexist->stop_coex_dm)
3460 return;
3461
3462 if(BTC_IPS_ENTER == type)
3463 {
3464 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], IPS ENTER notify\n"));
3465 coex_sta->under_ips = true;
3466
3467 // 0x4c[23]=1
3468 u4_tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
3469 u4_tmp |= BIT23;
3470 btcoexist->btc_write_4byte(btcoexist, 0x4c, u4_tmp);
3471
3472 halbtc8812a1ant_CoexAllOff(btcoexist);
3473 }
3474 else if(BTC_IPS_LEAVE == type)
3475 {
3476 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], IPS LEAVE notify\n"));
3477 coex_sta->under_ips = false;
3478 //halbtc8812a1ant_InitCoexDm(btcoexist);
3479 }
3480}
3481
3482void
3483EXhalbtc8812a1ant_LpsNotify(
3484 PBTC_COEXIST btcoexist,
3485 u1Byte type
3486 )
3487{
3488 if(btcoexist->manual_control || btcoexist->stop_coex_dm)
3489 return;
3490
3491 if(BTC_LPS_ENABLE == type)
3492 {
3493 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], LPS ENABLE notify\n"));
3494 coex_sta->under_lps = true;
3495 }
3496 else if(BTC_IPS_LEAVE == type)
3497 {
3498 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], LPS DISABLE notify\n"));
3499 coex_sta->under_lps = false;
3500 }
3501}
3502
3503void
3504EXhalbtc8812a1ant_ScanNotify(
3505 PBTC_COEXIST btcoexist,
3506 u1Byte type
3507 )
3508{
3509 PBTC_STACK_INFO stack_info=&btcoexist->stack_info;
3510 BOOLEAN wifi_connected=false;
3511
3512 if(btcoexist->manual_control ||btcoexist->stop_coex_dm)
3513 return;
3514
3515 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
3516 if(BTC_SCAN_START == type)
3517 {
3518 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], SCAN START notify\n"));
3519 if(!wifi_connected) // non-connected scan
3520 {
3521 //set 0x550[3]=1 before PsTdma
3522 //halbtc8812a1ant_Reg0x550Bit3(btcoexist, true);
3523 halbtc8812a1ant_ActionWifiNotConnectedAssoAuthScan(btcoexist);
3524 }
3525 else // wifi is connected
3526 {
3527 halbtc8812a1ant_ActionWifiConnectedScan(btcoexist);
3528 }
3529 }
3530 else if(BTC_SCAN_FINISH == type)
3531 {
3532 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], SCAN FINISH notify\n"));
3533 if(!wifi_connected) // non-connected scan
3534 {
3535 //halbtc8812a1ant_Reg0x550Bit3(btcoexist, false);
3536 halbtc8812a1ant_ActionWifiNotConnected(btcoexist);
3537 }
3538 else
3539 {
3540 halbtc8812a1ant_ActionWifiConnected(btcoexist);
3541 }
3542 }
3543}
3544
3545void
3546EXhalbtc8812a1ant_ConnectNotify(
3547 PBTC_COEXIST btcoexist,
3548 u1Byte type
3549 )
3550{
3551 PBTC_STACK_INFO stack_info=&btcoexist->stack_info;
3552 BOOLEAN wifi_connected=false;
3553
3554 if(btcoexist->manual_control ||btcoexist->stop_coex_dm)
3555 return;
3556
3557 if(BTC_ASSOCIATE_START == type)
3558 {
3559 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], CONNECT START notify\n"));
3560 if(btcoexist->bt_info.bt_disabled)
3561 {
3562 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
3563 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
3564 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
3565 }
3566 else
3567 {
3568 halbtc8812a1ant_ActionWifiNotConnectedAssoAuthScan(btcoexist);
3569 }
3570 }
3571 else if(BTC_ASSOCIATE_FINISH == type)
3572 {
3573 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], CONNECT FINISH notify\n"));
3574
3575 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
3576 if(!wifi_connected) // non-connected scan
3577 {
3578 //halbtc8812a1ant_Reg0x550Bit3(btcoexist, false);
3579 halbtc8812a1ant_ActionWifiNotConnected(btcoexist);
3580 }
3581 else
3582 {
3583 halbtc8812a1ant_ActionWifiConnected(btcoexist);
3584 }
3585 }
3586}
3587
3588void
3589EXhalbtc8812a1ant_MediaStatusNotify(
3590 PBTC_COEXIST btcoexist,
3591 u1Byte type
3592 )
3593{
3594 u1Byte dataLen=5;
3595 u1Byte buf[6] = {0};
3596 u1Byte h2c_parameter[3] ={0};
3597 BOOLEAN wifi_under5g=false;
3598 u4Byte wifi_bw;
3599 u1Byte wifi_central_chnl;
3600
3601 if(btcoexist->manual_control ||btcoexist->stop_coex_dm)
3602 return;
3603
3604 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under5g);
3605
3606 // only 2.4G we need to inform bt the chnl mask
3607 if(!wifi_under5g)
3608 {
3609 if(BTC_MEDIA_CONNECT == type)
3610 {
3611 h2c_parameter[0] = 0x1;
3612 }
3613 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3614 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifi_central_chnl);
3615 h2c_parameter[1] = wifi_central_chnl;
3616 if(BTC_WIFI_BW_HT40 == wifi_bw)
3617 h2c_parameter[2] = 0x30;
3618 else
3619 h2c_parameter[2] = 0x20;
3620 }
3621
3622 coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
3623 coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
3624 coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
3625
3626 buf[0] = dataLen;
3627 buf[1] = 0x5; // OP_Code
3628 buf[2] = 0x3; // OP_Code_Length
3629 buf[3] = h2c_parameter[0]; // OP_Code_Content
3630 buf[4] = h2c_parameter[1];
3631 buf[5] = h2c_parameter[2];
3632
3633 btcoexist->btc_set(btcoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]);
3634}
3635
3636void
3637EXhalbtc8812a1ant_SpecialPacketNotify(
3638 PBTC_COEXIST btcoexist,
3639 u1Byte type
3640 )
3641{
3642 BOOLEAN bSecurityLink=false;
3643
3644 if(btcoexist->manual_control ||btcoexist->stop_coex_dm)
3645 return;
3646
3647 //if(type == BTC_PACKET_DHCP)
3648 {
3649 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], special Packet(%d) notify\n", type));
3650 if(btcoexist->bt_info.bt_disabled)
3651 {
3652 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
3653 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
3654 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
3655 }
3656 else
3657 {
3658 halbtc8812a1ant_ActionWifiConnectedSpecialPacket(btcoexist);
3659 }
3660 }
3661}
3662
3663void
3664EXhalbtc8812a1ant_BtInfoNotify(
3665 PBTC_COEXIST btcoexist,
3666 pu1Byte tmp_buf,
3667 u1Byte length
3668 )
3669{
3670 u1Byte bt_info=0;
3671 u1Byte i, rsp_source=0;
3672 static u4Byte set_bt_lna_cnt=0, set_bt_psd_mode=0;
3673 BOOLEAN bt_busy=false, limited_dig=false;
3674 BOOLEAN wifi_connected=false;
3675 BOOLEAN bRejApAggPkt=false;
3676
3677 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify()===>\n"));
3678
3679
3680 rsp_source = tmp_buf[0]&0xf;
3681 if(rsp_source >= BT_INFO_SRC_8812A_1ANT_MAX)
3682 rsp_source = BT_INFO_SRC_8812A_1ANT_WIFI_FW;
3683 coex_sta->bt_info_c2h_cnt[rsp_source]++;
3684
3685 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rsp_source, length));
3686 for(i=0; i<length; i++)
3687 {
3688 coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
3689 if(i == 1)
3690 bt_info = tmp_buf[i];
3691 if(i == length-1)
3692 {
3693 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("0x%2x]\n", tmp_buf[i]));
3694 }
3695 else
3696 {
3697 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("0x%2x, ", tmp_buf[i]));
3698 }
3699 }
3700
3701 if(btcoexist->manual_control)
3702 {
3703 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n"));
3704 return;
3705 }
3706 if(btcoexist->stop_coex_dm)
3707 {
3708 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), return for Coex STOPPED!!<===\n"));
3709 return;
3710 }
3711
3712 if(BT_INFO_SRC_8812A_1ANT_WIFI_FW != rsp_source)
3713 {
3714 coex_sta->bt_retry_cnt =
3715 coex_sta->bt_info_c2h[rsp_source][2];
3716
3717 coex_sta->bt_rssi =
3718 coex_sta->bt_info_c2h[rsp_source][3]*2+10;
3719
3720 coex_sta->bt_info_ext =
3721 coex_sta->bt_info_c2h[rsp_source][4];
3722
3723 // Here we need to resend some wifi info to BT
3724 // because bt is reset and loss of the info.
3725 if( (coex_sta->bt_info_ext & BIT1) )
3726 {
3727 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, &wifi_connected);
3728 if(wifi_connected)
3729 {
3730 EXhalbtc8812a1ant_MediaStatusNotify(btcoexist, BTC_MEDIA_CONNECT);
3731 }
3732 else
3733 {
3734 EXhalbtc8812a1ant_MediaStatusNotify(btcoexist, BTC_MEDIA_DISCONNECT);
3735 }
3736
3737 set_bt_psd_mode = 0;
3738 }
3739
3740 // test-chip bt patch doesn't support, temporary remove.
3741 // need to add back when mp-chip. 12/20/2012
3742#if 0
3743 if(set_bt_psd_mode <= 3)
3744 {
3745 halbtc8812a1ant_SetBtPsdMode(btcoexist, FORCE_EXEC, 0xd);
3746 set_bt_psd_mode++;
3747 }
3748
3749 if(coex_dm->bCurBtLnaConstrain)
3750 {
3751 if( (coex_sta->bt_info_ext & BIT2) )
3752 {
3753 }
3754 else
3755 {
3756 if(set_bt_lna_cnt <= 3)
3757 {
3758 halbtc8812a1ant_SetBtLnaConstrain(btcoexist, FORCE_EXEC, true);
3759 set_bt_lna_cnt++;
3760 }
3761 }
3762 }
3763 else
3764 {
3765 set_bt_lna_cnt = 0;
3766 }
3767#endif
3768 // test-chip bt patch only rsp the status for BT_RSP,
3769 // so temporary we consider the following only under BT_RSP
3770 if(BT_INFO_SRC_8812A_1ANT_BT_RSP == rsp_source)
3771 {
3772 if( (coex_sta->bt_info_ext & BIT3) )
3773 {
3774 #if 0// temp disable because bt patch report the wrong value.
3775 halbtc8812a1ant_IgnoreWlanAct(btcoexist, FORCE_EXEC, false);
3776 #endif
3777 }
3778 else
3779 {
3780 // BT already NOT ignore Wlan active, do nothing here.
3781 }
3782
3783 if( (coex_sta->bt_info_ext & BIT4) )
3784 {
3785 // BT auto report already enabled, do nothing
3786 }
3787 else
3788 {
3789 halbtc8812a1ant_BtAutoReport(btcoexist, FORCE_EXEC, true);
3790 }
3791 }
3792 }
3793
3794 // check BIT2 first ==> check if bt is under inquiry or page scan
3795 if(bt_info & BT_INFO_8812A_1ANT_B_INQ_PAGE)
3796 {
3797 coex_sta->c2h_bt_inquiry_page = true;
3798 coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_INQ_PAGE;
3799 }
3800 else
3801 {
3802 coex_sta->c2h_bt_inquiry_page = false;
3803 if(!(bt_info&BT_INFO_8812A_1ANT_B_CONNECTION))
3804 {
3805 coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
3806 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt non-connected idle!!!\n"));
3807 }
3808 else if(bt_info == BT_INFO_8812A_1ANT_B_CONNECTION) // connection exists but no busy
3809 {
3810 coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE;
3811 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt connected-idle!!!\n"));
3812 }
3813 else if((bt_info&BT_INFO_8812A_1ANT_B_SCO_ESCO) ||
3814 (bt_info&BT_INFO_8812A_1ANT_B_SCO_BUSY))
3815 {
3816 coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_SCO_BUSY;
3817 bRejApAggPkt = true;
3818 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt sco busy!!!\n"));
3819 }
3820 else if(bt_info&BT_INFO_8812A_1ANT_B_ACL_BUSY)
3821 {
3822 if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
3823 coex_dm->reset_tdma_adjust = true;
3824 coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_ACL_BUSY;
3825 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt acl busy!!!\n"));
3826 }
3827#if 0
3828 else if(bt_info&BT_INFO_8812A_1ANT_B_SCO_ESCO)
3829 {
3830 coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY;
3831 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt acl/sco busy!!!\n"));
3832 }
3833#endif
3834 else
3835 {
3836 //DbgPrint("error, undefined bt_info=0x%x\n", bt_info);
3837 coex_dm->bt_status = BT_8812A_1ANT_BT_STATUS_MAX;
3838 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt non-defined state!!!\n"));
3839 }
3840
3841 // send delete BA to disable aggregation
3842 //btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejApAggPkt);
3843 }
3844
3845 if( (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
3846 (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
3847 (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status) )
3848 {
3849 bt_busy = true;
3850 }
3851 else
3852 {
3853 bt_busy = false;
3854 }
3855 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
3856
3857 if(bt_busy)
3858 {
3859 limited_dig = true;
3860 }
3861 else
3862 {
3863 limited_dig = false;
3864 }
3865 coex_dm->limited_dig = limited_dig;
3866 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
3867
3868 halbtc8812a1ant_RunCoexistMechanism(btcoexist);
3869 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify()<===\n"));
3870}
3871
3872void
3873EXhalbtc8812a1ant_StackOperationNotify(
3874 PBTC_COEXIST btcoexist,
3875 u1Byte type
3876 )
3877{
3878 if(BTC_STACK_OP_INQ_PAGE_PAIR_START == type)
3879 {
3880 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], StackOP Inquiry/page/pair start notify\n"));
3881 }
3882 else if(BTC_STACK_OP_INQ_PAGE_PAIR_FINISH == type)
3883 {
3884 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], StackOP Inquiry/page/pair finish notify\n"));
3885 }
3886}
3887
3888void
3889EXhalbtc8812a1ant_HaltNotify(
3890 PBTC_COEXIST btcoexist
3891 )
3892{
3893 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], Halt notify\n"));
3894
3895 halbtc8812a1ant_IgnoreWlanAct(btcoexist, FORCE_EXEC, true);
3896 halbtc8812a1ant_PsTdma(btcoexist, FORCE_EXEC, false, 0);
3897 btcoexist->btc_write_1byte(btcoexist, 0x4f, 0xf);
3898 halbtc8812a1ant_WifiParaAdjust(btcoexist, false);
3899}
3900
3901void
3902EXhalbtc8812a1ant_PnpNotify(
3903 PBTC_COEXIST btcoexist,
3904 u1Byte pnpState
3905 )
3906{
3907 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], Pnp notify\n"));
3908
3909 if(BTC_WIFI_PNP_SLEEP == pnpState)
3910 {
3911 btcoexist->stop_coex_dm = true;
3912 halbtc8812a1ant_IgnoreWlanAct(btcoexist, FORCE_EXEC, true);
3913 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
3914 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
3915 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
3916 }
3917 else if(BTC_WIFI_PNP_WAKE_UP == pnpState)
3918 {
3919
3920 }
3921}
3922
3923void
3924EXhalbtc8812a1ant_Periodical(
3925 PBTC_COEXIST btcoexist
3926 )
3927{
3928 BOOLEAN wifi_under5g=false;
3929
3930 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Periodical()===>\n"));
3931 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], 1Ant Periodical!!\n"));
3932
3933 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under5g);
3934
3935 if(wifi_under5g)
3936 {
3937 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Periodical(), return for 5G<===\n"));
3938 halbtc8812a1ant_CoexAllOff(btcoexist);
3939 return;
3940 }
3941
3942 halbtc8812a1ant_QueryBtInfo(btcoexist);
3943 halbtc8812a1ant_MonitorBtCtr(btcoexist);
3944 halbtc8812a1ant_MonitorBtEnableDisable(btcoexist);
3945 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Periodical()<===\n"));
3946}
3947
3948void
3949EXhalbtc8812a1ant_DbgControl(
3950 PBTC_COEXIST btcoexist,
3951 u1Byte opCode,
3952 u1Byte opLen,
3953 pu1Byte pData
3954 )
3955{
3956 switch(opCode)
3957 {
3958 case BTC_DBG_SET_COEX_NORMAL:
3959 btcoexist->manual_control = false;
3960 halbtc8812a1ant_InitCoexDm(btcoexist);
3961 break;
3962 case BTC_DBG_SET_COEX_WIFI_ONLY:
3963 btcoexist->manual_control = true;
3964 halbtc8812a1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
3965 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
3966 halbtc8812a1ant_PsTdma(btcoexist, NORMAL_EXEC, false, 9);
3967 break;
3968 case BTC_DBG_SET_COEX_BT_ONLY:
3969 // todo
3970 break;
3971 default:
3972 break;
3973 }
3974}
3975#endif
3976
diff --git a/drivers/staging/rtl8821ae/btcoexist/HalBtc8812a1Ant.h b/drivers/staging/rtl8821ae/btcoexist/HalBtc8812a1Ant.h
new file mode 100644
index 000000000000..37bdab5ae9f1
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/HalBtc8812a1Ant.h
@@ -0,0 +1,205 @@
1//===========================================
2// The following is for 8812A_1ANT BT Co-exist definition
3//===========================================
4#define BT_INFO_8812A_1ANT_B_FTP BIT7
5#define BT_INFO_8812A_1ANT_B_A2DP BIT6
6#define BT_INFO_8812A_1ANT_B_HID BIT5
7#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT4
8#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT3
9#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT2
10#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT1
11#define BT_INFO_8812A_1ANT_B_CONNECTION BIT0
12
13#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
14 (((_BT_INFO_EXT_&BIT0))? true:false)
15
16#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2
17
18#define
19#define OUT
20
21typedef enum _BT_INFO_SRC_8812A_1ANT{
22 BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0,
23 BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1,
24 BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2,
25 BT_INFO_SRC_8812A_1ANT_MAX
26}BT_INFO_SRC_8812A_1ANT,*PBT_INFO_SRC_8812A_1ANT;
27
28typedef enum _BT_8812A_1ANT_BT_STATUS{
29 BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
30 BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
31 BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
32 BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
33 BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
34 BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
35 BT_8812A_1ANT_BT_STATUS_MAX
36}BT_8812A_1ANT_BT_STATUS,*PBT_8812A_1ANT_BT_STATUS;
37
38typedef enum _BT_8812A_1ANT_COEX_ALGO{
39 BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
40 BT_8812A_1ANT_COEX_ALGO_SCO = 0x1,
41 BT_8812A_1ANT_COEX_ALGO_HID = 0x2,
42 BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3,
43 BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
44 BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5,
45 BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6,
46 BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
47 BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
48 BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
49 BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
50 BT_8812A_1ANT_COEX_ALGO_MAX = 0xb,
51}BT_8812A_1ANT_COEX_ALGO,*PBT_8812A_1ANT_COEX_ALGO;
52
53typedef struct _COEX_DM_8812A_1ANT{
54 // fw mechanism
55 bool pre_dec_bt_pwr;
56 bool cur_dec_bt_pwr;
57 bool bPreBtLnaConstrain;
58 bool bCurBtLnaConstrain;
59 u8 bPreBtPsdMode;
60 u8 bCurBtPsdMode;
61 u8 pre_fw_dac_swing_lvl;
62 u8 cur_fw_dac_swing_lvl;
63 bool cur_ignore_wlan_act;
64 bool pre_ignore_wlan_act;
65 u8 pre_ps_tdma;
66 u8 cur_ps_tdma;
67 u8 ps_tdma_para[5];
68 u8 ps_tdma_du_adj_type;
69 bool reset_tdma_adjust;
70 bool pre_ps_tdma_on;
71 bool cur_ps_tdma_on;
72 bool pre_bt_auto_report;
73 bool cur_bt_auto_report;
74 u8 pre_lps;
75 u8 cur_lps;
76 u8 pre_rpwm;
77 u8 cur_rpwm;
78
79 // sw mechanism
80 bool pre_rf_rx_lpf_shrink;
81 bool cur_rf_rx_lpf_shrink;
82 u32 bt_rf0x1e_backup;
83 bool pre_low_penalty_ra;
84 bool cur_low_penalty_ra;
85 bool pre_dac_swing_on;
86 u32 pre_dac_swing_lvl;
87 bool cur_dac_swing_on;
88 u32 cur_dac_swing_lvl;
89 bool pre_adc_back_off;
90 bool cur_adc_back_off;
91 bool pre_agc_table_en;
92 bool cur_agc_table_en;
93 u32 pre_val0x6c0;
94 u32 cur_val0x6c0;
95 u32 pre_val0x6c4;
96 u32 cur_val0x6c4;
97 u32 pre_val0x6c8;
98 u32 cur_val0x6c8;
99 u8 pre_val0x6cc;
100 u8 cur_val0x6cc;
101 bool limited_dig;
102
103 // algorithm related
104 u8 pre_algorithm;
105 u8 cur_algorithm;
106 u8 bt_status;
107 u8 wifi_chnl_info[3];
108
109 u8 error_condition;
110} COEX_DM_8812A_1ANT, *PCOEX_DM_8812A_1ANT;
111
112typedef struct _COEX_STA_8812A_1ANT{
113 bool under_lps;
114 bool under_ips;
115 u32 high_priority_tx;
116 u32 high_priority_rx;
117 u32 low_priority_tx;
118 u32 low_priority_rx;
119 u8 bt_rssi;
120 u8 pre_bt_rssi_state;
121 u8 pre_wifi_rssi_state[4];
122 bool c2h_bt_info_req_sent;
123 u8 bt_info_c2h[BT_INFO_SRC_8812A_1ANT_MAX][10];
124 u32 bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_MAX];
125 bool c2h_bt_inquiry_page;
126 u8 bt_retry_cnt;
127 u8 bt_info_ext;
128}COEX_STA_8812A_1ANT, *PCOEX_STA_8812A_1ANT;
129
130//===========================================
131// The following is interface which will notify coex module.
132//===========================================
133void
134EXhalbtc8812a1ant_InitHwConfig(
135 PBTC_COEXIST btcoexist
136 );
137void
138EXhalbtc8812a1ant_InitCoexDm(
139 PBTC_COEXIST btcoexist
140 );
141void
142EXhalbtc8812a1ant_IpsNotify(
143 PBTC_COEXIST btcoexist,
144 u8 type
145 );
146void
147EXhalbtc8812a1ant_LpsNotify(
148 PBTC_COEXIST btcoexist,
149 u8 type
150 );
151void
152EXhalbtc8812a1ant_ScanNotify(
153 PBTC_COEXIST btcoexist,
154 u8 type
155 );
156void
157EXhalbtc8812a1ant_ConnectNotify(
158 PBTC_COEXIST btcoexist,
159 u8 type
160 );
161void
162EXhalbtc8812a1ant_MediaStatusNotify(
163 PBTC_COEXIST btcoexist,
164 u8 type
165 );
166void
167EXhalbtc8812a1ant_SpecialPacketNotify(
168 PBTC_COEXIST btcoexist,
169 u8 type
170 );
171void
172EXhalbtc8812a1ant_BtInfoNotify(
173 PBTC_COEXIST btcoexist,
174 u8 *tmp_buf,
175 u8 length
176 );
177void
178EXhalbtc8812a1ant_StackOperationNotify(
179 PBTC_COEXIST btcoexist,
180 u8 type
181 );
182void
183EXhalbtc8812a1ant_HaltNotify(
184 PBTC_COEXIST btcoexist
185 );
186void
187EXhalbtc8812a1ant_PnpNotify(
188 PBTC_COEXIST btcoexist,
189 u8 pnpState
190 );
191void
192EXhalbtc8812a1ant_Periodical(
193 PBTC_COEXIST btcoexist
194 );
195void
196EXhalbtc8812a1ant_DisplayCoexInfo(
197 PBTC_COEXIST btcoexist
198 );
199void
200EXhalbtc8812a1ant_DbgControl(
201 PBTC_COEXIST btcoexist,
202 u8 opCode,
203 u8 opLen,
204 u8 *pData
205 );
diff --git a/drivers/staging/rtl8821ae/btcoexist/habtc8723a1ant.c b/drivers/staging/rtl8821ae/btcoexist/habtc8723a1ant.c
new file mode 100644
index 000000000000..e619923ef0ab
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/habtc8723a1ant.c
@@ -0,0 +1,1614 @@
1//============================================================
2// Description:
3//
4// This file is for RTL8723A Co-exist mechanism
5//
6// History
7// 2012/08/22 Cosa first check in.
8// 2012/11/14 Cosa Revise for 8723A 1Ant out sourcing.
9//
10//============================================================
11
12//============================================================
13// include files
14//============================================================
15#include "Mp_Precomp.h"
16#if(BT_30_SUPPORT == 1)
17//============================================================
18// Global variables, these are static variables
19//============================================================
20static COEX_DM_8723A_1ANT GLCoexDm8723a1Ant;
21static PCOEX_DM_8723A_1ANT pCoexDm=&GLCoexDm8723a1Ant;
22static COEX_STA_8723A_1ANT GLCoexSta8723a1Ant;
23static PCOEX_STA_8723A_1ANT pCoexSta=&GLCoexSta8723a1Ant;
24
25const char *const GLBtInfoSrc8723a1Ant[]={
26 "BT Info[wifi fw]",
27 "BT Info[bt rsp]",
28 "BT Info[bt auto report]",
29};
30
31//============================================================
32// local function proto type if needed
33//============================================================
34//============================================================
35// local function start with halbtc8723a1ant_
36//============================================================
37VOID
38halbtc8723a1ant_Reg0x550Bit3(
39 IN PBTC_COEXIST pBtCoexist,
40 IN BOOLEAN bSet
41 )
42{
43 u1Byte u1tmp=0;
44
45 u1tmp = pBtCoexist->btc_read_1byte(pBtCoexist, 0x550);
46 if(bSet)
47 {
48 u1tmp |= BIT3;
49 }
50 else
51 {
52 u1tmp &= ~BIT3;
53 }
54 pBtCoexist->btc_write_1byte(pBtCoexist, 0x550, u1tmp);
55 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], set 0x550[3]=%d\n", (bSet? 1:0)));
56}
57
58VOID
59halbtc8723a1ant_NotifyFwScan(
60 IN PBTC_COEXIST pBtCoexist,
61 IN u1Byte scanType
62 )
63{
64 u1Byte H2C_Parameter[1] ={0};
65
66 if(BTC_SCAN_START == scanType)
67 H2C_Parameter[0] = 0x1;
68
69 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], Notify FW for wifi scan, write 0x3b=0x%x\n",
70 H2C_Parameter[0]));
71
72 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x3b, 1, H2C_Parameter);
73}
74
75VOID
76halbtc8723a1ant_QueryBtInfo(
77 IN PBTC_COEXIST pBtCoexist
78 )
79{
80 u1Byte H2C_Parameter[1] ={0};
81
82 pCoexSta->bC2hBtInfoReqSent = true;
83
84 H2C_Parameter[0] |= BIT0; // trigger
85
86 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], Query Bt Info, FW write 0x38=0x%x\n",
87 H2C_Parameter[0]));
88
89 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x38, 1, H2C_Parameter);
90}
91
92VOID
93halbtc8723a1ant_SetSwRfRxLpfCorner(
94 IN PBTC_COEXIST pBtCoexist,
95 IN BOOLEAN bRxRfShrinkOn
96 )
97{
98 if(bRxRfShrinkOn)
99 {
100 //Shrink RF Rx LPF corner
101 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Shrink RF Rx LPF corner!!\n"));
102 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf0ff7);
103 }
104 else
105 {
106 //Resume RF Rx LPF corner
107 // After initialized, we can use pCoexDm->btRf0x1eBackup
108 if(pBtCoexist->initilized)
109 {
110 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Resume RF Rx LPF corner!!\n"));
111 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup);
112 }
113 }
114}
115
116VOID
117halbtc8723a1ant_RfShrink(
118 IN PBTC_COEXIST pBtCoexist,
119 IN BOOLEAN bForceExec,
120 IN BOOLEAN bRxRfShrinkOn
121 )
122{
123 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn Rx RF Shrink = %s\n",
124 (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF")));
125 pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn;
126
127 if(!bForceExec)
128 {
129 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreRfRxLpfShrink=%d, bCurRfRxLpfShrink=%d\n",
130 pCoexDm->bPreRfRxLpfShrink, pCoexDm->bCurRfRxLpfShrink));
131
132 if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink)
133 return;
134 }
135 halbtc8723a1ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink);
136
137 pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink;
138}
139
140VOID
141halbtc8723a1ant_SetSwPenaltyTxRateAdaptive(
142 IN PBTC_COEXIST pBtCoexist,
143 IN BOOLEAN bLowPenaltyRa
144 )
145{
146 u1Byte tmpU1;
147
148 tmpU1 = pBtCoexist->btc_read_1byte(pBtCoexist, 0x4fd);
149 tmpU1 |= BIT0;
150 if(bLowPenaltyRa)
151 {
152 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Tx rate adaptive, set low penalty!!\n"));
153 tmpU1 &= ~BIT2;
154 }
155 else
156 {
157 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Tx rate adaptive, set normal!!\n"));
158 tmpU1 |= BIT2;
159 }
160
161 pBtCoexist->btc_write_1byte(pBtCoexist, 0x4fd, tmpU1);
162}
163
164VOID
165halbtc8723a1ant_LowPenaltyRa(
166 IN PBTC_COEXIST pBtCoexist,
167 IN BOOLEAN bForceExec,
168 IN BOOLEAN bLowPenaltyRa
169 )
170{
171 return;
172 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn LowPenaltyRA = %s\n",
173 (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF")));
174 pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa;
175
176 if(!bForceExec)
177 {
178 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreLowPenaltyRa=%d, bCurLowPenaltyRa=%d\n",
179 pCoexDm->bPreLowPenaltyRa, pCoexDm->bCurLowPenaltyRa));
180
181 if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa)
182 return;
183 }
184 halbtc8723a1ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa);
185
186 pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa;
187}
188
189VOID
190halbtc8723a1ant_SetCoexTable(
191 IN PBTC_COEXIST pBtCoexist,
192 IN u4Byte val0x6c0,
193 IN u4Byte val0x6c8,
194 IN u1Byte val0x6cc
195 )
196{
197 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0));
198 pBtCoexist->btc_write_4byte(pBtCoexist, 0x6c0, val0x6c0);
199
200 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8));
201 pBtCoexist->btc_write_4byte(pBtCoexist, 0x6c8, val0x6c8);
202
203 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc));
204 pBtCoexist->btc_write_1byte(pBtCoexist, 0x6cc, val0x6cc);
205}
206
207VOID
208halbtc8723a1ant_CoexTable(
209 IN PBTC_COEXIST pBtCoexist,
210 IN BOOLEAN bForceExec,
211 IN u4Byte val0x6c0,
212 IN u4Byte val0x6c8,
213 IN u1Byte val0x6cc
214 )
215{
216 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
217 (bForceExec? "force to":""), val0x6c0, val0x6c8, val0x6cc));
218 pCoexDm->curVal0x6c0 = val0x6c0;
219 pCoexDm->curVal0x6c8 = val0x6c8;
220 pCoexDm->curVal0x6cc = val0x6cc;
221
222 if(!bForceExec)
223 {
224 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], preVal0x6c0=0x%x, preVal0x6c8=0x%x, preVal0x6cc=0x%x !!\n",
225 pCoexDm->preVal0x6c0, pCoexDm->preVal0x6c8, pCoexDm->preVal0x6cc));
226 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], curVal0x6c0=0x%x, curVal0x6c8=0x%x, curVal0x6cc=0x%x !!\n",
227 pCoexDm->curVal0x6c0, pCoexDm->curVal0x6c8, pCoexDm->curVal0x6cc));
228
229 if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) &&
230 (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) &&
231 (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) )
232 return;
233 }
234 halbtc8723a1ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c8, val0x6cc);
235
236 pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0;
237 pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8;
238 pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc;
239}
240
241VOID
242halbtc8723a1ant_SetFwIgnoreWlanAct(
243 IN PBTC_COEXIST pBtCoexist,
244 IN BOOLEAN bEnable
245 )
246{
247 u1Byte H2C_Parameter[1] ={0};
248
249 if(bEnable)
250 {
251 H2C_Parameter[0] |= BIT0; // function enable
252 }
253
254 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x25=0x%x\n",
255 H2C_Parameter[0]));
256
257 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x25, 1, H2C_Parameter);
258}
259
260VOID
261halbtc8723a1ant_IgnoreWlanAct(
262 IN PBTC_COEXIST pBtCoexist,
263 IN BOOLEAN bForceExec,
264 IN BOOLEAN bEnable
265 )
266{
267 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s turn Ignore WlanAct %s\n",
268 (bForceExec? "force to":""), (bEnable? "ON":"OFF")));
269 pCoexDm->bCurIgnoreWlanAct = bEnable;
270
271 if(!bForceExec)
272 {
273 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPreIgnoreWlanAct = %d, bCurIgnoreWlanAct = %d!!\n",
274 pCoexDm->bPreIgnoreWlanAct, pCoexDm->bCurIgnoreWlanAct));
275
276 if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct)
277 return;
278 }
279 halbtc8723a1ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable);
280
281 pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct;
282}
283
284VOID
285halbtc8723a1ant_SetFwPstdma(
286 IN PBTC_COEXIST pBtCoexist,
287 IN u1Byte type,
288 IN u1Byte byte1,
289 IN u1Byte byte2,
290 IN u1Byte byte3,
291 IN u1Byte byte4,
292 IN u1Byte byte5
293 )
294{
295 u1Byte H2C_Parameter[5] ={0};
296 u1Byte realByte1=byte1, realByte5=byte5;
297 BOOLEAN bApEnable=FALSE;
298
299 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable);
300
301 // byte1[1:0] != 0 means enable pstdma
302 // for 2Ant bt coexist, if byte1 != 0 means enable pstdma
303 if(byte1)
304 {
305 if(bApEnable)
306 {
307 if(type != 5 && type != 12)
308 {
309 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], FW for 1Ant AP mode\n"));
310 realByte1 &= ~BIT4;
311 realByte1 |= BIT5;
312
313 realByte5 |= BIT5;
314 realByte5 &= ~BIT6;
315 }
316 }
317 }
318 H2C_Parameter[0] = realByte1;
319 H2C_Parameter[1] = byte2;
320 H2C_Parameter[2] = byte3;
321 H2C_Parameter[3] = byte4;
322 H2C_Parameter[4] = realByte5;
323
324 pCoexDm->psTdmaPara[0] = realByte1;
325 pCoexDm->psTdmaPara[1] = byte2;
326 pCoexDm->psTdmaPara[2] = byte3;
327 pCoexDm->psTdmaPara[3] = byte4;
328 pCoexDm->psTdmaPara[4] = realByte5;
329
330 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], FW write 0x3a(5bytes)=0x%x%08x\n",
331 H2C_Parameter[0],
332 H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4]));
333
334 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x3a, 5, H2C_Parameter);
335}
336
337VOID
338halbtc8723a1ant_PsTdma(
339 IN PBTC_COEXIST pBtCoexist,
340 IN BOOLEAN bForceExec,
341 IN BOOLEAN bTurnOn,
342 IN u1Byte type
343 )
344{
345 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s turn %s PS TDMA, type=%d\n",
346 (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type));
347 pCoexDm->bCurPsTdmaOn = bTurnOn;
348 pCoexDm->curPsTdma = type;
349
350 if(!bForceExec)
351 {
352 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n",
353 pCoexDm->bPrePsTdmaOn, pCoexDm->bCurPsTdmaOn));
354 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n",
355 pCoexDm->prePsTdma, pCoexDm->curPsTdma));
356
357 if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) &&
358 (pCoexDm->prePsTdma == pCoexDm->curPsTdma) )
359 return;
360 }
361 if(pCoexDm->bCurPsTdmaOn)
362 {
363 switch(pCoexDm->curPsTdma)
364 {
365 case 1:
366 default:
367 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x1a, 0x1a, 0x0, 0x40);
368 break;
369 case 2:
370 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x12, 0x12, 0x0, 0x40);
371 break;
372 case 3:
373 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x3f, 0x3, 0x10, 0x40);
374 break;
375 case 4:
376 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x15, 0x3, 0x10, 0x0);
377 break;
378 case 5:
379 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0xa9, 0x15, 0x3, 0x35, 0xc0);
380 break;
381
382 case 8:
383 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0);
384 break;
385 case 9:
386 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x0, 0x40);
387 break;
388 case 10:
389 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x0, 0x40);
390 break;
391 case 11:
392 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x0, 0x40);
393 break;
394 case 12:
395 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0xa9, 0xa, 0x3, 0x15, 0xc0);
396 break;
397
398 case 18:
399 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0);
400 break;
401
402 case 20:
403 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x2a, 0x2a, 0x0, 0x0);
404 break;
405 case 21:
406 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x20, 0x3, 0x10, 0x40);
407 break;
408 case 22:
409 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x1a, 0x1a, 0x2, 0x40);
410 break;
411 case 23:
412 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x12, 0x12, 0x2, 0x40);
413 break;
414 case 24:
415 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x2, 0x40);
416 break;
417 case 25:
418 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x2, 0x40);
419 break;
420 case 26:
421 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0);
422 break;
423 case 27:
424 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x2, 0x40);
425 break;
426 case 28:
427 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x3, 0x2f, 0x2f, 0x0, 0x0);
428 break;
429
430 }
431 }
432 else
433 {
434 // disable PS tdma
435 switch(pCoexDm->curPsTdma)
436 {
437 case 8:
438 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x8, 0x0, 0x0, 0x0, 0x0);
439 break;
440 case 0:
441 default:
442 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x0, 0x0, 0x0, 0x0, 0x0);
443 pBtCoexist->btc_write_2byte(pBtCoexist, 0x860, 0x210);
444 break;
445 case 9:
446 halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x0, 0x0, 0x0, 0x0, 0x0);
447 pBtCoexist->btc_write_2byte(pBtCoexist, 0x860, 0x110);
448 break;
449
450 }
451 }
452
453 // update pre state
454 pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn;
455 pCoexDm->prePsTdma = pCoexDm->curPsTdma;
456}
457
458
459VOID
460halbtc8723a1ant_CoexAllOff(
461 IN PBTC_COEXIST pBtCoexist
462 )
463{
464 // fw all off
465 halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
466 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
467
468 // sw all off
469 halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
470 halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
471
472 // hw all off
473 halbtc8723a1ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
474}
475
476VOID
477halbtc8723a1ant_InitCoexDm(
478 IN PBTC_COEXIST pBtCoexist
479 )
480{
481 // force to reset coex mechanism
482 halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE);
483}
484
485VOID
486halbtc8723a1ant_BtEnableAction(
487 IN PBTC_COEXIST pBtCoexist
488 )
489{
490 halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE);
491}
492
493VOID
494halbtc8723a1ant_MonitorBtCtr(
495 IN PBTC_COEXIST pBtCoexist
496 )
497{
498 u4Byte regHPTxRx, regLPTxRx, u4Tmp;
499 u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0;
500 u1Byte u1Tmp;
501
502 regHPTxRx = 0x770;
503 regLPTxRx = 0x774;
504
505 u4Tmp = pBtCoexist->btc_read_4byte(pBtCoexist, regHPTxRx);
506 regHPTx = u4Tmp & MASKLWORD;
507 regHPRx = (u4Tmp & MASKHWORD)>>16;
508
509 u4Tmp = pBtCoexist->btc_read_4byte(pBtCoexist, regLPTxRx);
510 regLPTx = u4Tmp & MASKLWORD;
511 regLPRx = (u4Tmp & MASKHWORD)>>16;
512
513 pCoexSta->highPriorityTx = regHPTx;
514 pCoexSta->highPriorityRx = regHPRx;
515 pCoexSta->lowPriorityTx = regLPTx;
516 pCoexSta->lowPriorityRx = regLPRx;
517
518 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
519 regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx));
520 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
521 regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx));
522
523 // reset counter
524 pBtCoexist->btc_write_1byte(pBtCoexist, 0x76e, 0xc);
525}
526
527VOID
528halbtc8723a1ant_MonitorBtEnableDisable(
529 IN PBTC_COEXIST pBtCoexist
530 )
531{
532 static BOOLEAN bPreBtDisabled=FALSE;
533 static u4Byte btDisableCnt=0;
534 BOOLEAN bBtActive=true, bBtDisabled=FALSE;
535
536 // This function check if bt is disabled
537
538 if( pCoexSta->highPriorityTx == 0 &&
539 pCoexSta->highPriorityRx == 0 &&
540 pCoexSta->lowPriorityTx == 0 &&
541 pCoexSta->lowPriorityRx == 0)
542 {
543 bBtActive = FALSE;
544 }
545 if( pCoexSta->highPriorityTx == 0xffff &&
546 pCoexSta->highPriorityRx == 0xffff &&
547 pCoexSta->lowPriorityTx == 0xffff &&
548 pCoexSta->lowPriorityRx == 0xffff)
549 {
550 bBtActive = FALSE;
551 }
552 if(bBtActive)
553 {
554 btDisableCnt = 0;
555 bBtDisabled = FALSE;
556 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
557 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is enabled !!\n"));
558 }
559 else
560 {
561 btDisableCnt++;
562 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], bt all counters=0, %d times!!\n",
563 btDisableCnt));
564 if(btDisableCnt >= 2)
565 {
566 bBtDisabled = true;
567 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
568 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is disabled !!\n"));
569 }
570 }
571 if(bPreBtDisabled != bBtDisabled)
572 {
573 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is from %s to %s!!\n",
574 (bPreBtDisabled ? "disabled":"enabled"),
575 (bBtDisabled ? "disabled":"enabled")));
576 bPreBtDisabled = bBtDisabled;
577 if(!bBtDisabled)
578 {
579 halbtc8723a1ant_BtEnableAction(pBtCoexist);
580 }
581 else
582 {
583 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL);
584 }
585 }
586}
587
588VOID
589halbtc8723a1ant_TdmaDurationAdjust(
590 IN PBTC_COEXIST pBtCoexist
591 )
592{
593 static s4Byte up,dn,m,n,WaitCount;
594 s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration
595 u1Byte retryCount=0;
596 u1Byte btState;
597 BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE;
598 u4Byte wifiBw;
599
600 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
601 btState = pCoexDm->btStatus;
602
603 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], TdmaDurationAdjust()\n"));
604 if(pCoexDm->psTdmaGlobalCnt != pCoexDm->psTdmaMonitorCnt)
605 {
606 pCoexDm->psTdmaMonitorCnt = 0;
607 pCoexDm->psTdmaGlobalCnt = 0;
608 }
609 if(pCoexDm->psTdmaMonitorCnt == 0)
610 {
611 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], first run BT A2DP + WiFi busy state!!\n"));
612 if(btState == BT_STATE_8723A_1ANT_ACL_ONLY_BUSY)
613 {
614 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 1);
615 pCoexDm->psTdmaDuAdjType = 1;
616 }
617 else
618 {
619 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 22);
620 pCoexDm->psTdmaDuAdjType = 22;
621 }
622 //============
623 up = 0;
624 dn = 0;
625 m = 1;
626 n= 3;
627 result = 0;
628 WaitCount = 0;
629 }
630 else
631 {
632 //accquire the BT TRx retry count from BT_Info byte2
633 retryCount = pCoexSta->btRetryCnt;
634 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], retryCount = %d\n", retryCount));
635 result = 0;
636 WaitCount++;
637
638 if(retryCount == 0) // no retry in the last 2-second duration
639 {
640 up++;
641 dn--;
642
643 if (dn <= 0)
644 dn = 0;
645
646 if(up >= n) // if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration
647 {
648 WaitCount = 0;
649 n = 3;
650 up = 0;
651 dn = 0;
652 result = 1;
653 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Increase wifi duration!!\n"));
654 }
655 }
656 else if (retryCount <= 3) // <=3 retry in the last 2-second duration
657 {
658 up--;
659 dn++;
660
661 if (up <= 0)
662 up = 0;
663
664 if (dn == 2) // if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration
665 {
666 if (WaitCount <= 2)
667 m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^
668 else
669 m = 1;
670
671 if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
672 m = 20;
673
674 n = 3*m;
675 up = 0;
676 dn = 0;
677 WaitCount = 0;
678 result = -1;
679 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n"));
680 }
681 }
682 else //retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration
683 {
684 if (WaitCount == 1)
685 m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^
686 else
687 m = 1;
688
689 if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
690 m = 20;
691
692 n = 3*m;
693 up = 0;
694 dn = 0;
695 WaitCount = 0;
696 result = -1;
697 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n"));
698 }
699
700 {
701 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BT TxRx counter H+L <= 1200\n"));
702 if(btState != BT_STATE_8723A_1ANT_ACL_ONLY_BUSY)
703 {
704 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], NOT ACL only busy!\n"));
705 if(BTC_WIFI_BW_HT40 != wifiBw)
706 {
707 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], 20MHz\n"));
708 if(result == -1)
709 {
710 if(pCoexDm->curPsTdma == 22)
711 {
712 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 23);
713 pCoexDm->psTdmaDuAdjType = 23;
714 }
715 else if(pCoexDm->curPsTdma == 23)
716 {
717 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 24);
718 pCoexDm->psTdmaDuAdjType = 24;
719 }
720 else if(pCoexDm->curPsTdma == 24)
721 {
722 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 25);
723 pCoexDm->psTdmaDuAdjType = 25;
724 }
725 }
726 else if (result == 1)
727 {
728 if(pCoexDm->curPsTdma == 25)
729 {
730 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 24);
731 pCoexDm->psTdmaDuAdjType = 24;
732 }
733 else if(pCoexDm->curPsTdma == 24)
734 {
735 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 23);
736 pCoexDm->psTdmaDuAdjType = 23;
737 }
738 else if(pCoexDm->curPsTdma == 23)
739 {
740 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 22);
741 pCoexDm->psTdmaDuAdjType = 22;
742 }
743 }
744 // error handle, if not in the following state,
745 // set psTdma again.
746 if( (pCoexDm->psTdmaDuAdjType != 22) &&
747 (pCoexDm->psTdmaDuAdjType != 23) &&
748 (pCoexDm->psTdmaDuAdjType != 24) &&
749 (pCoexDm->psTdmaDuAdjType != 25) )
750 {
751 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], duration case out of handle!!\n"));
752 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 23);
753 pCoexDm->psTdmaDuAdjType = 23;
754 }
755 }
756 else
757 {
758 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], 40MHz\n"));
759 if(result == -1)
760 {
761 if(pCoexDm->curPsTdma == 23)
762 {
763 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 24);
764 pCoexDm->psTdmaDuAdjType = 24;
765 }
766 else if(pCoexDm->curPsTdma == 24)
767 {
768 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 25);
769 pCoexDm->psTdmaDuAdjType = 25;
770 }
771 else if(pCoexDm->curPsTdma == 25)
772 {
773 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 27);
774 pCoexDm->psTdmaDuAdjType = 27;
775 }
776 }
777 else if (result == 1)
778 {
779 if(pCoexDm->curPsTdma == 27)
780 {
781 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 25);
782 pCoexDm->psTdmaDuAdjType = 25;
783 }
784 else if(pCoexDm->curPsTdma == 25)
785 {
786 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 24);
787 pCoexDm->psTdmaDuAdjType = 24;
788 }
789 else if(pCoexDm->curPsTdma == 24)
790 {
791 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 23);
792 pCoexDm->psTdmaDuAdjType = 23;
793 }
794 }
795 // error handle, if not in the following state,
796 // set psTdma again.
797 if( (pCoexDm->psTdmaDuAdjType != 23) &&
798 (pCoexDm->psTdmaDuAdjType != 24) &&
799 (pCoexDm->psTdmaDuAdjType != 25) &&
800 (pCoexDm->psTdmaDuAdjType != 27) )
801 {
802 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], duration case out of handle!!\n"));
803 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 24);
804 pCoexDm->psTdmaDuAdjType = 24;
805 }
806 }
807 }
808 else
809 {
810 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], ACL only busy\n"));
811 if (result == -1)
812 {
813 if(pCoexDm->curPsTdma == 1)
814 {
815 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
816 pCoexDm->psTdmaDuAdjType = 2;
817 }
818 else if(pCoexDm->curPsTdma == 2)
819 {
820 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
821 pCoexDm->psTdmaDuAdjType = 9;
822 }
823 else if(pCoexDm->curPsTdma == 9)
824 {
825 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
826 pCoexDm->psTdmaDuAdjType = 11;
827 }
828 }
829 else if (result == 1)
830 {
831 if(pCoexDm->curPsTdma == 11)
832 {
833 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
834 pCoexDm->psTdmaDuAdjType = 9;
835 }
836 else if(pCoexDm->curPsTdma == 9)
837 {
838 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
839 pCoexDm->psTdmaDuAdjType = 2;
840 }
841 else if(pCoexDm->curPsTdma == 2)
842 {
843 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 1);
844 pCoexDm->psTdmaDuAdjType = 1;
845 }
846 }
847
848 // error handle, if not in the following state,
849 // set psTdma again.
850 if( (pCoexDm->psTdmaDuAdjType != 1) &&
851 (pCoexDm->psTdmaDuAdjType != 2) &&
852 (pCoexDm->psTdmaDuAdjType != 9) &&
853 (pCoexDm->psTdmaDuAdjType != 11) )
854 {
855 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], duration case out of handle!!\n"));
856 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
857 pCoexDm->psTdmaDuAdjType = 2;
858 }
859 }
860 }
861 }
862
863 // if current PsTdma not match with the recorded one (when scan, dhcp...),
864 // then we have to adjust it back to the previous record one.
865 if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType)
866 {
867 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n",
868 pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType));
869
870 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
871 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
872 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
873
874 if( !bScan && !bLink && !bRoam)
875 {
876 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, pCoexDm->psTdmaDuAdjType);
877 }
878 else
879 {
880 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"));
881 }
882 }
883 pCoexDm->psTdmaMonitorCnt++;
884}
885
886
887VOID
888halbtc8723a1ant_CoexForWifiConnect(
889 IN PBTC_COEXIST pBtCoexist
890 )
891{
892 BOOLEAN bWifiConnected=FALSE, bWifiBusy=FALSE;
893 u1Byte btState, btInfoOriginal=0;
894
895 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
896
897 btState = pCoexDm->btStatus;
898 btInfoOriginal = pCoexSta->btInfoC2h[BT_INFO_SRC_8723A_1ANT_BT_RSP][0];
899
900 if(bWifiConnected)
901 {
902 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], wifi connected!!\n"));
903 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
904
905 if( !bWifiBusy &&
906 ((BT_STATE_8723A_1ANT_NO_CONNECTION == btState) ||
907 (BT_STATE_8723A_1ANT_CONNECT_IDLE == btState)) )
908 {
909 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], [Wifi is idle] or [Bt is non connected idle or Bt is connected idle]!!\n"));
910
911 if(BT_STATE_8723A_1ANT_NO_CONNECTION == btState)
912 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
913 else if(BT_STATE_8723A_1ANT_CONNECT_IDLE == btState)
914 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
915
916 pBtCoexist->btc_setBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0);
917 }
918 else
919 {
920 if( (BT_STATE_8723A_1ANT_SCO_ONLY_BUSY == btState) ||
921 (BT_STATE_8723A_1ANT_ACL_SCO_BUSY == btState) ||
922 (BT_STATE_8723A_1ANT_HID_BUSY == btState) ||
923 (BT_STATE_8723A_1ANT_HID_SCO_BUSY == btState) )
924 {
925 pBtCoexist->btc_setBbReg(pBtCoexist, 0x880, 0xff000000, 0x60);
926 }
927 else
928 {
929 pBtCoexist->btc_setBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0);
930 }
931 switch(btState)
932 {
933 case BT_STATE_8723A_1ANT_NO_CONNECTION:
934 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 5);
935 break;
936 case BT_STATE_8723A_1ANT_CONNECT_IDLE:
937 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 12);
938 break;
939 case BT_STATE_8723A_1ANT_INQ_OR_PAG:
940 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
941 break;
942 case BT_STATE_8723A_1ANT_SCO_ONLY_BUSY:
943 case BT_STATE_8723A_1ANT_ACL_SCO_BUSY:
944 case BT_STATE_8723A_1ANT_HID_BUSY:
945 case BT_STATE_8723A_1ANT_HID_SCO_BUSY:
946 halbtc8723a1ant_TdmaDurationAdjust(pBtCoexist);
947 break;
948 case BT_STATE_8723A_1ANT_ACL_ONLY_BUSY:
949 if (btInfoOriginal&BT_INFO_8723A_1ANT_B_A2DP)
950 {
951 halbtc8723a1ant_TdmaDurationAdjust(pBtCoexist);
952 }
953 else if(btInfoOriginal&BT_INFO_8723A_1ANT_B_FTP)
954 {
955 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 1);
956 }
957 else if( (btInfoOriginal&BT_INFO_8723A_1ANT_B_A2DP) &&
958 (btInfoOriginal&BT_INFO_8723A_1ANT_B_FTP) )
959 {
960 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
961 }
962 else
963 {
964 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 1);
965 }
966 break;
967 default:
968 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], error!!!, undefined case in halbtc8723a1ant_CoexForWifiConnect()!!\n"));
969 break;
970 }
971 }
972 }
973 else
974 {
975 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], wifi is disconnected!!\n"));
976 }
977
978 pCoexDm->psTdmaGlobalCnt++;
979}
980
981//============================================================
982// work around function start with wa_halbtc8723a1ant_
983//============================================================
984VOID
985wa_halbtc8723a1ant_MonitorC2h(
986 IN PBTC_COEXIST pBtCoexist
987 )
988{
989 u1Byte tmp1b=0x0;
990 u4Byte curC2hTotalCnt=0x0;
991 static u4Byte preC2hTotalCnt=0x0, sameCntPollingTime=0x0;
992
993 curC2hTotalCnt+=pCoexSta->btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_BT_RSP];
994
995 if(curC2hTotalCnt == preC2hTotalCnt)
996 {
997 sameCntPollingTime++;
998 }
999 else
1000 {
1001 preC2hTotalCnt = curC2hTotalCnt;
1002 sameCntPollingTime = 0;
1003 }
1004
1005 if(sameCntPollingTime >= 2)
1006 {
1007 tmp1b = pBtCoexist->btc_read_1byte(pBtCoexist, 0x1af);
1008 if(tmp1b != 0x0)
1009 {
1010 pCoexSta->c2hHangDetectCnt++;
1011 pBtCoexist->btc_write_1byte(pBtCoexist, 0x1af, 0x0);
1012 }
1013 }
1014}
1015
1016//============================================================
1017// extern function start with EXhalbtc8723a1ant_
1018//============================================================
1019VOID
1020EXhalbtc8723a1ant_InitHwConfig(
1021 IN PBTC_COEXIST pBtCoexist
1022 )
1023{
1024 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], 1Ant Init HW Config!!\n"));
1025
1026 // backup rf 0x1e value
1027 pCoexDm->btRf0x1eBackup =
1028 pBtCoexist->btc_get_rf_reg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff);
1029
1030 pBtCoexist->btc_write_1byte(pBtCoexist, 0x40, 0x20);
1031
1032 // enable counter statistics
1033 pBtCoexist->btc_write_1byte(pBtCoexist, 0x76e, 0x4);
1034
1035 // coex table
1036 pBtCoexist->btc_write_1byte(pBtCoexist, 0x6cc, 0x0); // 1-Ant coex
1037 pBtCoexist->btc_write_4byte(pBtCoexist, 0x6c8, 0xffff); // wifi break table
1038 pBtCoexist->btc_write_4byte(pBtCoexist, 0x6c4, 0x55555555); //coex table
1039
1040 // antenna switch control parameter
1041 pBtCoexist->btc_write_4byte(pBtCoexist, 0x858, 0xaaaaaaaa);
1042
1043 pBtCoexist->btc_write_2byte(pBtCoexist, 0x860, 0x210); //set antenna at wifi side if ANTSW is software control
1044 pBtCoexist->btc_write_4byte(pBtCoexist, 0x870, 0x300); //SPDT(connected with TRSW) control by hardware PTA
1045 pBtCoexist->btc_write_4byte(pBtCoexist, 0x874, 0x22804000); //ANTSW keep by GNT_BT
1046
1047 // coexistence parameters
1048 pBtCoexist->btc_write_1byte(pBtCoexist, 0x778, 0x1); // enable RTK mode PTA
1049}
1050
1051VOID
1052EXhalbtc8723a1ant_InitCoexDm(
1053 IN PBTC_COEXIST pBtCoexist
1054 )
1055{
1056 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], Coex Mechanism Init!!\n"));
1057
1058 halbtc8723a1ant_InitCoexDm(pBtCoexist);
1059}
1060
1061VOID
1062EXhalbtc8723a1ant_DisplayCoexInfo(
1063 IN PBTC_COEXIST pBtCoexist
1064 )
1065{
1066 struct btc_board_info * pBoardInfo=&pBtCoexist->board_info;
1067 PBTC_STACK_INFO pStackInfo=&pBtCoexist->stack_info;
1068 pu1Byte cliBuf=pBtCoexist->cli_buf;
1069 u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0;
1070 u4Byte u4Tmp[4];
1071 BOOLEAN bRoam=FALSE, bScan=FALSE, bLink=FALSE, bWifiUnder5G=FALSE;
1072 BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
1073 s4Byte wifiRssi=0, btHsRssi=0;
1074 u4Byte wifiBw, wifiTrafficDir;
1075 u1Byte wifiDot11Chnl, wifiHsChnl;
1076
1077 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============");
1078 CL_PRINTF(cliBuf);
1079
1080 if(!pBoardInfo->bt_exist)
1081 {
1082 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n BT not exists !!!");
1083 CL_PRINTF(cliBuf);
1084 return;
1085 }
1086
1087 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \
1088 pBoardInfo->pg_ant_num, pBoardInfo->btdm_ant_num);
1089 CL_PRINTF(cliBuf);
1090
1091 if(pBtCoexist->manual_control)
1092 {
1093 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!");
1094 CL_PRINTF(cliBuf);
1095 }
1096
1097 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \
1098 ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion);
1099 CL_PRINTF(cliBuf);
1100
1101 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
1102 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiDot11Chnl);
1103 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifiHsChnl);
1104 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d(%d)", "Dot11 channel / HsChnl(HsMode)", \
1105 wifiDot11Chnl, wifiHsChnl, bBtHsOn);
1106 CL_PRINTF(cliBuf);
1107
1108 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "H2C Wifi inform bt chnl Info", \
1109 pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1],
1110 pCoexDm->wifiChnlInfo[2]);
1111 CL_PRINTF(cliBuf);
1112
1113 pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
1114 pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_HS_RSSI, &btHsRssi);
1115 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "Wifi rssi/ HS rssi", \
1116 wifiRssi, btHsRssi);
1117 CL_PRINTF(cliBuf);
1118
1119 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
1120 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
1121 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
1122 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Wifi bLink/ bRoam/ bScan", \
1123 bLink, bRoam, bScan);
1124 CL_PRINTF(cliBuf);
1125
1126 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G);
1127 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
1128 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
1129 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
1130 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s ", "Wifi status", \
1131 (bWifiUnder5G? "5G":"2.4G"),
1132 ((BTC_WIFI_BW_LEGACY==wifiBw)? "Legacy": (((BTC_WIFI_BW_HT40==wifiBw)? "HT40":"HT20"))),
1133 ((!bWifiBusy)? "idle": ((BTC_WIFI_TRAFFIC_TX==wifiTrafficDir)? "uplink":"downlink")));
1134 CL_PRINTF(cliBuf);
1135
1136 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \
1137 ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8723A_1ANT_BT_STATUS_IDLE == pCoexDm->btStatus)? "idle":( (BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy"))),
1138 pCoexSta->btRssi, pCoexSta->btRetryCnt);
1139 CL_PRINTF(cliBuf);
1140
1141 if(pStackInfo->bProfileNotified)
1142 {
1143 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \
1144 pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist);
1145 CL_PRINTF(cliBuf);
1146
1147 pBtCoexist->btc_disp_dbg_msg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO);
1148 }
1149
1150 btInfoExt = pCoexSta->btInfoExt;
1151 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \
1152 (btInfoExt&BIT0)? "Basic rate":"EDR rate");
1153 CL_PRINTF(cliBuf);
1154
1155 for(i=0; i<BT_INFO_SRC_8723A_1ANT_MAX; i++)
1156 {
1157 if(pCoexSta->btInfoC2hCnt[i])
1158 {
1159 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723a1Ant[i], \
1160 pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1],
1161 pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3],
1162 pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5],
1163 pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]);
1164 CL_PRINTF(cliBuf);
1165 }
1166 }
1167
1168 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "write 0x1af=0x0 num", \
1169 pCoexSta->c2hHangDetectCnt);
1170 CL_PRINTF(cliBuf);
1171
1172 // Sw mechanism
1173 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============");
1174 CL_PRINTF(cliBuf);
1175 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "SM1[ShRf/ LpRA/ LimDig]", \
1176 pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->limited_dig);
1177 CL_PRINTF(cliBuf);
1178
1179 // Fw mechanism
1180 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============");
1181 CL_PRINTF(cliBuf);
1182
1183 if(!pBtCoexist->manual_control)
1184 {
1185 psTdmaCase = pCoexDm->curPsTdma;
1186 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \
1187 pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1],
1188 pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3],
1189 pCoexDm->psTdmaPara[4], psTdmaCase);
1190 CL_PRINTF(cliBuf);
1191
1192 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IgnWlanAct", \
1193 pCoexDm->bCurIgnoreWlanAct);
1194 CL_PRINTF(cliBuf);
1195 }
1196
1197 // Hw setting
1198 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============");
1199 CL_PRINTF(cliBuf);
1200
1201 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \
1202 pCoexDm->btRf0x1eBackup);
1203 CL_PRINTF(cliBuf);
1204
1205 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x778);
1206 u1Tmp[1] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x783);
1207 u1Tmp[2] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x796);
1208 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/ 0x783/ 0x796", \
1209 u1Tmp[0], u1Tmp[1], u1Tmp[2]);
1210 CL_PRINTF(cliBuf);
1211
1212 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x880);
1213 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x880", \
1214 u4Tmp[0]);
1215 CL_PRINTF(cliBuf);
1216
1217 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x40);
1218 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \
1219 u1Tmp[0]);
1220 CL_PRINTF(cliBuf);
1221
1222 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x550);
1223 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x522);
1224 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \
1225 u4Tmp[0], u1Tmp[0]);
1226 CL_PRINTF(cliBuf);
1227
1228 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x484);
1229 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x484(rate adaptive)", \
1230 u4Tmp[0]);
1231 CL_PRINTF(cliBuf);
1232
1233 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xc50);
1234 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \
1235 u4Tmp[0]);
1236 CL_PRINTF(cliBuf);
1237
1238 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xda0);
1239 u4Tmp[1] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xda4);
1240 u4Tmp[2] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xda8);
1241 u4Tmp[3] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xdac);
1242 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0xda0/0xda4/0xda8/0xdac(FA cnt)", \
1243 u4Tmp[0], u4Tmp[1], u4Tmp[2], u4Tmp[3]);
1244 CL_PRINTF(cliBuf);
1245
1246 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x6c0);
1247 u4Tmp[1] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x6c4);
1248 u4Tmp[2] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x6c8);
1249 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x6cc);
1250 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \
1251 u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]);
1252 CL_PRINTF(cliBuf);
1253
1254 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770 (hp rx[31:16]/tx[15:0])", \
1255 pCoexSta->highPriorityRx, pCoexSta->highPriorityTx);
1256 CL_PRINTF(cliBuf);
1257 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \
1258 pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx);
1259 CL_PRINTF(cliBuf);
1260
1261 // Tx mgnt queue hang or not, 0x41b should = 0xf, ex: 0xd ==>hang
1262 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x41b);
1263 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x41b (mgntQ hang chk == 0xf)", \
1264 u1Tmp[0]);
1265 CL_PRINTF(cliBuf);
1266
1267 pBtCoexist->btc_disp_dbg_msg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS);
1268}
1269
1270
1271VOID
1272EXhalbtc8723a1ant_IpsNotify(
1273 IN PBTC_COEXIST pBtCoexist,
1274 IN u1Byte type
1275 )
1276{
1277 if(BTC_IPS_ENTER == type)
1278 {
1279 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], IPS ENTER notify\n"));
1280 halbtc8723a1ant_CoexAllOff(pBtCoexist);
1281 }
1282 else if(BTC_IPS_LEAVE == type)
1283 {
1284 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], IPS LEAVE notify\n"));
1285 //halbtc8723a1ant_InitCoexDm(pBtCoexist);
1286 }
1287}
1288
1289VOID
1290EXhalbtc8723a1ant_LpsNotify(
1291 IN PBTC_COEXIST pBtCoexist,
1292 IN u1Byte type
1293 )
1294{
1295 if(BTC_LPS_ENABLE == type)
1296 {
1297 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], LPS ENABLE notify\n"));
1298 }
1299 else if(BTC_LPS_DISABLE == type)
1300 {
1301 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], LPS DISABLE notify\n"));
1302 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
1303 }
1304}
1305
1306VOID
1307EXhalbtc8723a1ant_ScanNotify(
1308 IN PBTC_COEXIST pBtCoexist,
1309 IN u1Byte type
1310 )
1311{
1312 BOOLEAN bWifiConnected=FALSE;
1313
1314 halbtc8723a1ant_NotifyFwScan(pBtCoexist, type);
1315
1316 if(pBtCoexist->btInfo.bBtDisabled)
1317 {
1318 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
1319 }
1320 else
1321 {
1322 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
1323 if(BTC_SCAN_START == type)
1324 {
1325 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], SCAN START notify\n"));
1326 if(!bWifiConnected) // non-connected scan
1327 {
1328 //set 0x550[3]=1 before PsTdma
1329 halbtc8723a1ant_Reg0x550Bit3(pBtCoexist, true);
1330 }
1331
1332 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 4);
1333 }
1334 else if(BTC_SCAN_FINISH == type)
1335 {
1336 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], SCAN FINISH notify\n"));
1337 if(!bWifiConnected) // non-connected scan
1338 {
1339 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1340 }
1341 else
1342 {
1343 halbtc8723a1ant_CoexForWifiConnect(pBtCoexist);
1344 }
1345 }
1346 }
1347}
1348
1349VOID
1350EXhalbtc8723a1ant_ConnectNotify(
1351 IN PBTC_COEXIST pBtCoexist,
1352 IN u1Byte type
1353 )
1354{
1355 BOOLEAN bWifiConnected=FALSE;
1356
1357 if(pBtCoexist->btInfo.bBtDisabled)
1358 {
1359 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
1360 }
1361 else
1362 {
1363 if(BTC_ASSOCIATE_START == type)
1364 {
1365 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], CONNECT START notify\n"));
1366 //set 0x550[3]=1 before PsTdma
1367 halbtc8723a1ant_Reg0x550Bit3(pBtCoexist, true);
1368 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 8); // extend wifi slot
1369 }
1370 else if(BTC_ASSOCIATE_FINISH == type)
1371 {
1372 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], CONNECT FINISH notify\n"));
1373 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
1374 if(!bWifiConnected) // non-connected scan
1375 {
1376 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1377 }
1378 else
1379 {
1380 halbtc8723a1ant_CoexForWifiConnect(pBtCoexist);
1381 }
1382 }
1383 }
1384}
1385
1386VOID
1387EXhalbtc8723a1ant_MediaStatusNotify(
1388 IN PBTC_COEXIST pBtCoexist,
1389 IN u1Byte type
1390 )
1391{
1392 if(BTC_MEDIA_CONNECT == type)
1393 {
1394 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], MEDIA connect notify\n"));
1395 }
1396 else
1397 {
1398 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], MEDIA disconnect notify\n"));
1399 }
1400}
1401
1402VOID
1403EXhalbtc8723a1ant_SpecialPacketNotify(
1404 IN PBTC_COEXIST pBtCoexist,
1405 IN u1Byte type
1406 )
1407{
1408 if(type == BTC_PACKET_DHCP)
1409 {
1410 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], DHCP Packet notify\n"));
1411 if(pBtCoexist->btInfo.bBtDisabled)
1412 {
1413 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
1414 }
1415 else
1416 {
1417 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 18);
1418 }
1419 }
1420}
1421
1422VOID
1423EXhalbtc8723a1ant_BtInfoNotify(
1424 IN PBTC_COEXIST pBtCoexist,
1425 IN pu1Byte tmpBuf,
1426 IN u1Byte length
1427 )
1428{
1429 u1Byte btInfo=0;
1430 u1Byte i, rspSource=0;
1431 BOOLEAN bBtHsOn=FALSE, bBtBusy=FALSE, bForceLps=FALSE;
1432
1433 pCoexSta->bC2hBtInfoReqSent = FALSE;
1434
1435 rspSource = BT_INFO_SRC_8723A_1ANT_BT_RSP;
1436 pCoexSta->btInfoC2hCnt[rspSource]++;
1437
1438 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length));
1439 for(i=0; i<length; i++)
1440 {
1441 pCoexSta->btInfoC2h[rspSource][i] = tmpBuf[i];
1442 if(i == 0)
1443 btInfo = tmpBuf[i];
1444 if(i == length-1)
1445 {
1446 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("0x%02x]\n", tmpBuf[i]));
1447 }
1448 else
1449 {
1450 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("0x%02x, ", tmpBuf[i]));
1451 }
1452 }
1453
1454 if(BT_INFO_SRC_8723A_1ANT_WIFI_FW != rspSource)
1455 {
1456 pCoexSta->btRetryCnt =
1457 pCoexSta->btInfoC2h[rspSource][1];
1458
1459 pCoexSta->btRssi =
1460 pCoexSta->btInfoC2h[rspSource][2]*2+10;
1461
1462 pCoexSta->btInfoExt =
1463 pCoexSta->btInfoC2h[rspSource][3];
1464 }
1465
1466 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
1467 // check BIT2 first ==> check if bt is under inquiry or page scan
1468 if(btInfo & BT_INFO_8723A_1ANT_B_INQ_PAGE)
1469 {
1470 pCoexSta->bC2hBtInquiryPage = true;
1471 }
1472 else
1473 {
1474 pCoexSta->bC2hBtInquiryPage = FALSE;
1475 }
1476 btInfo &= ~BIT2;
1477 if(!(btInfo & BIT0))
1478 {
1479 pCoexDm->btStatus = BT_STATE_8723A_1ANT_NO_CONNECTION;
1480 bForceLps = FALSE;
1481 }
1482 else
1483 {
1484 bForceLps = true;
1485 if(btInfo == 0x1)
1486 {
1487 pCoexDm->btStatus = BT_STATE_8723A_1ANT_CONNECT_IDLE;
1488 }
1489 else if(btInfo == 0x9)
1490 {
1491 pCoexDm->btStatus = BT_STATE_8723A_1ANT_ACL_ONLY_BUSY;
1492 bBtBusy = true;
1493 }
1494 else if(btInfo == 0x13)
1495 {
1496 pCoexDm->btStatus = BT_STATE_8723A_1ANT_SCO_ONLY_BUSY;
1497 bBtBusy = true;
1498 }
1499 else if(btInfo == 0x1b)
1500 {
1501 pCoexDm->btStatus = BT_STATE_8723A_1ANT_ACL_SCO_BUSY;
1502 bBtBusy = true;
1503 }
1504 else if(btInfo == 0x29)
1505 {
1506 pCoexDm->btStatus = BT_STATE_8723A_1ANT_HID_BUSY;
1507 bBtBusy = true;
1508 }
1509 else if(btInfo == 0x3b)
1510 {
1511 pCoexDm->btStatus = BT_STATE_8723A_1ANT_HID_SCO_BUSY;
1512 bBtBusy = true;
1513 }
1514 }
1515 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy);
1516 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bBtBusy);
1517 if(bForceLps)
1518 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL);
1519 else
1520 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL);
1521
1522 if( (BT_STATE_8723A_1ANT_NO_CONNECTION == pCoexDm->btStatus) ||
1523 (BT_STATE_8723A_1ANT_CONNECT_IDLE == pCoexDm->btStatus) )
1524 {
1525 if(pCoexSta->bC2hBtInquiryPage)
1526 pCoexDm->btStatus = BT_STATE_8723A_1ANT_INQ_OR_PAG;
1527 }
1528}
1529
1530VOID
1531EXhalbtc8723a1ant_StackOperationNotify(
1532 IN PBTC_COEXIST pBtCoexist,
1533 IN u1Byte type
1534 )
1535{
1536 if(BTC_STACK_OP_INQ_PAGE_PAIR_START == type)
1537 {
1538 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], StackOP Inquiry/page/pair start notify\n"));
1539 }
1540 else if(BTC_STACK_OP_INQ_PAGE_PAIR_FINISH == type)
1541 {
1542 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], StackOP Inquiry/page/pair finish notify\n"));
1543 }
1544}
1545
1546VOID
1547EXhalbtc8723a1ant_HaltNotify(
1548 IN PBTC_COEXIST pBtCoexist
1549 )
1550{
1551 halbtc8723a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0);
1552
1553 halbtc8723a1ant_LowPenaltyRa(pBtCoexist, FORCE_EXEC, FALSE);
1554 halbtc8723a1ant_RfShrink(pBtCoexist, FORCE_EXEC, FALSE);
1555
1556 halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, true);
1557 EXhalbtc8723a1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT);
1558}
1559
1560VOID
1561EXhalbtc8723a1ant_Periodical(
1562 IN PBTC_COEXIST pBtCoexist
1563 )
1564{
1565 BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE, bWifiConnected=FALSE;
1566
1567 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], 1Ant Periodical!!\n"));
1568
1569 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
1570 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
1571 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
1572 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
1573
1574 // work around for c2h hang
1575 wa_halbtc8723a1ant_MonitorC2h(pBtCoexist);
1576
1577 halbtc8723a1ant_QueryBtInfo(pBtCoexist);
1578 halbtc8723a1ant_MonitorBtCtr(pBtCoexist);
1579 halbtc8723a1ant_MonitorBtEnableDisable(pBtCoexist);
1580
1581
1582 if(bScan)
1583 return;
1584 if(bLink)
1585 return;
1586
1587 if(bWifiConnected)
1588 {
1589 if(pBtCoexist->btInfo.bBtDisabled)
1590 {
1591 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
1592
1593 halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
1594 halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
1595 }
1596 else
1597 {
1598 halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, true);
1599 halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
1600 halbtc8723a1ant_CoexForWifiConnect(pBtCoexist);
1601 }
1602 }
1603 else
1604 {
1605 halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1606
1607 halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
1608 halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
1609 }
1610}
1611
1612
1613#endif
1614
diff --git a/drivers/staging/rtl8821ae/btcoexist/habtc8723a1ant.h b/drivers/staging/rtl8821ae/btcoexist/habtc8723a1ant.h
new file mode 100644
index 000000000000..60992f59eb37
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/habtc8723a1ant.h
@@ -0,0 +1,176 @@
1//===========================================
2// The following is for 8723A 1Ant BT Co-exist definition
3//===========================================
4#define BT_INFO_8723A_1ANT_B_FTP BIT7
5#define BT_INFO_8723A_1ANT_B_A2DP BIT6
6#define BT_INFO_8723A_1ANT_B_HID BIT5
7#define BT_INFO_8723A_1ANT_B_SCO_BUSY BIT4
8#define BT_INFO_8723A_1ANT_B_ACL_BUSY BIT3
9#define BT_INFO_8723A_1ANT_B_INQ_PAGE BIT2
10#define BT_INFO_8723A_1ANT_B_SCO_ESCO BIT1
11#define BT_INFO_8723A_1ANT_B_CONNECTION BIT0
12
13typedef enum _BT_STATE_8723A_1ANT{
14 BT_STATE_8723A_1ANT_DISABLED = 0,
15 BT_STATE_8723A_1ANT_NO_CONNECTION = 1,
16 BT_STATE_8723A_1ANT_CONNECT_IDLE = 2,
17 BT_STATE_8723A_1ANT_INQ_OR_PAG = 3,
18 BT_STATE_8723A_1ANT_ACL_ONLY_BUSY = 4,
19 BT_STATE_8723A_1ANT_SCO_ONLY_BUSY = 5,
20 BT_STATE_8723A_1ANT_ACL_SCO_BUSY = 6,
21 BT_STATE_8723A_1ANT_HID_BUSY = 7,
22 BT_STATE_8723A_1ANT_HID_SCO_BUSY = 8,
23 BT_STATE_8723A_1ANT_MAX
24}BT_STATE_8723A_1ANT, *PBT_STATE_8723A_1ANT;
25
26#define BTC_RSSI_COEX_THRESH_TOL_8723A_1ANT 2
27
28typedef enum _BT_INFO_SRC_8723A_1ANT{
29 BT_INFO_SRC_8723A_1ANT_WIFI_FW = 0x0,
30 BT_INFO_SRC_8723A_1ANT_BT_RSP = 0x1,
31 BT_INFO_SRC_8723A_1ANT_BT_ACTIVE_SEND = 0x2,
32 BT_INFO_SRC_8723A_1ANT_MAX
33}BT_INFO_SRC_8723A_1ANT,*PBT_INFO_SRC_8723A_1ANT;
34
35typedef enum _BT_8723A_1ANT_BT_STATUS{
36 BT_8723A_1ANT_BT_STATUS_IDLE = 0x0,
37 BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
38 BT_8723A_1ANT_BT_STATUS_NON_IDLE = 0x2,
39 BT_8723A_1ANT_BT_STATUS_MAX
40}BT_8723A_1ANT_BT_STATUS,*PBT_8723A_1ANT_BT_STATUS;
41
42typedef enum _BT_8723A_1ANT_COEX_ALGO{
43 BT_8723A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
44 BT_8723A_1ANT_COEX_ALGO_SCO = 0x1,
45 BT_8723A_1ANT_COEX_ALGO_HID = 0x2,
46 BT_8723A_1ANT_COEX_ALGO_A2DP = 0x3,
47 BT_8723A_1ANT_COEX_ALGO_PANEDR = 0x4,
48 BT_8723A_1ANT_COEX_ALGO_PANHS = 0x5,
49 BT_8723A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
50 BT_8723A_1ANT_COEX_ALGO_PANEDR_HID = 0x7,
51 BT_8723A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
52 BT_8723A_1ANT_COEX_ALGO_HID_A2DP = 0x9,
53 BT_8723A_1ANT_COEX_ALGO_MAX
54}BT_8723A_1ANT_COEX_ALGO,*PBT_8723A_1ANT_COEX_ALGO;
55
56typedef struct _COEX_DM_8723A_1ANT{
57 // fw mechanism
58 BOOLEAN bCurIgnoreWlanAct;
59 BOOLEAN bPreIgnoreWlanAct;
60 u1Byte prePsTdma;
61 u1Byte curPsTdma;
62 u1Byte psTdmaPara[5];
63 u1Byte psTdmaDuAdjType;
64 u4Byte psTdmaMonitorCnt;
65 u4Byte psTdmaGlobalCnt;
66 BOOLEAN bResetTdmaAdjust;
67 BOOLEAN bPrePsTdmaOn;
68 BOOLEAN bCurPsTdmaOn;
69
70 // sw mechanism
71 BOOLEAN bPreRfRxLpfShrink;
72 BOOLEAN bCurRfRxLpfShrink;
73 u4Byte btRf0x1eBackup;
74 BOOLEAN bPreLowPenaltyRa;
75 BOOLEAN bCurLowPenaltyRa;
76 u4Byte preVal0x6c0;
77 u4Byte curVal0x6c0;
78 u4Byte preVal0x6c8;
79 u4Byte curVal0x6c8;
80 u1Byte preVal0x6cc;
81 u1Byte curVal0x6cc;
82 BOOLEAN limited_dig;
83
84 // algorithm related
85 u1Byte preAlgorithm;
86 u1Byte curAlgorithm;
87 u1Byte btStatus;
88 u1Byte wifiChnlInfo[3];
89} COEX_DM_8723A_1ANT, *PCOEX_DM_8723A_1ANT;
90
91typedef struct _COEX_STA_8723A_1ANT{
92 u4Byte highPriorityTx;
93 u4Byte highPriorityRx;
94 u4Byte lowPriorityTx;
95 u4Byte lowPriorityRx;
96 u1Byte btRssi;
97 u1Byte preBtRssiState;
98 u1Byte preBtRssiState1;
99 u1Byte preWifiRssiState[4];
100 BOOLEAN bC2hBtInfoReqSent;
101 u1Byte btInfoC2h[BT_INFO_SRC_8723A_1ANT_MAX][10];
102 u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_MAX];
103 BOOLEAN bC2hBtInquiryPage;
104 u1Byte btRetryCnt;
105 u1Byte btInfoExt;
106 //BOOLEAN bHoldForStackOperation;
107 //u1Byte bHoldPeriodCnt;
108 // this is for c2h hang work-around
109 u4Byte c2hHangDetectCnt;
110}COEX_STA_8723A_1ANT, *PCOEX_STA_8723A_1ANT;
111
112//===========================================
113// The following is interface which will notify coex module.
114//===========================================
115VOID
116EXhalbtc8723a1ant_InitHwConfig(
117 IN PBTC_COEXIST pBtCoexist
118 );
119VOID
120EXhalbtc8723a1ant_InitCoexDm(
121 IN PBTC_COEXIST pBtCoexist
122 );
123VOID
124EXhalbtc8723a1ant_IpsNotify(
125 IN PBTC_COEXIST pBtCoexist,
126 IN u1Byte type
127 );
128VOID
129EXhalbtc8723a1ant_LpsNotify(
130 IN PBTC_COEXIST pBtCoexist,
131 IN u1Byte type
132 );
133VOID
134EXhalbtc8723a1ant_ScanNotify(
135 IN PBTC_COEXIST pBtCoexist,
136 IN u1Byte type
137 );
138VOID
139EXhalbtc8723a1ant_ConnectNotify(
140 IN PBTC_COEXIST pBtCoexist,
141 IN u1Byte type
142 );
143VOID
144EXhalbtc8723a1ant_MediaStatusNotify(
145 IN PBTC_COEXIST pBtCoexist,
146 IN u1Byte type
147 );
148VOID
149EXhalbtc8723a1ant_SpecialPacketNotify(
150 IN PBTC_COEXIST pBtCoexist,
151 IN u1Byte type
152 );
153VOID
154EXhalbtc8723a1ant_BtInfoNotify(
155 IN PBTC_COEXIST pBtCoexist,
156 IN pu1Byte tmpBuf,
157 IN u1Byte length
158 );
159VOID
160EXhalbtc8723a1ant_StackOperationNotify(
161 IN PBTC_COEXIST pBtCoexist,
162 IN u1Byte type
163 );
164VOID
165EXhalbtc8723a1ant_HaltNotify(
166 IN PBTC_COEXIST pBtCoexist
167 );
168VOID
169EXhalbtc8723a1ant_Periodical(
170 IN PBTC_COEXIST pBtCoexist
171 );
172VOID
173EXhalbtc8723a1ant_DisplayCoexInfo(
174 IN PBTC_COEXIST pBtCoexist
175 );
176
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbt_precomp.h b/drivers/staging/rtl8821ae/btcoexist/halbt_precomp.h
new file mode 100644
index 000000000000..d538ba3d0a2e
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbt_precomp.h
@@ -0,0 +1,99 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20#ifndef __HALBT_PRECOMP_H__
21#define __HALBT_PRECOMP_H__
22/*************************************************************
23 * include files
24 *************************************************************/
25#include "../wifi.h"
26#include "../efuse.h"
27#include "../base.h"
28#include "../regd.h"
29#include "../cam.h"
30#include "../ps.h"
31#include "../pci.h"
32#include "../rtl8821ae/reg.h"
33#include "../rtl8821ae/def.h"
34#include "../rtl8821ae/phy.h"
35#include "../rtl8821ae/dm.h"
36#include "../rtl8821ae/fw.h"
37#include "../rtl8821ae/led.h"
38#include "../rtl8821ae/hw.h"
39#include "../rtl8821ae/pwrseqcmd.h"
40#include "../rtl8821ae/pwrseq.h"
41
42#include "halbtcoutsrc.h"
43
44
45#include "halbtc8192e2ant.h"
46#include "halbtc8723b1ant.h"
47#include "halbtc8723b2ant.h"
48
49
50
51#define GetDefaultAdapter(padapter) padapter
52
53
54#define BIT0 0x00000001
55#define BIT1 0x00000002
56#define BIT2 0x00000004
57#define BIT3 0x00000008
58#define BIT4 0x00000010
59#define BIT5 0x00000020
60#define BIT6 0x00000040
61#define BIT7 0x00000080
62#define BIT8 0x00000100
63#define BIT9 0x00000200
64#define BIT10 0x00000400
65#define BIT11 0x00000800
66#define BIT12 0x00001000
67#define BIT13 0x00002000
68#define BIT14 0x00004000
69#define BIT15 0x00008000
70#define BIT16 0x00010000
71#define BIT17 0x00020000
72#define BIT18 0x00040000
73#define BIT19 0x00080000
74#define BIT20 0x00100000
75#define BIT21 0x00200000
76#define BIT22 0x00400000
77#define BIT23 0x00800000
78#define BIT24 0x01000000
79#define BIT25 0x02000000
80#define BIT26 0x04000000
81#define BIT27 0x08000000
82#define BIT28 0x10000000
83#define BIT29 0x20000000
84#define BIT30 0x40000000
85#define BIT31 0x80000000
86
87#define MASKBYTE0 0xff
88#define MASKBYTE1 0xff00
89#define MASKBYTE2 0xff0000
90#define MASKBYTE3 0xff000000
91#define MASKHWORD 0xffff0000
92#define MASKLWORD 0x0000ffff
93#define MASKDWORD 0xffffffff
94#define MASK12BITS 0xfff
95#define MASKH4BITS 0xf0000000
96#define MASKOFDM_D 0xffc00000
97#define MASKCCK 0x3f3f3f3f
98
99#endif /* __HALBT_PRECOMP_H__ */
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtc8192e1ant.c b/drivers/staging/rtl8821ae/btcoexist/halbtc8192e1ant.c
new file mode 100644
index 000000000000..973d0ea82cb8
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtc8192e1ant.c
@@ -0,0 +1,3891 @@
1//============================================================
2// Description:
3//
4// This file is for 8192e1ant Co-exist mechanism
5//
6// History
7// 2012/11/15 Cosa first check in.
8//
9//============================================================
10
11//============================================================
12// include files
13//============================================================
14#include "Mp_Precomp.h"
15#if(BT_30_SUPPORT == 1)
16//============================================================
17// Global variables, these are static variables
18//============================================================
19static COEX_DM_8192E_1ANT GLCoexDm8192e1Ant;
20static PCOEX_DM_8192E_1ANT pCoexDm=&GLCoexDm8192e1Ant;
21static COEX_STA_8192E_1ANT GLCoexSta8192e1Ant;
22static PCOEX_STA_8192E_1ANT pCoexSta=&GLCoexSta8192e1Ant;
23
24const char *const GLBtInfoSrc8192e1Ant[]={
25 "BT Info[wifi fw]",
26 "BT Info[bt rsp]",
27 "BT Info[bt auto report]",
28};
29
30u4Byte GLCoexVerDate8192e1Ant=20130729;
31u4Byte GLCoexVer8192e1Ant=0x10;
32
33//============================================================
34// local function proto type if needed
35//============================================================
36//============================================================
37// local function start with halbtc8192e1ant_
38//============================================================
39u1Byte
40halbtc8192e1ant_BtRssiState(
41 u1Byte levelNum,
42 u1Byte rssiThresh,
43 u1Byte rssiThresh1
44 )
45{
46 s4Byte btRssi=0;
47 u1Byte btRssiState=pCoexSta->preBtRssiState;
48
49 btRssi = pCoexSta->btRssi;
50
51 if(levelNum == 2)
52 {
53 if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) ||
54 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW))
55 {
56 if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
57 {
58 btRssiState = BTC_RSSI_STATE_HIGH;
59 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to High\n"));
60 }
61 else
62 {
63 btRssiState = BTC_RSSI_STATE_STAY_LOW;
64 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at Low\n"));
65 }
66 }
67 else
68 {
69 if(btRssi < rssiThresh)
70 {
71 btRssiState = BTC_RSSI_STATE_LOW;
72 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Low\n"));
73 }
74 else
75 {
76 btRssiState = BTC_RSSI_STATE_STAY_HIGH;
77 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at High\n"));
78 }
79 }
80 }
81 else if(levelNum == 3)
82 {
83 if(rssiThresh > rssiThresh1)
84 {
85 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi thresh error!!\n"));
86 return pCoexSta->preBtRssiState;
87 }
88
89 if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) ||
90 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW))
91 {
92 if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
93 {
94 btRssiState = BTC_RSSI_STATE_MEDIUM;
95 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Medium\n"));
96 }
97 else
98 {
99 btRssiState = BTC_RSSI_STATE_STAY_LOW;
100 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at Low\n"));
101 }
102 }
103 else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) ||
104 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM))
105 {
106 if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
107 {
108 btRssiState = BTC_RSSI_STATE_HIGH;
109 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to High\n"));
110 }
111 else if(btRssi < rssiThresh)
112 {
113 btRssiState = BTC_RSSI_STATE_LOW;
114 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Low\n"));
115 }
116 else
117 {
118 btRssiState = BTC_RSSI_STATE_STAY_MEDIUM;
119 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at Medium\n"));
120 }
121 }
122 else
123 {
124 if(btRssi < rssiThresh1)
125 {
126 btRssiState = BTC_RSSI_STATE_MEDIUM;
127 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Medium\n"));
128 }
129 else
130 {
131 btRssiState = BTC_RSSI_STATE_STAY_HIGH;
132 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at High\n"));
133 }
134 }
135 }
136
137 pCoexSta->preBtRssiState = btRssiState;
138
139 return btRssiState;
140}
141
142u1Byte
143halbtc8192e1ant_WifiRssiState(
144 IN PBTC_COEXIST pBtCoexist,
145 IN u1Byte index,
146 IN u1Byte levelNum,
147 IN u1Byte rssiThresh,
148 IN u1Byte rssiThresh1
149 )
150{
151 s4Byte wifiRssi=0;
152 u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index];
153
154 pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
155
156 if(levelNum == 2)
157 {
158 if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
159 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
160 {
161 if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
162 {
163 wifiRssiState = BTC_RSSI_STATE_HIGH;
164 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to High\n"));
165 }
166 else
167 {
168 wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
169 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at Low\n"));
170 }
171 }
172 else
173 {
174 if(wifiRssi < rssiThresh)
175 {
176 wifiRssiState = BTC_RSSI_STATE_LOW;
177 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Low\n"));
178 }
179 else
180 {
181 wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
182 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at High\n"));
183 }
184 }
185 }
186 else if(levelNum == 3)
187 {
188 if(rssiThresh > rssiThresh1)
189 {
190 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI thresh error!!\n"));
191 return pCoexSta->preWifiRssiState[index];
192 }
193
194 if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
195 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
196 {
197 if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
198 {
199 wifiRssiState = BTC_RSSI_STATE_MEDIUM;
200 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Medium\n"));
201 }
202 else
203 {
204 wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
205 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at Low\n"));
206 }
207 }
208 else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) ||
209 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM))
210 {
211 if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT))
212 {
213 wifiRssiState = BTC_RSSI_STATE_HIGH;
214 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to High\n"));
215 }
216 else if(wifiRssi < rssiThresh)
217 {
218 wifiRssiState = BTC_RSSI_STATE_LOW;
219 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Low\n"));
220 }
221 else
222 {
223 wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM;
224 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at Medium\n"));
225 }
226 }
227 else
228 {
229 if(wifiRssi < rssiThresh1)
230 {
231 wifiRssiState = BTC_RSSI_STATE_MEDIUM;
232 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Medium\n"));
233 }
234 else
235 {
236 wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
237 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at High\n"));
238 }
239 }
240 }
241
242 pCoexSta->preWifiRssiState[index] = wifiRssiState;
243
244 return wifiRssiState;
245}
246
247VOID
248halbtc8192e1ant_Updatera_mask(
249 IN PBTC_COEXIST pBtCoexist,
250 IN BOOLEAN bForceExec,
251 IN u1Byte type,
252 IN u4Byte rateMask
253 )
254{
255 if(BTC_RATE_DISABLE == type)
256 {
257 pCoexDm->curra_mask |= rateMask; // disable rate
258 }
259 else if(BTC_RATE_ENABLE == type)
260 {
261 pCoexDm->curra_mask &= ~rateMask; // enable rate
262 }
263
264 if( bForceExec || (pCoexDm->prera_mask != pCoexDm->curra_mask))
265 {
266 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_UPDATE_ra_mask, &pCoexDm->curra_mask);
267 }
268 pCoexDm->prera_mask = pCoexDm->curra_mask;
269}
270
271VOID
272halbtc8192e1ant_MonitorBtCtr(
273 IN PBTC_COEXIST pBtCoexist
274 )
275{
276 u4Byte regHPTxRx, regLPTxRx, u4Tmp;
277 u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0;
278 u1Byte u1Tmp;
279
280 regHPTxRx = 0x770;
281 regLPTxRx = 0x774;
282
283 u4Tmp = pBtCoexist->btc_read_4byte(pBtCoexist, regHPTxRx);
284 regHPTx = u4Tmp & MASKLWORD;
285 regHPRx = (u4Tmp & MASKHWORD)>>16;
286
287 u4Tmp = pBtCoexist->btc_read_4byte(pBtCoexist, regLPTxRx);
288 regLPTx = u4Tmp & MASKLWORD;
289 regLPRx = (u4Tmp & MASKHWORD)>>16;
290
291 pCoexSta->highPriorityTx = regHPTx;
292 pCoexSta->highPriorityRx = regHPRx;
293 pCoexSta->lowPriorityTx = regLPTx;
294 pCoexSta->lowPriorityRx = regLPRx;
295
296 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
297 regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx));
298 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
299 regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx));
300
301 // reset counter
302 pBtCoexist->btc_write_1byte(pBtCoexist, 0x76e, 0xc);
303}
304
305VOID
306halbtc8192e1ant_QueryBtInfo(
307 IN PBTC_COEXIST pBtCoexist
308 )
309{
310 u1Byte H2C_Parameter[1] ={0};
311
312 pCoexSta->bC2hBtInfoReqSent = true;
313
314 H2C_Parameter[0] |= BIT0; // trigger
315
316 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], Query Bt Info, FW write 0x61=0x%x\n",
317 H2C_Parameter[0]));
318
319 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x61, 1, H2C_Parameter);
320}
321
322BOOLEAN
323halbtc8192e1ant_IsWifiStatusChanged(
324 IN PBTC_COEXIST pBtCoexist
325 )
326{
327 static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE;
328 BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE;
329 BOOLEAN bWifiConnected=FALSE;
330
331 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
332 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
333 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
334 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way);
335
336 if(bWifiConnected)
337 {
338 if(bWifiBusy != bPreWifiBusy)
339 {
340 bPreWifiBusy = bWifiBusy;
341 return true;
342 }
343 if(bUnder4way != bPreUnder4way)
344 {
345 bPreUnder4way = bUnder4way;
346 return true;
347 }
348 if(bBtHsOn != bPreBtHsOn)
349 {
350 bPreBtHsOn = bBtHsOn;
351 return true;
352 }
353 }
354
355 return FALSE;
356}
357
358VOID
359halbtc8192e1ant_UpdateBtLinkInfo(
360 IN PBTC_COEXIST pBtCoexist
361 )
362{
363 PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->bt_link_info;
364
365 pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist;
366 pBtLinkInfo->bScoExist = pCoexSta->bScoExist;
367 pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist;
368 pBtLinkInfo->bPanExist = pCoexSta->bPanExist;
369 pBtLinkInfo->bHidExist = pCoexSta->bHidExist;
370
371 // check if Sco only
372 if( pBtLinkInfo->bScoExist &&
373 !pBtLinkInfo->bA2dpExist &&
374 !pBtLinkInfo->bPanExist &&
375 !pBtLinkInfo->bHidExist )
376 pBtLinkInfo->bScoOnly = true;
377 else
378 pBtLinkInfo->bScoOnly = FALSE;
379
380 // check if A2dp only
381 if( !pBtLinkInfo->bScoExist &&
382 pBtLinkInfo->bA2dpExist &&
383 !pBtLinkInfo->bPanExist &&
384 !pBtLinkInfo->bHidExist )
385 pBtLinkInfo->bA2dpOnly = true;
386 else
387 pBtLinkInfo->bA2dpOnly = FALSE;
388
389 // check if Pan only
390 if( !pBtLinkInfo->bScoExist &&
391 !pBtLinkInfo->bA2dpExist &&
392 pBtLinkInfo->bPanExist &&
393 !pBtLinkInfo->bHidExist )
394 pBtLinkInfo->bPanOnly = true;
395 else
396 pBtLinkInfo->bPanOnly = FALSE;
397
398 // check if Hid only
399 if( !pBtLinkInfo->bScoExist &&
400 !pBtLinkInfo->bA2dpExist &&
401 !pBtLinkInfo->bPanExist &&
402 pBtLinkInfo->bHidExist )
403 pBtLinkInfo->bHidOnly = true;
404 else
405 pBtLinkInfo->bHidOnly = FALSE;
406}
407
408u1Byte
409halbtc8192e1ant_ActionAlgorithm(
410 IN PBTC_COEXIST pBtCoexist
411 )
412{
413 PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->bt_link_info;
414 BOOLEAN bBtHsOn=FALSE;
415 u1Byte algorithm=BT_8192E_1ANT_COEX_ALGO_UNDEFINED;
416 u1Byte numOfDiffProfile=0;
417
418 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
419
420 if(!pBtLinkInfo->bBtLinkExist)
421 {
422 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], No BT link exists!!!\n"));
423 return algorithm;
424 }
425
426 if(pBtLinkInfo->bScoExist)
427 numOfDiffProfile++;
428 if(pBtLinkInfo->bHidExist)
429 numOfDiffProfile++;
430 if(pBtLinkInfo->bPanExist)
431 numOfDiffProfile++;
432 if(pBtLinkInfo->bA2dpExist)
433 numOfDiffProfile++;
434
435 if(numOfDiffProfile == 1)
436 {
437 if(pBtLinkInfo->bScoExist)
438 {
439 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO only\n"));
440 algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
441 }
442 else
443 {
444 if(pBtLinkInfo->bHidExist)
445 {
446 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID only\n"));
447 algorithm = BT_8192E_1ANT_COEX_ALGO_HID;
448 }
449 else if(pBtLinkInfo->bA2dpExist)
450 {
451 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP only\n"));
452 algorithm = BT_8192E_1ANT_COEX_ALGO_A2DP;
453 }
454 else if(pBtLinkInfo->bPanExist)
455 {
456 if(bBtHsOn)
457 {
458 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN(HS) only\n"));
459 algorithm = BT_8192E_1ANT_COEX_ALGO_PANHS;
460 }
461 else
462 {
463 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN(EDR) only\n"));
464 algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR;
465 }
466 }
467 }
468 }
469 else if(numOfDiffProfile == 2)
470 {
471 if(pBtLinkInfo->bScoExist)
472 {
473 if(pBtLinkInfo->bHidExist)
474 {
475 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID\n"));
476 algorithm = BT_8192E_1ANT_COEX_ALGO_HID;
477 }
478 else if(pBtLinkInfo->bA2dpExist)
479 {
480 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + A2DP ==> SCO\n"));
481 algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
482 }
483 else if(pBtLinkInfo->bPanExist)
484 {
485 if(bBtHsOn)
486 {
487 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + PAN(HS)\n"));
488 algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
489 }
490 else
491 {
492 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + PAN(EDR)\n"));
493 algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
494 }
495 }
496 }
497 else
498 {
499 if( pBtLinkInfo->bHidExist &&
500 pBtLinkInfo->bA2dpExist )
501 {
502 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + A2DP\n"));
503 algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
504 }
505 else if( pBtLinkInfo->bHidExist &&
506 pBtLinkInfo->bPanExist )
507 {
508 if(bBtHsOn)
509 {
510 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + PAN(HS)\n"));
511 algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
512 }
513 else
514 {
515 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + PAN(EDR)\n"));
516 algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
517 }
518 }
519 else if( pBtLinkInfo->bPanExist &&
520 pBtLinkInfo->bA2dpExist )
521 {
522 if(bBtHsOn)
523 {
524 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP + PAN(HS)\n"));
525 algorithm = BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS;
526 }
527 else
528 {
529 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP + PAN(EDR)\n"));
530 algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP;
531 }
532 }
533 }
534 }
535 else if(numOfDiffProfile == 3)
536 {
537 if(pBtLinkInfo->bScoExist)
538 {
539 if( pBtLinkInfo->bHidExist &&
540 pBtLinkInfo->bA2dpExist )
541 {
542 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + A2DP ==> HID\n"));
543 algorithm = BT_8192E_1ANT_COEX_ALGO_HID;
544 }
545 else if( pBtLinkInfo->bHidExist &&
546 pBtLinkInfo->bPanExist )
547 {
548 if(bBtHsOn)
549 {
550 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + PAN(HS)\n"));
551 algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
552 }
553 else
554 {
555 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + PAN(EDR)\n"));
556 algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
557 }
558 }
559 else if( pBtLinkInfo->bPanExist &&
560 pBtLinkInfo->bA2dpExist )
561 {
562 if(bBtHsOn)
563 {
564 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + A2DP + PAN(HS)\n"));
565 algorithm = BT_8192E_1ANT_COEX_ALGO_SCO;
566 }
567 else
568 {
569 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"));
570 algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
571 }
572 }
573 }
574 else
575 {
576 if( pBtLinkInfo->bHidExist &&
577 pBtLinkInfo->bPanExist &&
578 pBtLinkInfo->bA2dpExist )
579 {
580 if(bBtHsOn)
581 {
582 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + A2DP + PAN(HS)\n"));
583 algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP;
584 }
585 else
586 {
587 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + A2DP + PAN(EDR)\n"));
588 algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
589 }
590 }
591 }
592 }
593 else if(numOfDiffProfile >= 3)
594 {
595 if(pBtLinkInfo->bScoExist)
596 {
597 if( pBtLinkInfo->bHidExist &&
598 pBtLinkInfo->bPanExist &&
599 pBtLinkInfo->bA2dpExist )
600 {
601 if(bBtHsOn)
602 {
603 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"));
604
605 }
606 else
607 {
608 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"));
609 algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_HID;
610 }
611 }
612 }
613 }
614
615 return algorithm;
616}
617
618VOID
619halbtc8192e1ant_SetFwDacSwingLevel(
620 IN PBTC_COEXIST pBtCoexist,
621 IN u1Byte dacSwingLvl
622 )
623{
624 u1Byte H2C_Parameter[1] ={0};
625
626 // There are several type of dacswing
627 // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6
628 H2C_Parameter[0] = dacSwingLvl;
629
630 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl));
631 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], FW write 0x64=0x%x\n", H2C_Parameter[0]));
632
633 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x64, 1, H2C_Parameter);
634}
635
636VOID
637halbtc8192e1ant_SetFwDecBtPwr(
638 IN PBTC_COEXIST pBtCoexist,
639 IN u1Byte decBtPwrLvl
640 )
641{
642 u1Byte H2C_Parameter[1] ={0};
643
644 H2C_Parameter[0] = decBtPwrLvl;
645
646 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], decrease Bt Power level = %d, FW write 0x62=0x%x\n",
647 decBtPwrLvl, H2C_Parameter[0]));
648
649 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x62, 1, H2C_Parameter);
650}
651
652VOID
653halbtc8192e1ant_DecBtPwr(
654 IN PBTC_COEXIST pBtCoexist,
655 IN BOOLEAN bForceExec,
656 IN u1Byte decBtPwrLvl
657 )
658{
659 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s Dec BT power level = %d\n",
660 (bForceExec? "force to":""), decBtPwrLvl));
661 pCoexDm->curBtDecPwrLvl = decBtPwrLvl;
662
663 if(!bForceExec)
664 {
665 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], BtDecPwrLvl=%d, curBtDecPwrLvl=%d\n",
666 pCoexDm->preBtDecPwrLvl, pCoexDm->curBtDecPwrLvl));
667
668 if(pCoexDm->preBtDecPwrLvl == pCoexDm->curBtDecPwrLvl)
669 return;
670 }
671 halbtc8192e1ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->curBtDecPwrLvl);
672
673 pCoexDm->preBtDecPwrLvl = pCoexDm->curBtDecPwrLvl;
674}
675
676VOID
677halbtc8192e1ant_SetFwBtLnaConstrain(
678 IN PBTC_COEXIST pBtCoexist,
679 IN BOOLEAN bBtLnaConsOn
680 )
681{
682 u1Byte H2C_Parameter[2] ={0};
683
684 H2C_Parameter[0] = 0x3; // opCode, 0x3=BT_SET_LNA_CONSTRAIN
685
686 if(bBtLnaConsOn)
687 {
688 H2C_Parameter[1] |= BIT0;
689 }
690
691 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], set BT LNA Constrain: %s, FW write 0x69=0x%x\n",
692 (bBtLnaConsOn? "ON!!":"OFF!!"),
693 H2C_Parameter[0]<<8|H2C_Parameter[1]));
694
695 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x69, 2, H2C_Parameter);
696}
697
698VOID
699halbtc8192e1ant_SetBtLnaConstrain(
700 IN PBTC_COEXIST pBtCoexist,
701 IN BOOLEAN bForceExec,
702 IN BOOLEAN bBtLnaConsOn
703 )
704{
705 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s BT Constrain = %s\n",
706 (bForceExec? "force":""), ((bBtLnaConsOn)? "ON":"OFF")));
707 pCoexDm->bCurBtLnaConstrain = bBtLnaConsOn;
708
709 if(!bForceExec)
710 {
711 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPreBtLnaConstrain=%d, bCurBtLnaConstrain=%d\n",
712 pCoexDm->bPreBtLnaConstrain, pCoexDm->bCurBtLnaConstrain));
713
714 if(pCoexDm->bPreBtLnaConstrain == pCoexDm->bCurBtLnaConstrain)
715 return;
716 }
717 halbtc8192e1ant_SetFwBtLnaConstrain(pBtCoexist, pCoexDm->bCurBtLnaConstrain);
718
719 pCoexDm->bPreBtLnaConstrain = pCoexDm->bCurBtLnaConstrain;
720}
721
722VOID
723halbtc8192e1ant_SetFwBtPsdMode(
724 IN PBTC_COEXIST pBtCoexist,
725 IN u1Byte btPsdMode
726 )
727{
728 u1Byte H2C_Parameter[2] ={0};
729
730 H2C_Parameter[0] = 0x2; // opCode, 0x2=BT_SET_PSD_MODE
731
732 H2C_Parameter[1] = btPsdMode;
733
734 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], set BT PSD mode=0x%x, FW write 0x69=0x%x\n",
735 H2C_Parameter[1],
736 H2C_Parameter[0]<<8|H2C_Parameter[1]));
737
738 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x69, 2, H2C_Parameter);
739}
740
741
742VOID
743halbtc8192e1ant_SetBtPsdMode(
744 IN PBTC_COEXIST pBtCoexist,
745 IN BOOLEAN bForceExec,
746 IN u1Byte btPsdMode
747 )
748{
749 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s BT PSD mode = 0x%x\n",
750 (bForceExec? "force":""), btPsdMode));
751 pCoexDm->bCurBtPsdMode = btPsdMode;
752
753 if(!bForceExec)
754 {
755 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPreBtPsdMode=0x%x, bCurBtPsdMode=0x%x\n",
756 pCoexDm->bPreBtPsdMode, pCoexDm->bCurBtPsdMode));
757
758 if(pCoexDm->bPreBtPsdMode == pCoexDm->bCurBtPsdMode)
759 return;
760 }
761 halbtc8192e1ant_SetFwBtPsdMode(pBtCoexist, pCoexDm->bCurBtPsdMode);
762
763 pCoexDm->bPreBtPsdMode = pCoexDm->bCurBtPsdMode;
764}
765
766
767VOID
768halbtc8192e1ant_SetBtAutoReport(
769 IN PBTC_COEXIST pBtCoexist,
770 IN BOOLEAN bEnableAutoReport
771 )
772{
773 u1Byte H2C_Parameter[1] ={0};
774
775 H2C_Parameter[0] = 0;
776
777 if(bEnableAutoReport)
778 {
779 H2C_Parameter[0] |= BIT0;
780 }
781
782 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n",
783 (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0]));
784
785 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x68, 1, H2C_Parameter);
786}
787
788VOID
789halbtc8192e1ant_BtAutoReport(
790 IN PBTC_COEXIST pBtCoexist,
791 IN BOOLEAN bForceExec,
792 IN BOOLEAN bEnableAutoReport
793 )
794{
795 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s BT Auto report = %s\n",
796 (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled")));
797 pCoexDm->bCurBtAutoReport = bEnableAutoReport;
798
799 if(!bForceExec)
800 {
801 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPreBtAutoReport=%d, bCurBtAutoReport=%d\n",
802 pCoexDm->bPreBtAutoReport, pCoexDm->bCurBtAutoReport));
803
804 if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport)
805 return;
806 }
807 halbtc8192e1ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport);
808
809 pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport;
810}
811
812VOID
813halbtc8192e1ant_FwDacSwingLvl(
814 IN PBTC_COEXIST pBtCoexist,
815 IN BOOLEAN bForceExec,
816 IN u1Byte fwDacSwingLvl
817 )
818{
819 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s set FW Dac Swing level = %d\n",
820 (bForceExec? "force to":""), fwDacSwingLvl));
821 pCoexDm->curFwDacSwingLvl = fwDacSwingLvl;
822
823 if(!bForceExec)
824 {
825 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], preFwDacSwingLvl=%d, curFwDacSwingLvl=%d\n",
826 pCoexDm->preFwDacSwingLvl, pCoexDm->curFwDacSwingLvl));
827
828 if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl)
829 return;
830 }
831
832 halbtc8192e1ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl);
833
834 pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl;
835}
836
837VOID
838halbtc8192e1ant_SetSwRfRxLpfCorner(
839 IN PBTC_COEXIST pBtCoexist,
840 IN BOOLEAN bRxRfShrinkOn
841 )
842{
843 if(bRxRfShrinkOn)
844 {
845 //Shrink RF Rx LPF corner
846 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Shrink RF Rx LPF corner!!\n"));
847 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf0ff7);
848 }
849 else
850 {
851 //Resume RF Rx LPF corner
852 // After initialized, we can use pCoexDm->btRf0x1eBackup
853 if(pBtCoexist->initilized)
854 {
855 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Resume RF Rx LPF corner!!\n"));
856 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup);
857 }
858 }
859}
860
861VOID
862halbtc8192e1ant_RfShrink(
863 IN PBTC_COEXIST pBtCoexist,
864 IN BOOLEAN bForceExec,
865 IN BOOLEAN bRxRfShrinkOn
866 )
867{
868 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn Rx RF Shrink = %s\n",
869 (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF")));
870 pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn;
871
872 if(!bForceExec)
873 {
874 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreRfRxLpfShrink=%d, bCurRfRxLpfShrink=%d\n",
875 pCoexDm->bPreRfRxLpfShrink, pCoexDm->bCurRfRxLpfShrink));
876
877 if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink)
878 return;
879 }
880 halbtc8192e1ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink);
881
882 pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink;
883}
884
885VOID
886halbtc8192e1ant_SetSwPenaltyTxRateAdaptive(
887 IN PBTC_COEXIST pBtCoexist,
888 IN BOOLEAN bLowPenaltyRa
889 )
890{
891 u1Byte tmpU1;
892
893 tmpU1 = pBtCoexist->btc_read_1byte(pBtCoexist, 0x4fd);
894 tmpU1 |= BIT0;
895 if(bLowPenaltyRa)
896 {
897 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Tx rate adaptive, set low penalty!!\n"));
898 tmpU1 &= ~BIT2;
899 }
900 else
901 {
902 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Tx rate adaptive, set normal!!\n"));
903 tmpU1 |= BIT2;
904 }
905
906 pBtCoexist->btc_write_1byte(pBtCoexist, 0x4fd, tmpU1);
907}
908
909VOID
910halbtc8192e1ant_LowPenaltyRa(
911 IN PBTC_COEXIST pBtCoexist,
912 IN BOOLEAN bForceExec,
913 IN BOOLEAN bLowPenaltyRa
914 )
915{
916 return;
917 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn LowPenaltyRA = %s\n",
918 (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF")));
919 pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa;
920
921 if(!bForceExec)
922 {
923 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreLowPenaltyRa=%d, bCurLowPenaltyRa=%d\n",
924 pCoexDm->bPreLowPenaltyRa, pCoexDm->bCurLowPenaltyRa));
925
926 if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa)
927 return;
928 }
929 halbtc8192e1ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa);
930
931 pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa;
932}
933
934VOID
935halbtc8192e1ant_SetDacSwingReg(
936 IN PBTC_COEXIST pBtCoexist,
937 IN u4Byte level
938 )
939{
940 u1Byte val=(u1Byte)level;
941
942 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Write SwDacSwing = 0x%x\n", level));
943 pBtCoexist->btc_write_1byte_bitmask(pBtCoexist, 0x883, 0x3e, val);
944}
945
946VOID
947halbtc8192e1ant_SetSwFullTimeDacSwing(
948 IN PBTC_COEXIST pBtCoexist,
949 IN BOOLEAN bSwDacSwingOn,
950 IN u4Byte swDacSwingLvl
951 )
952{
953 if(bSwDacSwingOn)
954 {
955 halbtc8192e1ant_SetDacSwingReg(pBtCoexist, swDacSwingLvl);
956 }
957 else
958 {
959 halbtc8192e1ant_SetDacSwingReg(pBtCoexist, 0x18);
960 }
961}
962
963
964VOID
965halbtc8192e1ant_DacSwing(
966 IN PBTC_COEXIST pBtCoexist,
967 IN BOOLEAN bForceExec,
968 IN BOOLEAN bDacSwingOn,
969 IN u4Byte dacSwingLvl
970 )
971{
972 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n",
973 (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl));
974 pCoexDm->bCurDacSwingOn = bDacSwingOn;
975 pCoexDm->curDacSwingLvl = dacSwingLvl;
976
977 if(!bForceExec)
978 {
979 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl=0x%x, bCurDacSwingOn=%d, curDacSwingLvl=0x%x\n",
980 pCoexDm->bPreDacSwingOn, pCoexDm->preDacSwingLvl,
981 pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl));
982
983 if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) &&
984 (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) )
985 return;
986 }
987 mdelay(30);
988 halbtc8192e1ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl);
989
990 pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn;
991 pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl;
992}
993
994VOID
995halbtc8192e1ant_SetAdcBackOff(
996 IN PBTC_COEXIST pBtCoexist,
997 IN BOOLEAN bAdcBackOff
998 )
999{
1000 if(bAdcBackOff)
1001 {
1002 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], BB BackOff Level On!\n"));
1003 pBtCoexist->btc_write_1byte_bitmask(pBtCoexist, 0x8db, 0x60, 0x3);
1004 }
1005 else
1006 {
1007 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], BB BackOff Level Off!\n"));
1008 pBtCoexist->btc_write_1byte_bitmask(pBtCoexist, 0x8db, 0x60, 0x1);
1009 }
1010}
1011
1012VOID
1013halbtc8192e1ant_AdcBackOff(
1014 IN PBTC_COEXIST pBtCoexist,
1015 IN BOOLEAN bForceExec,
1016 IN BOOLEAN bAdcBackOff
1017 )
1018{
1019 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn AdcBackOff = %s\n",
1020 (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF")));
1021 pCoexDm->bCurAdcBackOff = bAdcBackOff;
1022
1023 if(!bForceExec)
1024 {
1025 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreAdcBackOff=%d, bCurAdcBackOff=%d\n",
1026 pCoexDm->bPreAdcBackOff, pCoexDm->bCurAdcBackOff));
1027
1028 if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff)
1029 return;
1030 }
1031 halbtc8192e1ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff);
1032
1033 pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff;
1034}
1035
1036VOID
1037halbtc8192e1ant_SetAgcTable(
1038 IN PBTC_COEXIST pBtCoexist,
1039 IN BOOLEAN bAgcTableEn
1040 )
1041{
1042 u1Byte rssiAdjustVal=0;
1043
1044 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000);
1045 if(bAgcTableEn)
1046 {
1047 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Agc Table On!\n"));
1048 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x3fa58);
1049 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x37a58);
1050 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x2fa58);
1051 rssiAdjustVal = 8;
1052 }
1053 else
1054 {
1055 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Agc Table Off!\n"));
1056 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x39258);
1057 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x31258);
1058 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x29258);
1059 }
1060 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
1061
1062 // set rssiAdjustVal for wifi module.
1063 pBtCoexist->btc_set(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal);
1064}
1065
1066
1067VOID
1068halbtc8192e1ant_AgcTable(
1069 IN PBTC_COEXIST pBtCoexist,
1070 IN BOOLEAN bForceExec,
1071 IN BOOLEAN bAgcTableEn
1072 )
1073{
1074 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s %s Agc Table\n",
1075 (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable")));
1076 pCoexDm->bCurAgcTableEn = bAgcTableEn;
1077
1078 if(!bForceExec)
1079 {
1080 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n",
1081 pCoexDm->bPreAgcTableEn, pCoexDm->bCurAgcTableEn));
1082
1083 if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn)
1084 return;
1085 }
1086 halbtc8192e1ant_SetAgcTable(pBtCoexist, bAgcTableEn);
1087
1088 pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn;
1089}
1090
1091VOID
1092halbtc8192e1ant_SetCoexTable(
1093 IN PBTC_COEXIST pBtCoexist,
1094 IN u4Byte val0x6c0,
1095 IN u4Byte val0x6c4,
1096 IN u4Byte val0x6c8,
1097 IN u1Byte val0x6cc
1098 )
1099{
1100 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0));
1101 pBtCoexist->btc_write_4byte(pBtCoexist, 0x6c0, val0x6c0);
1102
1103 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4));
1104 pBtCoexist->btc_write_4byte(pBtCoexist, 0x6c4, val0x6c4);
1105
1106 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8));
1107 pBtCoexist->btc_write_4byte(pBtCoexist, 0x6c8, val0x6c8);
1108
1109 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc));
1110 pBtCoexist->btc_write_1byte(pBtCoexist, 0x6cc, val0x6cc);
1111}
1112
1113VOID
1114halbtc8192e1ant_CoexTable(
1115 IN PBTC_COEXIST pBtCoexist,
1116 IN BOOLEAN bForceExec,
1117 IN u4Byte val0x6c0,
1118 IN u4Byte val0x6c4,
1119 IN u4Byte val0x6c8,
1120 IN u1Byte val0x6cc
1121 )
1122{
1123 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
1124 (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6c8, val0x6cc));
1125 pCoexDm->curVal0x6c0 = val0x6c0;
1126 pCoexDm->curVal0x6c4 = val0x6c4;
1127 pCoexDm->curVal0x6c8 = val0x6c8;
1128 pCoexDm->curVal0x6cc = val0x6cc;
1129
1130 if(!bForceExec)
1131 {
1132 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], preVal0x6c0=0x%x, preVal0x6c4=0x%x, preVal0x6c8=0x%x, preVal0x6cc=0x%x !!\n",
1133 pCoexDm->preVal0x6c0, pCoexDm->preVal0x6c4, pCoexDm->preVal0x6c8, pCoexDm->preVal0x6cc));
1134 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], curVal0x6c0=0x%x, curVal0x6c4=0x%x, curVal0x6c8=0x%x, curVal0x6cc=0x%x !!\n",
1135 pCoexDm->curVal0x6c0, pCoexDm->curVal0x6c4, pCoexDm->curVal0x6c8, pCoexDm->curVal0x6cc));
1136
1137 if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) &&
1138 (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) &&
1139 (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) &&
1140 (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) )
1141 return;
1142 }
1143 halbtc8192e1ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc);
1144
1145 pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0;
1146 pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4;
1147 pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8;
1148 pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc;
1149}
1150
1151VOID
1152halbtc8192e1ant_CoexTableWithType(
1153 IN PBTC_COEXIST pBtCoexist,
1154 IN BOOLEAN bForceExec,
1155 IN u1Byte type
1156 )
1157{
1158 switch(type)
1159 {
1160 case 0:
1161 halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, 0xffffff, 0x3);
1162 break;
1163 case 1:
1164 halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3);
1165 break;
1166 case 2:
1167 halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3);
1168 break;
1169 case 3:
1170 halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3);
1171 break;
1172 case 4:
1173 halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0xffffffff, 0xffffffff, 0xffffff, 0x3);
1174 break;
1175 case 5:
1176 halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3);
1177 break;
1178 case 6:
1179 halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3);
1180 break;
1181 case 7:
1182 halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0xddffddff, 0xddffddff, 0xffffff, 0x3);
1183 break;
1184 case 8:
1185 halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5afa5afa, 0xffffff, 0x3);
1186 break;
1187 case 9:
1188 halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x5f5f5f5f, 0x5f5f5f5f, 0xffffff, 0x3);
1189 break;
1190 default:
1191 break;
1192 }
1193}
1194
1195VOID
1196halbtc8192e1ant_SetFwIgnoreWlanAct(
1197 IN PBTC_COEXIST pBtCoexist,
1198 IN BOOLEAN bEnable
1199 )
1200{
1201 u1Byte H2C_Parameter[1] ={0};
1202
1203 if(bEnable)
1204 {
1205 H2C_Parameter[0] |= BIT0; // function enable
1206 }
1207
1208 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n",
1209 H2C_Parameter[0]));
1210
1211 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x63, 1, H2C_Parameter);
1212}
1213
1214VOID
1215halbtc8192e1ant_IgnoreWlanAct(
1216 IN PBTC_COEXIST pBtCoexist,
1217 IN BOOLEAN bForceExec,
1218 IN BOOLEAN bEnable
1219 )
1220{
1221 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s turn Ignore WlanAct %s\n",
1222 (bForceExec? "force to":""), (bEnable? "ON":"OFF")));
1223 pCoexDm->bCurIgnoreWlanAct = bEnable;
1224
1225 if(!bForceExec)
1226 {
1227 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPreIgnoreWlanAct = %d, bCurIgnoreWlanAct = %d!!\n",
1228 pCoexDm->bPreIgnoreWlanAct, pCoexDm->bCurIgnoreWlanAct));
1229
1230 if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct)
1231 return;
1232 }
1233 halbtc8192e1ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable);
1234
1235 pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct;
1236}
1237
1238VOID
1239halbtc8192e1ant_SetFwPstdma(
1240 IN PBTC_COEXIST pBtCoexist,
1241 IN u1Byte byte1,
1242 IN u1Byte byte2,
1243 IN u1Byte byte3,
1244 IN u1Byte byte4,
1245 IN u1Byte byte5
1246 )
1247{
1248 u1Byte H2C_Parameter[5] ={0};
1249
1250 H2C_Parameter[0] = byte1;
1251 H2C_Parameter[1] = byte2;
1252 H2C_Parameter[2] = byte3;
1253 H2C_Parameter[3] = byte4;
1254 H2C_Parameter[4] = byte5;
1255
1256 pCoexDm->psTdmaPara[0] = byte1;
1257 pCoexDm->psTdmaPara[1] = byte2;
1258 pCoexDm->psTdmaPara[2] = byte3;
1259 pCoexDm->psTdmaPara[3] = byte4;
1260 pCoexDm->psTdmaPara[4] = byte5;
1261
1262 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], FW write 0x60(5bytes)=0x%x%08x\n",
1263 H2C_Parameter[0],
1264 H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4]));
1265
1266 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x60, 5, H2C_Parameter);
1267}
1268
1269VOID
1270halbtc8192e1ant_SetLpsRpwm(
1271 IN PBTC_COEXIST pBtCoexist,
1272 IN u1Byte lpsVal,
1273 IN u1Byte rpwmVal
1274 )
1275{
1276 u1Byte lps=lpsVal;
1277 u1Byte rpwm=rpwmVal;
1278
1279 pBtCoexist->btc_set(pBtCoexist, BTC_SET_U1_1ANT_LPS, &lps);
1280 pBtCoexist->btc_set(pBtCoexist, BTC_SET_U1_1ANT_RPWM, &rpwm);
1281}
1282
1283VOID
1284halbtc8192e1ant_LpsRpwm(
1285 IN PBTC_COEXIST pBtCoexist,
1286 IN BOOLEAN bForceExec,
1287 IN u1Byte lpsVal,
1288 IN u1Byte rpwmVal
1289 )
1290{
1291 BOOLEAN bForceExecPwrCmd=FALSE;
1292
1293 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n",
1294 (bForceExec? "force to":""), lpsVal, rpwmVal));
1295 pCoexDm->curLps = lpsVal;
1296 pCoexDm->curRpwm = rpwmVal;
1297
1298 if(!bForceExec)
1299 {
1300 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], preLps/curLps=0x%x/0x%x, preRpwm/curRpwm=0x%x/0x%x!!\n",
1301 pCoexDm->preLps, pCoexDm->curLps, pCoexDm->preRpwm, pCoexDm->curRpwm));
1302
1303 if( (pCoexDm->preLps == pCoexDm->curLps) &&
1304 (pCoexDm->preRpwm == pCoexDm->curRpwm) )
1305 {
1306 return;
1307 }
1308 }
1309 halbtc8192e1ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal);
1310
1311 pCoexDm->preLps = pCoexDm->curLps;
1312 pCoexDm->preRpwm = pCoexDm->curRpwm;
1313}
1314
1315VOID
1316halbtc8192e1ant_SwMechanism1(
1317 IN PBTC_COEXIST pBtCoexist,
1318 IN BOOLEAN bShrinkRxLPF,
1319 IN BOOLEAN bLowPenaltyRA,
1320 IN BOOLEAN limited_dig,
1321 IN BOOLEAN bBTLNAConstrain
1322 )
1323{
1324 //halbtc8192e1ant_RfShrink(pBtCoexist, NORMAL_EXEC, bShrinkRxLPF);
1325 //halbtc8192e1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA);
1326
1327 //no limited DIG
1328 //halbtc8192e1ant_SetBtLnaConstrain(pBtCoexist, NORMAL_EXEC, bBTLNAConstrain);
1329}
1330
1331VOID
1332halbtc8192e1ant_SwMechanism2(
1333 IN PBTC_COEXIST pBtCoexist,
1334 IN BOOLEAN bAGCTableShift,
1335 IN BOOLEAN bADCBackOff,
1336 IN BOOLEAN bSWDACSwing,
1337 IN u4Byte dacSwingLvl
1338 )
1339{
1340 //halbtc8192e1ant_AgcTable(pBtCoexist, NORMAL_EXEC, bAGCTableShift);
1341 //halbtc8192e1ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, bADCBackOff);
1342 //halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, bSWDACSwing, dacSwingLvl);
1343}
1344
1345VOID
1346halbtc8192e1ant_PsTdma(
1347 IN PBTC_COEXIST pBtCoexist,
1348 IN BOOLEAN bForceExec,
1349 IN BOOLEAN bTurnOn,
1350 IN u1Byte type
1351 )
1352{
1353 BOOLEAN bTurnOnByCnt=FALSE;
1354 u1Byte psTdmaTypeByCnt=0, rssiAdjustVal=0;
1355
1356 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s turn %s PS TDMA, type=%d\n",
1357 (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type));
1358 pCoexDm->bCurPsTdmaOn = bTurnOn;
1359 pCoexDm->curPsTdma = type;
1360
1361 if(!bForceExec)
1362 {
1363 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n",
1364 pCoexDm->bPrePsTdmaOn, pCoexDm->bCurPsTdmaOn));
1365 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n",
1366 pCoexDm->prePsTdma, pCoexDm->curPsTdma));
1367
1368 if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) &&
1369 (pCoexDm->prePsTdma == pCoexDm->curPsTdma) )
1370 return;
1371 }
1372 if(bTurnOn)
1373 {
1374 switch(type)
1375 {
1376 default:
1377 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x53, 0x2c, 0x03, 0x10, 0x50);
1378 break;
1379 case 1:
1380 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x53, 0x2c, 0x03, 0x10, 0x50);
1381 rssiAdjustVal = 11;
1382 break;
1383 case 2:
1384 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x53, 0x25, 0x03, 0x10, 0x50);
1385 rssiAdjustVal = 14;
1386 break;
1387 case 3:
1388 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x40);
1389 break;
1390 case 4:
1391 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x14, 0x0);
1392 rssiAdjustVal = 17;
1393 break;
1394 case 5:
1395 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x61, 0x15, 0x3, 0x31, 0x0);
1396 break;
1397 case 6:
1398 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0x3, 0x0, 0x0);
1399 break;
1400 case 7:
1401 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x13, 0xc, 0x5, 0x0, 0x0);
1402 break;
1403 case 8:
1404 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0);
1405 break;
1406 case 9:
1407 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x53, 0x1e, 0x03, 0x10, 0x50);
1408 rssiAdjustVal = 18;
1409 break;
1410 case 10:
1411 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0xa, 0x0, 0x40);
1412 break;
1413 case 11:
1414 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x53, 0x12, 0x03, 0x10, 0x50);
1415 rssiAdjustVal = 20;
1416 break;
1417 case 12:
1418 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xeb, 0xa, 0x3, 0x31, 0x18);
1419 break;
1420
1421 case 15:
1422 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0x3, 0x8, 0x0);
1423 break;
1424 case 16:
1425 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x10, 0x0);
1426 rssiAdjustVal = 18;
1427 break;
1428
1429 case 18:
1430 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0);
1431 rssiAdjustVal = 14;
1432 break;
1433
1434 case 20:
1435 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x13, 0x25, 0x25, 0x0, 0x0);
1436 break;
1437 case 21:
1438 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x20, 0x3, 0x10, 0x40);
1439 break;
1440 case 22:
1441 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x13, 0x8, 0x8, 0x0, 0x40);
1442 break;
1443 case 23:
1444 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x18);
1445 rssiAdjustVal = 22;
1446 break;
1447 case 24:
1448 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x3, 0x31, 0x18);
1449 rssiAdjustVal = 22;
1450 break;
1451 case 25:
1452 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18);
1453 rssiAdjustVal = 22;
1454 break;
1455 case 26:
1456 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18);
1457 rssiAdjustVal = 22;
1458 break;
1459 case 27:
1460 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x98);
1461 rssiAdjustVal = 22;
1462 break;
1463 case 28:
1464 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x69, 0x25, 0x3, 0x31, 0x0);
1465 break;
1466 case 29:
1467 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xab, 0x1a, 0x1a, 0x1, 0x10);
1468 break;
1469 case 30:
1470 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x14, 0x0);
1471 break;
1472 case 31:
1473 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1a, 0x1a, 0, 0x58);
1474 break;
1475 case 32:
1476 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xab, 0xa, 0x3, 0x31, 0x90);
1477 break;
1478 case 33:
1479 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xa3, 0x25, 0x3, 0x30, 0x90);
1480 break;
1481 case 34:
1482 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1a, 0x1a, 0x0, 0x10);
1483 break;
1484 case 35:
1485 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x0, 0x10);
1486 break;
1487 case 36:
1488 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x12, 0x3, 0x14, 0x50);
1489 break;
1490 case 37:
1491 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x53, 0x25, 0x3, 0x10, 0x50);
1492 break;
1493 case 38:
1494 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90);
1495 break;
1496 }
1497 }
1498 else
1499 {
1500 // disable PS tdma
1501 switch(type)
1502 {
1503 case 8: //0x778 = 1, ant2PTA
1504 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x8, 0x0, 0x0, 0x0, 0x0);
1505 pBtCoexist->btc_write_1byte(pBtCoexist, 0x92c, 0x4);
1506 break;
1507 case 0: //0x778 = 1, ant2BT
1508 default:
1509 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0);
1510 mdelay(5);
1511 pBtCoexist->btc_write_1byte(pBtCoexist, 0x92c, 0x20);
1512 break;
1513 case 9: //0x778 = 1, ant2WIFI
1514 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0);
1515 pBtCoexist->btc_write_1byte(pBtCoexist, 0x92c, 0x4);
1516 break;
1517 case 10: //0x778 = 3, ant2BT
1518 halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0);
1519 mdelay(5);
1520 pBtCoexist->btc_write_1byte(pBtCoexist, 0x92c, 0x20);
1521 break;
1522 }
1523 }
1524 rssiAdjustVal =0;
1525 pBtCoexist->btc_set(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssiAdjustVal);
1526
1527 // update pre state
1528 pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn;
1529 pCoexDm->prePsTdma = pCoexDm->curPsTdma;
1530}
1531
1532VOID
1533halbtc8192e1ant_SetSwitchSsType(
1534 IN PBTC_COEXIST pBtCoexist,
1535 IN u1Byte ssType
1536 )
1537{
1538 u1Byte mimoPs=BTC_MIMO_PS_DYNAMIC;
1539
1540 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], REAL set SS Type = %d\n", ssType));
1541
1542 if(ssType == 1)
1543 {
1544 halbtc8192e1ant_Updatera_mask(pBtCoexist, FORCE_EXEC, BTC_RATE_DISABLE, 0xfff00000); // disable 2ss
1545 halbtc8192e1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0);
1546 // switch ofdm path
1547 pBtCoexist->btc_write_1byte(pBtCoexist, 0xc04, 0x11);
1548 pBtCoexist->btc_write_1byte(pBtCoexist, 0xd04, 0x1);
1549 pBtCoexist->btc_write_4byte(pBtCoexist, 0x90c, 0x81111111);
1550 // switch cck patch
1551 pBtCoexist->btc_write_1byte_bitmask(pBtCoexist, 0xe77, 0x4, 0x1);
1552 pBtCoexist->btc_write_1byte(pBtCoexist, 0xa07, 0x81);
1553 mimoPs=BTC_MIMO_PS_STATIC;
1554 }
1555 else if(ssType == 2)
1556 {
1557 halbtc8192e1ant_Updatera_mask(pBtCoexist, FORCE_EXEC, BTC_RATE_ENABLE, 0xfff00000); // enable 2ss
1558 halbtc8192e1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8);
1559 pBtCoexist->btc_write_1byte(pBtCoexist, 0xc04, 0x33);
1560 pBtCoexist->btc_write_1byte(pBtCoexist, 0xd04, 0x3);
1561 pBtCoexist->btc_write_4byte(pBtCoexist, 0x90c, 0x81121313);
1562 pBtCoexist->btc_write_1byte_bitmask(pBtCoexist, 0xe77, 0x4, 0x0);
1563 pBtCoexist->btc_write_1byte(pBtCoexist, 0xa07, 0x41);
1564 mimoPs=BTC_MIMO_PS_DYNAMIC;
1565 }
1566
1567 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_SEND_MIMO_PS, &mimoPs); // set rx 1ss or 2ss
1568}
1569
1570VOID
1571halbtc8192e1ant_SwitchSsType(
1572 IN PBTC_COEXIST pBtCoexist,
1573 IN BOOLEAN bForceExec,
1574 IN u1Byte newSsType
1575 )
1576{
1577 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], %s Switch SS Type = %d\n",
1578 (bForceExec? "force to":""), newSsType));
1579 pCoexDm->curSsType = newSsType;
1580
1581 if(!bForceExec)
1582 {
1583 if(pCoexDm->preSsType == pCoexDm->curSsType)
1584 return;
1585 }
1586 halbtc8192e1ant_SetSwitchSsType(pBtCoexist, pCoexDm->curSsType);
1587
1588 pCoexDm->preSsType = pCoexDm->curSsType;
1589}
1590
1591VOID
1592halbtc8192e1ant_CoexAllOff(
1593 IN PBTC_COEXIST pBtCoexist
1594 )
1595{
1596 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
1597
1598 // sw all off
1599 halbtc8192e1ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE);
1600 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
1601
1602
1603 // hw all off
1604 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0);
1605}
1606
1607BOOLEAN
1608halbtc8192e1ant_IsCommonAction(
1609 IN PBTC_COEXIST pBtCoexist
1610 )
1611{
1612 BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE;
1613
1614 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
1615 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
1616
1617 if(!bWifiConnected &&
1618 BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)
1619 {
1620 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"));
1621 halbtc8192e1ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE);
1622 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
1623
1624 bCommon = true;
1625 }
1626 else if(bWifiConnected &&
1627 (BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) )
1628 {
1629 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi connected + BT non connected-idle!!\n"));
1630 halbtc8192e1ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE);
1631 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
1632
1633 bCommon = true;
1634 }
1635 else if(!bWifiConnected &&
1636 (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) )
1637 {
1638 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"));
1639 halbtc8192e1ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE);
1640 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
1641
1642 bCommon = true;
1643 }
1644 else if(bWifiConnected &&
1645 (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) )
1646 {
1647 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi connected + BT connected-idle!!\n"));
1648 halbtc8192e1ant_SwMechanism1(pBtCoexist,true,true,true,true);
1649 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
1650
1651 bCommon = true;
1652 }
1653 else if(!bWifiConnected &&
1654 (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus) )
1655 {
1656 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi non connected-idle + BT Busy!!\n"));
1657 halbtc8192e1ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE);
1658 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
1659
1660 bCommon = true;
1661 }
1662 else
1663 {
1664 halbtc8192e1ant_SwMechanism1(pBtCoexist,true,true,true,true);
1665
1666 bCommon = FALSE;
1667 }
1668
1669 return bCommon;
1670}
1671
1672
1673VOID
1674halbtc8192e1ant_TdmaDurationAdjustForAcl(
1675 IN PBTC_COEXIST pBtCoexist,
1676 IN u1Byte wifiStatus
1677 )
1678{
1679 static s4Byte up,dn,m,n,WaitCount;
1680 s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration
1681 u1Byte retryCount=0, btInfoExt;
1682
1683 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], TdmaDurationAdjustForAcl()\n"));
1684
1685 if( (BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == wifiStatus) ||
1686 (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifiStatus) ||
1687 (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == wifiStatus) )
1688 {
1689 if( pCoexDm->curPsTdma != 1 &&
1690 pCoexDm->curPsTdma != 2 &&
1691 pCoexDm->curPsTdma != 3 &&
1692 pCoexDm->curPsTdma != 9 )
1693 {
1694 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
1695 pCoexDm->psTdmaDuAdjType = 9;
1696
1697 up = 0;
1698 dn = 0;
1699 m = 1;
1700 n= 3;
1701 result = 0;
1702 WaitCount = 0;
1703 }
1704 return;
1705 }
1706
1707 if(!pCoexDm->bAutoTdmaAdjust)
1708 {
1709 pCoexDm->bAutoTdmaAdjust = true;
1710 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], first run TdmaDurationAdjust()!!\n"));
1711
1712 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
1713 pCoexDm->psTdmaDuAdjType = 2;
1714 //============
1715 up = 0;
1716 dn = 0;
1717 m = 1;
1718 n= 3;
1719 result = 0;
1720 WaitCount = 0;
1721 }
1722 else
1723 {
1724 //accquire the BT TRx retry count from BT_Info byte2
1725 retryCount = pCoexSta->btRetryCnt;
1726 btInfoExt = pCoexSta->btInfoExt;
1727 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], retryCount = %d\n", retryCount));
1728 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n",
1729 up, dn, m, n, WaitCount));
1730 result = 0;
1731 WaitCount++;
1732
1733 if(retryCount == 0) // no retry in the last 2-second duration
1734 {
1735 up++;
1736 dn--;
1737
1738 if (dn <= 0)
1739 dn = 0;
1740
1741 if(up >= n) // if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration
1742 {
1743 WaitCount = 0;
1744 n = 3;
1745 up = 0;
1746 dn = 0;
1747 result = 1;
1748 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], Increase wifi duration!!\n"));
1749 }
1750 }
1751 else if (retryCount <= 3) // <=3 retry in the last 2-second duration
1752 {
1753 up--;
1754 dn++;
1755
1756 if (up <= 0)
1757 up = 0;
1758
1759 if (dn == 2) // if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration
1760 {
1761 if (WaitCount <= 2)
1762 m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^
1763 else
1764 m = 1;
1765
1766 if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
1767 m = 20;
1768
1769 n = 3*m;
1770 up = 0;
1771 dn = 0;
1772 WaitCount = 0;
1773 result = -1;
1774 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n"));
1775 }
1776 }
1777 else //retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration
1778 {
1779 if (WaitCount == 1)
1780 m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^
1781 else
1782 m = 1;
1783
1784 if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
1785 m = 20;
1786
1787 n = 3*m;
1788 up = 0;
1789 dn = 0;
1790 WaitCount = 0;
1791 result = -1;
1792 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n"));
1793 }
1794
1795 if(result == -1)
1796 {
1797 if( (BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(btInfoExt)) &&
1798 ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) )
1799 {
1800 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
1801 pCoexDm->psTdmaDuAdjType = 9;
1802 }
1803 else if(pCoexDm->curPsTdma == 1)
1804 {
1805 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
1806 pCoexDm->psTdmaDuAdjType = 2;
1807 }
1808 else if(pCoexDm->curPsTdma == 2)
1809 {
1810 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
1811 pCoexDm->psTdmaDuAdjType = 9;
1812 }
1813 else if(pCoexDm->curPsTdma == 9)
1814 {
1815 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
1816 pCoexDm->psTdmaDuAdjType = 11;
1817 }
1818 }
1819 else if(result == 1)
1820 {
1821 if( (BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(btInfoExt)) &&
1822 ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) )
1823 {
1824 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
1825 pCoexDm->psTdmaDuAdjType = 9;
1826 }
1827 else if(pCoexDm->curPsTdma == 11)
1828 {
1829 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
1830 pCoexDm->psTdmaDuAdjType = 9;
1831 }
1832 else if(pCoexDm->curPsTdma == 9)
1833 {
1834 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
1835 pCoexDm->psTdmaDuAdjType = 2;
1836 }
1837 else if(pCoexDm->curPsTdma == 2)
1838 {
1839 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 1);
1840 pCoexDm->psTdmaDuAdjType = 1;
1841 }
1842 }
1843
1844 if( pCoexDm->curPsTdma != 1 &&
1845 pCoexDm->curPsTdma != 2 &&
1846 pCoexDm->curPsTdma != 9 &&
1847 pCoexDm->curPsTdma != 11 )
1848 {
1849 // recover to previous adjust type
1850 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, pCoexDm->psTdmaDuAdjType);
1851 }
1852 }
1853}
1854
1855u1Byte
1856halbtc8192e1ant_PsTdmaTypeByWifiRssi(
1857 IN s4Byte wifiRssi,
1858 IN s4Byte preWifiRssi,
1859 IN u1Byte wifiRssiThresh
1860 )
1861{
1862 u1Byte psTdmaType=0;
1863
1864 if(wifiRssi > preWifiRssi)
1865 {
1866 if(wifiRssi > (wifiRssiThresh+5))
1867 {
1868 psTdmaType = 26;
1869 }
1870 else
1871 {
1872 psTdmaType = 25;
1873 }
1874 }
1875 else
1876 {
1877 if(wifiRssi > wifiRssiThresh)
1878 {
1879 psTdmaType = 26;
1880 }
1881 else
1882 {
1883 psTdmaType = 25;
1884 }
1885 }
1886
1887 return psTdmaType;
1888}
1889
1890VOID
1891halbtc8192e1ant_PsTdmaCheckForPowerSaveState(
1892 IN PBTC_COEXIST pBtCoexist,
1893 IN BOOLEAN bNewPsState
1894 )
1895{
1896 u1Byte lpsMode=0x0;
1897
1898 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode);
1899
1900 if(lpsMode) // already under LPS state
1901 {
1902 if(bNewPsState)
1903 {
1904 // keep state under LPS, do nothing.
1905 }
1906 else
1907 {
1908 // will leave LPS state, turn off psTdma first
1909 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1910 }
1911 }
1912 else // NO PS state
1913 {
1914 if(bNewPsState)
1915 {
1916 // will enter LPS state, turn off psTdma first
1917 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1918 }
1919 else
1920 {
1921 // keep state under NO PS state, do nothing.
1922 }
1923 }
1924}
1925
1926VOID
1927halbtc8192e1ant_PowerSaveState(
1928 IN PBTC_COEXIST pBtCoexist,
1929 IN u1Byte psType,
1930 IN u1Byte lpsVal,
1931 IN u1Byte rpwmVal
1932 )
1933{
1934 BOOLEAN bLowPwrDisable=FALSE;
1935
1936 switch(psType)
1937 {
1938 case BTC_PS_WIFI_NATIVE:
1939 // recover to original 32k low power setting
1940 bLowPwrDisable = FALSE;
1941 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable);
1942 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL);
1943 break;
1944 case BTC_PS_LPS_ON:
1945 halbtc8192e1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, true);
1946 halbtc8192e1ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal);
1947 // when coex force to enter LPS, do not enter 32k low power.
1948 bLowPwrDisable = true;
1949 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable);
1950 // power save must executed before psTdma.
1951 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL);
1952 break;
1953 case BTC_PS_LPS_OFF:
1954 halbtc8192e1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE);
1955 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
1956 break;
1957 default:
1958 break;
1959 }
1960}
1961
1962
1963VOID
1964halbtc8192e1ant_ActionWifiOnly(
1965 IN PBTC_COEXIST pBtCoexist
1966 )
1967{
1968 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0);
1969 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
1970}
1971
1972VOID
1973halbtc8192e1ant_MonitorBtEnableDisable(
1974 IN PBTC_COEXIST pBtCoexist
1975 )
1976{
1977 static BOOLEAN bPreBtDisabled=FALSE;
1978 static u4Byte btDisableCnt=0;
1979 BOOLEAN bBtActive=true, bBtDisabled=FALSE;
1980
1981 // This function check if bt is disabled
1982
1983 if( pCoexSta->highPriorityTx == 0 &&
1984 pCoexSta->highPriorityRx == 0 &&
1985 pCoexSta->lowPriorityTx == 0 &&
1986 pCoexSta->lowPriorityRx == 0)
1987 {
1988 bBtActive = FALSE;
1989 }
1990 if( pCoexSta->highPriorityTx == 0xffff &&
1991 pCoexSta->highPriorityRx == 0xffff &&
1992 pCoexSta->lowPriorityTx == 0xffff &&
1993 pCoexSta->lowPriorityRx == 0xffff)
1994 {
1995 bBtActive = FALSE;
1996 }
1997 if(bBtActive)
1998 {
1999 btDisableCnt = 0;
2000 bBtDisabled = FALSE;
2001 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
2002 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is enabled !!\n"));
2003 }
2004 else
2005 {
2006 btDisableCnt++;
2007 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], bt all counters=0, %d times!!\n",
2008 btDisableCnt));
2009 if(btDisableCnt >= 2)
2010 {
2011 bBtDisabled = true;
2012 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
2013 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is disabled !!\n"));
2014 halbtc8192e1ant_ActionWifiOnly(pBtCoexist);
2015 }
2016 }
2017 if(bPreBtDisabled != bBtDisabled)
2018 {
2019 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is from %s to %s!!\n",
2020 (bPreBtDisabled ? "disabled":"enabled"),
2021 (bBtDisabled ? "disabled":"enabled")));
2022 bPreBtDisabled = bBtDisabled;
2023 if(!bBtDisabled)
2024 {
2025 }
2026 else
2027 {
2028 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2029 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL);
2030 }
2031 }
2032}
2033
2034//=============================================
2035//
2036// Software Coex Mechanism start
2037//
2038//=============================================
2039
2040// SCO only or SCO+PAN(HS)
2041VOID
2042halbtc8192e1ant_ActionSco(
2043 IN PBTC_COEXIST pBtCoexist
2044 )
2045{
2046 u1Byte wifiRssiState;
2047 u4Byte wifiBw;
2048
2049 wifiRssiState = halbtc8192e1ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
2050
2051 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2052
2053 if(BTC_WIFI_BW_HT40 == wifiBw)
2054 {
2055 // sw mechanism
2056 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2057 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2058 {
2059 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2060 }
2061 else
2062 {
2063 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,true,FALSE,0x18);
2064 }
2065 }
2066 else
2067 {
2068 // sw mechanism
2069 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2070 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2071 {
2072 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2073 }
2074 else
2075 {
2076 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2077 }
2078 }
2079}
2080
2081
2082VOID
2083halbtc8192e1ant_ActionHid(
2084 IN PBTC_COEXIST pBtCoexist
2085 )
2086{
2087 u1Byte wifiRssiState;
2088 u4Byte wifiBw;
2089
2090 wifiRssiState = halbtc8192e1ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
2091
2092 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2093
2094 if(BTC_WIFI_BW_HT40 == wifiBw)
2095 {
2096 // sw mechanism
2097 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2098 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2099 {
2100 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,FALSE,FALSE,0x18);
2101 }
2102 else
2103 {
2104 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2105 }
2106 }
2107 else
2108 {
2109 // sw mechanism
2110 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2111 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2112 {
2113 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2114 }
2115 else
2116 {
2117 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2118 }
2119 }
2120}
2121
2122//A2DP only / PAN(EDR) only/ A2DP+PAN(HS)
2123VOID
2124halbtc8192e1ant_ActionA2dp(
2125 IN PBTC_COEXIST pBtCoexist
2126 )
2127{
2128 u1Byte wifiRssiState;
2129 u4Byte wifiBw;
2130
2131 wifiRssiState = halbtc8192e1ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
2132
2133 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2134
2135 if(BTC_WIFI_BW_HT40 == wifiBw)
2136 {
2137 // sw mechanism
2138 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2139 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2140 {
2141 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2142 }
2143 else
2144 {
2145 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,true,FALSE,0x18);
2146 }
2147 }
2148 else
2149 {
2150 // sw mechanism
2151 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2152 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2153 {
2154 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2155 }
2156 else
2157 {
2158 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2159 }
2160 }
2161}
2162
2163VOID
2164halbtc8192e1ant_ActionA2dpPanHs(
2165 IN PBTC_COEXIST pBtCoexist
2166 )
2167{
2168 u1Byte wifiRssiState, btInfoExt;
2169 u4Byte wifiBw;
2170
2171 btInfoExt = pCoexSta->btInfoExt;
2172 wifiRssiState = halbtc8192e1ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
2173
2174 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2175
2176 if(BTC_WIFI_BW_HT40 == wifiBw)
2177 {
2178 // sw mechanism
2179 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2180 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2181 {
2182 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2183 }
2184 else
2185 {
2186 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,true,FALSE,0x18);
2187 }
2188 }
2189 else
2190 {
2191 // sw mechanism
2192 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2193 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2194 {
2195 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2196 }
2197 else
2198 {
2199 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2200 }
2201 }
2202}
2203
2204VOID
2205halbtc8192e1ant_ActionPanEdr(
2206 IN PBTC_COEXIST pBtCoexist
2207 )
2208{
2209 u1Byte wifiRssiState;
2210 u4Byte wifiBw;
2211
2212 wifiRssiState = halbtc8192e1ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
2213
2214 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2215
2216 if(BTC_WIFI_BW_HT40 == wifiBw)
2217 {
2218 // sw mechanism
2219 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2220 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2221 {
2222 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2223 }
2224 else
2225 {
2226 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,true,FALSE,0x18);
2227 }
2228 }
2229 else
2230 {
2231 // sw mechanism
2232 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2233 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2234 {
2235 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2236 }
2237 else
2238 {
2239 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2240 }
2241 }
2242}
2243
2244
2245//PAN(HS) only
2246VOID
2247halbtc8192e1ant_ActionPanHs(
2248 IN PBTC_COEXIST pBtCoexist
2249 )
2250{
2251 u1Byte wifiRssiState;
2252 u4Byte wifiBw;
2253
2254 wifiRssiState = halbtc8192e1ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
2255
2256 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2257
2258 if(BTC_WIFI_BW_HT40 == wifiBw)
2259 {
2260 // sw mechanism
2261 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2262 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2263 {
2264 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2265 }
2266 else
2267 {
2268 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,true,FALSE,0x18);
2269 }
2270 }
2271 else
2272 {
2273 // sw mechanism
2274 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2275 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2276 {
2277 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2278 }
2279 else
2280 {
2281 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2282 }
2283 }
2284}
2285
2286//PAN(EDR)+A2DP
2287VOID
2288halbtc8192e1ant_ActionPanEdrA2dp(
2289 IN PBTC_COEXIST pBtCoexist
2290 )
2291{
2292 u1Byte wifiRssiState, btInfoExt;
2293 u4Byte wifiBw;
2294
2295 btInfoExt = pCoexSta->btInfoExt;
2296 wifiRssiState = halbtc8192e1ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
2297
2298 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2299
2300 if(BTC_WIFI_BW_HT40 == wifiBw)
2301 {
2302 // sw mechanism
2303 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2304 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2305 {
2306 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2307 }
2308 else
2309 {
2310 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,true,FALSE,0x18);
2311 }
2312 }
2313 else
2314 {
2315 // sw mechanism
2316 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2317 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2318 {
2319 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2320 }
2321 else
2322 {
2323 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2324 }
2325 }
2326}
2327
2328VOID
2329halbtc8192e1ant_ActionPanEdrHid(
2330 IN PBTC_COEXIST pBtCoexist
2331 )
2332{
2333 u1Byte wifiRssiState;
2334 u4Byte wifiBw;
2335
2336 wifiRssiState = halbtc8192e1ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
2337
2338 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2339
2340 if(BTC_WIFI_BW_HT40 == wifiBw)
2341 {
2342 // sw mechanism
2343 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2344 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2345 {
2346 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2347 }
2348 else
2349 {
2350 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,true,FALSE,0x18);
2351 }
2352 }
2353 else
2354 {
2355 // sw mechanism
2356 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2357 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2358 {
2359 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2360 }
2361 else
2362 {
2363 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2364 }
2365 }
2366}
2367
2368// HID+A2DP+PAN(EDR)
2369VOID
2370halbtc8192e1ant_ActionHidA2dpPanEdr(
2371 IN PBTC_COEXIST pBtCoexist
2372 )
2373{
2374 u1Byte wifiRssiState, btInfoExt;
2375 u4Byte wifiBw;
2376
2377 btInfoExt = pCoexSta->btInfoExt;
2378 wifiRssiState = halbtc8192e1ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
2379
2380 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2381
2382 if(BTC_WIFI_BW_HT40 == wifiBw)
2383 {
2384 // sw mechanism
2385 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2386 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2387 {
2388 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2389 }
2390 else
2391 {
2392 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,true,FALSE,0x18);
2393 }
2394 }
2395 else
2396 {
2397 // sw mechanism
2398 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2399 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2400 {
2401 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2402 }
2403 else
2404 {
2405 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2406 }
2407 }
2408}
2409
2410VOID
2411halbtc8192e1ant_ActionHidA2dp(
2412 IN PBTC_COEXIST pBtCoexist
2413 )
2414{
2415 u1Byte wifiRssiState, btInfoExt;
2416 u4Byte wifiBw;
2417
2418 btInfoExt = pCoexSta->btInfoExt;
2419 wifiRssiState = halbtc8192e1ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0);
2420
2421 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2422
2423 if(BTC_WIFI_BW_HT40 == wifiBw)
2424 {
2425 // sw mechanism
2426 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2427 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2428 {
2429 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2430 }
2431 else
2432 {
2433 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,true,FALSE,0x18);
2434 }
2435 }
2436 else
2437 {
2438 // sw mechanism
2439 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2440 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2441 {
2442 halbtc8192e1ant_SwMechanism2(pBtCoexist,true,true,FALSE,0x18);
2443 }
2444 else
2445 {
2446 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2447 }
2448 }
2449}
2450
2451//=============================================
2452//
2453// Non-Software Coex Mechanism start
2454//
2455//=============================================
2456VOID
2457halbtc8192e1ant_ActionBtInquiry(
2458 IN PBTC_COEXIST pBtCoexist
2459 )
2460{
2461 PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->bt_link_info;
2462 BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE;
2463
2464 // Note:
2465 // Do not do DacSwing here, use original setting.
2466
2467 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
2468
2469 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
2470 if(bBtHsOn)
2471 return;
2472
2473 if(!bWifiConnected)
2474 {
2475 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
2476
2477 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2478
2479 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
2480 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0);
2481 }
2482 else if( (pBtLinkInfo->bScoExist) ||
2483 (pBtLinkInfo->bHidOnly) )
2484 {
2485 // SCO/HID-only busy
2486 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
2487
2488 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2489
2490 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 32);
2491 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1);
2492 }
2493 else
2494 {
2495 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x0);
2496
2497 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2498
2499 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 30);
2500 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0);
2501 }
2502}
2503
2504VOID
2505halbtc8192e1ant_ActionBtScoHidOnlyBusy(
2506 IN PBTC_COEXIST pBtCoexist,
2507 IN u1Byte wifiStatus
2508 )
2509{
2510 PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->bt_link_info;
2511 u1Byte btRssiState=BTC_RSSI_STATE_HIGH;
2512
2513 if(BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == wifiStatus)
2514 {
2515 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2516 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2517
2518 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
2519 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0);
2520 }
2521 else
2522 {
2523 if(pBtLinkInfo->bHidOnly)
2524 {
2525 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2526 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2527
2528 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
2529 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2);
2530 }
2531 else
2532 {
2533 // dec bt power for diff level
2534 btRssiState = halbtc8192e1ant_BtRssiState(3, 34, 42);
2535 if( (btRssiState == BTC_RSSI_STATE_LOW) ||
2536 (btRssiState == BTC_RSSI_STATE_STAY_LOW) )
2537 {
2538 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2539 }
2540 else if( (btRssiState == BTC_RSSI_STATE_MEDIUM) ||
2541 (btRssiState == BTC_RSSI_STATE_STAY_MEDIUM) )
2542 {
2543 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2);
2544 }
2545 else if( (btRssiState == BTC_RSSI_STATE_HIGH) ||
2546 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2547 {
2548 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 6);
2549 }
2550
2551 // sw dacSwing
2552 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, true, 0xc);
2553
2554 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2555 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7);
2556 }
2557 }
2558}
2559
2560VOID
2561halbtc8192e1ant_ActionHs(
2562 IN PBTC_COEXIST pBtCoexist
2563 )
2564{
2565 PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->bt_link_info;
2566
2567 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action for HS!!!\n"));
2568
2569 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
2570
2571 if(BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)
2572 {
2573 // error, should not be here
2574 pCoexDm->errorCondition = 1;
2575 }
2576 else if(BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)
2577 {
2578 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2579 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, true, 6);
2580
2581 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 10);
2582 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0);
2583 }
2584 else if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus &&
2585 !pBtCoexist->bt_link_info.bHidOnly)
2586 {
2587 if(pCoexDm->curSsType == 1)
2588 {
2589 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2590 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, true, 6);
2591 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 10);
2592 //halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 38);
2593 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0);
2594 }
2595 }
2596 else
2597 {
2598 halbtc8192e1ant_ActionBtScoHidOnlyBusy(pBtCoexist,
2599 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY);
2600 }
2601}
2602
2603VOID
2604halbtc8192e1ant_ActionWifiConnectedBtAclBusy(
2605 IN PBTC_COEXIST pBtCoexist,
2606 IN u1Byte wifiStatus
2607 )
2608{
2609 PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->bt_link_info;
2610
2611 if(pBtLinkInfo->bHidOnly)
2612 {
2613 halbtc8192e1ant_ActionBtScoHidOnlyBusy(pBtCoexist, wifiStatus);
2614 pCoexDm->bAutoTdmaAdjust = FALSE;
2615 return;
2616 }
2617
2618 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2619 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2620
2621 if( (pBtLinkInfo->bA2dpOnly) ||
2622 (pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist) )
2623 {
2624 halbtc8192e1ant_TdmaDurationAdjustForAcl(pBtCoexist, wifiStatus);
2625 }
2626 else if( (pBtLinkInfo->bPanOnly) ||
2627 (pBtLinkInfo->bHidExist&&pBtLinkInfo->bPanExist) )
2628 {
2629 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2630 pCoexDm->bAutoTdmaAdjust = FALSE;
2631 }
2632 else
2633 {
2634 if( (BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == wifiStatus) ||
2635 (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifiStatus) ||
2636 (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == wifiStatus) )
2637 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
2638 else
2639 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2640 pCoexDm->bAutoTdmaAdjust = FALSE;
2641 }
2642
2643 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1);
2644}
2645
2646
2647VOID
2648halbtc8192e1ant_ActionWifiNotConnected(
2649 IN PBTC_COEXIST pBtCoexist
2650 )
2651{
2652 // power save state
2653 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
2654
2655 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2656 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2657
2658 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
2659 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0);
2660}
2661
2662VOID
2663halbtc8192e1ant_ActionWifiNotConnectedAssoAuthScan(
2664 IN PBTC_COEXIST pBtCoexist
2665 )
2666{
2667 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
2668
2669 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2670 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2671
2672 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
2673 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0);
2674}
2675
2676VOID
2677halbtc8192e1ant_ActionWifiConnectedScan(
2678 IN PBTC_COEXIST pBtCoexist
2679 )
2680{
2681 // power save state
2682 if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus && !pBtCoexist->bt_link_info.bHidOnly)
2683 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x0);
2684 else
2685 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
2686
2687 if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus)
2688 {
2689 halbtc8192e1ant_ActionWifiConnectedBtAclBusy(pBtCoexist,
2690 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN);
2691 }
2692 else if( (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) ||
2693 (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) )
2694 {
2695 halbtc8192e1ant_ActionBtScoHidOnlyBusy(pBtCoexist,
2696 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN);
2697 }
2698 else
2699 {
2700 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2701 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2702 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
2703 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2);
2704 }
2705}
2706
2707
2708VOID
2709halbtc8192e1ant_ActionWifiConnectedSpecialPacket(
2710 IN PBTC_COEXIST pBtCoexist
2711 )
2712{
2713 // power save state
2714 if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus && !pBtCoexist->bt_link_info.bHidOnly)
2715 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x0);
2716 else
2717 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
2718
2719 if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus)
2720 {
2721 halbtc8192e1ant_ActionWifiConnectedBtAclBusy(pBtCoexist,
2722 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT);
2723 }
2724 else
2725 {
2726 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2727 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2728 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
2729 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2);
2730 }
2731}
2732
2733VOID
2734halbtc8192e1ant_ActionWifiConnected(
2735 IN PBTC_COEXIST pBtCoexist
2736 )
2737{
2738 BOOLEAN bWifiConnected=FALSE, bWifiBusy=FALSE;
2739 BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE;
2740 BOOLEAN bUnder4way=FALSE;
2741 u4Byte wifiBw;
2742
2743 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], CoexForWifiConnect()===>\n"));
2744
2745 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
2746 if(!bWifiConnected)
2747 {
2748 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], CoexForWifiConnect(), return for wifi not connected<===\n"));
2749 return;
2750 }
2751
2752 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way);
2753 if(bUnder4way)
2754 {
2755 halbtc8192e1ant_ActionWifiConnectedSpecialPacket(pBtCoexist);
2756 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n"));
2757 return;
2758 }
2759
2760 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
2761 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
2762 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
2763 if(bScan || bLink || bRoam)
2764 {
2765 halbtc8192e1ant_ActionWifiConnectedScan(pBtCoexist);
2766 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n"));
2767 return;
2768 }
2769
2770 // power save state
2771 if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus && !pBtCoexist->bt_link_info.bHidOnly)
2772 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x0);
2773 else
2774 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
2775
2776 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
2777 if(!bWifiBusy)
2778 {
2779 if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus)
2780 {
2781 halbtc8192e1ant_ActionWifiConnectedBtAclBusy(pBtCoexist,
2782 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE);
2783 }
2784 else if( (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) ||
2785 (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) )
2786 {
2787 halbtc8192e1ant_ActionBtScoHidOnlyBusy(pBtCoexist,
2788 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE);
2789 }
2790 else
2791 {
2792 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2793 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2794 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
2795 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2);
2796 }
2797 }
2798 else
2799 {
2800 if(BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)
2801 {
2802 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2803 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2804 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 5);
2805 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2);
2806 }
2807 else if(BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)
2808 {
2809 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2810 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2811 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 5);
2812 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2);
2813 }
2814 else if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus)
2815 {
2816 halbtc8192e1ant_ActionWifiConnectedBtAclBusy(pBtCoexist,
2817 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY);
2818 }
2819 else if( (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) ||
2820 (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) )
2821 {
2822 halbtc8192e1ant_ActionBtScoHidOnlyBusy(pBtCoexist,
2823 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY);
2824 }
2825 else
2826 {
2827 halbtc8192e1ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0);
2828 halbtc8192e1ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2829 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8);
2830 halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2);
2831 }
2832 }
2833}
2834
2835VOID
2836halbtc8192e1ant_RunSwCoexistMechanism(
2837 IN PBTC_COEXIST pBtCoexist
2838 )
2839{
2840 BOOLEAN bWifiUnder5G=FALSE, bWifiBusy=FALSE, bWifiConnected=FALSE;
2841 u1Byte btInfoOriginal=0, btRetryCnt=0;
2842 u1Byte algorithm=0;
2843
2844 return;
2845
2846 algorithm = halbtc8192e1ant_ActionAlgorithm(pBtCoexist);
2847 pCoexDm->curAlgorithm = algorithm;
2848
2849 if(halbtc8192e1ant_IsCommonAction(pBtCoexist))
2850 {
2851 }
2852 else
2853 {
2854 switch(pCoexDm->curAlgorithm)
2855 {
2856 case BT_8192E_1ANT_COEX_ALGO_SCO:
2857 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = SCO.\n"));
2858 halbtc8192e1ant_ActionSco(pBtCoexist);
2859 break;
2860 case BT_8192E_1ANT_COEX_ALGO_HID:
2861 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = HID.\n"));
2862 halbtc8192e1ant_ActionHid(pBtCoexist);
2863 break;
2864 case BT_8192E_1ANT_COEX_ALGO_A2DP:
2865 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = A2DP.\n"));
2866 halbtc8192e1ant_ActionA2dp(pBtCoexist);
2867 break;
2868 case BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS:
2869 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = A2DP+PAN(HS).\n"));
2870 halbtc8192e1ant_ActionA2dpPanHs(pBtCoexist);
2871 break;
2872 case BT_8192E_1ANT_COEX_ALGO_PANEDR:
2873 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = PAN(EDR).\n"));
2874 halbtc8192e1ant_ActionPanEdr(pBtCoexist);
2875 break;
2876 case BT_8192E_1ANT_COEX_ALGO_PANHS:
2877 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = HS mode.\n"));
2878 halbtc8192e1ant_ActionPanHs(pBtCoexist);
2879 break;
2880 case BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP:
2881 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = PAN+A2DP.\n"));
2882 halbtc8192e1ant_ActionPanEdrA2dp(pBtCoexist);
2883 break;
2884 case BT_8192E_1ANT_COEX_ALGO_PANEDR_HID:
2885 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = PAN(EDR)+HID.\n"));
2886 halbtc8192e1ant_ActionPanEdrHid(pBtCoexist);
2887 break;
2888 case BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
2889 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = HID+A2DP+PAN.\n"));
2890 halbtc8192e1ant_ActionHidA2dpPanEdr(pBtCoexist);
2891 break;
2892 case BT_8192E_1ANT_COEX_ALGO_HID_A2DP:
2893 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = HID+A2DP.\n"));
2894 halbtc8192e1ant_ActionHidA2dp(pBtCoexist);
2895 break;
2896 default:
2897 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action algorithm = coexist All Off!!\n"));
2898 halbtc8192e1ant_CoexAllOff(pBtCoexist);
2899 break;
2900 }
2901 pCoexDm->preAlgorithm = pCoexDm->curAlgorithm;
2902 }
2903}
2904
2905VOID
2906halbtc8192e1ant_RunCoexistMechanism(
2907 IN PBTC_COEXIST pBtCoexist
2908 )
2909{
2910 PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->bt_link_info;
2911 BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE;
2912
2913 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], RunCoexistMechanism()===>\n"));
2914
2915 if(pBtCoexist->manual_control)
2916 {
2917 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"));
2918 return;
2919 }
2920
2921 if(pBtCoexist->bStopCoexDm)
2922 {
2923 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"));
2924 return;
2925 }
2926
2927 if(pCoexSta->bUnderIps)
2928 {
2929 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], wifi is under IPS !!!\n"));
2930 return;
2931 }
2932
2933 halbtc8192e1ant_RunSwCoexistMechanism(pBtCoexist);
2934
2935 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
2936 if(pCoexSta->bC2hBtInquiryPage)
2937 {
2938 halbtc8192e1ant_ActionBtInquiry(pBtCoexist);
2939 return;
2940 }
2941
2942 // 1ss or 2ss
2943 if(pBtLinkInfo->bScoExist)
2944 {
2945 halbtc8192e1ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 1);
2946 }
2947 else if(bBtHsOn)
2948 {
2949 if(pBtLinkInfo->bHidOnly)
2950 halbtc8192e1ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 2);
2951 else
2952 halbtc8192e1ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 1);
2953 }
2954 else
2955 halbtc8192e1ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 2);
2956
2957 if(bBtHsOn)
2958 {
2959 halbtc8192e1ant_ActionHs(pBtCoexist);
2960 return;
2961 }
2962
2963 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
2964 if(!bWifiConnected)
2965 {
2966 BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE;
2967
2968 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], wifi is non connected-idle !!!\n"));
2969
2970 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
2971 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
2972 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
2973
2974 if(bScan || bLink || bRoam)
2975 halbtc8192e1ant_ActionWifiNotConnectedAssoAuthScan(pBtCoexist);
2976 else
2977 halbtc8192e1ant_ActionWifiNotConnected(pBtCoexist);
2978 }
2979 else
2980 {
2981 halbtc8192e1ant_ActionWifiConnected(pBtCoexist);
2982 }
2983}
2984
2985VOID
2986halbtc8192e1ant_InitCoexDm(
2987 IN PBTC_COEXIST pBtCoexist
2988 )
2989{
2990 // force to reset coex mechanism
2991 halbtc8192e1ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6);
2992 halbtc8192e1ant_DecBtPwr(pBtCoexist, FORCE_EXEC, 0);
2993
2994 // sw all off
2995 halbtc8192e1ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE);
2996 halbtc8192e1ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18);
2997
2998 halbtc8192e1ant_SwitchSsType(pBtCoexist, FORCE_EXEC, 2);
2999
3000 halbtc8192e1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8);
3001 halbtc8192e1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0);
3002}
3003
3004//============================================================
3005// work around function start with wa_halbtc8192e1ant_
3006//============================================================
3007//============================================================
3008// extern function start with EXhalbtc8192e1ant_
3009//============================================================
3010VOID
3011EXhalbtc8192e1ant_InitHwConfig(
3012 IN PBTC_COEXIST pBtCoexist
3013 )
3014{
3015 u4Byte u4Tmp=0;
3016 u16 u2Tmp=0;
3017 u1Byte u1Tmp=0;
3018
3019 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], 1Ant Init HW Config!!\n"));
3020
3021 // backup rf 0x1e value
3022 pCoexDm->btRf0x1eBackup =
3023 pBtCoexist->btc_get_rf_reg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff);
3024
3025 // antenna sw ctrl to bt
3026 pBtCoexist->btc_write_1byte(pBtCoexist, 0x4f, 0x6);
3027 pBtCoexist->btc_write_1byte(pBtCoexist, 0x944, 0x24);
3028 pBtCoexist->btc_write_4byte(pBtCoexist, 0x930, 0x700700);
3029 pBtCoexist->btc_write_1byte(pBtCoexist, 0x92c, 0x20);
3030 if(pBtCoexist->chipInterface == BTC_INTF_USB)
3031 pBtCoexist->btc_write_4byte(pBtCoexist, 0x64, 0x30430004);
3032 else
3033 pBtCoexist->btc_write_4byte(pBtCoexist, 0x64, 0x30030004);
3034
3035 halbtc8192e1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0);
3036
3037 // antenna switch control parameter
3038 pBtCoexist->btc_write_4byte(pBtCoexist, 0x858, 0x55555555);
3039
3040 // coex parameters
3041 pBtCoexist->btc_write_1byte(pBtCoexist, 0x778, 0x1);
3042 // 0x790[5:0]=0x5
3043 u1Tmp = pBtCoexist->btc_read_1byte(pBtCoexist, 0x790);
3044 u1Tmp &= 0xc0;
3045 u1Tmp |= 0x5;
3046 pBtCoexist->btc_write_1byte(pBtCoexist, 0x790, u1Tmp);
3047
3048 // enable counter statistics
3049 pBtCoexist->btc_write_1byte(pBtCoexist, 0x76e, 0x4);
3050
3051 // enable PTA
3052 pBtCoexist->btc_write_1byte(pBtCoexist, 0x40, 0x20);
3053 // enable mailbox interface
3054 u2Tmp = pBtCoexist->btc_read_2byte(pBtCoexist, 0x40);
3055 u2Tmp |= BIT9;
3056 pBtCoexist->btc_write_2byte(pBtCoexist, 0x40, u2Tmp);
3057
3058 // enable PTA I2C mailbox
3059 u1Tmp = pBtCoexist->btc_read_1byte(pBtCoexist, 0x101);
3060 u1Tmp |= BIT4;
3061 pBtCoexist->btc_write_1byte(pBtCoexist, 0x101, u1Tmp);
3062
3063 // enable bt clock when wifi is disabled.
3064 u1Tmp = pBtCoexist->btc_read_1byte(pBtCoexist, 0x93);
3065 u1Tmp |= BIT0;
3066 pBtCoexist->btc_write_1byte(pBtCoexist, 0x93, u1Tmp);
3067 // enable bt clock when suspend.
3068 u1Tmp = pBtCoexist->btc_read_1byte(pBtCoexist, 0x7);
3069 u1Tmp |= BIT0;
3070 pBtCoexist->btc_write_1byte(pBtCoexist, 0x7, u1Tmp);
3071}
3072
3073VOID
3074EXhalbtc8192e1ant_InitCoexDm(
3075 IN PBTC_COEXIST pBtCoexist
3076 )
3077{
3078 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], Coex Mechanism Init!!\n"));
3079
3080 pBtCoexist->bStopCoexDm = FALSE;
3081
3082 halbtc8192e1ant_InitCoexDm(pBtCoexist);
3083}
3084
3085VOID
3086EXhalbtc8192e1ant_DisplayCoexInfo(
3087 IN PBTC_COEXIST pBtCoexist
3088 )
3089{
3090 struct btc_board_info * pBoardInfo=&pBtCoexist->board_info;
3091 PBTC_STACK_INFO pStackInfo=&pBtCoexist->stack_info;
3092 PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->bt_link_info;
3093 pu1Byte cliBuf=pBtCoexist->cli_buf;
3094 u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0;
3095 u4Byte u4Tmp[4];
3096 BOOLEAN bRoam=FALSE, bScan=FALSE, bLink=FALSE, bWifiUnder5G=FALSE;
3097 BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
3098 s4Byte wifiRssi=0, btHsRssi=0;
3099 u4Byte wifiBw, wifiTrafficDir;
3100 u1Byte wifiDot11Chnl, wifiHsChnl;
3101 u4Byte fwVer=0, btPatchVer=0;
3102
3103 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============");
3104 CL_PRINTF(cliBuf);
3105
3106 if(pBtCoexist->manual_control)
3107 {
3108 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============");
3109 CL_PRINTF(cliBuf);
3110 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ==========================================");
3111 CL_PRINTF(cliBuf);
3112 }
3113 if(pBtCoexist->bStopCoexDm)
3114 {
3115 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Coex is STOPPED]============");
3116 CL_PRINTF(cliBuf);
3117 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ==========================================");
3118 CL_PRINTF(cliBuf);
3119 }
3120
3121 if(!pBoardInfo->bt_exist)
3122 {
3123 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n BT not exists !!!");
3124 CL_PRINTF(cliBuf);
3125 return;
3126 }
3127
3128 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \
3129 pBoardInfo->pg_ant_num, pBoardInfo->btdm_ant_num);
3130 CL_PRINTF(cliBuf);
3131
3132 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \
3133 ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion);
3134 CL_PRINTF(cliBuf);
3135
3136 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer);
3137 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer);
3138 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \
3139 GLCoexVerDate8192e1Ant, GLCoexVer8192e1Ant, fwVer, btPatchVer, btPatchVer);
3140 CL_PRINTF(cliBuf);
3141
3142 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
3143 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiDot11Chnl);
3144 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifiHsChnl);
3145 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d(%d)", "Dot11 channel / HsChnl(HsMode)", \
3146 wifiDot11Chnl, wifiHsChnl, bBtHsOn);
3147 CL_PRINTF(cliBuf);
3148
3149 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "H2C Wifi inform bt chnl Info", \
3150 pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1],
3151 pCoexDm->wifiChnlInfo[2]);
3152 CL_PRINTF(cliBuf);
3153
3154 pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
3155 pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_HS_RSSI, &btHsRssi);
3156 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "Wifi rssi/ HS rssi", \
3157 wifiRssi, btHsRssi);
3158 CL_PRINTF(cliBuf);
3159
3160 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
3161 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
3162 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
3163 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Wifi bLink/ bRoam/ bScan", \
3164 bLink, bRoam, bScan);
3165 CL_PRINTF(cliBuf);
3166
3167 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G);
3168 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
3169 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
3170 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
3171 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s ", "Wifi status", \
3172 (bWifiUnder5G? "5G":"2.4G"),
3173 ((BTC_WIFI_BW_LEGACY==wifiBw)? "Legacy": (((BTC_WIFI_BW_HT40==wifiBw)? "HT40":"HT20"))),
3174 ((!bWifiBusy)? "idle": ((BTC_WIFI_TRAFFIC_TX==wifiTrafficDir)? "uplink":"downlink")));
3175 CL_PRINTF(cliBuf);
3176 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \
3177 ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle":
3178 ( (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))),
3179 pCoexSta->btRssi, pCoexSta->btRetryCnt);
3180 CL_PRINTF(cliBuf);
3181
3182 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \
3183 pBtLinkInfo->bScoExist, pBtLinkInfo->bHidExist, pBtLinkInfo->bPanExist, pBtLinkInfo->bA2dpExist);
3184 CL_PRINTF(cliBuf);
3185 pBtCoexist->btc_disp_dbg_msg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO);
3186
3187 btInfoExt = pCoexSta->btInfoExt;
3188 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \
3189 (btInfoExt&BIT0)? "Basic rate":"EDR rate");
3190 CL_PRINTF(cliBuf);
3191
3192 for(i=0; i<BT_INFO_SRC_8192E_1ANT_MAX; i++)
3193 {
3194 if(pCoexSta->btInfoC2hCnt[i])
3195 {
3196 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8192e1Ant[i], \
3197 pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1],
3198 pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3],
3199 pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5],
3200 pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]);
3201 CL_PRINTF(cliBuf);
3202 }
3203 }
3204 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/%s, (0x%x/0x%x)", "PS state, IPS/LPS, (lps/rpwm)", \
3205 ((pCoexSta->bUnderIps? "IPS ON":"IPS OFF")),
3206 ((pCoexSta->bUnderLps? "LPS ON":"LPS OFF")),
3207 pBtCoexist->btInfo.lps1Ant,
3208 pBtCoexist->btInfo.rpwm_1ant);
3209 CL_PRINTF(cliBuf);
3210 pBtCoexist->btc_disp_dbg_msg(pBtCoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD);
3211
3212 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "SS Type", \
3213 pCoexDm->curSsType);
3214 CL_PRINTF(cliBuf);
3215
3216 if(!pBtCoexist->manual_control)
3217 {
3218 // Sw mechanism
3219 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============");
3220 CL_PRINTF(cliBuf);
3221
3222 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d ", "SM1[ShRf/ LpRA/ LimDig/ btLna]", \
3223 pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->limited_dig, pCoexDm->bCurBtLnaConstrain);
3224 CL_PRINTF(cliBuf);
3225 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \
3226 pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl);
3227 CL_PRINTF(cliBuf);
3228
3229 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %d ", "DelBA/ BtCtrlAgg/ AggSize", \
3230 (pBtCoexist->btInfo.reject_agg_pkt? "Yes":"No"), (pBtCoexist->btInfo.b_bt_ctrl_agg_buf_size? "Yes":"No"),
3231 pBtCoexist->btInfo.aggBufSize);
3232 CL_PRINTF(cliBuf);
3233 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask", \
3234 pBtCoexist->btInfo.ra_mask);
3235 CL_PRINTF(cliBuf);
3236
3237 // Fw mechanism
3238 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============");
3239 CL_PRINTF(cliBuf);
3240
3241 psTdmaCase = pCoexDm->curPsTdma;
3242 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", "PS TDMA", \
3243 pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1],
3244 pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3],
3245 pCoexDm->psTdmaPara[4], psTdmaCase, pCoexDm->bAutoTdmaAdjust);
3246 CL_PRINTF(cliBuf);
3247
3248 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)", \
3249 pCoexDm->errorCondition);
3250 CL_PRINTF(cliBuf);
3251
3252 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwrLvl/ IgnWlanAct", \
3253 pCoexDm->curBtDecPwrLvl, pCoexDm->bCurIgnoreWlanAct);
3254 CL_PRINTF(cliBuf);
3255 }
3256
3257 // Hw setting
3258 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============");
3259 CL_PRINTF(cliBuf);
3260
3261 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \
3262 pCoexDm->btRf0x1eBackup);
3263 CL_PRINTF(cliBuf);
3264
3265 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xc04);
3266 u4Tmp[1] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xd04);
3267 u4Tmp[2] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x90c);
3268 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0xc04/ 0xd04/ 0x90c", \
3269 u4Tmp[0], u4Tmp[1], u4Tmp[2]);
3270 CL_PRINTF(cliBuf);
3271
3272 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x778);
3273 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", \
3274 u1Tmp[0]);
3275 CL_PRINTF(cliBuf);
3276
3277 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x92c);
3278 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x930);
3279 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x92c/ 0x930", \
3280 (u1Tmp[0]), u4Tmp[0]);
3281 CL_PRINTF(cliBuf);
3282
3283 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x40);
3284 u1Tmp[1] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x4f);
3285 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x40/ 0x4f", \
3286 u1Tmp[0], u1Tmp[1]);
3287 CL_PRINTF(cliBuf);
3288
3289 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x550);
3290 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x522);
3291 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \
3292 u4Tmp[0], u1Tmp[0]);
3293 CL_PRINTF(cliBuf);
3294
3295 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xc50);
3296 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \
3297 u4Tmp[0]);
3298 CL_PRINTF(cliBuf);
3299
3300 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x6c0);
3301 u4Tmp[1] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x6c4);
3302 u4Tmp[2] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x6c8);
3303 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x6cc);
3304 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \
3305 u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]);
3306 CL_PRINTF(cliBuf);
3307
3308 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(hp rx[31:16]/tx[15:0])", \
3309 pCoexSta->highPriorityRx, pCoexSta->highPriorityTx);
3310 CL_PRINTF(cliBuf);
3311 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \
3312 pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx);
3313 CL_PRINTF(cliBuf);
3314#if(BT_AUTO_REPORT_ONLY_8192E_1ANT == 1)
3315 halbtc8192e1ant_MonitorBtCtr(pBtCoexist);
3316#endif
3317
3318 pBtCoexist->btc_disp_dbg_msg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS);
3319}
3320
3321
3322VOID
3323EXhalbtc8192e1ant_IpsNotify(
3324 IN PBTC_COEXIST pBtCoexist,
3325 IN u1Byte type
3326 )
3327{
3328 u4Byte u4Tmp=0;
3329
3330 if(pBtCoexist->manual_control || pBtCoexist->bStopCoexDm)
3331 return;
3332
3333 if(BTC_IPS_ENTER == type)
3334 {
3335 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], IPS ENTER notify\n"));
3336 pCoexSta->bUnderIps = true;
3337 halbtc8192e1ant_CoexAllOff(pBtCoexist);
3338 }
3339 else if(BTC_IPS_LEAVE == type)
3340 {
3341 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], IPS LEAVE notify\n"));
3342 pCoexSta->bUnderIps = FALSE;
3343 }
3344}
3345
3346VOID
3347EXhalbtc8192e1ant_LpsNotify(
3348 IN PBTC_COEXIST pBtCoexist,
3349 IN u1Byte type
3350 )
3351{
3352 if(pBtCoexist->manual_control || pBtCoexist->bStopCoexDm)
3353 return;
3354
3355 if(BTC_LPS_ENABLE == type)
3356 {
3357 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], LPS ENABLE notify\n"));
3358 pCoexSta->bUnderLps = true;
3359 }
3360 else if(BTC_LPS_DISABLE == type)
3361 {
3362 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], LPS DISABLE notify\n"));
3363 pCoexSta->bUnderLps = FALSE;
3364 }
3365}
3366
3367VOID
3368EXhalbtc8192e1ant_ScanNotify(
3369 IN PBTC_COEXIST pBtCoexist,
3370 IN u1Byte type
3371 )
3372{
3373 BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE;
3374
3375 if(pBtCoexist->manual_control ||
3376 pBtCoexist->bStopCoexDm ||
3377 pBtCoexist->btInfo.bBtDisabled )
3378 return;
3379
3380 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
3381 if(pCoexSta->bC2hBtInquiryPage)
3382 {
3383 halbtc8192e1ant_ActionBtInquiry(pBtCoexist);
3384 return;
3385 }
3386 else if(bBtHsOn)
3387 {
3388 halbtc8192e1ant_ActionHs(pBtCoexist);
3389 return;
3390 }
3391
3392 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
3393 if(BTC_SCAN_START == type)
3394 {
3395 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], SCAN START notify\n"));
3396 if(!bWifiConnected) // non-connected scan
3397 {
3398 halbtc8192e1ant_ActionWifiNotConnectedAssoAuthScan(pBtCoexist);
3399 }
3400 else // wifi is connected
3401 {
3402 halbtc8192e1ant_ActionWifiConnectedScan(pBtCoexist);
3403 }
3404 }
3405 else if(BTC_SCAN_FINISH == type)
3406 {
3407 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], SCAN FINISH notify\n"));
3408 if(!bWifiConnected) // non-connected scan
3409 {
3410 halbtc8192e1ant_ActionWifiNotConnected(pBtCoexist);
3411 }
3412 else
3413 {
3414 halbtc8192e1ant_ActionWifiConnected(pBtCoexist);
3415 }
3416 }
3417}
3418
3419VOID
3420EXhalbtc8192e1ant_ConnectNotify(
3421 IN PBTC_COEXIST pBtCoexist,
3422 IN u1Byte type
3423 )
3424{
3425 BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE;
3426
3427 if(pBtCoexist->manual_control ||
3428 pBtCoexist->bStopCoexDm ||
3429 pBtCoexist->btInfo.bBtDisabled )
3430 return;
3431
3432 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
3433 if(pCoexSta->bC2hBtInquiryPage)
3434 {
3435 halbtc8192e1ant_ActionBtInquiry(pBtCoexist);
3436 return;
3437 }
3438 else if(bBtHsOn)
3439 {
3440 halbtc8192e1ant_ActionHs(pBtCoexist);
3441 return;
3442 }
3443
3444 if(BTC_ASSOCIATE_START == type)
3445 {
3446 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], CONNECT START notify\n"));
3447 halbtc8192e1ant_ActionWifiNotConnectedAssoAuthScan(pBtCoexist);
3448 }
3449 else if(BTC_ASSOCIATE_FINISH == type)
3450 {
3451 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], CONNECT FINISH notify\n"));
3452
3453 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
3454 if(!bWifiConnected) // non-connected scan
3455 {
3456 halbtc8192e1ant_ActionWifiNotConnected(pBtCoexist);
3457 }
3458 else
3459 {
3460 halbtc8192e1ant_ActionWifiConnected(pBtCoexist);
3461 }
3462 }
3463}
3464
3465VOID
3466EXhalbtc8192e1ant_MediaStatusNotify(
3467 IN PBTC_COEXIST pBtCoexist,
3468 IN u1Byte type
3469 )
3470{
3471 u1Byte H2C_Parameter[3] ={0};
3472 u4Byte wifiBw;
3473 u1Byte wifiCentralChnl;
3474
3475 if(pBtCoexist->manual_control ||
3476 pBtCoexist->bStopCoexDm ||
3477 pBtCoexist->btInfo.bBtDisabled )
3478 return;
3479
3480 if(BTC_MEDIA_CONNECT == type)
3481 {
3482 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], MEDIA connect notify\n"));
3483 }
3484 else
3485 {
3486 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], MEDIA disconnect notify\n"));
3487 }
3488
3489 // only 2.4G we need to inform bt the chnl mask
3490 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl);
3491 if( (BTC_MEDIA_CONNECT == type) &&
3492 (wifiCentralChnl <= 14) )
3493 {
3494 H2C_Parameter[0] = 0x1;
3495 H2C_Parameter[1] = wifiCentralChnl;
3496 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
3497 if(BTC_WIFI_BW_HT40 == wifiBw)
3498 H2C_Parameter[2] = 0x30;
3499 else
3500 H2C_Parameter[2] = 0x20;
3501 }
3502
3503 pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0];
3504 pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1];
3505 pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2];
3506
3507 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], FW write 0x66=0x%x\n",
3508 H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2]));
3509
3510 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x66, 3, H2C_Parameter);
3511}
3512
3513VOID
3514EXhalbtc8192e1ant_SpecialPacketNotify(
3515 IN PBTC_COEXIST pBtCoexist,
3516 IN u1Byte type
3517 )
3518{
3519 BOOLEAN bBtHsOn=FALSE;
3520
3521 if(pBtCoexist->manual_control ||
3522 pBtCoexist->bStopCoexDm ||
3523 pBtCoexist->btInfo.bBtDisabled )
3524 return;
3525
3526 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
3527 if(pCoexSta->bC2hBtInquiryPage)
3528 {
3529 halbtc8192e1ant_ActionBtInquiry(pBtCoexist);
3530 return;
3531 }
3532 else if(bBtHsOn)
3533 {
3534 halbtc8192e1ant_ActionHs(pBtCoexist);
3535 return;
3536 }
3537
3538 if( BTC_PACKET_DHCP == type ||
3539 BTC_PACKET_EAPOL == type )
3540 {
3541 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], special Packet(%d) notify\n", type));
3542 halbtc8192e1ant_ActionWifiConnectedSpecialPacket(pBtCoexist);
3543 }
3544}
3545
3546VOID
3547EXhalbtc8192e1ant_BtInfoNotify(
3548 IN PBTC_COEXIST pBtCoexist,
3549 IN pu1Byte tmpBuf,
3550 IN u1Byte length
3551 )
3552{
3553 PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->bt_link_info;
3554 u1Byte btInfo=0;
3555 u1Byte i, rspSource=0;
3556 static u4Byte setBtPsdMode=0;
3557 BOOLEAN bBtBusy=FALSE, limited_dig=FALSE;
3558 BOOLEAN bWifiConnected=FALSE;
3559 BOOLEAN b_bt_ctrl_agg_buf_size=FALSE;
3560
3561 pCoexSta->bC2hBtInfoReqSent = FALSE;
3562
3563 rspSource = tmpBuf[0]&0xf;
3564 if(rspSource >= BT_INFO_SRC_8192E_1ANT_MAX)
3565 rspSource = BT_INFO_SRC_8192E_1ANT_WIFI_FW;
3566 pCoexSta->btInfoC2hCnt[rspSource]++;
3567
3568 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length));
3569 for(i=0; i<length; i++)
3570 {
3571 pCoexSta->btInfoC2h[rspSource][i] = tmpBuf[i];
3572 if(i == 1)
3573 btInfo = tmpBuf[i];
3574 if(i == length-1)
3575 {
3576 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("0x%02x]\n", tmpBuf[i]));
3577 }
3578 else
3579 {
3580 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("0x%02x, ", tmpBuf[i]));
3581 }
3582 }
3583
3584 if(pBtCoexist->btInfo.bBtDisabled)
3585 {
3586 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), return for BT is disabled <===\n"));
3587 return;
3588 }
3589
3590 if(pBtCoexist->manual_control)
3591 {
3592 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n"));
3593 return;
3594 }
3595 if(pBtCoexist->bStopCoexDm)
3596 {
3597 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), return for Coex STOPPED!!<===\n"));
3598 return;
3599 }
3600
3601 if(BT_INFO_SRC_8192E_1ANT_WIFI_FW != rspSource)
3602 {
3603 pCoexSta->btRetryCnt = // [3:0]
3604 pCoexSta->btInfoC2h[rspSource][2]&0xf;
3605
3606 pCoexSta->btRssi =
3607 pCoexSta->btInfoC2h[rspSource][3]*2+10;
3608
3609 pCoexSta->btInfoExt =
3610 pCoexSta->btInfoC2h[rspSource][4];
3611
3612 // Here we need to resend some wifi info to BT
3613 // because bt is reset and loss of the info.
3614 if( (pCoexSta->btInfoExt & BIT1) )
3615 {
3616 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"));
3617 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
3618 if(bWifiConnected)
3619 {
3620 EXhalbtc8192e1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT);
3621 }
3622 else
3623 {
3624 EXhalbtc8192e1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT);
3625 }
3626
3627 setBtPsdMode = 0;
3628 }
3629
3630 // test-chip bt patch only rsp the status for BT_RSP,
3631 // so temporary we consider the following only under BT_RSP
3632 if(BT_INFO_SRC_8192E_1ANT_BT_RSP == rspSource)
3633 {
3634 if( (pCoexSta->btInfoExt & BIT3) )
3635 {
3636 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"));
3637 halbtc8192e1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE);
3638 }
3639 else
3640 {
3641 // BT already NOT ignore Wlan active, do nothing here.
3642 }
3643#if(BT_AUTO_REPORT_ONLY_8192E_1ANT == 0)
3644 if( (pCoexSta->btInfoExt & BIT4) )
3645 {
3646 // BT auto report already enabled, do nothing
3647 }
3648 else
3649 {
3650 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BT ext info bit4 check, set BT to enable Auto Report!!\n"));
3651 halbtc8192e1ant_BtAutoReport(pBtCoexist, FORCE_EXEC, true);
3652 }
3653#endif
3654 }
3655 }
3656
3657 // check BIT2 first ==> check if bt is under inquiry or page scan
3658 if(btInfo & BT_INFO_8192E_1ANT_B_INQ_PAGE)
3659 pCoexSta->bC2hBtInquiryPage = true;
3660 else
3661 pCoexSta->bC2hBtInquiryPage = FALSE;
3662
3663 // set link exist status
3664 if(!(btInfo&BT_INFO_8192E_1ANT_B_CONNECTION))
3665 {
3666 pCoexSta->bBtLinkExist = FALSE;
3667 pCoexSta->bPanExist = FALSE;
3668 pCoexSta->bA2dpExist = FALSE;
3669 pCoexSta->bHidExist = FALSE;
3670 pCoexSta->bScoExist = FALSE;
3671 }
3672 else // connection exists
3673 {
3674 pCoexSta->bBtLinkExist = true;
3675 if(btInfo & BT_INFO_8192E_1ANT_B_FTP)
3676 pCoexSta->bPanExist = true;
3677 else
3678 pCoexSta->bPanExist = FALSE;
3679 if(btInfo & BT_INFO_8192E_1ANT_B_A2DP)
3680 pCoexSta->bA2dpExist = true;
3681 else
3682 pCoexSta->bA2dpExist = FALSE;
3683 if(btInfo & BT_INFO_8192E_1ANT_B_HID)
3684 pCoexSta->bHidExist = true;
3685 else
3686 pCoexSta->bHidExist = FALSE;
3687 if(btInfo & BT_INFO_8192E_1ANT_B_SCO_ESCO)
3688 pCoexSta->bScoExist = true;
3689 else
3690 pCoexSta->bScoExist = FALSE;
3691 }
3692
3693 halbtc8192e1ant_UpdateBtLinkInfo(pBtCoexist);
3694
3695 if(!(btInfo&BT_INFO_8192E_1ANT_B_CONNECTION))
3696 {
3697 pCoexDm->btStatus = BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
3698 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt non-connected idle!!!\n"));
3699 }
3700 else if(btInfo == BT_INFO_8192E_1ANT_B_CONNECTION) // connection exists but no busy
3701 {
3702 pCoexDm->btStatus = BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE;
3703 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt connected-idle!!!\n"));
3704 }
3705 else if((btInfo&BT_INFO_8192E_1ANT_B_SCO_ESCO) ||
3706 (btInfo&BT_INFO_8192E_1ANT_B_SCO_BUSY))
3707 {
3708 pCoexDm->btStatus = BT_8192E_1ANT_BT_STATUS_SCO_BUSY;
3709 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt sco busy!!!\n"));
3710 }
3711 else if( (btInfo&BT_INFO_8192E_1ANT_B_ACL_BUSY) ||
3712 (btInfo&BT_INFO_8192E_1ANT_B_A2DP) ||
3713 (btInfo&BT_INFO_8192E_1ANT_B_FTP) )
3714 {
3715 if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY != pCoexDm->btStatus)
3716 pCoexDm->bAutoTdmaAdjust = FALSE;
3717 pCoexDm->btStatus = BT_8192E_1ANT_BT_STATUS_ACL_BUSY;
3718 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt acl busy!!!\n"));
3719 }
3720 else
3721 {
3722 pCoexDm->btStatus = BT_8192E_1ANT_BT_STATUS_MAX;
3723 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], BtInfoNotify(), bt non-defined state!!!\n"));
3724 }
3725
3726 // ra mask check
3727 if(pBtLinkInfo->bScoExist || pBtLinkInfo->bHidExist)
3728 {
3729 halbtc8192e1ant_Updatera_mask(pBtCoexist, NORMAL_EXEC, BTC_RATE_DISABLE, 0x00000003); // disable tx cck 1M/2M
3730 }
3731 else
3732 {
3733 halbtc8192e1ant_Updatera_mask(pBtCoexist, NORMAL_EXEC, BTC_RATE_ENABLE, 0x00000003); // enable tx cck 1M/2M
3734 }
3735
3736 if( (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) ||
3737 (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) ||
3738 (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) )
3739 {
3740 bBtBusy = true;
3741 limited_dig = true;
3742 if(pBtLinkInfo->bHidExist)
3743 b_bt_ctrl_agg_buf_size = true;
3744 }
3745 else
3746 {
3747 bBtBusy = FALSE;
3748 limited_dig = FALSE;
3749 }
3750 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy);
3751
3752 //============================================
3753 // Aggregation related setting
3754 //============================================
3755 // if sco, reject AddBA
3756 //pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejApAggPkt);
3757
3758 // decide BT control aggregation buf size or not
3759 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &b_bt_ctrl_agg_buf_size);
3760 // real update aggregation setting
3761 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
3762 //============================================
3763
3764 pCoexDm->limited_dig = limited_dig;
3765 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
3766
3767 halbtc8192e1ant_RunCoexistMechanism(pBtCoexist);
3768}
3769
3770VOID
3771EXhalbtc8192e1ant_StackOperationNotify(
3772 IN PBTC_COEXIST pBtCoexist,
3773 IN u1Byte type
3774 )
3775{
3776 if(BTC_STACK_OP_INQ_PAGE_PAIR_START == type)
3777 {
3778 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], StackOP Inquiry/page/pair start notify\n"));
3779 }
3780 else if(BTC_STACK_OP_INQ_PAGE_PAIR_FINISH == type)
3781 {
3782 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], StackOP Inquiry/page/pair finish notify\n"));
3783 }
3784}
3785
3786VOID
3787EXhalbtc8192e1ant_HaltNotify(
3788 IN PBTC_COEXIST pBtCoexist
3789 )
3790{
3791 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], Halt notify\n"));
3792
3793 pBtCoexist->bStopCoexDm = true;
3794 halbtc8192e1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, true);
3795
3796 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
3797
3798 halbtc8192e1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0);
3799 pBtCoexist->btc_write_1byte(pBtCoexist, 0x4f, 0xf);
3800
3801 EXhalbtc8192e1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT);
3802}
3803
3804VOID
3805EXhalbtc8192e1ant_PnpNotify(
3806 IN PBTC_COEXIST pBtCoexist,
3807 IN u1Byte pnpState
3808 )
3809{
3810 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], Pnp notify\n"));
3811
3812 if(BTC_WIFI_PNP_SLEEP == pnpState)
3813 {
3814 pBtCoexist->bStopCoexDm = true;
3815 halbtc8192e1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, true);
3816 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
3817 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
3818 }
3819 else if(BTC_WIFI_PNP_WAKE_UP == pnpState)
3820 {
3821
3822 }
3823}
3824
3825VOID
3826EXhalbtc8192e1ant_Periodical(
3827 IN PBTC_COEXIST pBtCoexist
3828 )
3829{
3830 static u1Byte disVerInfoCnt=0;
3831 u4Byte fwVer=0, btPatchVer=0;
3832 struct btc_board_info * pBoardInfo=&pBtCoexist->board_info;
3833 PBTC_STACK_INFO pStackInfo=&pBtCoexist->stack_info;
3834
3835 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], ==========================Periodical===========================\n"));
3836
3837 if(disVerInfoCnt <= 5)
3838 {
3839 disVerInfoCnt += 1;
3840 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], ****************************************************************\n"));
3841 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", \
3842 pBoardInfo->pg_ant_num, pBoardInfo->btdm_ant_num, pBoardInfo->btdm_ant_pos));
3843 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", \
3844 ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion));
3845 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer);
3846 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer);
3847 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", \
3848 GLCoexVerDate8192e1Ant, GLCoexVer8192e1Ant, fwVer, btPatchVer, btPatchVer));
3849 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], ****************************************************************\n"));
3850 }
3851#if(BT_AUTO_REPORT_ONLY_8192E_1ANT == 0)
3852 halbtc8192e1ant_QueryBtInfo(pBtCoexist);
3853 halbtc8192e1ant_MonitorBtCtr(pBtCoexist);
3854 halbtc8192e1ant_MonitorBtEnableDisable(pBtCoexist);
3855#else
3856 if( halbtc8192e1ant_IsWifiStatusChanged(pBtCoexist) ||
3857 pCoexDm->bAutoTdmaAdjust)
3858 {
3859 halbtc8192e1ant_RunCoexistMechanism(pBtCoexist);
3860 }
3861#endif
3862}
3863
3864VOID
3865EXhalbtc8192e1ant_DbgControl(
3866 IN PBTC_COEXIST pBtCoexist,
3867 IN u1Byte opCode,
3868 IN u1Byte opLen,
3869 IN pu1Byte pData
3870 )
3871{
3872 switch(opCode)
3873 {
3874 case BTC_DBG_SET_COEX_NORMAL:
3875 pBtCoexist->manual_control = FALSE;
3876 halbtc8192e1ant_InitCoexDm(pBtCoexist);
3877 break;
3878 case BTC_DBG_SET_COEX_WIFI_ONLY:
3879 pBtCoexist->manual_control = true;
3880 halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0);
3881 halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9);
3882 break;
3883 case BTC_DBG_SET_COEX_BT_ONLY:
3884 // todo
3885 break;
3886 default:
3887 break;
3888 }
3889}
3890#endif
3891
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtc8192e1ant.h b/drivers/staging/rtl8821ae/btcoexist/halbtc8192e1ant.h
new file mode 100644
index 000000000000..a759b758faef
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtc8192e1ant.h
@@ -0,0 +1,226 @@
1//===========================================
2// The following is for 8192E_1ANT BT Co-exist definition
3//===========================================
4#define BT_AUTO_REPORT_ONLY_8192E_1ANT 0
5
6#define BT_INFO_8192E_1ANT_B_FTP BIT7
7#define BT_INFO_8192E_1ANT_B_A2DP BIT6
8#define BT_INFO_8192E_1ANT_B_HID BIT5
9#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT4
10#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT3
11#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT2
12#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT1
13#define BT_INFO_8192E_1ANT_B_CONNECTION BIT0
14
15#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
16 (((_BT_INFO_EXT_&BIT0))? true:FALSE)
17
18#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2
19
20typedef enum _BT_INFO_SRC_8192E_1ANT{
21 BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0,
22 BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1,
23 BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2,
24 BT_INFO_SRC_8192E_1ANT_MAX
25}BT_INFO_SRC_8192E_1ANT,*PBT_INFO_SRC_8192E_1ANT;
26
27typedef enum _BT_8192E_1ANT_BT_STATUS{
28 BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
29 BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
30 BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2,
31 BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3,
32 BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4,
33 BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
34 BT_8192E_1ANT_BT_STATUS_MAX
35}BT_8192E_1ANT_BT_STATUS,*PBT_8192E_1ANT_BT_STATUS;
36
37typedef enum _BT_8192E_1ANT_WIFI_STATUS{
38 BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
39 BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
40 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
41 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
42 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
43 BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
44 BT_8192E_1ANT_WIFI_STATUS_MAX
45}BT_8192E_1ANT_WIFI_STATUS,*PBT_8192E_1ANT_WIFI_STATUS;
46
47typedef enum _BT_8192E_1ANT_COEX_ALGO{
48 BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0,
49 BT_8192E_1ANT_COEX_ALGO_SCO = 0x1,
50 BT_8192E_1ANT_COEX_ALGO_HID = 0x2,
51 BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3,
52 BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
53 BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5,
54 BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6,
55 BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
56 BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
57 BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
58 BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa,
59 BT_8192E_1ANT_COEX_ALGO_MAX = 0xb,
60}BT_8192E_1ANT_COEX_ALGO,*PBT_8192E_1ANT_COEX_ALGO;
61
62typedef struct _COEX_DM_8192E_1ANT{
63 // fw mechanism
64 u1Byte preBtDecPwrLvl;
65 u1Byte curBtDecPwrLvl;
66 BOOLEAN bPreBtLnaConstrain;
67 BOOLEAN bCurBtLnaConstrain;
68 u1Byte bPreBtPsdMode;
69 u1Byte bCurBtPsdMode;
70 u1Byte preFwDacSwingLvl;
71 u1Byte curFwDacSwingLvl;
72 BOOLEAN bCurIgnoreWlanAct;
73 BOOLEAN bPreIgnoreWlanAct;
74 u1Byte prePsTdma;
75 u1Byte curPsTdma;
76 u1Byte psTdmaPara[5];
77 u1Byte psTdmaDuAdjType;
78 BOOLEAN bAutoTdmaAdjust;
79 BOOLEAN bPrePsTdmaOn;
80 BOOLEAN bCurPsTdmaOn;
81 BOOLEAN bPreBtAutoReport;
82 BOOLEAN bCurBtAutoReport;
83 u1Byte preLps;
84 u1Byte curLps;
85 u1Byte preRpwm;
86 u1Byte curRpwm;
87
88 // sw mechanism
89 BOOLEAN bPreRfRxLpfShrink;
90 BOOLEAN bCurRfRxLpfShrink;
91 u4Byte btRf0x1eBackup;
92 BOOLEAN bPreLowPenaltyRa;
93 BOOLEAN bCurLowPenaltyRa;
94 BOOLEAN bPreDacSwingOn;
95 u4Byte preDacSwingLvl;
96 BOOLEAN bCurDacSwingOn;
97 u4Byte curDacSwingLvl;
98 BOOLEAN bPreAdcBackOff;
99 BOOLEAN bCurAdcBackOff;
100 BOOLEAN bPreAgcTableEn;
101 BOOLEAN bCurAgcTableEn;
102 u4Byte preVal0x6c0;
103 u4Byte curVal0x6c0;
104 u4Byte preVal0x6c4;
105 u4Byte curVal0x6c4;
106 u4Byte preVal0x6c8;
107 u4Byte curVal0x6c8;
108 u1Byte preVal0x6cc;
109 u1Byte curVal0x6cc;
110 BOOLEAN limited_dig;
111
112 // algorithm related
113 u1Byte preAlgorithm;
114 u1Byte curAlgorithm;
115 u1Byte btStatus;
116 u1Byte wifiChnlInfo[3];
117
118 u1Byte preSsType;
119 u1Byte curSsType;
120
121 u4Byte prera_mask;
122 u4Byte curra_mask;
123
124 u1Byte errorCondition;
125} COEX_DM_8192E_1ANT, *PCOEX_DM_8192E_1ANT;
126
127typedef struct _COEX_STA_8192E_1ANT{
128 BOOLEAN bBtLinkExist;
129 BOOLEAN bScoExist;
130 BOOLEAN bA2dpExist;
131 BOOLEAN bHidExist;
132 BOOLEAN bPanExist;
133
134 BOOLEAN bUnderLps;
135 BOOLEAN bUnderIps;
136 u4Byte highPriorityTx;
137 u4Byte highPriorityRx;
138 u4Byte lowPriorityTx;
139 u4Byte lowPriorityRx;
140 u1Byte btRssi;
141 u1Byte preBtRssiState;
142 u1Byte preWifiRssiState[4];
143 BOOLEAN bC2hBtInfoReqSent;
144 u1Byte btInfoC2h[BT_INFO_SRC_8192E_1ANT_MAX][10];
145 u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_1ANT_MAX];
146 BOOLEAN bC2hBtInquiryPage;
147 u1Byte btRetryCnt;
148 u1Byte btInfoExt;
149}COEX_STA_8192E_1ANT, *PCOEX_STA_8192E_1ANT;
150
151//===========================================
152// The following is interface which will notify coex module.
153//===========================================
154VOID
155EXhalbtc8192e1ant_InitHwConfig(
156 IN PBTC_COEXIST pBtCoexist
157 );
158VOID
159EXhalbtc8192e1ant_InitCoexDm(
160 IN PBTC_COEXIST pBtCoexist
161 );
162VOID
163EXhalbtc8192e1ant_IpsNotify(
164 IN PBTC_COEXIST pBtCoexist,
165 IN u1Byte type
166 );
167VOID
168EXhalbtc8192e1ant_LpsNotify(
169 IN PBTC_COEXIST pBtCoexist,
170 IN u1Byte type
171 );
172VOID
173EXhalbtc8192e1ant_ScanNotify(
174 IN PBTC_COEXIST pBtCoexist,
175 IN u1Byte type
176 );
177VOID
178EXhalbtc8192e1ant_ConnectNotify(
179 IN PBTC_COEXIST pBtCoexist,
180 IN u1Byte type
181 );
182VOID
183EXhalbtc8192e1ant_MediaStatusNotify(
184 IN PBTC_COEXIST pBtCoexist,
185 IN u1Byte type
186 );
187VOID
188EXhalbtc8192e1ant_SpecialPacketNotify(
189 IN PBTC_COEXIST pBtCoexist,
190 IN u1Byte type
191 );
192VOID
193EXhalbtc8192e1ant_BtInfoNotify(
194 IN PBTC_COEXIST pBtCoexist,
195 IN pu1Byte tmpBuf,
196 IN u1Byte length
197 );
198VOID
199EXhalbtc8192e1ant_StackOperationNotify(
200 IN PBTC_COEXIST pBtCoexist,
201 IN u1Byte type
202 );
203VOID
204EXhalbtc8192e1ant_HaltNotify(
205 IN PBTC_COEXIST pBtCoexist
206 );
207VOID
208EXhalbtc8192e1ant_PnpNotify(
209 IN PBTC_COEXIST pBtCoexist,
210 IN u1Byte pnpState
211 );
212VOID
213EXhalbtc8192e1ant_Periodical(
214 IN PBTC_COEXIST pBtCoexist
215 );
216VOID
217EXhalbtc8192e1ant_DisplayCoexInfo(
218 IN PBTC_COEXIST pBtCoexist
219 );
220VOID
221EXhalbtc8192e1ant_DbgControl(
222 IN PBTC_COEXIST pBtCoexist,
223 IN u1Byte opCode,
224 IN u1Byte opLen,
225 IN pu1Byte pData
226 );
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtc8192e2ant.c b/drivers/staging/rtl8821ae/btcoexist/halbtc8192e2ant.c
new file mode 100644
index 000000000000..44ec78562e2d
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtc8192e2ant.c
@@ -0,0 +1,4242 @@
1/**************************************************************
2 * Description:
3 *
4 * This file is for RTL8192E Co-exist mechanism
5 *
6 * History
7 * 2012/11/15 Cosa first check in.
8 *
9 **************************************************************/
10
11/**************************************************************
12 * include files
13 **************************************************************/
14#include "halbt_precomp.h"
15#if 1
16/**************************************************************
17 * Global variables, these are static variables
18 **************************************************************/
19static struct coex_dm_8192e_2ant glcoex_dm_8192e_2ant;
20static struct coex_dm_8192e_2ant *coex_dm = &glcoex_dm_8192e_2ant;
21static struct coex_sta_8192e_2ant glcoex_sta_8192e_2ant;
22static struct coex_sta_8192e_2ant *coex_sta = &glcoex_sta_8192e_2ant;
23
24const char *const GLBtInfoSrc8192e2Ant[]={
25 "BT Info[wifi fw]",
26 "BT Info[bt rsp]",
27 "BT Info[bt auto report]",
28};
29
30u32 glcoex_ver_date_8192e_2ant = 20130902;
31u32 glcoex_ver_8192e_2ant = 0x34;
32
33/**************************************************************
34 * local function proto type if needed
35 **************************************************************/
36/**************************************************************
37 * local function start with halbtc8192e2ant_
38 **************************************************************/
39u8 halbtc8192e2ant_btrssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
40{
41 int btrssi=0;
42 u8 btrssi_state = coex_sta->pre_bt_rssi_state;
43
44 btrssi = coex_sta->bt_rssi;
45
46 if (level_num == 2) {
47 if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
48 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
49 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
50 "BT Rssi pre state=LOW\n");
51 if (btrssi >= (rssi_thresh +
52 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
53 btrssi_state = BTC_RSSI_STATE_HIGH;
54 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
55 "BT Rssi state switch to High\n");
56 } else {
57 btrssi_state = BTC_RSSI_STATE_STAY_LOW;
58 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
59 "BT Rssi state stay at Low\n");
60 }
61 } else {
62 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
63 "BT Rssi pre state=HIGH\n");
64 if (btrssi < rssi_thresh) {
65 btrssi_state = BTC_RSSI_STATE_LOW;
66 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
67 "BT Rssi state switch to Low\n");
68 } else {
69 btrssi_state = BTC_RSSI_STATE_STAY_HIGH;
70 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
71 "BT Rssi state stay at High\n");
72 }
73 }
74 } else if (level_num == 3) {
75 if (rssi_thresh > rssi_thresh1) {
76 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
77 "BT Rssi thresh error!!\n");
78 return coex_sta->pre_bt_rssi_state;
79 }
80
81 if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
82 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
83 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
84 "BT Rssi pre state=LOW\n");
85 if(btrssi >= (rssi_thresh +
86 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
87 btrssi_state = BTC_RSSI_STATE_MEDIUM;
88 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
89 "BT Rssi state switch to Medium\n");
90 } else {
91 btrssi_state = BTC_RSSI_STATE_STAY_LOW;
92 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
93 "BT Rssi state stay at Low\n");
94 }
95 } else if ((coex_sta->pre_bt_rssi_state ==
96 BTC_RSSI_STATE_MEDIUM) ||
97 (coex_sta->pre_bt_rssi_state ==
98 BTC_RSSI_STATE_STAY_MEDIUM)) {
99 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
100 "[BTCoex], BT Rssi pre state=MEDIUM\n");
101 if (btrssi >= (rssi_thresh1 +
102 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
103 btrssi_state = BTC_RSSI_STATE_HIGH;
104 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
105 "BT Rssi state switch to High\n");
106 } else if (btrssi < rssi_thresh) {
107 btrssi_state = BTC_RSSI_STATE_LOW;
108 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
109 "BT Rssi state switch to Low\n");
110 } else {
111 btrssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
112 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
113 "BT Rssi state stay at Medium\n");
114 }
115 } else {
116 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
117 "BT Rssi pre state=HIGH\n");
118 if (btrssi < rssi_thresh1) {
119 btrssi_state = BTC_RSSI_STATE_MEDIUM;
120 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
121 "BT Rssi state switch to Medium\n");
122 } else {
123 btrssi_state = BTC_RSSI_STATE_STAY_HIGH;
124 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
125 "BT Rssi state stay at High\n");
126 }
127 }
128 }
129
130 coex_sta->pre_bt_rssi_state = btrssi_state;
131
132 return btrssi_state;
133}
134
135u8 halbtc8192e2ant_wifirssi_state(struct btc_coexist * btcoexist, u8 index,
136 u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
137{
138 int wifirssi = 0;
139 u8 wifirssi_state = coex_sta->pre_wifi_rssi_state[index];
140
141 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifirssi);
142
143 if (level_num == 2) {
144 if ((coex_sta->pre_wifi_rssi_state[index] ==
145 BTC_RSSI_STATE_LOW) ||
146 (coex_sta->pre_wifi_rssi_state[index] ==
147 BTC_RSSI_STATE_STAY_LOW)) {
148 if (wifirssi >= (rssi_thresh +
149 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
150 wifirssi_state = BTC_RSSI_STATE_HIGH;
151 BTC_PRINT(BTC_MSG_ALGORITHM,
152 ALGO_WIFI_RSSI_STATE,
153 "wifi RSSI state switch to High\n");
154 } else {
155 wifirssi_state = BTC_RSSI_STATE_STAY_LOW;
156 BTC_PRINT(BTC_MSG_ALGORITHM,
157 ALGO_WIFI_RSSI_STATE,
158 "wifi RSSI state stay at Low\n");
159 }
160 } else {
161 if (wifirssi < rssi_thresh) {
162 wifirssi_state = BTC_RSSI_STATE_LOW;
163 BTC_PRINT(BTC_MSG_ALGORITHM,
164 ALGO_WIFI_RSSI_STATE,
165 "wifi RSSI state switch to Low\n");
166 } else {
167 wifirssi_state = BTC_RSSI_STATE_STAY_HIGH;
168 BTC_PRINT(BTC_MSG_ALGORITHM,
169 ALGO_WIFI_RSSI_STATE,
170 "wifi RSSI state stay at High\n");
171 }
172 }
173 } else if (level_num == 3) {
174 if (rssi_thresh > rssi_thresh1) {
175 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE,
176 "wifi RSSI thresh error!!\n");
177 return coex_sta->pre_wifi_rssi_state[index];
178 }
179
180 if ((coex_sta->pre_wifi_rssi_state[index] ==
181 BTC_RSSI_STATE_LOW) ||
182 (coex_sta->pre_wifi_rssi_state[index] ==
183 BTC_RSSI_STATE_STAY_LOW)) {
184 if (wifirssi >= (rssi_thresh +
185 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
186 wifirssi_state = BTC_RSSI_STATE_MEDIUM;
187 BTC_PRINT(BTC_MSG_ALGORITHM,
188 ALGO_WIFI_RSSI_STATE,
189 "wifi RSSI state switch to Medium\n");
190 } else {
191 wifirssi_state = BTC_RSSI_STATE_STAY_LOW;
192 BTC_PRINT(BTC_MSG_ALGORITHM,
193 ALGO_WIFI_RSSI_STATE,
194 "wifi RSSI state stay at Low\n");
195 }
196 } else if ((coex_sta->pre_wifi_rssi_state[index] ==
197 BTC_RSSI_STATE_MEDIUM) ||
198 (coex_sta->pre_wifi_rssi_state[index] ==
199 BTC_RSSI_STATE_STAY_MEDIUM)) {
200 if (wifirssi >= (rssi_thresh1 +
201 BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) {
202 wifirssi_state = BTC_RSSI_STATE_HIGH;
203 BTC_PRINT(BTC_MSG_ALGORITHM,
204 ALGO_WIFI_RSSI_STATE,
205 "wifi RSSI state switch to High\n");
206 } else if (wifirssi < rssi_thresh) {
207 wifirssi_state = BTC_RSSI_STATE_LOW;
208 BTC_PRINT(BTC_MSG_ALGORITHM,
209 ALGO_WIFI_RSSI_STATE,
210 "wifi RSSI state switch to Low\n");
211 } else {
212 wifirssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
213 BTC_PRINT(BTC_MSG_ALGORITHM,
214 ALGO_WIFI_RSSI_STATE,
215 "wifi RSSI state stay at Medium\n");
216 }
217 } else {
218 if (wifirssi < rssi_thresh1) {
219 wifirssi_state = BTC_RSSI_STATE_MEDIUM;
220 BTC_PRINT(BTC_MSG_ALGORITHM,
221 ALGO_WIFI_RSSI_STATE,
222 "wifi RSSI state switch to Medium\n");
223 } else {
224 wifirssi_state = BTC_RSSI_STATE_STAY_HIGH;
225 BTC_PRINT(BTC_MSG_ALGORITHM,
226 ALGO_WIFI_RSSI_STATE,
227 "wifi RSSI state stay at High\n");
228 }
229 }
230 }
231
232 coex_sta->pre_wifi_rssi_state[index] = wifirssi_state;
233
234 return wifirssi_state;
235}
236
237void halbtc8192e2ant_monitor_bt_enable_disable(struct btc_coexist *btcoexist)
238{
239 static bool pre_bt_disabled = false;
240 static u32 bt_disable_cnt = 0;
241 bool bt_active = true, bt_disabled = false;
242
243 /* This function check if bt is disabled */
244
245 if (coex_sta->high_priority_tx == 0 &&
246 coex_sta->high_priority_rx == 0 &&
247 coex_sta->low_priority_tx == 0 &&
248 coex_sta->low_priority_rx == 0)
249 bt_active = false;
250
251 if (coex_sta->high_priority_tx == 0xffff &&
252 coex_sta->high_priority_rx == 0xffff &&
253 coex_sta->low_priority_tx == 0xffff &&
254 coex_sta->low_priority_rx == 0xffff)
255 bt_active = false;
256
257 if (bt_active) {
258 bt_disable_cnt = 0;
259 bt_disabled = false;
260 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
261 &bt_disabled);
262 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
263 "[BTCoex], BT is enabled !!\n");
264 } else {
265 bt_disable_cnt++;
266 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
267 "[BTCoex], bt all counters=0, %d times!!\n",
268 bt_disable_cnt);
269 if (bt_disable_cnt >= 2) {
270 bt_disabled = true;
271 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
272 &bt_disabled);
273 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
274 "[BTCoex], BT is disabled !!\n");
275 }
276 }
277 if (pre_bt_disabled != bt_disabled) {
278 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
279 "[BTCoex], BT is from %s to %s!!\n",
280 (pre_bt_disabled ? "disabled":"enabled"),
281 (bt_disabled ? "disabled":"enabled"));
282 pre_bt_disabled = bt_disabled;
283 }
284}
285
286u32 halbtc8192e2ant_decidera_mask(struct btc_coexist *btcoexist,
287 u8 sstype, u32 ra_masktype)
288{
289 u32 disra_mask = 0x0;
290
291 switch (ra_masktype) {
292 case 0: /* normal mode */
293 if (sstype == 2)
294 disra_mask = 0x0; /* enable 2ss */
295 else
296 disra_mask = 0xfff00000;/* disable 2ss */
297 break;
298 case 1: /* disable cck 1/2 */
299 if(sstype == 2)
300 disra_mask = 0x00000003;/* enable 2ss */
301 else
302 disra_mask = 0xfff00003;/* disable 2ss */
303 break;
304 case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
305 if(sstype == 2)
306 disra_mask = 0x0001f1f7;/* enable 2ss */
307 else
308 disra_mask = 0xfff1f1f7;/* disable 2ss */
309 break;
310 default:
311 break;
312 }
313
314 return disra_mask;
315}
316
317void halbtc8192e2ant_Updatera_mask(struct btc_coexist *btcoexist,
318 bool force_exec, u32 dis_ratemask)
319{
320 coex_dm->curra_mask = dis_ratemask;
321
322 if (force_exec || (coex_dm->prera_mask != coex_dm->curra_mask))
323 btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_ra_mask,
324 &coex_dm->curra_mask);
325 coex_dm->prera_mask = coex_dm->curra_mask;
326}
327
328void halbtc8192e2ant_autorate_fallback_retry(struct btc_coexist *btcoexist,
329 bool force_exec, u8 type)
330{
331 bool wifi_under_bmode = false;
332
333 coex_dm->cur_arfrtype = type;
334
335 if (force_exec || (coex_dm->pre_arfrtype != coex_dm->cur_arfrtype)) {
336 switch (coex_dm->cur_arfrtype) {
337 case 0: /* normal mode */
338 btcoexist->btc_write_4byte(btcoexist, 0x430,
339 coex_dm->backup_arfr_cnt1);
340 btcoexist->btc_write_4byte(btcoexist, 0x434,
341 coex_dm->backup_arfr_cnt2);
342 break;
343 case 1:
344 btcoexist->btc_get(btcoexist,
345 BTC_GET_BL_WIFI_UNDER_B_MODE,
346 &wifi_under_bmode);
347 if (wifi_under_bmode) {
348 btcoexist->btc_write_4byte(btcoexist, 0x430,
349 0x0);
350 btcoexist->btc_write_4byte(btcoexist, 0x434,
351 0x01010101);
352 } else {
353 btcoexist->btc_write_4byte(btcoexist, 0x430,
354 0x0);
355 btcoexist->btc_write_4byte(btcoexist, 0x434,
356 0x04030201);
357 }
358 break;
359 default:
360 break;
361 }
362 }
363
364 coex_dm->pre_arfrtype = coex_dm->cur_arfrtype;
365}
366
367void halbtc8192e2ant_retrylimit(struct btc_coexist *btcoexist,
368 bool force_exec, u8 type)
369{
370 coex_dm->cur_retrylimit_type = type;
371
372 if (force_exec || (coex_dm->pre_retrylimit_type !=
373 coex_dm->cur_retrylimit_type)) {
374 switch (coex_dm->cur_retrylimit_type) {
375 case 0: /* normal mode */
376 btcoexist->btc_write_2byte(btcoexist, 0x42a,
377 coex_dm->backup_retrylimit);
378 break;
379 case 1: /* retry limit=8 */
380 btcoexist->btc_write_2byte(btcoexist, 0x42a,
381 0x0808);
382 break;
383 default:
384 break;
385 }
386 }
387
388 coex_dm->pre_retrylimit_type = coex_dm->cur_retrylimit_type;
389}
390
391void halbtc8192e2ant_ampdu_maxtime(struct btc_coexist *btcoexist,
392 bool force_exec, u8 type)
393{
394 coex_dm->cur_ampdutime_type = type;
395
396 if (force_exec || (coex_dm->pre_ampdutime_type !=
397 coex_dm->cur_ampdutime_type)) {
398 switch (coex_dm->cur_ampdutime_type) {
399 case 0: /* normal mode */
400 btcoexist->btc_write_1byte(btcoexist, 0x456,
401 coex_dm->backup_ampdu_maxtime);
402 break;
403 case 1: /* AMPDU timw = 0x38 * 32us */
404 btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38);
405 break;
406 default:
407 break;
408 }
409 }
410
411 coex_dm->pre_ampdutime_type = coex_dm->cur_ampdutime_type;
412}
413
414void halbtc8192e2ant_limited_tx(struct btc_coexist *btcoexist,
415 bool force_exec, u8 ra_masktype, u8 arfr_type,
416 u8 retrylimit_type, u8 ampdutime_type)
417{
418 u32 disra_mask = 0x0;
419
420 coex_dm->curra_masktype = ra_masktype;
421 disra_mask = halbtc8192e2ant_decidera_mask(btcoexist,
422 coex_dm->cur_sstype,
423 ra_masktype);
424 halbtc8192e2ant_Updatera_mask(btcoexist, force_exec, disra_mask);
425
426 halbtc8192e2ant_autorate_fallback_retry(btcoexist, force_exec,
427 arfr_type);
428 halbtc8192e2ant_retrylimit(btcoexist, force_exec, retrylimit_type);
429 halbtc8192e2ant_ampdu_maxtime(btcoexist, force_exec, ampdutime_type);
430}
431
432void halbtc8192e2ant_limited_rx(struct btc_coexist *btcoexist,
433 bool force_exec, bool rej_ap_agg_pkt,
434 bool b_bt_ctrl_agg_buf_size,
435 u8 agg_buf_size)
436{
437 bool reject_rx_agg = rej_ap_agg_pkt;
438 bool bt_ctrl_rx_agg_size = b_bt_ctrl_agg_buf_size;
439 u8 rx_agg_size = agg_buf_size;
440
441 /*********************************************
442 * Rx Aggregation related setting
443 *********************************************/
444 btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
445 &reject_rx_agg);
446 /* decide BT control aggregation buf size or not */
447 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
448 &bt_ctrl_rx_agg_size);
449 /* aggregation buf size, only work
450 * when BT control Rx aggregation size. */
451 btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
452 /* real update aggregation setting */
453 btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
454
455
456}
457
458void halbtc8192e2ant_monitor_bt_ctr(struct btc_coexist *btcoexist)
459{
460 u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
461 u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
462
463 reg_hp_txrx = 0x770;
464 reg_lp_txrx = 0x774;
465
466 u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
467 reg_hp_tx = u32tmp & MASKLWORD;
468 reg_hp_rx = (u32tmp & MASKHWORD)>>16;
469
470 u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
471 reg_lp_tx = u32tmp & MASKLWORD;
472 reg_lp_rx = (u32tmp & MASKHWORD)>>16;
473
474 coex_sta->high_priority_tx = reg_hp_tx;
475 coex_sta->high_priority_rx = reg_hp_rx;
476 coex_sta->low_priority_tx = reg_lp_tx;
477 coex_sta->low_priority_rx = reg_lp_rx;
478
479 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
480 "[BTCoex] High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
481 reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
482 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
483 "[BTCoex] Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
484 reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
485
486 /* reset counter */
487 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
488}
489
490void halbtc8192e2ant_querybt_info(struct btc_coexist *btcoexist)
491{
492 u8 h2c_parameter[1] ={0};
493
494 coex_sta->c2h_bt_info_req_sent = true;
495
496 h2c_parameter[0] |= BIT0; /* trigger */
497
498 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
499 "[BTCoex], Query Bt Info, FW write 0x61=0x%x\n",
500 h2c_parameter[0]);
501
502 btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
503}
504
505bool halbtc8192e2ant_iswifi_status_changed(struct btc_coexist *btcoexist)
506{
507 static bool pre_wifi_busy = false;
508 static bool pre_under_4way = false, pre_bt_hson = false;
509 bool wifi_busy = false, under_4way = false, bt_hson = false;
510 bool wifi_connected = false;
511
512 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
513 &wifi_connected);
514 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
515 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
516 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
517 &under_4way);
518
519 if (wifi_connected) {
520 if (wifi_busy != pre_wifi_busy) {
521 pre_wifi_busy = wifi_busy;
522 return true;
523 }
524 if (under_4way != pre_under_4way) {
525 pre_under_4way = under_4way;
526 return true;
527 }
528 if (bt_hson != pre_bt_hson) {
529 pre_bt_hson = bt_hson;
530 return true;
531 }
532 }
533
534 return false;
535}
536
537void halbtc8192e2ant_update_btlink_info(struct btc_coexist *btcoexist)
538{
539 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
540 bool bt_hson = false;
541
542 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
543
544 bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
545 bt_link_info->sco_exist = coex_sta->sco_exist;
546 bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
547 bt_link_info->pan_exist = coex_sta->pan_exist;
548 bt_link_info->hid_exist = coex_sta->hid_exist;
549
550 /* work around for HS mode. */
551 if (bt_hson) {
552 bt_link_info->pan_exist = true;
553 bt_link_info->bt_link_exist = true;
554 }
555
556 /* check if Sco only */
557 if (bt_link_info->sco_exist &&
558 !bt_link_info->a2dp_exist &&
559 !bt_link_info->pan_exist &&
560 !bt_link_info->hid_exist)
561 bt_link_info->sco_only = true;
562 else
563 bt_link_info->sco_only = false;
564
565 /* check if A2dp only */
566 if (!bt_link_info->sco_exist &&
567 bt_link_info->a2dp_exist &&
568 !bt_link_info->pan_exist &&
569 !bt_link_info->hid_exist)
570 bt_link_info->a2dp_only = true;
571 else
572 bt_link_info->a2dp_only = false;
573
574 /* check if Pan only */
575 if (!bt_link_info->sco_exist &&
576 !bt_link_info->a2dp_exist &&
577 bt_link_info->pan_exist &&
578 !bt_link_info->hid_exist)
579 bt_link_info->pan_only = true;
580 else
581 bt_link_info->pan_only = false;
582
583 /* check if Hid only */
584 if (!bt_link_info->sco_exist &&
585 !bt_link_info->a2dp_exist &&
586 !bt_link_info->pan_exist &&
587 bt_link_info->hid_exist)
588 bt_link_info->hid_only = true;
589 else
590 bt_link_info->hid_only = false;
591}
592
593u8 halbtc8192e2ant_action_algorithm(struct btc_coexist *btcoexist)
594{
595 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
596 struct btc_stack_info *stack_info = &btcoexist->stack_info;
597 bool bt_hson=false;
598 u8 algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED;
599 u8 numOfDiffProfile = 0;
600
601 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
602
603 if (!bt_link_info->bt_link_exist) {
604 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
605 "No BT link exists!!!\n");
606 return algorithm;
607 }
608
609 if (bt_link_info->sco_exist)
610 numOfDiffProfile++;
611 if (bt_link_info->hid_exist)
612 numOfDiffProfile++;
613 if (bt_link_info->pan_exist)
614 numOfDiffProfile++;
615 if (bt_link_info->a2dp_exist)
616 numOfDiffProfile++;
617
618 if (numOfDiffProfile == 1) {
619 if (bt_link_info->sco_exist) {
620 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
621 "SCO only\n");
622 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
623 } else {
624 if (bt_link_info->hid_exist) {
625 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
626 "HID only\n");
627 algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
628 } else if (bt_link_info->a2dp_exist) {
629 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
630 "A2DP only\n");
631 algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP;
632 } else if (bt_link_info->pan_exist) {
633 if (bt_hson) {
634 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
635 "PAN(HS) only\n");
636 algorithm =
637 BT_8192E_2ANT_COEX_ALGO_PANHS;
638 } else {
639 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
640 "PAN(EDR) only\n");
641 algorithm =
642 BT_8192E_2ANT_COEX_ALGO_PANEDR;
643 }
644 }
645 }
646 } else if (numOfDiffProfile == 2) {
647 if (bt_link_info->sco_exist) {
648 if (bt_link_info->hid_exist) {
649 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
650 "SCO + HID\n");
651 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
652 } else if (bt_link_info->a2dp_exist) {
653 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
654 "SCO + A2DP ==> SCO\n");
655 algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
656 } else if (bt_link_info->pan_exist) {
657 if (bt_hson) {
658 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
659 "SCO + PAN(HS)\n");
660 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
661 } else {
662 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
663 "SCO + PAN(EDR)\n");
664 algorithm =
665 BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
666 }
667 }
668 } else {
669 if (bt_link_info->hid_exist &&
670 bt_link_info->a2dp_exist) {
671 if (stack_info->num_of_hid >= 2) {
672 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
673 "HID*2 + A2DP\n");
674 algorithm =
675 BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
676 } else {
677 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
678 "HID + A2DP\n");
679 algorithm =
680 BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
681 }
682 } else if (bt_link_info->hid_exist &&
683 bt_link_info->pan_exist) {
684 if (bt_hson) {
685 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
686 "HID + PAN(HS)\n");
687 algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
688 } else {
689 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
690 "HID + PAN(EDR)\n");
691 algorithm =
692 BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
693 }
694 } else if (bt_link_info->pan_exist &&
695 bt_link_info->a2dp_exist) {
696 if (bt_hson) {
697 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
698 "A2DP + PAN(HS)\n");
699 algorithm =
700 BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS;
701 } else {
702 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
703 "A2DP + PAN(EDR)\n");
704 algorithm =
705 BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP;
706 }
707 }
708 }
709 } else if (numOfDiffProfile == 3) {
710 if (bt_link_info->sco_exist) {
711 if (bt_link_info->hid_exist &&
712 bt_link_info->a2dp_exist) {
713 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
714 "SCO + HID + A2DP ==> HID\n");
715 algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
716 } else if (bt_link_info->hid_exist &&
717 bt_link_info->pan_exist) {
718 if (bt_hson) {
719 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
720 "SCO + HID + PAN(HS)\n");
721 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
722 } else {
723 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
724 "SCO + HID + PAN(EDR)\n");
725 algorithm =
726 BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
727 }
728 } else if (bt_link_info->pan_exist &&
729 bt_link_info->a2dp_exist) {
730 if (bt_hson) {
731 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
732 "SCO + A2DP + PAN(HS)\n");
733 algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
734 } else {
735 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
736 "SCO + A2DP + PAN(EDR)\n");
737 algorithm =
738 BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
739 }
740 }
741 } else {
742 if (bt_link_info->hid_exist &&
743 bt_link_info->pan_exist &&
744 bt_link_info->a2dp_exist) {
745 if (bt_hson) {
746 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
747 "HID + A2DP + PAN(HS)\n");
748 algorithm =
749 BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
750 } else {
751 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
752 "HID + A2DP + PAN(EDR)\n");
753 algorithm =
754 BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
755 }
756 }
757 }
758 } else if (numOfDiffProfile >= 3) {
759 if (bt_link_info->sco_exist) {
760 if (bt_link_info->hid_exist &&
761 bt_link_info->pan_exist &&
762 bt_link_info->a2dp_exist) {
763 if (bt_hson) {
764 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
765 "ErrorSCO+HID+A2DP+PAN(HS)\n");
766
767 } else {
768 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
769 "SCO+HID+A2DP+PAN(EDR)\n");
770 algorithm =
771 BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
772 }
773 }
774 }
775 }
776
777 return algorithm;
778}
779
780void halbtc8192e2ant_setfw_dac_swinglevel(struct btc_coexist *btcoexist,
781 u8 dac_swinglvl)
782{
783 u8 h2c_parameter[1] ={0};
784
785 /* There are several type of dacswing
786 * 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
787 h2c_parameter[0] = dac_swinglvl;
788
789 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
790 "[BTCoex], Set Dac Swing Level=0x%x\n", dac_swinglvl);
791 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
792 "[BTCoex], FW write 0x64=0x%x\n", h2c_parameter[0]);
793
794 btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
795}
796
797void halbtc8192e2ant_set_fwdec_btpwr(struct btc_coexist *btcoexist,
798 u8 dec_btpwr_lvl)
799{
800 u8 h2c_parameter[1] ={0};
801
802 h2c_parameter[0] = dec_btpwr_lvl;
803
804 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
805 "[BTCoex] decrease Bt Power level = %d, FW write 0x62=0x%x\n",
806 dec_btpwr_lvl, h2c_parameter[0]);
807
808 btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
809}
810
811void halbtc8192e2ant_dec_btpwr(struct btc_coexist *btcoexist,
812 bool force_exec, u8 dec_btpwr_lvl)
813{
814 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
815 "[BTCoex], %s Dec BT power level = %d\n",
816 (force_exec? "force to":""), dec_btpwr_lvl);
817 coex_dm->cur_dec_bt_pwr = dec_btpwr_lvl;
818
819 if (!force_exec) {
820 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
821 "[BTCoex], preBtDecPwrLvl=%d, curBtDecPwrLvl=%d\n",
822 coex_dm->pre_dec_bt_pwr, coex_dm->cur_dec_bt_pwr);
823 }
824 halbtc8192e2ant_set_fwdec_btpwr(btcoexist, coex_dm->cur_dec_bt_pwr);
825
826 coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr;
827}
828
829void halbtc8192e2ant_set_bt_autoreport(struct btc_coexist *btcoexist,
830 bool enable_autoreport)
831{
832 u8 h2c_parameter[1] ={0};
833
834 h2c_parameter[0] = 0;
835
836 if (enable_autoreport)
837 h2c_parameter[0] |= BIT0;
838
839 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
840 "[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n",
841 (enable_autoreport? "Enabled!!":"Disabled!!"),
842 h2c_parameter[0]);
843
844 btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
845}
846
847void halbtc8192e2ant_bt_autoreport(struct btc_coexist *btcoexist,
848 bool force_exec, bool enable_autoreport)
849{
850 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
851 "[BTCoex], %s BT Auto report = %s\n",
852 (force_exec? "force to":""),
853 ((enable_autoreport)? "Enabled":"Disabled"));
854 coex_dm->cur_bt_auto_report = enable_autoreport;
855
856 if (!force_exec) {
857 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
858 "[BTCoex] bPreBtAutoReport=%d, bCurBtAutoReport=%d\n",
859 coex_dm->pre_bt_auto_report,
860 coex_dm->cur_bt_auto_report);
861
862 if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
863 return;
864 }
865 halbtc8192e2ant_set_bt_autoreport(btcoexist,
866 coex_dm->cur_bt_auto_report);
867
868 coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
869}
870
871void halbtc8192e2ant_fw_dac_swinglvl(struct btc_coexist *btcoexist,
872 bool force_exec, u8 fw_dac_swinglvl)
873{
874 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
875 "[BTCoex], %s set FW Dac Swing level = %d\n",
876 (force_exec? "force to":""), fw_dac_swinglvl);
877 coex_dm->cur_fw_dac_swing_lvl = fw_dac_swinglvl;
878
879 if (!force_exec) {
880 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
881 "[BTCoex] preFwDacSwingLvl=%d, curFwDacSwingLvl=%d\n",
882 coex_dm->pre_fw_dac_swing_lvl,
883 coex_dm->cur_fw_dac_swing_lvl);
884
885 if (coex_dm->pre_fw_dac_swing_lvl ==
886 coex_dm->cur_fw_dac_swing_lvl)
887 return;
888 }
889
890 halbtc8192e2ant_setfw_dac_swinglevel(btcoexist,
891 coex_dm->cur_fw_dac_swing_lvl);
892
893 coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
894}
895
896void halbtc8192e2ant_set_sw_rf_rx_lpf_corner(struct btc_coexist *btcoexist,
897 bool rx_rf_shrink_on)
898{
899 if (rx_rf_shrink_on) {
900 /* Shrink RF Rx LPF corner */
901 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
902 "[BTCoex], Shrink RF Rx LPF corner!!\n");
903 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
904 0xfffff, 0xffffc);
905 } else {
906 /* Resume RF Rx LPF corner
907 * After initialized, we can use coex_dm->btRf0x1eBackup */
908 if (btcoexist->initilized) {
909 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
910 "[BTCoex], Resume RF Rx LPF corner!!\n");
911 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
912 0xfffff,
913 coex_dm->bt_rf0x1e_backup);
914 }
915 }
916}
917
918void halbtc8192e2ant_rf_shrink(struct btc_coexist *btcoexist,
919 bool force_exec, bool rx_rf_shrink_on)
920{
921 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
922 "[BTCoex], %s turn Rx RF Shrink = %s\n",
923 (force_exec? "force to":""), ((rx_rf_shrink_on)? "ON":"OFF"));
924 coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
925
926 if (!force_exec) {
927 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
928 "[BTCoex]bPreRfRxLpfShrink=%d,bCurRfRxLpfShrink=%d\n",
929 coex_dm->pre_rf_rx_lpf_shrink,
930 coex_dm->cur_rf_rx_lpf_shrink);
931
932 if (coex_dm->pre_rf_rx_lpf_shrink ==
933 coex_dm->cur_rf_rx_lpf_shrink)
934 return;
935 }
936 halbtc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist,
937 coex_dm->cur_rf_rx_lpf_shrink);
938
939 coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
940}
941
942void halbtc8192e2ant_set_sw_penalty_tx_rateadaptive(
943 struct btc_coexist *btcoexist,
944 bool low_penalty_ra)
945{
946 u8 h2c_parameter[6] ={0};
947
948 h2c_parameter[0] = 0x6; /* opCode, 0x6= Retry_Penalty */
949
950 if (low_penalty_ra) {
951 h2c_parameter[1] |= BIT0;
952 /* normal rate except MCS7/6/5, OFDM54/48/36 */
953 h2c_parameter[2] = 0x00;
954 h2c_parameter[3] = 0xf7; /* MCS7 or OFDM54 */
955 h2c_parameter[4] = 0xf8; /* MCS6 or OFDM48 */
956 h2c_parameter[5] = 0xf9; /* MCS5 or OFDM36 */
957 }
958
959 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
960 "[BTCoex], set WiFi Low-Penalty Retry: %s",
961 (low_penalty_ra? "ON!!":"OFF!!"));
962
963 btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
964}
965
966void halbtc8192e2ant_low_penalty_ra(struct btc_coexist *btcoexist,
967 bool force_exec, bool low_penalty_ra)
968{
969 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
970 "[BTCoex], %s turn LowPenaltyRA = %s\n",
971 (force_exec? "force to":""), ((low_penalty_ra)? "ON":"OFF"));
972 coex_dm->cur_low_penalty_ra = low_penalty_ra;
973
974 if (!force_exec) {
975 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
976 "[BTCoex] bPreLowPenaltyRa=%d, bCurLowPenaltyRa=%d\n",
977 coex_dm->pre_low_penalty_ra,
978 coex_dm->cur_low_penalty_ra);
979
980 if (coex_dm->pre_low_penalty_ra ==
981 coex_dm->cur_low_penalty_ra)
982 return;
983 }
984 halbtc8192e2ant_set_sw_penalty_tx_rateadaptive(btcoexist,
985 coex_dm->cur_low_penalty_ra);
986
987 coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
988}
989
990void halbtc8192e2ant_set_dac_swingreg(struct btc_coexist *btcoexist,
991 u32 level)
992{
993 u8 val = (u8)level;
994
995 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
996 "[BTCoex], Write SwDacSwing = 0x%x\n", level);
997 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
998}
999
1000void halbtc8192e2ant_setsw_fulltime_dacswing(struct btc_coexist *btcoexist,
1001 bool sw_dac_swingon,
1002 u32 sw_dac_swinglvl)
1003{
1004 if (sw_dac_swingon)
1005 halbtc8192e2ant_set_dac_swingreg(btcoexist, sw_dac_swinglvl);
1006 else
1007 halbtc8192e2ant_set_dac_swingreg(btcoexist, 0x18);
1008}
1009
1010
1011void halbtc8192e2ant_DacSwing(struct btc_coexist *btcoexist,
1012 bool force_exec, bool dac_swingon,
1013 u32 dac_swinglvl)
1014{
1015 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
1016 "[BTCoex], %s turn DacSwing=%s, dac_swinglvl=0x%x\n",
1017 (force_exec? "force to":""),
1018 ((dac_swingon)? "ON":"OFF"), dac_swinglvl);
1019 coex_dm->cur_dac_swing_on = dac_swingon;
1020 coex_dm->cur_dac_swing_lvl = dac_swinglvl;
1021
1022 if (!force_exec) {
1023 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1024 "[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl=0x%x, ",
1025 coex_dm->pre_dac_swing_on,
1026 coex_dm->pre_dac_swing_lvl);
1027 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1028 "bCurDacSwingOn=%d, curDacSwingLvl=0x%x\n",
1029 coex_dm->cur_dac_swing_on,
1030 coex_dm->cur_dac_swing_lvl);
1031
1032 if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
1033 (coex_dm->pre_dac_swing_lvl == coex_dm->cur_dac_swing_lvl))
1034 return;
1035 }
1036 mdelay(30);
1037 halbtc8192e2ant_setsw_fulltime_dacswing(btcoexist, dac_swingon,
1038 dac_swinglvl);
1039
1040 coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
1041 coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
1042}
1043
1044void halbtc8192e2ant_set_adc_backoff(struct btc_coexist *btcoexist,
1045 bool adc_backoff)
1046{
1047 if(adc_backoff)
1048 {
1049 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1050 "[BTCoex], BB BackOff Level On!\n");
1051 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3);
1052 }
1053 else
1054 {
1055 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1056 "[BTCoex], BB BackOff Level Off!\n");
1057 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1);
1058 }
1059}
1060
1061void halbtc8192e2ant_adc_backoff(struct btc_coexist *btcoexist,
1062 bool force_exec, bool adc_backoff)
1063{
1064 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
1065 "[BTCoex], %s turn AdcBackOff = %s\n",
1066 (force_exec? "force to":""), ((adc_backoff)? "ON":"OFF"));
1067 coex_dm->cur_adc_back_off = adc_backoff;
1068
1069 if (!force_exec) {
1070 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1071 "[BTCoex], bPreAdcBackOff=%d, bCurAdcBackOff=%d\n",
1072 coex_dm->pre_adc_back_off, coex_dm->cur_adc_back_off);
1073
1074 if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
1075 return;
1076 }
1077 halbtc8192e2ant_set_adc_backoff(btcoexist, coex_dm->cur_adc_back_off);
1078
1079 coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
1080}
1081
1082void halbtc8192e2ant_set_agc_table(struct btc_coexist *btcoexist,
1083 bool agc_table_en)
1084{
1085
1086 /* BB AGC Gain Table */
1087 if (agc_table_en) {
1088 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1089 "[BTCoex], BB Agc Table On!\n");
1090 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001);
1091 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001);
1092 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001);
1093 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001);
1094 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001);
1095 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001);
1096 } else {
1097 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1098 "[BTCoex], BB Agc Table Off!\n");
1099 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
1100 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
1101 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
1102 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
1103 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
1104 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
1105 }
1106}
1107
1108void halbtc8192e2ant_AgcTable(struct btc_coexist *btcoexist,
1109 bool force_exec, bool agc_table_en)
1110{
1111 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
1112 "[BTCoex], %s %s Agc Table\n",
1113 (force_exec? "force to":""),
1114 ((agc_table_en)? "Enable":"Disable"));
1115 coex_dm->cur_agc_table_en = agc_table_en;
1116
1117 if (!force_exec) {
1118 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1119 "[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n",
1120 coex_dm->pre_agc_table_en, coex_dm->cur_agc_table_en);
1121
1122 if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
1123 return;
1124 }
1125 halbtc8192e2ant_set_agc_table(btcoexist, agc_table_en);
1126
1127 coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
1128}
1129
1130void halbtc8192e2ant_set_coex_table(struct btc_coexist *btcoexist,
1131 u32 val0x6c0, u32 val0x6c4,
1132 u32 val0x6c8, u8 val0x6cc)
1133{
1134 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1135 "[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0);
1136 btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
1137
1138 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1139 "[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4);
1140 btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
1141
1142 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1143 "[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8);
1144 btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
1145
1146 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1147 "[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc);
1148 btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
1149}
1150
1151void halbtc8192e2ant_coex_table(struct btc_coexist *btcoexist, bool force_exec,
1152 u32 val0x6c0, u32 val0x6c4,
1153 u32 val0x6c8, u8 val0x6cc)
1154{
1155 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
1156 "[BTCoex], %s write Coex Table 0x6c0=0x%x, ",
1157 (force_exec? "force to":""), val0x6c0);
1158 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
1159 "0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
1160 val0x6c4, val0x6c8, val0x6cc);
1161 coex_dm->cur_val0x6c0 = val0x6c0;
1162 coex_dm->cur_val0x6c4 = val0x6c4;
1163 coex_dm->cur_val0x6c8 = val0x6c8;
1164 coex_dm->cur_val0x6cc = val0x6cc;
1165
1166 if (!force_exec) {
1167 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1168 "[BTCoex], preVal0x6c0=0x%x, preVal0x6c4=0x%x, ",
1169 coex_dm->pre_val0x6c0, coex_dm->pre_val0x6c4);
1170 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1171 "preVal0x6c8=0x%x, preVal0x6cc=0x%x !!\n",
1172 coex_dm->pre_val0x6c8, coex_dm->pre_val0x6cc);
1173 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1174 "[BTCoex], curVal0x6c0=0x%x, curVal0x6c4=0x%x, \n",
1175 coex_dm->cur_val0x6c0, coex_dm->cur_val0x6c4);
1176 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1177 "curVal0x6c8=0x%x, curVal0x6cc=0x%x !!\n",
1178 coex_dm->cur_val0x6c8, coex_dm->cur_val0x6cc);
1179
1180 if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
1181 (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
1182 (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
1183 (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
1184 return;
1185 }
1186 halbtc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4,
1187 val0x6c8, val0x6cc);
1188
1189 coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
1190 coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
1191 coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
1192 coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
1193}
1194
1195void halbtc8192e2ant_coex_table_with_type(struct btc_coexist *btcoexist,
1196 bool force_exec, u8 type)
1197{
1198 switch (type) {
1199 case 0:
1200 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
1201 0x5a5a5a5a, 0xffffff, 0x3);
1202 break;
1203 case 1:
1204 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
1205 0x5a5a5a5a, 0xffffff, 0x3);
1206 break;
1207 case 2:
1208 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
1209 0x5ffb5ffb, 0xffffff, 0x3);
1210 break;
1211 case 3:
1212 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
1213 0x5fdb5fdb, 0xffffff, 0x3);
1214 break;
1215 case 4:
1216 halbtc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
1217 0x5ffb5ffb, 0xffffff, 0x3);
1218 break;
1219 default:
1220 break;
1221 }
1222}
1223
1224void halbtc8192e2ant_set_fw_ignore_wlanact(struct btc_coexist *btcoexist,
1225 bool enable)
1226{
1227 u8 h2c_parameter[1] ={0};
1228
1229 if (enable)
1230 h2c_parameter[0] |= BIT0; /* function enable */
1231
1232 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
1233 "[BTCoex]set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n",
1234 h2c_parameter[0]);
1235
1236 btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
1237}
1238
1239void halbtc8192e2ant_IgnoreWlanAct(struct btc_coexist *btcoexist,
1240 bool force_exec, bool enable)
1241{
1242 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
1243 "[BTCoex], %s turn Ignore WlanAct %s\n",
1244 (force_exec? "force to":""), (enable? "ON":"OFF"));
1245 coex_dm->cur_ignore_wlan_act = enable;
1246
1247 if (!force_exec) {
1248 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1249 "[BTCoex], bPreIgnoreWlanAct = %d ",
1250 coex_dm->pre_ignore_wlan_act);
1251 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1252 "bCurIgnoreWlanAct = %d!!\n",
1253 coex_dm->cur_ignore_wlan_act);
1254
1255 if (coex_dm->pre_ignore_wlan_act ==
1256 coex_dm->cur_ignore_wlan_act)
1257 return;
1258 }
1259 halbtc8192e2ant_set_fw_ignore_wlanact(btcoexist, enable);
1260
1261 coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
1262}
1263
1264void halbtc8192e2ant_SetFwPstdma(struct btc_coexist *btcoexist, u8 byte1,
1265 u8 byte2, u8 byte3, u8 byte4, u8 byte5)
1266{
1267 u8 h2c_parameter[5] ={0};
1268
1269 h2c_parameter[0] = byte1;
1270 h2c_parameter[1] = byte2;
1271 h2c_parameter[2] = byte3;
1272 h2c_parameter[3] = byte4;
1273 h2c_parameter[4] = byte5;
1274
1275 coex_dm->ps_tdma_para[0] = byte1;
1276 coex_dm->ps_tdma_para[1] = byte2;
1277 coex_dm->ps_tdma_para[2] = byte3;
1278 coex_dm->ps_tdma_para[3] = byte4;
1279 coex_dm->ps_tdma_para[4] = byte5;
1280
1281 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
1282 "[BTCoex], FW write 0x60(5bytes)=0x%x%08x\n",
1283 h2c_parameter[0],
1284 h2c_parameter[1] << 24 | h2c_parameter[2] << 16 |
1285 h2c_parameter[3] << 8 | h2c_parameter[4]);
1286
1287 btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
1288}
1289
1290void halbtc8192e2ant_sw_mechanism1(struct btc_coexist *btcoexist,
1291 bool shrink_rx_lpf, bool low_penalty_ra,
1292 bool limited_dig, bool btlan_constrain)
1293{
1294 halbtc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
1295}
1296
1297void halbtc8192e2ant_sw_mechanism2(struct btc_coexist *btcoexist,
1298 bool agc_table_shift, bool adc_backoff,
1299 bool sw_dac_swing, u32 dac_swinglvl)
1300{
1301 halbtc8192e2ant_AgcTable(btcoexist, NORMAL_EXEC, agc_table_shift);
1302 halbtc8192e2ant_DacSwing(btcoexist, NORMAL_EXEC, sw_dac_swing,
1303 dac_swinglvl);
1304}
1305
1306void halbtc8192e2ant_ps_tdma(struct btc_coexist *btcoexist,
1307 bool force_exec, bool turn_on, u8 type)
1308{
1309
1310 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
1311 "[BTCoex], %s turn %s PS TDMA, type=%d\n",
1312 (force_exec? "force to":""), (turn_on? "ON":"OFF"), type);
1313 coex_dm->cur_ps_tdma_on = turn_on;
1314 coex_dm->cur_ps_tdma = type;
1315
1316 if (!force_exec) {
1317 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1318 "[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n",
1319 coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on);
1320 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1321 "[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n",
1322 coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma);
1323
1324 if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
1325 (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
1326 return;
1327 }
1328 if (turn_on) {
1329 switch (type) {
1330 case 1:
1331 default:
1332 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
1333 0x1a, 0xe1, 0x90);
1334 break;
1335 case 2:
1336 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
1337 0x12, 0xe1, 0x90);
1338 break;
1339 case 3:
1340 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
1341 0x3, 0xf1, 0x90);
1342 break;
1343 case 4:
1344 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x10,
1345 0x3, 0xf1, 0x90);
1346 break;
1347 case 5:
1348 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
1349 0x1a, 0x60, 0x90);
1350 break;
1351 case 6:
1352 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
1353 0x12, 0x60, 0x90);
1354 break;
1355 case 7:
1356 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
1357 0x3, 0x70, 0x90);
1358 break;
1359 case 8:
1360 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xa3, 0x10,
1361 0x3, 0x70, 0x90);
1362 break;
1363 case 9:
1364 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
1365 0x1a, 0xe1, 0x10);
1366 break;
1367 case 10:
1368 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
1369 0x12, 0xe1, 0x10);
1370 break;
1371 case 11:
1372 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
1373 0x3, 0xf1, 0x10);
1374 break;
1375 case 12:
1376 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x10,
1377 0x3, 0xf1, 0x10);
1378 break;
1379 case 13:
1380 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
1381 0x1a, 0xe0, 0x10);
1382 break;
1383 case 14:
1384 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
1385 0x12, 0xe0, 0x10);
1386 break;
1387 case 15:
1388 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1c,
1389 0x3, 0xf0, 0x10);
1390 break;
1391 case 16:
1392 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x12,
1393 0x3, 0xf0, 0x10);
1394 break;
1395 case 17:
1396 halbtc8192e2ant_SetFwPstdma(btcoexist, 0x61, 0x20,
1397 0x03, 0x10, 0x10);
1398 break;
1399 case 18:
1400 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x5,
1401 0x5, 0xe1, 0x90);
1402 break;
1403 case 19:
1404 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x25,
1405 0x25, 0xe1, 0x90);
1406 break;
1407 case 20:
1408 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x25,
1409 0x25, 0x60, 0x90);
1410 break;
1411 case 21:
1412 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x15,
1413 0x03, 0x70, 0x90);
1414 break;
1415 case 71:
1416 halbtc8192e2ant_SetFwPstdma(btcoexist, 0xe3, 0x1a,
1417 0x1a, 0xe1, 0x90);
1418 break;
1419 }
1420 } else {
1421 /* disable PS tdma */
1422 switch (type) {
1423 default:
1424 case 0:
1425 halbtc8192e2ant_SetFwPstdma(btcoexist, 0x8, 0x0, 0x0,
1426 0x0, 0x0);
1427 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
1428 break;
1429 case 1:
1430 halbtc8192e2ant_SetFwPstdma(btcoexist, 0x0, 0x0, 0x0,
1431 0x8, 0x0);
1432 mdelay(5);
1433 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
1434 break;
1435 }
1436 }
1437
1438 /* update pre state */
1439 coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
1440 coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
1441}
1442
1443void halbtc8192e2ant_set_switch_sstype(struct btc_coexist *btcoexist, u8 sstype)
1444{
1445 u8 mimops = BTC_MIMO_PS_DYNAMIC;
1446 u32 disra_mask = 0x0;
1447
1448 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1449 "[BTCoex], REAL set SS Type = %d\n", sstype);
1450
1451 disra_mask = halbtc8192e2ant_decidera_mask(btcoexist, sstype,
1452 coex_dm->curra_masktype);
1453 halbtc8192e2ant_Updatera_mask(btcoexist, FORCE_EXEC, disra_mask);
1454
1455 if (sstype == 1) {
1456 halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
1457 /* switch ofdm path */
1458 btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11);
1459 btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1);
1460 btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111);
1461 /* switch cck patch */
1462 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1);
1463 btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81);
1464 mimops=BTC_MIMO_PS_STATIC;
1465 } else if (sstype == 2) {
1466 halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
1467 btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33);
1468 btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3);
1469 btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313);
1470 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0);
1471 btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41);
1472 mimops=BTC_MIMO_PS_DYNAMIC;
1473 }
1474 /* set rx 1ss or 2ss */
1475 btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS, &mimops);
1476}
1477
1478void halbtc8192e2ant_switch_sstype(struct btc_coexist *btcoexist,
1479 bool force_exec, u8 new_sstype)
1480{
1481 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1482 "[BTCoex], %s Switch SS Type = %d\n",
1483 (force_exec? "force to":""), new_sstype);
1484 coex_dm->cur_sstype = new_sstype;
1485
1486 if (!force_exec) {
1487 if (coex_dm->pre_sstype == coex_dm->cur_sstype)
1488 return;
1489 }
1490 halbtc8192e2ant_set_switch_sstype(btcoexist, coex_dm->cur_sstype);
1491
1492 coex_dm->pre_sstype = coex_dm->cur_sstype;
1493}
1494
1495void halbtc8192e2ant_coex_alloff(struct btc_coexist *btcoexist)
1496{
1497 /* fw all off */
1498 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
1499 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
1500 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
1501
1502 /* sw all off */
1503 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
1504 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
1505
1506 /* hw all off */
1507 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
1508}
1509
1510void halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist)
1511{
1512 /* force to reset coex mechanism */
1513
1514 halbtc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
1515 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, FORCE_EXEC, 6);
1516 halbtc8192e2ant_dec_btpwr(btcoexist, FORCE_EXEC, 0);
1517
1518 halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
1519 halbtc8192e2ant_switch_sstype(btcoexist, FORCE_EXEC, 2);
1520
1521 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
1522 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
1523}
1524
1525void halbtc8192e2ant_action_bt_inquiry(struct btc_coexist *btcoexist)
1526{
1527 bool low_pwr_disable = true;
1528
1529 btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
1530 &low_pwr_disable);
1531
1532 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
1533
1534 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
1535 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
1536 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
1537 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
1538
1539 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
1540 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
1541}
1542
1543bool halbtc8192e2ant_is_common_action(struct btc_coexist *btcoexist)
1544{
1545 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
1546 bool common = false, wifi_connected = false, wifi_busy = false;
1547 bool bt_hson = false, low_pwr_disable = false;
1548
1549 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
1550 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
1551 &wifi_connected);
1552 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
1553
1554 if (bt_link_info->sco_exist || bt_link_info->hid_exist)
1555 halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0);
1556 else
1557 halbtc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
1558
1559 if (!wifi_connected) {
1560 low_pwr_disable = false;
1561 btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
1562 &low_pwr_disable);
1563
1564 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1565 "[BTCoex], Wifi non-connected idle!!\n");
1566
1567 if ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
1568 coex_dm->bt_status) ||
1569 (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
1570 coex_dm->bt_status)) {
1571 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC,
1572 2);
1573 halbtc8192e2ant_coex_table_with_type(btcoexist,
1574 NORMAL_EXEC, 1);
1575 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
1576 0);
1577 } else {
1578 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC,
1579 1);
1580 halbtc8192e2ant_coex_table_with_type(btcoexist,
1581 NORMAL_EXEC, 0);
1582 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
1583 1);
1584 }
1585
1586 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
1587 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
1588
1589 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false, false,
1590 false);
1591 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false, false,
1592 0x18);
1593
1594 common = true;
1595 } else {
1596 if (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
1597 coex_dm->bt_status) {
1598 low_pwr_disable = false;
1599 btcoexist->btc_set(btcoexist,
1600 BTC_SET_ACT_DISABLE_LOW_POWER,
1601 &low_pwr_disable);
1602
1603 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1604 "Wifi connected + BT non connected-idle!!\n");
1605
1606 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC,
1607 2);
1608 halbtc8192e2ant_coex_table_with_type(btcoexist,
1609 NORMAL_EXEC, 1);
1610 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
1611 0);
1612 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC,
1613 6);
1614 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
1615
1616 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
1617 false, false);
1618 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
1619 false, 0x18);
1620
1621 common = true;
1622 } else if (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
1623 coex_dm->bt_status) {
1624 low_pwr_disable = true;
1625 btcoexist->btc_set(btcoexist,
1626 BTC_SET_ACT_DISABLE_LOW_POWER,
1627 &low_pwr_disable);
1628
1629 if (bt_hson)
1630 return false;
1631 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1632 "Wifi connected + BT connected-idle!!\n");
1633
1634 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC,
1635 2);
1636 halbtc8192e2ant_coex_table_with_type(btcoexist,
1637 NORMAL_EXEC, 1);
1638 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
1639 0);
1640 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC,
1641 6);
1642 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
1643
1644 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
1645 false, false);
1646 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
1647 false, 0x18);
1648
1649 common = true;
1650 } else {
1651 low_pwr_disable = true;
1652 btcoexist->btc_set(btcoexist,
1653 BTC_SET_ACT_DISABLE_LOW_POWER,
1654 &low_pwr_disable);
1655
1656 if (wifi_busy) {
1657 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1658 "Wifi Connected-Busy + BT Busy!!\n");
1659 common = false;
1660 } else {
1661 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1662 "Wifi Connected-Idle + BT Busy!!\n");
1663
1664 halbtc8192e2ant_switch_sstype(btcoexist,
1665 NORMAL_EXEC, 1);
1666 halbtc8192e2ant_coex_table_with_type(btcoexist,
1667 NORMAL_EXEC,
1668 2);
1669 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1670 true, 21);
1671 halbtc8192e2ant_fw_dac_swinglvl(btcoexist,
1672 NORMAL_EXEC, 6);
1673 halbtc8192e2ant_dec_btpwr(btcoexist,
1674 NORMAL_EXEC, 0);
1675 halbtc8192e2ant_sw_mechanism1(btcoexist, false,
1676 false, false,
1677 false);
1678 halbtc8192e2ant_sw_mechanism2(btcoexist, false,
1679 false, false,
1680 0x18);
1681 common = true;
1682 }
1683 }
1684 }
1685 return common;
1686}
1687
1688void halbtc8192e2ant_tdma_duration_adjust(struct btc_coexist *btcoexist,
1689 bool sco_hid, bool tx_pause,
1690 u8 max_interval)
1691{
1692 static int up, dn, m, n, wait_cnt;
1693 /* 0: no change, +1: increase WiFi duration,
1694 * -1: decrease WiFi duration */
1695 int result;
1696 u8 retry_cnt = 0;
1697
1698 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
1699 "[BTCoex], TdmaDurationAdjust()\n");
1700
1701 if (!coex_dm->auto_tdma_adjust) {
1702 coex_dm->auto_tdma_adjust = true;
1703 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1704 "[BTCoex], first run TdmaDurationAdjust()!!\n");
1705 if (sco_hid) {
1706 if (tx_pause) {
1707 if (max_interval == 1) {
1708 halbtc8192e2ant_ps_tdma(btcoexist,
1709 NORMAL_EXEC,
1710 true, 13);
1711 coex_dm->ps_tdma_du_adj_type = 13;
1712 } else if (max_interval == 2) {
1713 halbtc8192e2ant_ps_tdma(btcoexist,
1714 NORMAL_EXEC,
1715 true, 14);
1716 coex_dm->ps_tdma_du_adj_type = 14;
1717 } else if (max_interval == 3) {
1718 halbtc8192e2ant_ps_tdma(btcoexist,
1719 NORMAL_EXEC,
1720 true, 15);
1721 coex_dm->ps_tdma_du_adj_type = 15;
1722 } else {
1723 halbtc8192e2ant_ps_tdma(btcoexist,
1724 NORMAL_EXEC,
1725 true, 15);
1726 coex_dm->ps_tdma_du_adj_type = 15;
1727 }
1728 } else {
1729 if (max_interval == 1) {
1730 halbtc8192e2ant_ps_tdma(btcoexist,
1731 NORMAL_EXEC,
1732 true, 9);
1733 coex_dm->ps_tdma_du_adj_type = 9;
1734 } else if (max_interval == 2) {
1735 halbtc8192e2ant_ps_tdma(btcoexist,
1736 NORMAL_EXEC,
1737 true, 10);
1738 coex_dm->ps_tdma_du_adj_type = 10;
1739 } else if (max_interval == 3) {
1740 halbtc8192e2ant_ps_tdma(btcoexist,
1741 NORMAL_EXEC,
1742 true, 11);
1743 coex_dm->ps_tdma_du_adj_type = 11;
1744 } else {
1745 halbtc8192e2ant_ps_tdma(btcoexist,
1746 NORMAL_EXEC,
1747 true, 11);
1748 coex_dm->ps_tdma_du_adj_type = 11;
1749 }
1750 }
1751 } else {
1752 if (tx_pause) {
1753 if (max_interval == 1) {
1754 halbtc8192e2ant_ps_tdma(btcoexist,
1755 NORMAL_EXEC,
1756 true, 5);
1757 coex_dm->ps_tdma_du_adj_type = 5;
1758 } else if (max_interval == 2) {
1759 halbtc8192e2ant_ps_tdma(btcoexist,
1760 NORMAL_EXEC,
1761 true, 6);
1762 coex_dm->ps_tdma_du_adj_type = 6;
1763 } else if (max_interval == 3) {
1764 halbtc8192e2ant_ps_tdma(btcoexist,
1765 NORMAL_EXEC,
1766 true, 7);
1767 coex_dm->ps_tdma_du_adj_type = 7;
1768 } else {
1769 halbtc8192e2ant_ps_tdma(btcoexist,
1770 NORMAL_EXEC,
1771 true, 7);
1772 coex_dm->ps_tdma_du_adj_type = 7;
1773 }
1774 } else {
1775 if (max_interval == 1) {
1776 halbtc8192e2ant_ps_tdma(btcoexist,
1777 NORMAL_EXEC,
1778 true, 1);
1779 coex_dm->ps_tdma_du_adj_type = 1;
1780 } else if (max_interval == 2) {
1781 halbtc8192e2ant_ps_tdma(btcoexist,
1782 NORMAL_EXEC,
1783 true, 2);
1784 coex_dm->ps_tdma_du_adj_type = 2;
1785 } else if (max_interval == 3) {
1786 halbtc8192e2ant_ps_tdma(btcoexist,
1787 NORMAL_EXEC,
1788 true, 3);
1789 coex_dm->ps_tdma_du_adj_type = 3;
1790 } else {
1791 halbtc8192e2ant_ps_tdma(btcoexist,
1792 NORMAL_EXEC,
1793 true, 3);
1794 coex_dm->ps_tdma_du_adj_type = 3;
1795 }
1796 }
1797 }
1798
1799 up = 0;
1800 dn = 0;
1801 m = 1;
1802 n= 3;
1803 result = 0;
1804 wait_cnt = 0;
1805 } else {
1806 /* accquire the BT TRx retry count from BT_Info byte2 */
1807 retry_cnt = coex_sta->bt_retry_cnt;
1808 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1809 "[BTCoex], retry_cnt = %d\n", retry_cnt);
1810 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1811 "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_cnt=%d\n",
1812 up, dn, m, n, wait_cnt);
1813 result = 0;
1814 wait_cnt++;
1815 /* no retry in the last 2-second duration */
1816 if (retry_cnt == 0) {
1817 up++;
1818 dn--;
1819
1820 if (dn <= 0)
1821 dn = 0;
1822
1823 if (up >= n) {
1824 wait_cnt = 0;
1825 n = 3;
1826 up = 0;
1827 dn = 0;
1828 result = 1;
1829 BTC_PRINT(BTC_MSG_ALGORITHM,
1830 ALGO_TRACE_FW_DETAIL,
1831 "[BTCoex]Increase wifi duration!!\n");
1832 }
1833 } else if (retry_cnt <= 3) {
1834 up--;
1835 dn++;
1836
1837 if (up <= 0)
1838 up = 0;
1839
1840 if (dn == 2) {
1841 if (wait_cnt <= 2)
1842 m++;
1843 else
1844 m = 1;
1845
1846 if (m >= 20)
1847 m = 20;
1848
1849 n = 3 * m;
1850 up = 0;
1851 dn = 0;
1852 wait_cnt = 0;
1853 result = -1;
1854 BTC_PRINT(BTC_MSG_ALGORITHM,
1855 ALGO_TRACE_FW_DETAIL,
1856 "Reduce wifi duration for retry<3\n");
1857 }
1858 } else {
1859 if (wait_cnt == 1)
1860 m++;
1861 else
1862 m = 1;
1863
1864 if (m >= 20)
1865 m = 20;
1866
1867 n = 3*m;
1868 up = 0;
1869 dn = 0;
1870 wait_cnt = 0;
1871 result = -1;
1872 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1873 "Decrease wifi duration for retryCounter>3!!\n");
1874 }
1875
1876 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1877 "[BTCoex], max Interval = %d\n", max_interval);
1878 if (max_interval == 1) {
1879 if (tx_pause) {
1880 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1881 "[BTCoex], TxPause = 1\n");
1882
1883 if (coex_dm->cur_ps_tdma == 71) {
1884 halbtc8192e2ant_ps_tdma(btcoexist,
1885 NORMAL_EXEC,
1886 true, 5);
1887 coex_dm->ps_tdma_du_adj_type = 5;
1888 } else if (coex_dm->cur_ps_tdma == 1) {
1889 halbtc8192e2ant_ps_tdma(btcoexist,
1890 NORMAL_EXEC,
1891 true, 5);
1892 coex_dm->ps_tdma_du_adj_type = 5;
1893 } else if (coex_dm->cur_ps_tdma == 2) {
1894 halbtc8192e2ant_ps_tdma(btcoexist,
1895 NORMAL_EXEC,
1896 true, 6);
1897 coex_dm->ps_tdma_du_adj_type = 6;
1898 } else if (coex_dm->cur_ps_tdma == 3) {
1899 halbtc8192e2ant_ps_tdma(btcoexist,
1900 NORMAL_EXEC,
1901 true, 7);
1902 coex_dm->ps_tdma_du_adj_type = 7;
1903 } else if (coex_dm->cur_ps_tdma == 4) {
1904 halbtc8192e2ant_ps_tdma(btcoexist,
1905 NORMAL_EXEC,
1906 true, 8);
1907 coex_dm->ps_tdma_du_adj_type = 8;
1908 }
1909 if (coex_dm->cur_ps_tdma == 9) {
1910 halbtc8192e2ant_ps_tdma(btcoexist,
1911 NORMAL_EXEC,
1912 true, 13);
1913 coex_dm->ps_tdma_du_adj_type = 13;
1914 } else if (coex_dm->cur_ps_tdma == 10) {
1915 halbtc8192e2ant_ps_tdma(btcoexist,
1916 NORMAL_EXEC,
1917 true, 14);
1918 coex_dm->ps_tdma_du_adj_type = 14;
1919 } else if (coex_dm->cur_ps_tdma == 11) {
1920 halbtc8192e2ant_ps_tdma(btcoexist,
1921 NORMAL_EXEC,
1922 true, 15);
1923 coex_dm->ps_tdma_du_adj_type = 15;
1924 } else if (coex_dm->cur_ps_tdma == 12) {
1925 halbtc8192e2ant_ps_tdma(btcoexist,
1926 NORMAL_EXEC,
1927 true, 16);
1928 coex_dm->ps_tdma_du_adj_type = 16;
1929 }
1930
1931 if (result == -1) {
1932 if (coex_dm->cur_ps_tdma == 5) {
1933 halbtc8192e2ant_ps_tdma(
1934 btcoexist,
1935 NORMAL_EXEC,
1936 true, 6);
1937 coex_dm->ps_tdma_du_adj_type =
1938 6;
1939 } else if (coex_dm->cur_ps_tdma == 6) {
1940 halbtc8192e2ant_ps_tdma(
1941 btcoexist,
1942 NORMAL_EXEC,
1943 true, 7);
1944 coex_dm->ps_tdma_du_adj_type =
1945 7;
1946 } else if (coex_dm->cur_ps_tdma == 7) {
1947 halbtc8192e2ant_ps_tdma(
1948 btcoexist,
1949 NORMAL_EXEC,
1950 true, 8);
1951 coex_dm->ps_tdma_du_adj_type =
1952 8;
1953 } else if (coex_dm->cur_ps_tdma == 13) {
1954 halbtc8192e2ant_ps_tdma(
1955 btcoexist,
1956 NORMAL_EXEC,
1957 true, 14);
1958 coex_dm->ps_tdma_du_adj_type =
1959 14;
1960 } else if (coex_dm->cur_ps_tdma == 14) {
1961 halbtc8192e2ant_ps_tdma(
1962 btcoexist,
1963 NORMAL_EXEC,
1964 true, 15);
1965 coex_dm->ps_tdma_du_adj_type =
1966 15;
1967 } else if (coex_dm->cur_ps_tdma == 15) {
1968 halbtc8192e2ant_ps_tdma(
1969 btcoexist,
1970 NORMAL_EXEC,
1971 true, 16);
1972 coex_dm->ps_tdma_du_adj_type =
1973 16;
1974 }
1975 } else if (result == 1) {
1976 if (coex_dm->cur_ps_tdma == 8) {
1977 halbtc8192e2ant_ps_tdma(
1978 btcoexist,
1979 NORMAL_EXEC,
1980 true, 7);
1981 coex_dm->ps_tdma_du_adj_type =
1982 7;
1983 } else if (coex_dm->cur_ps_tdma == 7) {
1984 halbtc8192e2ant_ps_tdma(
1985 btcoexist,
1986 NORMAL_EXEC,
1987 true, 6);
1988 coex_dm->ps_tdma_du_adj_type =
1989 6;
1990 } else if (coex_dm->cur_ps_tdma == 6) {
1991 halbtc8192e2ant_ps_tdma(
1992 btcoexist,
1993 NORMAL_EXEC,
1994 true, 5);
1995 coex_dm->ps_tdma_du_adj_type =
1996 5;
1997 } else if (coex_dm->cur_ps_tdma == 16) {
1998 halbtc8192e2ant_ps_tdma(
1999 btcoexist,
2000 NORMAL_EXEC,
2001 true, 15);
2002 coex_dm->ps_tdma_du_adj_type =
2003 15;
2004 } else if (coex_dm->cur_ps_tdma == 15) {
2005 halbtc8192e2ant_ps_tdma(
2006 btcoexist,
2007 NORMAL_EXEC,
2008 true, 14);
2009 coex_dm->ps_tdma_du_adj_type =
2010 14;
2011 } else if (coex_dm->cur_ps_tdma == 14) {
2012 halbtc8192e2ant_ps_tdma(
2013 btcoexist,
2014 NORMAL_EXEC,
2015 true, 13);
2016 coex_dm->ps_tdma_du_adj_type =
2017 13;
2018 }
2019 }
2020 } else {
2021 BTC_PRINT(BTC_MSG_ALGORITHM,
2022 ALGO_TRACE_FW_DETAIL,
2023 "[BTCoex], TxPause = 0\n");
2024 if (coex_dm->cur_ps_tdma == 5) {
2025 halbtc8192e2ant_ps_tdma(btcoexist,
2026 NORMAL_EXEC,
2027 true, 71);
2028 coex_dm->ps_tdma_du_adj_type = 71;
2029 } else if (coex_dm->cur_ps_tdma == 6) {
2030 halbtc8192e2ant_ps_tdma(btcoexist,
2031 NORMAL_EXEC,
2032 true, 2);
2033 coex_dm->ps_tdma_du_adj_type = 2;
2034 } else if (coex_dm->cur_ps_tdma == 7) {
2035 halbtc8192e2ant_ps_tdma(btcoexist,
2036 NORMAL_EXEC,
2037 true, 3);
2038 coex_dm->ps_tdma_du_adj_type = 3;
2039 } else if (coex_dm->cur_ps_tdma == 8) {
2040 halbtc8192e2ant_ps_tdma(btcoexist,
2041 NORMAL_EXEC,
2042 true, 4);
2043 coex_dm->ps_tdma_du_adj_type = 4;
2044 }
2045 if (coex_dm->cur_ps_tdma == 13) {
2046 halbtc8192e2ant_ps_tdma(btcoexist,
2047 NORMAL_EXEC,
2048 true, 9);
2049 coex_dm->ps_tdma_du_adj_type = 9;
2050 } else if (coex_dm->cur_ps_tdma == 14) {
2051 halbtc8192e2ant_ps_tdma(btcoexist,
2052 NORMAL_EXEC,
2053 true, 10);
2054 coex_dm->ps_tdma_du_adj_type = 10;
2055 } else if (coex_dm->cur_ps_tdma == 15) {
2056 halbtc8192e2ant_ps_tdma(btcoexist,
2057 NORMAL_EXEC,
2058 true, 11);
2059 coex_dm->ps_tdma_du_adj_type = 11;
2060 } else if (coex_dm->cur_ps_tdma == 16) {
2061 halbtc8192e2ant_ps_tdma(btcoexist,
2062 NORMAL_EXEC,
2063 true, 12);
2064 coex_dm->ps_tdma_du_adj_type = 12;
2065 }
2066
2067 if (result == -1) {
2068 if (coex_dm->cur_ps_tdma == 71) {
2069 halbtc8192e2ant_ps_tdma(
2070 btcoexist,
2071 NORMAL_EXEC,
2072 true, 1);
2073 coex_dm->ps_tdma_du_adj_type =
2074 1;
2075 } else if (coex_dm->cur_ps_tdma == 1) {
2076 halbtc8192e2ant_ps_tdma(
2077 btcoexist,
2078 NORMAL_EXEC,
2079 true, 2);
2080 coex_dm->ps_tdma_du_adj_type =
2081 2;
2082 } else if (coex_dm->cur_ps_tdma == 2) {
2083 halbtc8192e2ant_ps_tdma(
2084 btcoexist,
2085 NORMAL_EXEC,
2086 true, 3);
2087 coex_dm->ps_tdma_du_adj_type =
2088 3;
2089 } else if (coex_dm->cur_ps_tdma == 3) {
2090 halbtc8192e2ant_ps_tdma(
2091 btcoexist,
2092 NORMAL_EXEC,
2093 true, 4);
2094 coex_dm->ps_tdma_du_adj_type =
2095 4;
2096 } else if (coex_dm->cur_ps_tdma == 9) {
2097 halbtc8192e2ant_ps_tdma(
2098 btcoexist,
2099 NORMAL_EXEC,
2100 true, 10);
2101 coex_dm->ps_tdma_du_adj_type =
2102 10;
2103 } else if (coex_dm->cur_ps_tdma == 10) {
2104 halbtc8192e2ant_ps_tdma(
2105 btcoexist,
2106 NORMAL_EXEC,
2107 true, 11);
2108 coex_dm->ps_tdma_du_adj_type =
2109 11;
2110 } else if (coex_dm->cur_ps_tdma == 11) {
2111 halbtc8192e2ant_ps_tdma(
2112 btcoexist,
2113 NORMAL_EXEC,
2114 true, 12);
2115 coex_dm->ps_tdma_du_adj_type =
2116 12;
2117 }
2118 } else if (result == 1) {
2119 if (coex_dm->cur_ps_tdma == 4) {
2120 halbtc8192e2ant_ps_tdma(
2121 btcoexist,
2122 NORMAL_EXEC,
2123 true, 3);
2124 coex_dm->ps_tdma_du_adj_type =
2125 3;
2126 } else if (coex_dm->cur_ps_tdma == 3) {
2127 halbtc8192e2ant_ps_tdma(
2128 btcoexist,
2129 NORMAL_EXEC,
2130 true, 2);
2131 coex_dm->ps_tdma_du_adj_type =
2132 2;
2133 } else if (coex_dm->cur_ps_tdma == 2) {
2134 halbtc8192e2ant_ps_tdma(
2135 btcoexist,
2136 NORMAL_EXEC,
2137 true, 1);
2138 coex_dm->ps_tdma_du_adj_type =
2139 1;
2140 } else if (coex_dm->cur_ps_tdma == 1) {
2141 halbtc8192e2ant_ps_tdma(
2142 btcoexist,
2143 NORMAL_EXEC,
2144 true, 71);
2145 coex_dm->ps_tdma_du_adj_type =
2146 71;
2147 } else if (coex_dm->cur_ps_tdma == 12) {
2148 halbtc8192e2ant_ps_tdma(
2149 btcoexist,
2150 NORMAL_EXEC,
2151 true, 11);
2152 coex_dm->ps_tdma_du_adj_type =
2153 11;
2154 } else if (coex_dm->cur_ps_tdma == 11) {
2155 halbtc8192e2ant_ps_tdma(
2156 btcoexist,
2157 NORMAL_EXEC,
2158 true, 10);
2159 coex_dm->ps_tdma_du_adj_type =
2160 10;
2161 } else if (coex_dm->cur_ps_tdma == 10) {
2162 halbtc8192e2ant_ps_tdma(
2163 btcoexist,
2164 NORMAL_EXEC,
2165 true, 9);
2166 coex_dm->ps_tdma_du_adj_type =
2167 9;
2168 }
2169 }
2170 }
2171 } else if (max_interval == 2) {
2172 if (tx_pause) {
2173 BTC_PRINT(BTC_MSG_ALGORITHM,
2174 ALGO_TRACE_FW_DETAIL,
2175 "[BTCoex], TxPause = 1\n");
2176 if (coex_dm->cur_ps_tdma == 1) {
2177 halbtc8192e2ant_ps_tdma(btcoexist,
2178 NORMAL_EXEC,
2179 true, 6);
2180 coex_dm->ps_tdma_du_adj_type = 6;
2181 } else if (coex_dm->cur_ps_tdma == 2) {
2182 halbtc8192e2ant_ps_tdma(btcoexist,
2183 NORMAL_EXEC,
2184 true, 6);
2185 coex_dm->ps_tdma_du_adj_type = 6;
2186 } else if (coex_dm->cur_ps_tdma == 3) {
2187 halbtc8192e2ant_ps_tdma(btcoexist,
2188 NORMAL_EXEC,
2189 true, 7);
2190 coex_dm->ps_tdma_du_adj_type = 7;
2191 } else if (coex_dm->cur_ps_tdma == 4) {
2192 halbtc8192e2ant_ps_tdma(btcoexist,
2193 NORMAL_EXEC,
2194 true, 8);
2195 coex_dm->ps_tdma_du_adj_type = 8;
2196 }
2197 if (coex_dm->cur_ps_tdma == 9) {
2198 halbtc8192e2ant_ps_tdma(btcoexist,
2199 NORMAL_EXEC,
2200 true, 14);
2201 coex_dm->ps_tdma_du_adj_type = 14;
2202 } else if (coex_dm->cur_ps_tdma == 10) {
2203 halbtc8192e2ant_ps_tdma(btcoexist,
2204 NORMAL_EXEC,
2205 true, 14);
2206 coex_dm->ps_tdma_du_adj_type = 14;
2207 } else if (coex_dm->cur_ps_tdma == 11) {
2208 halbtc8192e2ant_ps_tdma(btcoexist,
2209 NORMAL_EXEC,
2210 true, 15);
2211 coex_dm->ps_tdma_du_adj_type = 15;
2212 } else if (coex_dm->cur_ps_tdma == 12) {
2213 halbtc8192e2ant_ps_tdma(btcoexist,
2214 NORMAL_EXEC,
2215 true, 16);
2216 coex_dm->ps_tdma_du_adj_type = 16;
2217 }
2218 if (result == -1) {
2219 if (coex_dm->cur_ps_tdma == 5) {
2220 halbtc8192e2ant_ps_tdma(
2221 btcoexist,
2222 NORMAL_EXEC,
2223 true, 6);
2224 coex_dm->ps_tdma_du_adj_type =
2225 6;
2226 } else if (coex_dm->cur_ps_tdma == 6) {
2227 halbtc8192e2ant_ps_tdma(
2228 btcoexist,
2229 NORMAL_EXEC,
2230 true, 7);
2231 coex_dm->ps_tdma_du_adj_type =
2232 7;
2233 } else if (coex_dm->cur_ps_tdma == 7) {
2234 halbtc8192e2ant_ps_tdma(
2235 btcoexist,
2236 NORMAL_EXEC,
2237 true, 8);
2238 coex_dm->ps_tdma_du_adj_type =
2239 8;
2240 } else if (coex_dm->cur_ps_tdma == 13) {
2241 halbtc8192e2ant_ps_tdma(
2242 btcoexist,
2243 NORMAL_EXEC,
2244 true, 14);
2245 coex_dm->ps_tdma_du_adj_type =
2246 14;
2247 } else if (coex_dm->cur_ps_tdma == 14) {
2248 halbtc8192e2ant_ps_tdma(
2249 btcoexist,
2250 NORMAL_EXEC,
2251 true, 15);
2252 coex_dm->ps_tdma_du_adj_type =
2253 15;
2254 } else if (coex_dm->cur_ps_tdma == 15) {
2255 halbtc8192e2ant_ps_tdma(
2256 btcoexist,
2257 NORMAL_EXEC,
2258 true, 16);
2259 coex_dm->ps_tdma_du_adj_type =
2260 16;
2261 }
2262 } else if (result == 1) {
2263 if (coex_dm->cur_ps_tdma == 8) {
2264 halbtc8192e2ant_ps_tdma(
2265 btcoexist,
2266 NORMAL_EXEC,
2267 true, 7);
2268 coex_dm->ps_tdma_du_adj_type =
2269 7;
2270 } else if (coex_dm->cur_ps_tdma == 7) {
2271 halbtc8192e2ant_ps_tdma(
2272 btcoexist,
2273 NORMAL_EXEC,
2274 true, 6);
2275 coex_dm->ps_tdma_du_adj_type =
2276 6;
2277 } else if (coex_dm->cur_ps_tdma == 6) {
2278 halbtc8192e2ant_ps_tdma(
2279 btcoexist,
2280 NORMAL_EXEC,
2281 true, 6);
2282 coex_dm->ps_tdma_du_adj_type =
2283 6;
2284 } else if (coex_dm->cur_ps_tdma == 16) {
2285 halbtc8192e2ant_ps_tdma(
2286 btcoexist,
2287 NORMAL_EXEC,
2288 true, 15);
2289 coex_dm->ps_tdma_du_adj_type =
2290 15;
2291 } else if (coex_dm->cur_ps_tdma == 15) {
2292 halbtc8192e2ant_ps_tdma(
2293 btcoexist,
2294 NORMAL_EXEC,
2295 true, 14);
2296 coex_dm->ps_tdma_du_adj_type =
2297 14;
2298 } else if (coex_dm->cur_ps_tdma == 14) {
2299 halbtc8192e2ant_ps_tdma(
2300 btcoexist,
2301 NORMAL_EXEC,
2302 true, 14);
2303 coex_dm->ps_tdma_du_adj_type =
2304 14;
2305 }
2306 }
2307 } else {
2308 BTC_PRINT(BTC_MSG_ALGORITHM,
2309 ALGO_TRACE_FW_DETAIL,
2310 "[BTCoex], TxPause = 0\n");
2311 if (coex_dm->cur_ps_tdma == 5) {
2312 halbtc8192e2ant_ps_tdma(btcoexist,
2313 NORMAL_EXEC,
2314 true, 2);
2315 coex_dm->ps_tdma_du_adj_type = 2;
2316 } else if (coex_dm->cur_ps_tdma == 6) {
2317 halbtc8192e2ant_ps_tdma(btcoexist,
2318 NORMAL_EXEC,
2319 true, 2);
2320 coex_dm->ps_tdma_du_adj_type = 2;
2321 } else if (coex_dm->cur_ps_tdma == 7) {
2322 halbtc8192e2ant_ps_tdma(btcoexist,
2323 NORMAL_EXEC,
2324 true, 3);
2325 coex_dm->ps_tdma_du_adj_type = 3;
2326 } else if (coex_dm->cur_ps_tdma == 8) {
2327 halbtc8192e2ant_ps_tdma(btcoexist,
2328 NORMAL_EXEC,
2329 true, 4);
2330 coex_dm->ps_tdma_du_adj_type = 4;
2331 }
2332 if (coex_dm->cur_ps_tdma == 13) {
2333 halbtc8192e2ant_ps_tdma(btcoexist,
2334 NORMAL_EXEC,
2335 true, 10);
2336 coex_dm->ps_tdma_du_adj_type = 10;
2337 } else if (coex_dm->cur_ps_tdma == 14) {
2338 halbtc8192e2ant_ps_tdma(btcoexist,
2339 NORMAL_EXEC,
2340 true, 10);
2341 coex_dm->ps_tdma_du_adj_type = 10;
2342 } else if (coex_dm->cur_ps_tdma == 15) {
2343 halbtc8192e2ant_ps_tdma(btcoexist,
2344 NORMAL_EXEC,
2345 true, 11);
2346 coex_dm->ps_tdma_du_adj_type = 11;
2347 } else if (coex_dm->cur_ps_tdma == 16) {
2348 halbtc8192e2ant_ps_tdma(btcoexist,
2349 NORMAL_EXEC,
2350 true, 12);
2351 coex_dm->ps_tdma_du_adj_type = 12;
2352 }
2353 if (result == -1) {
2354 if (coex_dm->cur_ps_tdma == 1) {
2355 halbtc8192e2ant_ps_tdma(
2356 btcoexist,
2357 NORMAL_EXEC,
2358 true, 2);
2359 coex_dm->ps_tdma_du_adj_type =
2360 2;
2361 } else if (coex_dm->cur_ps_tdma == 2) {
2362 halbtc8192e2ant_ps_tdma(
2363 btcoexist,
2364 NORMAL_EXEC,
2365 true, 3);
2366 coex_dm->ps_tdma_du_adj_type =
2367 3;
2368 } else if (coex_dm->cur_ps_tdma == 3) {
2369 halbtc8192e2ant_ps_tdma(
2370 btcoexist,
2371 NORMAL_EXEC,
2372 true, 4);
2373 coex_dm->ps_tdma_du_adj_type =
2374 4;
2375 } else if (coex_dm->cur_ps_tdma == 9) {
2376 halbtc8192e2ant_ps_tdma(
2377 btcoexist,
2378 NORMAL_EXEC,
2379 true, 10);
2380 coex_dm->ps_tdma_du_adj_type =
2381 10;
2382 } else if (coex_dm->cur_ps_tdma == 10) {
2383 halbtc8192e2ant_ps_tdma(
2384 btcoexist,
2385 NORMAL_EXEC,
2386 true, 11);
2387 coex_dm->ps_tdma_du_adj_type =
2388 11;
2389 } else if (coex_dm->cur_ps_tdma == 11) {
2390 halbtc8192e2ant_ps_tdma(
2391 btcoexist,
2392 NORMAL_EXEC,
2393 true, 12);
2394 coex_dm->ps_tdma_du_adj_type =
2395 12;
2396 }
2397 } else if (result == 1) {
2398 if (coex_dm->cur_ps_tdma == 4) {
2399 halbtc8192e2ant_ps_tdma(
2400 btcoexist,
2401 NORMAL_EXEC,
2402 true, 3);
2403 coex_dm->ps_tdma_du_adj_type =
2404 3;
2405 } else if (coex_dm->cur_ps_tdma == 3) {
2406 halbtc8192e2ant_ps_tdma(
2407 btcoexist,
2408 NORMAL_EXEC,
2409 true, 2);
2410 coex_dm->ps_tdma_du_adj_type =
2411 2;
2412 } else if (coex_dm->cur_ps_tdma == 2) {
2413 halbtc8192e2ant_ps_tdma(
2414 btcoexist,
2415 NORMAL_EXEC,
2416 true, 2);
2417 coex_dm->ps_tdma_du_adj_type =
2418 2;
2419 } else if(coex_dm->cur_ps_tdma == 12) {
2420 halbtc8192e2ant_ps_tdma(
2421 btcoexist,
2422 NORMAL_EXEC,
2423 true, 11);
2424 coex_dm->ps_tdma_du_adj_type =
2425 11;
2426 } else if(coex_dm->cur_ps_tdma == 11) {
2427 halbtc8192e2ant_ps_tdma(
2428 btcoexist,
2429 NORMAL_EXEC,
2430 true, 10);
2431 coex_dm->ps_tdma_du_adj_type =
2432 10;
2433 } else if(coex_dm->cur_ps_tdma == 10) {
2434 halbtc8192e2ant_ps_tdma(
2435 btcoexist,
2436 NORMAL_EXEC,
2437 true, 10);
2438 coex_dm->ps_tdma_du_adj_type =
2439 10;
2440 }
2441 }
2442 }
2443 } else if (max_interval == 3) {
2444 if (tx_pause) {
2445 BTC_PRINT(BTC_MSG_ALGORITHM,
2446 ALGO_TRACE_FW_DETAIL,
2447 "[BTCoex], TxPause = 1\n");
2448 if (coex_dm->cur_ps_tdma == 1) {
2449 halbtc8192e2ant_ps_tdma(btcoexist,
2450 NORMAL_EXEC,
2451 true, 7);
2452 coex_dm->ps_tdma_du_adj_type = 7;
2453 } else if (coex_dm->cur_ps_tdma == 2) {
2454 halbtc8192e2ant_ps_tdma(btcoexist,
2455 NORMAL_EXEC,
2456 true, 7);
2457 coex_dm->ps_tdma_du_adj_type = 7;
2458 } else if (coex_dm->cur_ps_tdma == 3) {
2459 halbtc8192e2ant_ps_tdma(btcoexist,
2460 NORMAL_EXEC,
2461 true, 7);
2462 coex_dm->ps_tdma_du_adj_type = 7;
2463 } else if (coex_dm->cur_ps_tdma == 4) {
2464 halbtc8192e2ant_ps_tdma(btcoexist,
2465 NORMAL_EXEC,
2466 true, 8);
2467 coex_dm->ps_tdma_du_adj_type = 8;
2468 }
2469 if (coex_dm->cur_ps_tdma == 9) {
2470 halbtc8192e2ant_ps_tdma(btcoexist,
2471 NORMAL_EXEC,
2472 true, 15);
2473 coex_dm->ps_tdma_du_adj_type = 15;
2474 } else if (coex_dm->cur_ps_tdma == 10) {
2475 halbtc8192e2ant_ps_tdma(btcoexist,
2476 NORMAL_EXEC,
2477 true, 15);
2478 coex_dm->ps_tdma_du_adj_type = 15;
2479 } else if (coex_dm->cur_ps_tdma == 11) {
2480 halbtc8192e2ant_ps_tdma(btcoexist,
2481 NORMAL_EXEC,
2482 true, 15);
2483 coex_dm->ps_tdma_du_adj_type = 15;
2484 } else if (coex_dm->cur_ps_tdma == 12) {
2485 halbtc8192e2ant_ps_tdma(btcoexist,
2486 NORMAL_EXEC,
2487 true, 16);
2488 coex_dm->ps_tdma_du_adj_type = 16;
2489 }
2490 if (result == -1) {
2491 if (coex_dm->cur_ps_tdma == 5) {
2492 halbtc8192e2ant_ps_tdma(
2493 btcoexist,
2494 NORMAL_EXEC,
2495 true, 7);
2496 coex_dm->ps_tdma_du_adj_type =
2497 7;
2498 } else if (coex_dm->cur_ps_tdma == 6) {
2499 halbtc8192e2ant_ps_tdma(
2500 btcoexist,
2501 NORMAL_EXEC,
2502 true, 7);
2503 coex_dm->ps_tdma_du_adj_type =
2504 7;
2505 } else if (coex_dm->cur_ps_tdma == 7) {
2506 halbtc8192e2ant_ps_tdma(
2507 btcoexist,
2508 NORMAL_EXEC,
2509 true, 8);
2510 coex_dm->ps_tdma_du_adj_type =
2511 8;
2512 } else if (coex_dm->cur_ps_tdma == 13) {
2513 halbtc8192e2ant_ps_tdma(
2514 btcoexist,
2515 NORMAL_EXEC,
2516 true, 15);
2517 coex_dm->ps_tdma_du_adj_type =
2518 15;
2519 } else if (coex_dm->cur_ps_tdma == 14) {
2520 halbtc8192e2ant_ps_tdma(
2521 btcoexist,
2522 NORMAL_EXEC,
2523 true, 15);
2524 coex_dm->ps_tdma_du_adj_type =
2525 15;
2526 } else if (coex_dm->cur_ps_tdma == 15) {
2527 halbtc8192e2ant_ps_tdma(
2528 btcoexist,
2529 NORMAL_EXEC,
2530 true, 16);
2531 coex_dm->ps_tdma_du_adj_type =
2532 16;
2533 }
2534 } else if (result == 1) {
2535 if (coex_dm->cur_ps_tdma == 8) {
2536 halbtc8192e2ant_ps_tdma(
2537 btcoexist,
2538 NORMAL_EXEC,
2539 true, 7);
2540 coex_dm->ps_tdma_du_adj_type =
2541 7;
2542 } else if (coex_dm->cur_ps_tdma == 7) {
2543 halbtc8192e2ant_ps_tdma(
2544 btcoexist,
2545 NORMAL_EXEC,
2546 true, 7);
2547 coex_dm->ps_tdma_du_adj_type =
2548 7;
2549 } else if (coex_dm->cur_ps_tdma == 6) {
2550 halbtc8192e2ant_ps_tdma(
2551 btcoexist,
2552 NORMAL_EXEC,
2553 true, 7);
2554 coex_dm->ps_tdma_du_adj_type =
2555 7;
2556 } else if (coex_dm->cur_ps_tdma == 16) {
2557 halbtc8192e2ant_ps_tdma(
2558 btcoexist,
2559 NORMAL_EXEC,
2560 true, 15);
2561 coex_dm->ps_tdma_du_adj_type =
2562 15;
2563 } else if (coex_dm->cur_ps_tdma == 15) {
2564 halbtc8192e2ant_ps_tdma(
2565 btcoexist,
2566 NORMAL_EXEC,
2567 true, 15);
2568 coex_dm->ps_tdma_du_adj_type =
2569 15;
2570 } else if (coex_dm->cur_ps_tdma == 14) {
2571 halbtc8192e2ant_ps_tdma(
2572 btcoexist,
2573 NORMAL_EXEC,
2574 true, 15);
2575 coex_dm->ps_tdma_du_adj_type =
2576 15;
2577 }
2578 }
2579 } else {
2580 BTC_PRINT(BTC_MSG_ALGORITHM,
2581 ALGO_TRACE_FW_DETAIL,
2582 "[BTCoex], TxPause = 0\n");
2583 if (coex_dm->cur_ps_tdma == 5) {
2584 halbtc8192e2ant_ps_tdma(btcoexist,
2585 NORMAL_EXEC,
2586 true, 3);
2587 coex_dm->ps_tdma_du_adj_type = 3;
2588 } else if (coex_dm->cur_ps_tdma == 6) {
2589 halbtc8192e2ant_ps_tdma(btcoexist,
2590 NORMAL_EXEC,
2591 true, 3);
2592 coex_dm->ps_tdma_du_adj_type = 3;
2593 } else if (coex_dm->cur_ps_tdma == 7) {
2594 halbtc8192e2ant_ps_tdma(btcoexist,
2595 NORMAL_EXEC,
2596 true, 3);
2597 coex_dm->ps_tdma_du_adj_type = 3;
2598 } else if (coex_dm->cur_ps_tdma == 8) {
2599 halbtc8192e2ant_ps_tdma(btcoexist,
2600 NORMAL_EXEC,
2601 true, 4);
2602 coex_dm->ps_tdma_du_adj_type = 4;
2603 }
2604 if (coex_dm->cur_ps_tdma == 13) {
2605 halbtc8192e2ant_ps_tdma(btcoexist,
2606 NORMAL_EXEC,
2607 true, 11);
2608 coex_dm->ps_tdma_du_adj_type = 11;
2609 } else if (coex_dm->cur_ps_tdma == 14) {
2610 halbtc8192e2ant_ps_tdma(btcoexist,
2611 NORMAL_EXEC,
2612 true, 11);
2613 coex_dm->ps_tdma_du_adj_type = 11;
2614 } else if (coex_dm->cur_ps_tdma == 15) {
2615 halbtc8192e2ant_ps_tdma(btcoexist,
2616 NORMAL_EXEC,
2617 true, 11);
2618 coex_dm->ps_tdma_du_adj_type = 11;
2619 } else if (coex_dm->cur_ps_tdma == 16) {
2620 halbtc8192e2ant_ps_tdma(btcoexist,
2621 NORMAL_EXEC,
2622 true, 12);
2623 coex_dm->ps_tdma_du_adj_type = 12;
2624 }
2625 if (result == -1) {
2626 if (coex_dm->cur_ps_tdma == 1) {
2627 halbtc8192e2ant_ps_tdma(
2628 btcoexist,
2629 NORMAL_EXEC,
2630 true, 3);
2631 coex_dm->ps_tdma_du_adj_type =
2632 3;
2633 } else if (coex_dm->cur_ps_tdma == 2) {
2634 halbtc8192e2ant_ps_tdma(
2635 btcoexist,
2636 NORMAL_EXEC,
2637 true, 3);
2638 coex_dm->ps_tdma_du_adj_type =
2639 3;
2640 } else if (coex_dm->cur_ps_tdma == 3) {
2641 halbtc8192e2ant_ps_tdma(
2642 btcoexist,
2643 NORMAL_EXEC,
2644 true, 4);
2645 coex_dm->ps_tdma_du_adj_type =
2646 4;
2647 } else if (coex_dm->cur_ps_tdma == 9) {
2648 halbtc8192e2ant_ps_tdma(
2649 btcoexist,
2650 NORMAL_EXEC,
2651 true, 11);
2652 coex_dm->ps_tdma_du_adj_type =
2653 11;
2654 } else if (coex_dm->cur_ps_tdma == 10) {
2655 halbtc8192e2ant_ps_tdma(
2656 btcoexist,
2657 NORMAL_EXEC,
2658 true, 11);
2659 coex_dm->ps_tdma_du_adj_type =
2660 11;
2661 } else if (coex_dm->cur_ps_tdma == 11) {
2662 halbtc8192e2ant_ps_tdma(
2663 btcoexist,
2664 NORMAL_EXEC,
2665 true, 12);
2666 coex_dm->ps_tdma_du_adj_type =
2667 12;
2668 }
2669 } else if (result == 1) {
2670 if (coex_dm->cur_ps_tdma == 4) {
2671 halbtc8192e2ant_ps_tdma(
2672 btcoexist,
2673 NORMAL_EXEC,
2674 true, 3);
2675 coex_dm->ps_tdma_du_adj_type =
2676 3;
2677 } else if (coex_dm->cur_ps_tdma == 3) {
2678 halbtc8192e2ant_ps_tdma(
2679 btcoexist,
2680 NORMAL_EXEC,
2681 true, 3);
2682 coex_dm->ps_tdma_du_adj_type =
2683 3;
2684 } else if (coex_dm->cur_ps_tdma == 2) {
2685 halbtc8192e2ant_ps_tdma(
2686 btcoexist,
2687 NORMAL_EXEC,
2688 true, 3);
2689 coex_dm->ps_tdma_du_adj_type =
2690 3;
2691 } else if (coex_dm->cur_ps_tdma == 12) {
2692 halbtc8192e2ant_ps_tdma(
2693 btcoexist,
2694 NORMAL_EXEC,
2695 true, 11);
2696 coex_dm->ps_tdma_du_adj_type =
2697 11;
2698 } else if (coex_dm->cur_ps_tdma == 11) {
2699 halbtc8192e2ant_ps_tdma(
2700 btcoexist,
2701 NORMAL_EXEC,
2702 true, 11);
2703 coex_dm->ps_tdma_du_adj_type =
2704 11;
2705 } else if (coex_dm->cur_ps_tdma == 10) {
2706 halbtc8192e2ant_ps_tdma(
2707 btcoexist,
2708 NORMAL_EXEC,
2709 true, 11);
2710 coex_dm->ps_tdma_du_adj_type =
2711 11;
2712 }
2713 }
2714 }
2715 }
2716 }
2717
2718 /* if current PsTdma not match with
2719 * the recorded one (when scan, dhcp...),
2720 * then we have to adjust it back to the previous record one. */
2721 if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
2722 bool scan = false, link = false, roam = false;
2723 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
2724 "[BTCoex], PsTdma type dismatch!!!, " );
2725 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
2726 "curPsTdma=%d, recordPsTdma=%d\n",
2727 coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
2728
2729 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
2730 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
2731 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
2732
2733 if ( !scan && !link && !roam)
2734 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
2735 true,
2736 coex_dm->ps_tdma_du_adj_type);
2737 else
2738 BTC_PRINT(BTC_MSG_ALGORITHM,
2739 ALGO_TRACE_FW_DETAIL,
2740 "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
2741 }
2742}
2743
2744/* SCO only or SCO+PAN(HS) */
2745void halbtc8192e2ant_action_sco(struct btc_coexist *btcoexist)
2746{
2747 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_STAY_LOW;
2748 u32 wifi_bw;
2749
2750 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2751
2752 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2753 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2754
2755 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2756
2757 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
2758
2759 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2760
2761 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2762 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2763 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2764 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
2765 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2766 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2767 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2768 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
2769 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2770 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2771 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2772 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
2773 }
2774
2775 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2776
2777 /* sw mechanism */
2778 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2779 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2780 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2781 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
2782 false, false);
2783 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
2784 false, 0x6);
2785 } else {
2786 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
2787 false, false);
2788 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
2789 false, 0x6);
2790 }
2791 } else {
2792 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2793 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2794 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
2795 false, false);
2796 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
2797 false, 0x6);
2798 } else {
2799 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
2800 false, false);
2801 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
2802 false, 0x6);
2803 }
2804 }
2805}
2806
2807void halbtc8192e2ant_action_sco_pan(struct btc_coexist *btcoexist)
2808{
2809 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_STAY_LOW;
2810 u32 wifi_bw;
2811
2812 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2813
2814 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2815 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2816
2817 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2818
2819 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
2820
2821 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2822
2823 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2824 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2825 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2826 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
2827 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2828 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2829 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2830 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
2831 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2832 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2833 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2834 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
2835 }
2836
2837 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2838
2839 /* sw mechanism */
2840 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2841 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2842 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2843 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
2844 false, false);
2845 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
2846 false, 0x6);
2847 } else {
2848 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
2849 false, false);
2850 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
2851 false, 0x6);
2852 }
2853 } else {
2854 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2855 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2856 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
2857 false, false);
2858 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
2859 false, 0x6);
2860 } else {
2861 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
2862 false, false);
2863 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
2864 false, 0x6);
2865 }
2866 }
2867}
2868
2869void halbtc8192e2ant_action_hid(struct btc_coexist *btcoexist)
2870{
2871 u8 wifirssi_state, btrssi_state=BTC_RSSI_STATE_HIGH;
2872 u32 wifi_bw;
2873
2874 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2875 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2876
2877 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2878 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
2879
2880 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2881
2882 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2883
2884 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
2885
2886 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2887 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2888 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2889 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
2890 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2891 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2892 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2893 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
2894 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2895 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2896 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2897 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
2898 }
2899
2900 /* sw mechanism */
2901 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2902 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2903 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2904 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
2905 false, false);
2906 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
2907 false, 0x18);
2908 } else {
2909 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
2910 false, false);
2911 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
2912 false, 0x18);
2913 }
2914 } else {
2915 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2916 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2917 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
2918 false, false);
2919 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
2920 false, 0x18);
2921 } else {
2922 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
2923 false, false);
2924 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
2925 false, 0x18);
2926 }
2927 }
2928}
2929
2930/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
2931void halbtc8192e2ant_action_a2dp(struct btc_coexist *btcoexist)
2932{
2933 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
2934 u32 wifi_bw;
2935 bool long_dist = false;
2936
2937 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
2938 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
2939
2940 if ((btrssi_state == BTC_RSSI_STATE_LOW ||
2941 btrssi_state == BTC_RSSI_STATE_STAY_LOW) &&
2942 (wifirssi_state == BTC_RSSI_STATE_LOW ||
2943 wifirssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2944 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
2945 "[BTCoex], A2dp, wifi/bt rssi both LOW!!\n");
2946 long_dist = true;
2947 }
2948 if (long_dist) {
2949 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 2);
2950 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
2951 0x4);
2952 } else {
2953 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
2954 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
2955 0x8);
2956 }
2957
2958 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
2959
2960 if (long_dist)
2961 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
2962 else
2963 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
2964
2965
2966 if (long_dist) {
2967 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17);
2968 coex_dm->auto_tdma_adjust = false;
2969 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2970 } else {
2971 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
2972 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
2973 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
2974 true, 1);
2975 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
2976 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
2977 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
2978 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
2979 false, 1);
2980 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
2981 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
2982 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2983 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false,
2984 false, 1);
2985 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
2986 }
2987 }
2988
2989 /* sw mechanism */
2990 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2991 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2992 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
2993 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2994 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
2995 false, false);
2996 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
2997 false, 0x18);
2998 } else {
2999 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
3000 false, false);
3001 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3002 false, 0x18);
3003 }
3004 } else {
3005 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3006 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3007 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
3008 false, false);
3009 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3010 false, 0x18);
3011 } else {
3012 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
3013 false, false);
3014 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3015 false, 0x18);
3016 }
3017 }
3018}
3019
3020void halbtc8192e2ant_action_a2dp_pan_hs(struct btc_coexist *btcoexist)
3021{
3022 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
3023 u32 wifi_bw;
3024
3025 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
3026 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
3027
3028 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
3029 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
3030
3031 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
3032 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
3033
3034 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
3035 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
3036 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2);
3037 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
3038 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
3039 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
3040 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false,
3041 2);
3042 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
3043 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
3044 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3045 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false,
3046 2);
3047 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
3048 }
3049
3050 /* sw mechanism */
3051 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3052 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3053 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3054 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3055 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
3056 false, false);
3057 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3058 true, 0x6);
3059 } else {
3060 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
3061 false, false);
3062 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3063 true, 0x6);
3064 }
3065 } else {
3066 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3067 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3068 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
3069 false, false);
3070 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3071 true, 0x6);
3072 } else {
3073 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
3074 false, false);
3075 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3076 true, 0x6);
3077 }
3078 }
3079}
3080
3081void halbtc8192e2ant_action_pan_edr(struct btc_coexist *btcoexist)
3082{
3083 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
3084 u32 wifi_bw;
3085
3086 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
3087 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
3088
3089 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
3090 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
3091
3092 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
3093
3094 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
3095
3096 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
3097 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
3098 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
3099 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
3100 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
3101 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
3102 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
3103 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
3104 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
3105 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3106 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
3107 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
3108 }
3109
3110 /* sw mechanism */
3111 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3112 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3113 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3114 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3115 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
3116 false, false);
3117 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3118 false, 0x18);
3119 } else {
3120 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
3121 false, false);
3122 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3123 false, 0x18);
3124 }
3125 } else {
3126 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3127 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3128 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
3129 false, false);
3130 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3131 false, 0x18);
3132 } else {
3133 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
3134 false, false);
3135 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3136 false, 0x18);
3137 }
3138 }
3139}
3140
3141/* PAN(HS) only */
3142void halbtc8192e2ant_action_pan_hs(struct btc_coexist *btcoexist)
3143{
3144 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
3145 u32 wifi_bw;
3146
3147 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
3148 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
3149
3150 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
3151 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
3152
3153 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
3154
3155 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
3156
3157 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
3158 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
3159 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
3160 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
3161 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
3162 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
3163 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
3164 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3165 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
3166 }
3167 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
3168
3169 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3170 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3171 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3172 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3173 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
3174 false, false);
3175 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3176 false, 0x18);
3177 } else {
3178 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
3179 false, false);
3180 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3181 false, 0x18);
3182 }
3183 } else {
3184 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3185 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3186 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
3187 false, false);
3188 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3189 false, 0x18);
3190 } else {
3191 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
3192 false, false);
3193 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3194 false, 0x18);
3195 }
3196 }
3197}
3198
3199/* PAN(EDR)+A2DP */
3200void halbtc8192e2ant_action_pan_edr_a2dp(struct btc_coexist *btcoexist)
3201{
3202 u8 wifirssi_state, btrssi_state=BTC_RSSI_STATE_HIGH;
3203 u32 wifi_bw;
3204
3205 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
3206 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
3207
3208 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
3209 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
3210
3211 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
3212
3213 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
3214
3215 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3216
3217 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
3218 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
3219 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
3220 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 3);
3221 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
3222 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
3223 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
3224 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false,
3225 3);
3226 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
3227 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3228 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
3229 halbtc8192e2ant_tdma_duration_adjust(btcoexist, false, false,
3230 3);
3231 }
3232
3233 /* sw mechanism */
3234 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3235 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3236 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3237 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
3238 false, false);
3239 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3240 false, 0x18);
3241 } else {
3242 halbtc8192e2ant_sw_mechanism1(btcoexist, true, false,
3243 false, false);
3244 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3245 false, 0x18);
3246 }
3247 } else {
3248 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3249 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3250 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
3251 false, false);
3252 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3253 false, 0x18);
3254 } else {
3255 halbtc8192e2ant_sw_mechanism1(btcoexist, false, false,
3256 false, false);
3257 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3258 false, 0x18);
3259 }
3260 }
3261}
3262
3263void halbtc8192e2ant_action_pan_edr_hid(struct btc_coexist *btcoexist)
3264{
3265 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
3266 u32 wifi_bw;
3267
3268 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
3269 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
3270
3271 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3272
3273 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
3274 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
3275
3276 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
3277
3278 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
3279
3280 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
3281 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
3282 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
3283 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
3284 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
3285 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
3286 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
3287 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
3288 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
3289 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3290 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
3291 halbtc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
3292 }
3293
3294 /* sw mechanism */
3295 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3296 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3297 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3298 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
3299 false, false);
3300 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3301 false, 0x18);
3302 } else {
3303 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
3304 false, false);
3305 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3306 false, 0x18);
3307 }
3308 } else {
3309 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3310 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3311 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
3312 false, false);
3313 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3314 false, 0x18);
3315 } else {
3316 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
3317 false, false);
3318 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3319 false, 0x18);
3320 }
3321 }
3322}
3323
3324/* HID+A2DP+PAN(EDR) */
3325void halbtc8192e2ant_action_hid_a2dp_pan_edr(struct btc_coexist *btcoexist)
3326{
3327 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
3328 u32 wifi_bw;
3329
3330 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
3331 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
3332
3333 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
3334 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
3335
3336 halbtc8192e2ant_fw_dac_swinglvl(btcoexist, NORMAL_EXEC, 6);
3337
3338 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3339
3340 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
3341
3342 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
3343 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
3344 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
3345 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 3);
3346 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
3347 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
3348 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
3349 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
3350 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
3351 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3352 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
3353 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
3354 }
3355
3356 /* sw mechanism */
3357 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3358 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3359 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3360 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
3361 false, false);
3362 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3363 false, 0x18);
3364 } else {
3365 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
3366 false, false);
3367 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3368 false, 0x18);
3369 }
3370 } else {
3371 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3372 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3373 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
3374 false, false);
3375 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3376 false, 0x18);
3377 } else {
3378 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
3379 false, false);
3380 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3381 false, 0x18);
3382 }
3383 }
3384}
3385
3386void halbtc8192e2ant_action_hid_a2dp(struct btc_coexist *btcoexist)
3387{
3388 u8 wifirssi_state, btrssi_state = BTC_RSSI_STATE_HIGH;
3389 u32 wifi_bw;
3390
3391 wifirssi_state = halbtc8192e2ant_wifirssi_state(btcoexist, 0, 2, 15, 0);
3392 btrssi_state = halbtc8192e2ant_btrssi_state(3, 34, 42);
3393
3394 halbtc8192e2ant_switch_sstype(btcoexist, NORMAL_EXEC, 1);
3395 halbtc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
3396
3397 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3398
3399 halbtc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
3400
3401 if ((btrssi_state == BTC_RSSI_STATE_LOW) ||
3402 (btrssi_state == BTC_RSSI_STATE_STAY_LOW)) {
3403 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 0);
3404 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 2);
3405 } else if ((btrssi_state == BTC_RSSI_STATE_MEDIUM) ||
3406 (btrssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
3407 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 2);
3408 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
3409 } else if ((btrssi_state == BTC_RSSI_STATE_HIGH) ||
3410 (btrssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3411 halbtc8192e2ant_dec_btpwr(btcoexist, NORMAL_EXEC, 4);
3412 halbtc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
3413 }
3414
3415 /* sw mechanism */
3416 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3417 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3418 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3419 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
3420 false, false);
3421 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3422 false, 0x18);
3423 } else {
3424 halbtc8192e2ant_sw_mechanism1(btcoexist, true, true,
3425 false, false);
3426 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3427 false, 0x18);
3428 }
3429 } else {
3430 if ((wifirssi_state == BTC_RSSI_STATE_HIGH) ||
3431 (wifirssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3432 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
3433 false, false);
3434 halbtc8192e2ant_sw_mechanism2(btcoexist, true, false,
3435 false, 0x18);
3436 } else {
3437 halbtc8192e2ant_sw_mechanism1(btcoexist, false, true,
3438 false, false);
3439 halbtc8192e2ant_sw_mechanism2(btcoexist, false, false,
3440 false, 0x18);
3441 }
3442 }
3443}
3444
3445void halbtc8192e2ant_run_coexist_mechanism(struct btc_coexist *btcoexist)
3446{
3447 u8 algorithm = 0;
3448
3449 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3450 "[BTCoex], RunCoexistMechanism()===>\n");
3451
3452 if (btcoexist->manual_control) {
3453 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3454 "[BTCoex], return for Manual CTRL <===\n");
3455 return;
3456 }
3457
3458 if (coex_sta->under_ips) {
3459 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3460 "[BTCoex], wifi is under IPS !!!\n");
3461 return;
3462 }
3463
3464 algorithm = halbtc8192e2ant_action_algorithm(btcoexist);
3465 if (coex_sta->c2h_bt_inquiry_page &&
3466 (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) {
3467 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3468 "[BTCoex], BT is under inquiry/page scan !!\n");
3469 halbtc8192e2ant_action_bt_inquiry(btcoexist);
3470 return;
3471 }
3472
3473 coex_dm->cur_algorithm = algorithm;
3474 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3475 "[BTCoex], Algorithm = %d \n", coex_dm->cur_algorithm);
3476
3477 if (halbtc8192e2ant_is_common_action(btcoexist)) {
3478 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3479 "[BTCoex], Action 2-Ant common.\n");
3480 coex_dm->auto_tdma_adjust = false;
3481 } else {
3482 if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
3483 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3484 "[BTCoex] preAlgorithm=%d, curAlgorithm=%d\n",
3485 coex_dm->pre_algorithm,
3486 coex_dm->cur_algorithm);
3487 coex_dm->auto_tdma_adjust = false;
3488 }
3489 switch (coex_dm->cur_algorithm) {
3490 case BT_8192E_2ANT_COEX_ALGO_SCO:
3491 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3492 "Action 2-Ant, algorithm = SCO.\n");
3493 halbtc8192e2ant_action_sco(btcoexist);
3494 break;
3495 case BT_8192E_2ANT_COEX_ALGO_SCO_PAN:
3496 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3497 "Action 2-Ant, algorithm = SCO+PAN(EDR).\n");
3498 halbtc8192e2ant_action_sco_pan(btcoexist);
3499 break;
3500 case BT_8192E_2ANT_COEX_ALGO_HID:
3501 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3502 "Action 2-Ant, algorithm = HID.\n");
3503 halbtc8192e2ant_action_hid(btcoexist);
3504 break;
3505 case BT_8192E_2ANT_COEX_ALGO_A2DP:
3506 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3507 "Action 2-Ant, algorithm = A2DP.\n");
3508 halbtc8192e2ant_action_a2dp(btcoexist);
3509 break;
3510 case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS:
3511 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3512 "Action 2-Ant, algorithm = A2DP+PAN(HS).\n");
3513 halbtc8192e2ant_action_a2dp_pan_hs(btcoexist);
3514 break;
3515 case BT_8192E_2ANT_COEX_ALGO_PANEDR:
3516 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3517 "Action 2-Ant, algorithm = PAN(EDR).\n");
3518 halbtc8192e2ant_action_pan_edr(btcoexist);
3519 break;
3520 case BT_8192E_2ANT_COEX_ALGO_PANHS:
3521 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3522 "Action 2-Ant, algorithm = HS mode.\n");
3523 halbtc8192e2ant_action_pan_hs(btcoexist);
3524 break;
3525 case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP:
3526 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3527 "Action 2-Ant, algorithm = PAN+A2DP.\n");
3528 halbtc8192e2ant_action_pan_edr_a2dp(btcoexist);
3529 break;
3530 case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID:
3531 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3532 "Action 2-Ant, algorithm = PAN(EDR)+HID.\n");
3533 halbtc8192e2ant_action_pan_edr_hid(btcoexist);
3534 break;
3535 case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
3536 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3537 "Action 2-Ant, algorithm = HID+A2DP+PAN.\n");
3538 halbtc8192e2ant_action_hid_a2dp_pan_edr(btcoexist);
3539 break;
3540 case BT_8192E_2ANT_COEX_ALGO_HID_A2DP:
3541 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3542 "Action 2-Ant, algorithm = HID+A2DP.\n");
3543 halbtc8192e2ant_action_hid_a2dp(btcoexist);
3544 break;
3545 default:
3546 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3547 "Action 2-Ant, algorithm = unknown!!\n");
3548 /* halbtc8192e2ant_coex_alloff(btcoexist); */
3549 break;
3550 }
3551 coex_dm->pre_algorithm = coex_dm->cur_algorithm;
3552 }
3553}
3554
3555void halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist, bool backup)
3556{
3557 u16 u16tmp = 0;
3558 u8 u8tmp = 0;
3559
3560 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
3561 "[BTCoex], 2Ant Init HW Config!!\n");
3562
3563 if (backup) {
3564 /* backup rf 0x1e value */
3565 coex_dm->bt_rf0x1e_backup =
3566 btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A,
3567 0x1e, 0xfffff);
3568
3569 coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
3570 0x430);
3571 coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
3572 0x434);
3573 coex_dm->backup_retrylimit = btcoexist->btc_read_2byte(
3574 btcoexist,
3575 0x42a);
3576 coex_dm->backup_ampdu_maxtime = btcoexist->btc_read_1byte(
3577 btcoexist,
3578 0x456);
3579 }
3580
3581 /* antenna sw ctrl to bt */
3582 btcoexist->btc_write_1byte(btcoexist, 0x4f, 0x6);
3583 btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24);
3584 btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700);
3585 btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
3586 if (btcoexist->chip_interface == BTC_INTF_USB)
3587 btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
3588 else
3589 btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
3590
3591 halbtc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
3592
3593 /* antenna switch control parameter */
3594 btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555);
3595
3596 /* coex parameters */
3597 btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
3598 /* 0x790[5:0]=0x5 */
3599 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
3600 u8tmp &= 0xc0;
3601 u8tmp |= 0x5;
3602 btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
3603
3604 /* enable counter statistics */
3605 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
3606
3607 /* enable PTA */
3608 btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
3609 /* enable mailbox interface */
3610 u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40);
3611 u16tmp |= BIT9;
3612 btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp);
3613
3614 /* enable PTA I2C mailbox */
3615 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101);
3616 u8tmp |= BIT4;
3617 btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp);
3618
3619 /* enable bt clock when wifi is disabled. */
3620 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93);
3621 u8tmp |= BIT0;
3622 btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp);
3623 /* enable bt clock when suspend. */
3624 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
3625 u8tmp |= BIT0;
3626 btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
3627}
3628
3629/*************************************************************
3630 * work around function start with wa_halbtc8192e2ant_
3631 *************************************************************/
3632
3633/************************************************************
3634 * extern function start with EXhalbtc8192e2ant_
3635 ************************************************************/
3636
3637void ex_halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist)
3638{
3639 halbtc8192e2ant_init_hwconfig(btcoexist, true);
3640}
3641
3642void ex_halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist)
3643{
3644 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
3645 "[BTCoex], Coex Mechanism Init!!\n");
3646 halbtc8192e2ant_init_coex_dm(btcoexist);
3647}
3648
3649void ex_halbtc8192e2ant_display_coex_info(struct btc_coexist *btcoexist)
3650{
3651 struct btc_board_info *board_info = &btcoexist->board_info;
3652 struct btc_stack_info*stack_info = &btcoexist->stack_info;
3653 u8 *cli_buf = btcoexist->cli_buf;
3654 u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
3655 u16 u16tmp[4];
3656 u32 u32tmp[4];
3657 bool roam = false, scan = false, link = false, wifi_under_5g = false;
3658 bool bt_hson = false, wifi_busy = false;
3659 int wifirssi = 0, bt_hs_rssi = 0;
3660 u32 wifi_bw, wifi_traffic_dir;
3661 u8 wifi_dot11_chnl, wifi_hs_chnl;
3662 u32 fw_ver = 0, bt_patch_ver = 0;
3663
3664 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3665 "\r\n ============[BT Coexist info]============");
3666 CL_PRINTF(cli_buf);
3667
3668 if (btcoexist->manual_control) {
3669 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3670 "\r\n ===========[Under Manual Control]===========");
3671 CL_PRINTF(cli_buf);
3672 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3673 "\r\n ==========================================");
3674 CL_PRINTF(cli_buf);
3675 }
3676
3677 if (!board_info->bt_exist) {
3678 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n BT not exists !!!");
3679 CL_PRINTF(cli_buf);
3680 return;
3681 }
3682
3683 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3684 "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:",
3685 board_info->pg_ant_num, board_info->btdm_ant_num);
3686 CL_PRINTF(cli_buf);
3687
3688 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d",
3689 "BT stack/ hci ext ver",
3690 ((stack_info->profile_notified) ? "Yes" : "No"),
3691 stack_info->hci_version);
3692 CL_PRINTF(cli_buf);
3693
3694 btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
3695 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
3696 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3697 "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
3698 "CoexVer/ FwVer/ PatchVer",
3699 glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
3700 fw_ver, bt_patch_ver, bt_patch_ver);
3701 CL_PRINTF(cli_buf);
3702
3703 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hson);
3704 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_DOT11_CHNL,
3705 &wifi_dot11_chnl);
3706 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifi_hs_chnl);
3707 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d(%d)",
3708 "Dot11 channel / HsMode(HsChnl)",
3709 wifi_dot11_chnl, bt_hson, wifi_hs_chnl);
3710 CL_PRINTF(cli_buf);
3711
3712 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
3713 "H2C Wifi inform bt chnl Info", coex_dm->wifi_chnl_info[0],
3714 coex_dm->wifi_chnl_info[1], coex_dm->wifi_chnl_info[2]);
3715 CL_PRINTF(cli_buf);
3716
3717 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifirssi);
3718 btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi);
3719 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
3720 "Wifi rssi/ HS rssi", wifirssi, bt_hs_rssi);
3721 CL_PRINTF(cli_buf);
3722
3723 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
3724 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
3725 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
3726 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
3727 "Wifi link/ roam/ scan", link, roam, scan);
3728 CL_PRINTF(cli_buf);
3729
3730 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
3731 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3732 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
3733 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
3734 &wifi_traffic_dir);
3735 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s ",
3736 "Wifi status", (wifi_under_5g ? "5G" : "2.4G"),
3737 ((BTC_WIFI_BW_LEGACY == wifi_bw) ? "Legacy" :
3738 (((BTC_WIFI_BW_HT40 == wifi_bw) ? "HT40" : "HT20"))),
3739 ((!wifi_busy) ? "idle" :
3740 ((BTC_WIFI_TRAFFIC_TX == wifi_traffic_dir) ?
3741 "uplink" : "downlink")));
3742 CL_PRINTF(cli_buf);
3743
3744 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
3745 "BT [status/ rssi/ retryCnt]",
3746 ((btcoexist->bt_info.bt_disabled) ? ("disabled") :
3747 ((coex_sta->c2h_bt_inquiry_page) ?
3748 ("inquiry/page scan") :
3749 ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
3750 coex_dm->bt_status) ? "non-connected idle" :
3751 ((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
3752 coex_dm->bt_status) ? "connected-idle" : "busy")))),
3753 coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
3754 CL_PRINTF(cli_buf);
3755
3756 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
3757 "SCO/HID/PAN/A2DP", stack_info->sco_exist,
3758 stack_info->hid_exist, stack_info->pan_exist,
3759 stack_info->a2dp_exist);
3760 CL_PRINTF(cli_buf);
3761 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
3762
3763 bt_info_ext = coex_sta->bt_info_ext;
3764 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
3765 "BT Info A2DP rate",
3766 (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate");
3767 CL_PRINTF(cli_buf);
3768
3769 for (i=0; i<BT_INFO_SRC_8192E_2ANT_MAX; i++) {
3770 if (coex_sta->bt_info_c2h_cnt[i]) {
3771 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3772 "\r\n %-35s = %02x %02x %02x %02x ",
3773 GLBtInfoSrc8192e2Ant[i],
3774 coex_sta->bt_info_c2h[i][0],
3775 coex_sta->bt_info_c2h[i][1],
3776 coex_sta->bt_info_c2h[i][2],
3777 coex_sta->bt_info_c2h[i][3]);
3778 CL_PRINTF(cli_buf);
3779 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3780 "%02x %02x %02x(%d)",
3781 coex_sta->bt_info_c2h[i][4],
3782 coex_sta->bt_info_c2h[i][5],
3783 coex_sta->bt_info_c2h[i][6],
3784 coex_sta->bt_info_c2h_cnt[i]);
3785 CL_PRINTF(cli_buf);
3786 }
3787 }
3788
3789 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/%s",
3790 "PS state, IPS/LPS",
3791 ((coex_sta->under_ips ? "IPS ON" : "IPS OFF")),
3792 ((coex_sta->under_lps ? "LPS ON" : "LPS OFF")));
3793 CL_PRINTF(cli_buf);
3794 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD);
3795
3796 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "SS Type",
3797 coex_dm->cur_sstype);
3798 CL_PRINTF(cli_buf);
3799
3800 /* Sw mechanism */
3801 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
3802 "============[Sw mechanism]============");
3803 CL_PRINTF(cli_buf);
3804 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
3805 "SM1[ShRf/ LpRA/ LimDig]", coex_dm->cur_rf_rx_lpf_shrink,
3806 coex_dm->cur_low_penalty_ra, coex_dm->limited_dig);
3807 CL_PRINTF(cli_buf);
3808 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
3809 "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
3810 coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
3811 coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
3812 CL_PRINTF(cli_buf);
3813
3814 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask",
3815 btcoexist->bt_info.ra_mask);
3816 CL_PRINTF(cli_buf);
3817
3818 /* Fw mechanism */
3819 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
3820 "============[Fw mechanism]============");
3821 CL_PRINTF(cli_buf);
3822
3823 ps_tdma_case = coex_dm->cur_ps_tdma;
3824 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3825 "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)",
3826 "PS TDMA", coex_dm->ps_tdma_para[0],
3827 coex_dm->ps_tdma_para[1], coex_dm->ps_tdma_para[2],
3828 coex_dm->ps_tdma_para[3], coex_dm->ps_tdma_para[4],
3829 ps_tdma_case, coex_dm->auto_tdma_adjust);
3830 CL_PRINTF(cli_buf);
3831
3832 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
3833 "DecBtPwr/ IgnWlanAct",
3834 coex_dm->cur_dec_bt_pwr, coex_dm->cur_ignore_wlan_act);
3835 CL_PRINTF(cli_buf);
3836
3837 /* Hw setting */
3838 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
3839 "============[Hw setting]============");
3840 CL_PRINTF(cli_buf);
3841
3842 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
3843 "RF-A, 0x1e initVal", coex_dm->bt_rf0x1e_backup);
3844 CL_PRINTF(cli_buf);
3845
3846 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
3847 "backup ARFR1/ARFR2/RL/AMaxTime", coex_dm->backup_arfr_cnt1,
3848 coex_dm->backup_arfr_cnt2, coex_dm->backup_retrylimit,
3849 coex_dm->backup_ampdu_maxtime);
3850 CL_PRINTF(cli_buf);
3851
3852 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
3853 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
3854 u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
3855 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
3856 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
3857 "0x430/0x434/0x42a/0x456",
3858 u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
3859 CL_PRINTF(cli_buf);
3860
3861 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04);
3862 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04);
3863 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c);
3864 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
3865 "0xc04/ 0xd04/ 0x90c", u32tmp[0], u32tmp[1], u32tmp[2]);
3866 CL_PRINTF(cli_buf);
3867
3868 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
3869 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778",
3870 u8tmp[0]);
3871 CL_PRINTF(cli_buf);
3872
3873 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c);
3874 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930);
3875 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
3876 "0x92c/ 0x930", (u8tmp[0]), u32tmp[0]);
3877 CL_PRINTF(cli_buf);
3878
3879 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
3880 u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f);
3881 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
3882 "0x40/ 0x4f", u8tmp[0], u8tmp[1]);
3883 CL_PRINTF(cli_buf);
3884
3885 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
3886 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
3887 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
3888 "0x550(bcn ctrl)/0x522", u32tmp[0], u8tmp[0]);
3889 CL_PRINTF(cli_buf);
3890
3891 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
3892 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)",
3893 u32tmp[0]);
3894 CL_PRINTF(cli_buf);
3895
3896 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
3897 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
3898 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
3899 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
3900 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3901 "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
3902 "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
3903 u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
3904 CL_PRINTF(cli_buf);
3905
3906 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
3907 "0x770(hp rx[31:16]/tx[15:0])",
3908 coex_sta->high_priority_rx, coex_sta->high_priority_tx);
3909 CL_PRINTF(cli_buf);
3910 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
3911 "0x774(lp rx[31:16]/tx[15:0])",
3912 coex_sta->low_priority_rx, coex_sta->low_priority_tx);
3913 CL_PRINTF(cli_buf);
3914#if(BT_AUTO_REPORT_ONLY_8192E_2ANT == 1)
3915 halbtc8192e2ant_monitor_bt_ctr(btcoexist);
3916#endif
3917 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
3918}
3919
3920
3921void ex_halbtc8192e2ant_ips_notify(struct btc_coexist *btcoexist, u8 type)
3922{
3923 if (BTC_IPS_ENTER == type) {
3924 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3925 "[BTCoex], IPS ENTER notify\n");
3926 coex_sta->under_ips = true;
3927 halbtc8192e2ant_coex_alloff(btcoexist);
3928 } else if (BTC_IPS_LEAVE == type) {
3929 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3930 "[BTCoex], IPS LEAVE notify\n");
3931 coex_sta->under_ips = false;
3932 }
3933}
3934
3935void ex_halbtc8192e2ant_lps_notify(struct btc_coexist *btcoexist, u8 type)
3936{
3937 if (BTC_LPS_ENABLE == type) {
3938 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3939 "[BTCoex], LPS ENABLE notify\n");
3940 coex_sta->under_lps = true;
3941 } else if (BTC_LPS_DISABLE == type) {
3942 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3943 "[BTCoex], LPS DISABLE notify\n");
3944 coex_sta->under_lps = false;
3945 }
3946}
3947
3948void ex_halbtc8192e2ant_scan_notify(struct btc_coexist *btcoexist, u8 type)
3949{
3950 if (BTC_SCAN_START == type)
3951 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3952 "[BTCoex], SCAN START notify\n");
3953 else if(BTC_SCAN_FINISH == type)
3954 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3955 "[BTCoex], SCAN FINISH notify\n");
3956}
3957
3958void ex_halbtc8192e2ant_connect_notify(struct btc_coexist *btcoexist, u8 type)
3959{
3960 if (BTC_ASSOCIATE_START == type)
3961 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3962 "[BTCoex], CONNECT START notify\n");
3963 else if(BTC_ASSOCIATE_FINISH == type)
3964 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3965 "[BTCoex], CONNECT FINISH notify\n");
3966}
3967
3968void ex_halbtc8192e2ant_media_status_notify(struct btc_coexist *btcoexist,
3969 u8 type)
3970{
3971 u8 h2c_parameter[3] ={0};
3972 u32 wifi_bw;
3973 u8 wifi_center_chnl;
3974
3975 if (btcoexist->manual_control ||
3976 btcoexist->stop_coex_dm ||
3977 btcoexist->bt_info.bt_disabled)
3978 return;
3979
3980 if (BTC_MEDIA_CONNECT == type)
3981 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3982 "[BTCoex], MEDIA connect notify\n");
3983 else
3984 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3985 "[BTCoex], MEDIA disconnect notify\n");
3986
3987 /* only 2.4G we need to inform bt the chnl mask */
3988 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
3989 &wifi_center_chnl);
3990 if ((BTC_MEDIA_CONNECT == type) &&
3991 (wifi_center_chnl <= 14)) {
3992 h2c_parameter[0] = 0x1;
3993 h2c_parameter[1] = wifi_center_chnl;
3994 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3995 if (BTC_WIFI_BW_HT40 == wifi_bw)
3996 h2c_parameter[2] = 0x30;
3997 else
3998 h2c_parameter[2] = 0x20;
3999 }
4000
4001 coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
4002 coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
4003 coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
4004
4005 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
4006 "[BTCoex], FW write 0x66=0x%x\n",
4007 h2c_parameter[0] << 16 | h2c_parameter[1] << 8 |
4008 h2c_parameter[2]);
4009
4010 btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
4011}
4012
4013void ex_halbtc8192e2ant_special_packet_notify(struct btc_coexist *btcoexist,
4014 u8 type)
4015{
4016 if (type == BTC_PACKET_DHCP)
4017 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
4018 "[BTCoex], DHCP Packet notify\n");
4019 }
4020
4021void ex_halbtc8192e2ant_bt_info_notify(struct btc_coexist *btcoexist,
4022 u8 *tmp_buf, u8 length )
4023{
4024 u8 bt_info = 0;
4025 u8 i, rspSource = 0;
4026 bool bt_busy = false, limited_dig = false;
4027 bool wifi_connected = false;
4028
4029 coex_sta->c2h_bt_info_req_sent = false;
4030
4031 rspSource = tmp_buf[0] & 0xf;
4032 if (rspSource >= BT_INFO_SRC_8192E_2ANT_MAX)
4033 rspSource = BT_INFO_SRC_8192E_2ANT_WIFI_FW;
4034 coex_sta->bt_info_c2h_cnt[rspSource]++;
4035
4036 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
4037 "[BTCoex], Bt info[%d], length=%d, hex data=[",
4038 rspSource, length);
4039 for (i = 0; i < length; i++) {
4040 coex_sta->bt_info_c2h[rspSource][i] = tmp_buf[i];
4041 if (i == 1)
4042 bt_info = tmp_buf[i];
4043 if (i == length-1)
4044 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
4045 "0x%02x]\n", tmp_buf[i]);
4046 else
4047 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
4048 "0x%02x, ", tmp_buf[i]);
4049 }
4050
4051 if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rspSource) {
4052 coex_sta->bt_retry_cnt = /* [3:0] */
4053 coex_sta->bt_info_c2h[rspSource][2] & 0xf;
4054
4055 coex_sta->bt_rssi =
4056 coex_sta->bt_info_c2h[rspSource][3] * 2 + 10;
4057
4058 coex_sta->bt_info_ext =
4059 coex_sta->bt_info_c2h[rspSource][4];
4060
4061 /* Here we need to resend some wifi info to BT
4062 * because bt is reset and loss of the info. */
4063 if ((coex_sta->bt_info_ext & BIT1)) {
4064 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4065 "bit1, send wifi BW&Chnl to BT!!\n");
4066 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
4067 &wifi_connected);
4068 if (wifi_connected)
4069 ex_halbtc8192e2ant_media_status_notify(
4070 btcoexist,
4071 BTC_MEDIA_CONNECT);
4072 else
4073 ex_halbtc8192e2ant_media_status_notify(
4074 btcoexist,
4075 BTC_MEDIA_DISCONNECT);
4076 }
4077
4078 if ((coex_sta->bt_info_ext & BIT3)) {
4079 if (!btcoexist->manual_control &&
4080 !btcoexist->stop_coex_dm) {
4081 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4082 "bit3, BT NOT ignore Wlan active!\n");
4083 halbtc8192e2ant_IgnoreWlanAct(btcoexist,
4084 FORCE_EXEC,
4085 false);
4086 }
4087 } else {
4088 /* BT already NOT ignore Wlan active,
4089 * do nothing here. */
4090 }
4091
4092#if(BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
4093 if ((coex_sta->bt_info_ext & BIT4)) {
4094 /* BT auto report already enabled, do nothing */
4095 } else {
4096 halbtc8192e2ant_bt_autoreport(btcoexist, FORCE_EXEC,
4097 true);
4098 }
4099#endif
4100 }
4101
4102 /* check BIT2 first ==> check if bt is under inquiry or page scan */
4103 if(bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE)
4104 coex_sta->c2h_bt_inquiry_page = true;
4105 else
4106 coex_sta->c2h_bt_inquiry_page = false;
4107
4108 /* set link exist status */
4109 if (!(bt_info&BT_INFO_8192E_2ANT_B_CONNECTION)) {
4110 coex_sta->bt_link_exist = false;
4111 coex_sta->pan_exist = false;
4112 coex_sta->a2dp_exist = false;
4113 coex_sta->hid_exist = false;
4114 coex_sta->sco_exist = false;
4115 } else {/* connection exists */
4116 coex_sta->bt_link_exist = true;
4117 if (bt_info & BT_INFO_8192E_2ANT_B_FTP)
4118 coex_sta->pan_exist = true;
4119 else
4120 coex_sta->pan_exist = false;
4121 if (bt_info & BT_INFO_8192E_2ANT_B_A2DP)
4122 coex_sta->a2dp_exist = true;
4123 else
4124 coex_sta->a2dp_exist = false;
4125 if (bt_info & BT_INFO_8192E_2ANT_B_HID)
4126 coex_sta->hid_exist = true;
4127 else
4128 coex_sta->hid_exist = false;
4129 if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO)
4130 coex_sta->sco_exist = true;
4131 else
4132 coex_sta->sco_exist = false;
4133 }
4134
4135 halbtc8192e2ant_update_btlink_info(btcoexist);
4136
4137 if (!(bt_info&BT_INFO_8192E_2ANT_B_CONNECTION)) {
4138 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
4139 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4140 "[BTCoex], BT Non-Connected idle!!!\n");
4141 } else if (bt_info == BT_INFO_8192E_2ANT_B_CONNECTION) {
4142 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE;
4143 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4144 "[BTCoex], bt_infoNotify(), BT Connected-idle!!!\n");
4145 } else if ((bt_info&BT_INFO_8192E_2ANT_B_SCO_ESCO) ||
4146 (bt_info&BT_INFO_8192E_2ANT_B_SCO_BUSY)) {
4147 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY;
4148 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4149 "[BTCoex], bt_infoNotify(), BT SCO busy!!!\n");
4150 } else if (bt_info&BT_INFO_8192E_2ANT_B_ACL_BUSY) {
4151 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY;
4152 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4153 "[BTCoex], bt_infoNotify(), BT ACL busy!!!\n");
4154 } else {
4155 coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX;
4156 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4157 "[BTCoex]bt_infoNotify(), BT Non-Defined state!!!\n");
4158 }
4159
4160 if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
4161 (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
4162 (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
4163 bt_busy = true;
4164 limited_dig = true;
4165 } else {
4166 bt_busy = false;
4167 limited_dig = false;
4168 }
4169
4170 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
4171
4172 coex_dm->limited_dig = limited_dig;
4173 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
4174
4175 halbtc8192e2ant_run_coexist_mechanism(btcoexist);
4176}
4177
4178void ex_halbtc8192e2ant_stack_operation_notify(struct btc_coexist *btcoexist,
4179 u8 type)
4180{
4181 if (BTC_STACK_OP_INQ_PAGE_PAIR_START == type)
4182 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
4183 "[BTCoex] StackOP Inquiry/page/pair start notify\n");
4184 else if(BTC_STACK_OP_INQ_PAGE_PAIR_FINISH == type)
4185 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
4186 "[BTCoex] StackOP Inquiry/page/pair finish notify\n");
4187}
4188
4189void ex_halbtc8192e2ant_halt_notify(struct btc_coexist *btcoexist)
4190{
4191 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, "[BTCoex], Halt notify\n");
4192
4193 halbtc8192e2ant_IgnoreWlanAct(btcoexist, FORCE_EXEC, true);
4194 ex_halbtc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
4195}
4196
4197void ex_halbtc8192e2ant_periodical(struct btc_coexist *btcoexist)
4198{
4199 static u8 dis_ver_info_cnt = 0;
4200 u32 fw_ver = 0, bt_patch_ver = 0;
4201 struct btc_board_info *board_info=&btcoexist->board_info;
4202 struct btc_stack_info *stack_info=&btcoexist->stack_info;
4203
4204 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4205 "=======================Periodical=======================\n");
4206 if (dis_ver_info_cnt <= 5) {
4207 dis_ver_info_cnt += 1;
4208 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4209 "************************************************\n");
4210 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4211 "Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n",
4212 board_info->pg_ant_num, board_info->btdm_ant_num,
4213 board_info->btdm_ant_pos);
4214 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4215 "BT stack/ hci ext ver = %s / %d\n",
4216 ((stack_info->profile_notified) ? "Yes" : "No"),
4217 stack_info->hci_version);
4218 btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
4219 &bt_patch_ver);
4220 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
4221 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4222 "CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n",
4223 glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
4224 fw_ver, bt_patch_ver, bt_patch_ver);
4225 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4226 "************************************************\n");
4227 }
4228
4229#if(BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
4230 halbtc8192e2ant_querybt_info(btcoexist);
4231 halbtc8192e2ant_monitor_bt_ctr(btcoexist);
4232 halbtc8192e2ant_monitor_bt_enable_disable(btcoexist);
4233#else
4234 if (halbtc8192e2ant_iswifi_status_changed(btcoexist) ||
4235 coex_dm->auto_tdma_adjust)
4236 halbtc8192e2ant_run_coexist_mechanism(btcoexist);
4237#endif
4238}
4239
4240
4241#endif
4242
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtc8192e2ant.h b/drivers/staging/rtl8821ae/btcoexist/halbtc8192e2ant.h
new file mode 100644
index 000000000000..6d109edb8950
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtc8192e2ant.h
@@ -0,0 +1,162 @@
1/*****************************************************************
2 * The following is for 8192E 2Ant BT Co-exist definition
3 *****************************************************************/
4#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0
5
6#define BT_INFO_8192E_2ANT_B_FTP BIT7
7#define BT_INFO_8192E_2ANT_B_A2DP BIT6
8#define BT_INFO_8192E_2ANT_B_HID BIT5
9#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
10#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
11#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
12#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
13#define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
14
15#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2
16
17enum bt_info_src_8192e_2ant{
18 BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0,
19 BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1,
20 BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2,
21 BT_INFO_SRC_8192E_2ANT_MAX
22};
23
24enum bt_8192e_2ant_bt_status{
25 BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
26 BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
27 BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2,
28 BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3,
29 BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4,
30 BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
31 BT_8192E_2ANT_BT_STATUS_MAX
32};
33
34enum bt_8192e_2ant_coex_algo{
35 BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0,
36 BT_8192E_2ANT_COEX_ALGO_SCO = 0x1,
37 BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2,
38 BT_8192E_2ANT_COEX_ALGO_HID = 0x3,
39 BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4,
40 BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
41 BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6,
42 BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7,
43 BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
44 BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
45 BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
46 BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb,
47 BT_8192E_2ANT_COEX_ALGO_MAX = 0xc
48};
49
50struct coex_dm_8192e_2ant{
51 /* fw mechanism */
52 u8 pre_dec_bt_pwr;
53 u8 cur_dec_bt_pwr;
54 u8 pre_fw_dac_swing_lvl;
55 u8 cur_fw_dac_swing_lvl;
56 bool cur_ignore_wlan_act;
57 bool pre_ignore_wlan_act;
58 u8 pre_ps_tdma;
59 u8 cur_ps_tdma;
60 u8 ps_tdma_para[5];
61 u8 ps_tdma_du_adj_type;
62 bool reset_tdma_adjust;
63 bool auto_tdma_adjust;
64 bool pre_ps_tdma_on;
65 bool cur_ps_tdma_on;
66 bool pre_bt_auto_report;
67 bool cur_bt_auto_report;
68
69 /* sw mechanism */
70 bool pre_rf_rx_lpf_shrink;
71 bool cur_rf_rx_lpf_shrink;
72 u32 bt_rf0x1e_backup;
73 bool pre_low_penalty_ra;
74 bool cur_low_penalty_ra;
75 bool pre_dac_swing_on;
76 u32 pre_dac_swing_lvl;
77 bool cur_dac_swing_on;
78 u32 cur_dac_swing_lvl;
79 bool pre_adc_back_off;
80 bool cur_adc_back_off;
81 bool pre_agc_table_en;
82 bool cur_agc_table_en;
83 u32 pre_val0x6c0;
84 u32 cur_val0x6c0;
85 u32 pre_val0x6c4;
86 u32 cur_val0x6c4;
87 u32 pre_val0x6c8;
88 u32 cur_val0x6c8;
89 u8 pre_val0x6cc;
90 u8 cur_val0x6cc;
91 bool limited_dig;
92
93 u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
94 u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
95 u16 backup_retrylimit;
96 u8 backup_ampdu_maxtime;
97
98 /* algorithm related */
99 u8 pre_algorithm;
100 u8 cur_algorithm;
101 u8 bt_status;
102 u8 wifi_chnl_info[3];
103
104 u8 pre_sstype;
105 u8 cur_sstype;
106
107 u32 prera_mask;
108 u32 curra_mask;
109 u8 curra_masktype;
110 u8 pre_arfrtype;
111 u8 cur_arfrtype;
112 u8 pre_retrylimit_type;
113 u8 cur_retrylimit_type;
114 u8 pre_ampdutime_type;
115 u8 cur_ampdutime_type;
116};
117
118struct coex_sta_8192e_2ant{
119 bool bt_link_exist;
120 bool sco_exist;
121 bool a2dp_exist;
122 bool hid_exist;
123 bool pan_exist;
124
125 bool under_lps;
126 bool under_ips;
127 u32 high_priority_tx;
128 u32 high_priority_rx;
129 u32 low_priority_tx;
130 u32 low_priority_rx;
131 u8 bt_rssi;
132 u8 pre_bt_rssi_state;
133 u8 pre_wifi_rssi_state[4];
134 bool c2h_bt_info_req_sent;
135 u8 bt_info_c2h[BT_INFO_SRC_8192E_2ANT_MAX][10];
136 u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_2ANT_MAX];
137 bool c2h_bt_inquiry_page;
138 u8 bt_retry_cnt;
139 u8 bt_info_ext;
140};
141
142/****************************************************************
143 * The following is interface which will notify coex module.
144 ****************************************************************/
145void ex_halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist);
146void ex_halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist);
147void ex_halbtc8192e2ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
148void ex_halbtc8192e2ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
149void ex_halbtc8192e2ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
150void ex_halbtc8192e2ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
151void ex_halbtc8192e2ant_media_status_notify(struct btc_coexist *btcoexist,
152 u8 type);
153void ex_halbtc8192e2ant_special_packet_notify(struct btc_coexist *btcoexist,
154 u8 type);
155void ex_halbtc8192e2ant_bt_info_notify(struct btc_coexist *btcoexist,
156 u8 *tmpBuf,u8 length);
157void ex_halbtc8192e2ant_stack_operation_notify(struct btc_coexist *btcoexist,
158 u8 type);
159void ex_halbtc8192e2ant_halt_notify(struct btc_coexist *btcoexist);
160void ex_halbtc8192e2ant_periodical(struct btc_coexist *btcoexist);
161void ex_halbtc8192e2ant_display_coex_info(struct btc_coexist *btcoexist);
162
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtc8723a2ant.c b/drivers/staging/rtl8821ae/btcoexist/halbtc8723a2ant.c
new file mode 100644
index 000000000000..180d6f12e7b5
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtc8723a2ant.c
@@ -0,0 +1,3780 @@
1//============================================================
2// Description:
3//
4// This file is for RTL8723A Co-exist mechanism
5//
6// History
7// 2012/08/22 Cosa first check in.
8// 2012/11/14 Cosa Revise for 8723A 2Ant out sourcing.
9//
10//============================================================
11
12//============================================================
13// include files
14//============================================================
15#include "Mp_Precomp.h"
16#if(BT_30_SUPPORT == 1)
17//============================================================
18// Global variables, these are static variables
19//============================================================
20static COEX_DM_8723A_2ANT GLCoexDm8723a2Ant;
21static PCOEX_DM_8723A_2ANT pCoexDm=&GLCoexDm8723a2Ant;
22static COEX_STA_8723A_2ANT GLCoexSta8723a2Ant;
23static PCOEX_STA_8723A_2ANT pCoexSta=&GLCoexSta8723a2Ant;
24
25const char *const GLBtInfoSrc8723a2Ant[]={
26 "BT Info[wifi fw]",
27 "BT Info[bt rsp]",
28 "BT Info[bt auto report]",
29};
30
31//============================================================
32// local function proto type if needed
33//============================================================
34//============================================================
35// local function start with halbtc8723a2ant_
36//============================================================
37BOOLEAN
38halbtc8723a2ant_IsWifiIdle(
39 IN PBTC_COEXIST pBtCoexist
40 )
41{
42 BOOLEAN bWifiConnected=FALSE, bScan=FALSE, bLink=FALSE, bRoam=FALSE;
43
44 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
45 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
46 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
47 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
48
49 if(bWifiConnected)
50 return FALSE;
51 if(bScan)
52 return FALSE;
53 if(bLink)
54 return FALSE;
55 if(bRoam)
56 return FALSE;
57
58 return true;
59}
60
61u1Byte
62halbtc8723a2ant_BtRssiState(
63 u1Byte levelNum,
64 u1Byte rssiThresh,
65 u1Byte rssiThresh1
66 )
67{
68 s4Byte btRssi=0;
69 u1Byte btRssiState=pCoexSta->preBtRssiState;
70
71 btRssi = pCoexSta->btRssi;
72
73 if(levelNum == 2)
74 {
75 if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) ||
76 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW))
77 {
78 if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
79 {
80 btRssiState = BTC_RSSI_STATE_HIGH;
81 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to High\n"));
82 }
83 else
84 {
85 btRssiState = BTC_RSSI_STATE_STAY_LOW;
86 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at Low\n"));
87 }
88 }
89 else
90 {
91 if(btRssi < rssiThresh)
92 {
93 btRssiState = BTC_RSSI_STATE_LOW;
94 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Low\n"));
95 }
96 else
97 {
98 btRssiState = BTC_RSSI_STATE_STAY_HIGH;
99 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at High\n"));
100 }
101 }
102 }
103 else if(levelNum == 3)
104 {
105 if(rssiThresh > rssiThresh1)
106 {
107 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi thresh error!!\n"));
108 return pCoexSta->preBtRssiState;
109 }
110
111 if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) ||
112 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW))
113 {
114 if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
115 {
116 btRssiState = BTC_RSSI_STATE_MEDIUM;
117 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Medium\n"));
118 }
119 else
120 {
121 btRssiState = BTC_RSSI_STATE_STAY_LOW;
122 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at Low\n"));
123 }
124 }
125 else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) ||
126 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM))
127 {
128 if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
129 {
130 btRssiState = BTC_RSSI_STATE_HIGH;
131 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to High\n"));
132 }
133 else if(btRssi < rssiThresh)
134 {
135 btRssiState = BTC_RSSI_STATE_LOW;
136 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Low\n"));
137 }
138 else
139 {
140 btRssiState = BTC_RSSI_STATE_STAY_MEDIUM;
141 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at Medium\n"));
142 }
143 }
144 else
145 {
146 if(btRssi < rssiThresh1)
147 {
148 btRssiState = BTC_RSSI_STATE_MEDIUM;
149 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state switch to Medium\n"));
150 }
151 else
152 {
153 btRssiState = BTC_RSSI_STATE_STAY_HIGH;
154 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE, ("[BTCoex], BT Rssi state stay at High\n"));
155 }
156 }
157 }
158
159 pCoexSta->preBtRssiState = btRssiState;
160
161 return btRssiState;
162}
163
164u1Byte
165halbtc8723a2ant_WifiRssiState(
166 IN PBTC_COEXIST pBtCoexist,
167 IN u1Byte index,
168 IN u1Byte levelNum,
169 IN u1Byte rssiThresh,
170 IN u1Byte rssiThresh1
171 )
172{
173 s4Byte wifiRssi=0;
174 u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index];
175
176 pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
177
178 if(levelNum == 2)
179 {
180 if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
181 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
182 {
183 if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
184 {
185 wifiRssiState = BTC_RSSI_STATE_HIGH;
186 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to High\n"));
187 }
188 else
189 {
190 wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
191 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at Low\n"));
192 }
193 }
194 else
195 {
196 if(wifiRssi < rssiThresh)
197 {
198 wifiRssiState = BTC_RSSI_STATE_LOW;
199 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Low\n"));
200 }
201 else
202 {
203 wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
204 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at High\n"));
205 }
206 }
207 }
208 else if(levelNum == 3)
209 {
210 if(rssiThresh > rssiThresh1)
211 {
212 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI thresh error!!\n"));
213 return pCoexSta->preWifiRssiState[index];
214 }
215
216 if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) ||
217 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW))
218 {
219 if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
220 {
221 wifiRssiState = BTC_RSSI_STATE_MEDIUM;
222 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Medium\n"));
223 }
224 else
225 {
226 wifiRssiState = BTC_RSSI_STATE_STAY_LOW;
227 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at Low\n"));
228 }
229 }
230 else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) ||
231 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM))
232 {
233 if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT))
234 {
235 wifiRssiState = BTC_RSSI_STATE_HIGH;
236 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to High\n"));
237 }
238 else if(wifiRssi < rssiThresh)
239 {
240 wifiRssiState = BTC_RSSI_STATE_LOW;
241 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Low\n"));
242 }
243 else
244 {
245 wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM;
246 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at Medium\n"));
247 }
248 }
249 else
250 {
251 if(wifiRssi < rssiThresh1)
252 {
253 wifiRssiState = BTC_RSSI_STATE_MEDIUM;
254 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state switch to Medium\n"));
255 }
256 else
257 {
258 wifiRssiState = BTC_RSSI_STATE_STAY_HIGH;
259 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE, ("[BTCoex], wifi RSSI state stay at High\n"));
260 }
261 }
262 }
263
264 pCoexSta->preWifiRssiState[index] = wifiRssiState;
265
266 return wifiRssiState;
267}
268
269VOID
270halbtc8723a2ant_IndicateWifiChnlBwInfo(
271 IN PBTC_COEXIST pBtCoexist,
272 IN u1Byte type
273 )
274{
275 u1Byte H2C_Parameter[3] ={0};
276 u4Byte wifiBw;
277 u1Byte wifiCentralChnl;
278
279 // only 2.4G we need to inform bt the chnl mask
280 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl);
281 if( (BTC_MEDIA_CONNECT == type) &&
282 (wifiCentralChnl <= 14) )
283 {
284 H2C_Parameter[0] = 0x1;
285 H2C_Parameter[1] = wifiCentralChnl;
286 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
287 if(BTC_WIFI_BW_HT40 == wifiBw)
288 H2C_Parameter[2] = 0x30;
289 else
290 H2C_Parameter[2] = 0x20;
291 }
292
293 pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0];
294 pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1];
295 pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2];
296
297 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], FW write 0x19=0x%x\n",
298 H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2]));
299
300 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x19, 3, H2C_Parameter);
301}
302
303VOID
304halbtc8723a2ant_QueryBtInfo(
305 IN PBTC_COEXIST pBtCoexist
306 )
307{
308 u1Byte H2C_Parameter[1] ={0};
309
310 pCoexSta->bC2hBtInfoReqSent = true;
311
312 H2C_Parameter[0] |= BIT0; // trigger
313
314 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], Query Bt Info, FW write 0x38=0x%x\n",
315 H2C_Parameter[0]));
316
317 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x38, 1, H2C_Parameter);
318}
319u1Byte
320halbtc8723a2ant_ActionAlgorithm(
321 IN PBTC_COEXIST pBtCoexist
322 )
323{
324 PBTC_STACK_INFO pStackInfo=&pBtCoexist->stack_info;
325 BOOLEAN bBtHsOn=FALSE, bBtBusy=FALSE, limited_dig=FALSE;
326 u1Byte algorithm=BT_8723A_2ANT_COEX_ALGO_UNDEFINED;
327 u1Byte numOfDiffProfile=0;
328
329 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
330
331 //======================
332 // here we get BT status first
333 //======================
334 pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_IDLE;
335
336 if((pStackInfo->bScoExist) ||(bBtHsOn) ||(pStackInfo->bHidExist))
337 {
338 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO or HID or HS exists, set BT non-idle !!!\n"));
339 pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE;
340 }
341 else
342 {
343 // A2dp profile
344 if( (pBtCoexist->stack_info.numOfLink == 1) &&
345 (pStackInfo->bA2dpExist) )
346 {
347 if( (pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 100)
348 {
349 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP, low priority tx+rx < 100, set BT connected-idle!!!\n"));
350 pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE;
351 }
352 else
353 {
354 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP, low priority tx+rx >= 100, set BT non-idle!!!\n"));
355 pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE;
356 }
357 }
358 // Pan profile
359 if( (pBtCoexist->stack_info.numOfLink == 1) &&
360 (pStackInfo->bPanExist) )
361 {
362 if((pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 600)
363 {
364 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN, low priority tx+rx < 600, set BT connected-idle!!!\n"));
365 pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE;
366 }
367 else
368 {
369 if(pCoexSta->lowPriorityTx)
370 {
371 if((pCoexSta->lowPriorityRx /pCoexSta->lowPriorityTx)>9 )
372 {
373 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN, low priority rx/tx > 9, set BT connected-idle!!!\n"));
374 pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE;
375 }
376 }
377 }
378 if(BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus)
379 {
380 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN, set BT non-idle!!!\n"));
381 pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE;
382 }
383 }
384 // Pan+A2dp profile
385 if( (pBtCoexist->stack_info.numOfLink == 2) &&
386 (pStackInfo->bA2dpExist) &&
387 (pStackInfo->bPanExist) )
388 {
389 if((pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 600)
390 {
391 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN+A2DP, low priority tx+rx < 600, set BT connected-idle!!!\n"));
392 pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE;
393 }
394 else
395 {
396 if(pCoexSta->lowPriorityTx)
397 {
398 if((pCoexSta->lowPriorityRx /pCoexSta->lowPriorityTx)>9 )
399 {
400 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN+A2DP, low priority rx/tx > 9, set BT connected-idle!!!\n"));
401 pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE;
402 }
403 }
404 }
405 if(BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus)
406 {
407 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN+A2DP, set BT non-idle!!!\n"));
408 pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE;
409 }
410 }
411 }
412 if(BT_8723A_2ANT_BT_STATUS_IDLE != pCoexDm->btStatus)
413 {
414 bBtBusy = true;
415 limited_dig = true;
416 }
417 else
418 {
419 bBtBusy = FALSE;
420 limited_dig = FALSE;
421 }
422 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy);
423 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
424 //======================
425
426 if(!pStackInfo->bBtLinkExist)
427 {
428 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], No profile exists!!!\n"));
429 return algorithm;
430 }
431
432 if(pStackInfo->bScoExist)
433 numOfDiffProfile++;
434 if(pStackInfo->bHidExist)
435 numOfDiffProfile++;
436 if(pStackInfo->bPanExist)
437 numOfDiffProfile++;
438 if(pStackInfo->bA2dpExist)
439 numOfDiffProfile++;
440
441 if(numOfDiffProfile == 1)
442 {
443 if(pStackInfo->bScoExist)
444 {
445 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO only\n"));
446 algorithm = BT_8723A_2ANT_COEX_ALGO_SCO;
447 }
448 else
449 {
450 if(pStackInfo->bHidExist)
451 {
452 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID only\n"));
453 algorithm = BT_8723A_2ANT_COEX_ALGO_HID;
454 }
455 else if(pStackInfo->bA2dpExist)
456 {
457 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP only\n"));
458 algorithm = BT_8723A_2ANT_COEX_ALGO_A2DP;
459 }
460 else if(pStackInfo->bPanExist)
461 {
462 if(bBtHsOn)
463 {
464 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN(HS) only\n"));
465 algorithm = BT_8723A_2ANT_COEX_ALGO_PANHS;
466 }
467 else
468 {
469 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], PAN(EDR) only\n"));
470 algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR;
471 }
472 }
473 }
474 }
475 else if(numOfDiffProfile == 2)
476 {
477 if(pStackInfo->bScoExist)
478 {
479 if(pStackInfo->bHidExist)
480 {
481 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID\n"));
482 algorithm = BT_8723A_2ANT_COEX_ALGO_HID;
483 }
484 else if(pStackInfo->bA2dpExist)
485 {
486 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + A2DP ==> SCO\n"));
487 algorithm = BT_8723A_2ANT_COEX_ALGO_SCO;
488 }
489 else if(pStackInfo->bPanExist)
490 {
491 if(bBtHsOn)
492 {
493 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + PAN(HS)\n"));
494 algorithm = BT_8723A_2ANT_COEX_ALGO_SCO;
495 }
496 else
497 {
498 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + PAN(EDR)\n"));
499 algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID;
500 }
501 }
502 }
503 else
504 {
505 if( pStackInfo->bHidExist &&
506 pStackInfo->bA2dpExist )
507 {
508 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + A2DP\n"));
509 algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP;
510 }
511 else if( pStackInfo->bHidExist &&
512 pStackInfo->bPanExist )
513 {
514 if(bBtHsOn)
515 {
516 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + PAN(HS)\n"));
517 algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP;
518 }
519 else
520 {
521 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + PAN(EDR)\n"));
522 algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID;
523 }
524 }
525 else if( pStackInfo->bPanExist &&
526 pStackInfo->bA2dpExist )
527 {
528 if(bBtHsOn)
529 {
530 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP + PAN(HS)\n"));
531 algorithm = BT_8723A_2ANT_COEX_ALGO_A2DP;
532 }
533 else
534 {
535 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], A2DP + PAN(EDR)\n"));
536 algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP;
537 }
538 }
539 }
540 }
541 else if(numOfDiffProfile == 3)
542 {
543 if(pStackInfo->bScoExist)
544 {
545 if( pStackInfo->bHidExist &&
546 pStackInfo->bA2dpExist )
547 {
548 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + A2DP ==> HID\n"));
549 algorithm = BT_8723A_2ANT_COEX_ALGO_HID;
550 }
551 else if( pStackInfo->bHidExist &&
552 pStackInfo->bPanExist )
553 {
554 if(bBtHsOn)
555 {
556 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + PAN(HS)\n"));
557 algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP;
558 }
559 else
560 {
561 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + PAN(EDR)\n"));
562 algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID;
563 }
564 }
565 else if( pStackInfo->bPanExist &&
566 pStackInfo->bA2dpExist )
567 {
568 if(bBtHsOn)
569 {
570 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + A2DP + PAN(HS)\n"));
571 algorithm = BT_8723A_2ANT_COEX_ALGO_SCO;
572 }
573 else
574 {
575 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"));
576 algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID;
577 }
578 }
579 }
580 else
581 {
582 if( pStackInfo->bHidExist &&
583 pStackInfo->bPanExist &&
584 pStackInfo->bA2dpExist )
585 {
586 if(bBtHsOn)
587 {
588 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + A2DP + PAN(HS)\n"));
589 algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP;
590 }
591 else
592 {
593 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], HID + A2DP + PAN(EDR)\n"));
594 algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
595 }
596 }
597 }
598 }
599 else if(numOfDiffProfile >= 3)
600 {
601 if(pStackInfo->bScoExist)
602 {
603 if( pStackInfo->bHidExist &&
604 pStackInfo->bPanExist &&
605 pStackInfo->bA2dpExist )
606 {
607 if(bBtHsOn)
608 {
609 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"));
610
611 }
612 else
613 {
614 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"));
615 algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID;
616 }
617 }
618 }
619 }
620
621 return algorithm;
622}
623
624BOOLEAN
625halbtc8723a2ant_NeedToDecBtPwr(
626 IN PBTC_COEXIST pBtCoexist
627 )
628{
629 BOOLEAN bRet=FALSE;
630 BOOLEAN bBtHsOn=FALSE, bWifiConnected=FALSE;
631 s4Byte btHsRssi=0;
632
633 if(!pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn))
634 return FALSE;
635 if(!pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected))
636 return FALSE;
637 if(!pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_HS_RSSI, &btHsRssi))
638 return FALSE;
639
640 if(bWifiConnected)
641 {
642 if(bBtHsOn)
643 {
644 if(btHsRssi > 37)
645 {
646 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], Need to decrease bt power for HS mode!!\n"));
647 bRet = true;
648 }
649 }
650 else
651 {
652 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], Need to decrease bt power for Wifi is connected!!\n"));
653 bRet = true;
654 }
655 }
656
657 return bRet;
658}
659
660VOID
661halbtc8723a2ant_SetFwDacSwingLevel(
662 IN PBTC_COEXIST pBtCoexist,
663 IN u1Byte dacSwingLvl
664 )
665{
666 u1Byte H2C_Parameter[1] ={0};
667
668 // There are several type of dacswing
669 // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6
670 H2C_Parameter[0] = dacSwingLvl;
671
672 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl));
673 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], FW write 0x29=0x%x\n", H2C_Parameter[0]));
674
675 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x29, 1, H2C_Parameter);
676}
677
678VOID
679halbtc8723a2ant_SetFwDecBtPwr(
680 IN PBTC_COEXIST pBtCoexist,
681 IN BOOLEAN bDecBtPwr
682 )
683{
684 u1Byte H2C_Parameter[1] ={0};
685
686 H2C_Parameter[0] = 0;
687
688 if(bDecBtPwr)
689 {
690 H2C_Parameter[0] |= BIT1;
691 }
692
693 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], decrease Bt Power : %s, FW write 0x21=0x%x\n",
694 (bDecBtPwr? "Yes!!":"No!!"), H2C_Parameter[0]));
695
696 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x21, 1, H2C_Parameter);
697}
698
699VOID
700halbtc8723a2ant_DecBtPwr(
701 IN PBTC_COEXIST pBtCoexist,
702 IN BOOLEAN bForceExec,
703 IN BOOLEAN bDecBtPwr
704 )
705{
706 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s Dec BT power = %s\n",
707 (bForceExec? "force to":""), ((bDecBtPwr)? "ON":"OFF")));
708 pCoexDm->bCurDecBtPwr = bDecBtPwr;
709
710 if(!bForceExec)
711 {
712 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPreDecBtPwr=%d, bCurDecBtPwr=%d\n",
713 pCoexDm->bPreDecBtPwr, pCoexDm->bCurDecBtPwr));
714
715 if(pCoexDm->bPreDecBtPwr == pCoexDm->bCurDecBtPwr)
716 return;
717 }
718 halbtc8723a2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->bCurDecBtPwr);
719
720 pCoexDm->bPreDecBtPwr = pCoexDm->bCurDecBtPwr;
721}
722
723VOID
724halbtc8723a2ant_FwDacSwingLvl(
725 IN PBTC_COEXIST pBtCoexist,
726 IN BOOLEAN bForceExec,
727 IN u1Byte fwDacSwingLvl
728 )
729{
730 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s set FW Dac Swing level = %d\n",
731 (bForceExec? "force to":""), fwDacSwingLvl));
732 pCoexDm->curFwDacSwingLvl = fwDacSwingLvl;
733
734 if(!bForceExec)
735 {
736 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], preFwDacSwingLvl=%d, curFwDacSwingLvl=%d\n",
737 pCoexDm->preFwDacSwingLvl, pCoexDm->curFwDacSwingLvl));
738
739 if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl)
740 return;
741 }
742
743 halbtc8723a2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl);
744
745 pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl;
746}
747
748VOID
749halbtc8723a2ant_SetSwRfRxLpfCorner(
750 IN PBTC_COEXIST pBtCoexist,
751 IN BOOLEAN bRxRfShrinkOn
752 )
753{
754 if(bRxRfShrinkOn)
755 {
756 //Shrink RF Rx LPF corner
757 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Shrink RF Rx LPF corner!!\n"));
758 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf0ff7);
759 }
760 else
761 {
762 //Resume RF Rx LPF corner
763 // After initialized, we can use pCoexDm->btRf0x1eBackup
764 if(pBtCoexist->initilized)
765 {
766 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Resume RF Rx LPF corner!!\n"));
767 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup);
768 }
769 }
770}
771
772VOID
773halbtc8723a2ant_RfShrink(
774 IN PBTC_COEXIST pBtCoexist,
775 IN BOOLEAN bForceExec,
776 IN BOOLEAN bRxRfShrinkOn
777 )
778{
779 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn Rx RF Shrink = %s\n",
780 (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF")));
781 pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn;
782
783 if(!bForceExec)
784 {
785 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreRfRxLpfShrink=%d, bCurRfRxLpfShrink=%d\n",
786 pCoexDm->bPreRfRxLpfShrink, pCoexDm->bCurRfRxLpfShrink));
787
788 if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink)
789 return;
790 }
791 halbtc8723a2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink);
792
793 pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink;
794}
795
796VOID
797halbtc8723a2ant_SetSwPenaltyTxRateAdaptive(
798 IN PBTC_COEXIST pBtCoexist,
799 IN BOOLEAN bLowPenaltyRa
800 )
801{
802 u1Byte tmpU1;
803
804 tmpU1 = pBtCoexist->btc_read_1byte(pBtCoexist, 0x4fd);
805 tmpU1 |= BIT0;
806 if(bLowPenaltyRa)
807 {
808 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Tx rate adaptive, set low penalty!!\n"));
809 tmpU1 &= ~BIT2;
810 }
811 else
812 {
813 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Tx rate adaptive, set normal!!\n"));
814 tmpU1 |= BIT2;
815 }
816
817 pBtCoexist->btc_write_1byte(pBtCoexist, 0x4fd, tmpU1);
818}
819
820VOID
821halbtc8723a2ant_LowPenaltyRa(
822 IN PBTC_COEXIST pBtCoexist,
823 IN BOOLEAN bForceExec,
824 IN BOOLEAN bLowPenaltyRa
825 )
826{
827 return;
828 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn LowPenaltyRA = %s\n",
829 (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF")));
830 pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa;
831
832 if(!bForceExec)
833 {
834 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreLowPenaltyRa=%d, bCurLowPenaltyRa=%d\n",
835 pCoexDm->bPreLowPenaltyRa, pCoexDm->bCurLowPenaltyRa));
836
837 if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa)
838 return;
839 }
840 halbtc8723a2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa);
841
842 pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa;
843}
844
845VOID
846halbtc8723a2ant_SetSwFullTimeDacSwing(
847 IN PBTC_COEXIST pBtCoexist,
848 IN BOOLEAN bSwDacSwingOn,
849 IN u4Byte swDacSwingLvl
850 )
851{
852 if(bSwDacSwingOn)
853 {
854 pBtCoexist->btc_setBbReg(pBtCoexist, 0x880, 0xff000000, swDacSwingLvl);
855 }
856 else
857 {
858 pBtCoexist->btc_setBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0);
859 }
860}
861
862
863VOID
864halbtc8723a2ant_DacSwing(
865 IN PBTC_COEXIST pBtCoexist,
866 IN BOOLEAN bForceExec,
867 IN BOOLEAN bDacSwingOn,
868 IN u4Byte dacSwingLvl
869 )
870{
871 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n",
872 (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl));
873 pCoexDm->bCurDacSwingOn = bDacSwingOn;
874 pCoexDm->curDacSwingLvl = dacSwingLvl;
875
876 if(!bForceExec)
877 {
878 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl=0x%x, bCurDacSwingOn=%d, curDacSwingLvl=0x%x\n",
879 pCoexDm->bPreDacSwingOn, pCoexDm->preDacSwingLvl,
880 pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl));
881
882 if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) &&
883 (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) )
884 return;
885 }
886 mdelay(30);
887 halbtc8723a2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl);
888
889 pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn;
890 pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl;
891}
892
893VOID
894halbtc8723a2ant_SetAdcBackOff(
895 IN PBTC_COEXIST pBtCoexist,
896 IN BOOLEAN bAdcBackOff
897 )
898{
899 if(bAdcBackOff)
900 {
901 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], BB BackOff Level On!\n"));
902 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc04,0x3a07611);
903 }
904 else
905 {
906 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], BB BackOff Level Off!\n"));
907 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc04,0x3a05611);
908 }
909}
910
911VOID
912halbtc8723a2ant_AdcBackOff(
913 IN PBTC_COEXIST pBtCoexist,
914 IN BOOLEAN bForceExec,
915 IN BOOLEAN bAdcBackOff
916 )
917{
918 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s turn AdcBackOff = %s\n",
919 (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF")));
920 pCoexDm->bCurAdcBackOff = bAdcBackOff;
921
922 if(!bForceExec)
923 {
924 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreAdcBackOff=%d, bCurAdcBackOff=%d\n",
925 pCoexDm->bPreAdcBackOff, pCoexDm->bCurAdcBackOff));
926
927 if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff)
928 return;
929 }
930 halbtc8723a2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff);
931
932 pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff;
933}
934
935VOID
936halbtc8723a2ant_SetAgcTable(
937 IN PBTC_COEXIST pBtCoexist,
938 IN BOOLEAN bAgcTableEn
939 )
940{
941 u1Byte rssiAdjustVal=0;
942
943 if(bAgcTableEn)
944 {
945 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Agc Table On!\n"));
946 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc78,0x4e1c0001);
947 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc78,0x4d1d0001);
948 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc78,0x4c1e0001);
949 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc78,0x4b1f0001);
950 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc78,0x4a200001);
951
952 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000);
953 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x90000);
954 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x51000);
955 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x12000);
956 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x00355);
957
958 rssiAdjustVal = 6;
959 }
960 else
961 {
962 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], Agc Table Off!\n"));
963 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc78,0x641c0001);
964 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc78,0x631d0001);
965 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc78,0x621e0001);
966 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc78,0x611f0001);
967 pBtCoexist->btc_write_4byte(pBtCoexist, 0xc78,0x60200001);
968
969 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x32000);
970 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x71000);
971 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xb0000);
972 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xfc000);
973 pBtCoexist->btc_set_rf_reg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x30355);
974 }
975
976 // set rssiAdjustVal for wifi module.
977 pBtCoexist->btc_set(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal);
978}
979
980
981VOID
982halbtc8723a2ant_AgcTable(
983 IN PBTC_COEXIST pBtCoexist,
984 IN BOOLEAN bForceExec,
985 IN BOOLEAN bAgcTableEn
986 )
987{
988 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s %s Agc Table\n",
989 (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable")));
990 pCoexDm->bCurAgcTableEn = bAgcTableEn;
991
992 if(!bForceExec)
993 {
994 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n",
995 pCoexDm->bPreAgcTableEn, pCoexDm->bCurAgcTableEn));
996
997 if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn)
998 return;
999 }
1000 halbtc8723a2ant_SetAgcTable(pBtCoexist, bAgcTableEn);
1001
1002 pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn;
1003}
1004
1005VOID
1006halbtc8723a2ant_SetCoexTable(
1007 IN PBTC_COEXIST pBtCoexist,
1008 IN u4Byte val0x6c0,
1009 IN u4Byte val0x6c8,
1010 IN u1Byte val0x6cc
1011 )
1012{
1013 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0));
1014 pBtCoexist->btc_write_4byte(pBtCoexist, 0x6c0, val0x6c0);
1015
1016 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8));
1017 pBtCoexist->btc_write_4byte(pBtCoexist, 0x6c8, val0x6c8);
1018
1019 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc));
1020 pBtCoexist->btc_write_1byte(pBtCoexist, 0x6cc, val0x6cc);
1021}
1022
1023VOID
1024halbtc8723a2ant_CoexTable(
1025 IN PBTC_COEXIST pBtCoexist,
1026 IN BOOLEAN bForceExec,
1027 IN u4Byte val0x6c0,
1028 IN u4Byte val0x6c8,
1029 IN u1Byte val0x6cc
1030 )
1031{
1032 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
1033 (bForceExec? "force to":""), val0x6c0, val0x6c8, val0x6cc));
1034 pCoexDm->curVal0x6c0 = val0x6c0;
1035 pCoexDm->curVal0x6c8 = val0x6c8;
1036 pCoexDm->curVal0x6cc = val0x6cc;
1037
1038 if(!bForceExec)
1039 {
1040 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], preVal0x6c0=0x%x, preVal0x6c8=0x%x, preVal0x6cc=0x%x !!\n",
1041 pCoexDm->preVal0x6c0, pCoexDm->preVal0x6c8, pCoexDm->preVal0x6cc));
1042 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL, ("[BTCoex], curVal0x6c0=0x%x, curVal0x6c8=0x%x, curVal0x6cc=0x%x !!\n",
1043 pCoexDm->curVal0x6c0, pCoexDm->curVal0x6c8, pCoexDm->curVal0x6cc));
1044
1045 if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) &&
1046 (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) &&
1047 (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) )
1048 return;
1049 }
1050 halbtc8723a2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c8, val0x6cc);
1051
1052 pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0;
1053 pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8;
1054 pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc;
1055}
1056
1057VOID
1058halbtc8723a2ant_SetFwIgnoreWlanAct(
1059 IN PBTC_COEXIST pBtCoexist,
1060 IN BOOLEAN bEnable
1061 )
1062{
1063 u1Byte H2C_Parameter[1] ={0};
1064
1065 if(bEnable)
1066 {
1067 H2C_Parameter[0] |= BIT0; // function enable
1068 }
1069
1070 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x25=0x%x\n",
1071 H2C_Parameter[0]));
1072
1073 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x25, 1, H2C_Parameter);
1074}
1075
1076VOID
1077halbtc8723a2ant_IgnoreWlanAct(
1078 IN PBTC_COEXIST pBtCoexist,
1079 IN BOOLEAN bForceExec,
1080 IN BOOLEAN bEnable
1081 )
1082{
1083 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s turn Ignore WlanAct %s\n",
1084 (bForceExec? "force to":""), (bEnable? "ON":"OFF")));
1085 pCoexDm->bCurIgnoreWlanAct = bEnable;
1086
1087 if(!bForceExec)
1088 {
1089 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPreIgnoreWlanAct = %d, bCurIgnoreWlanAct = %d!!\n",
1090 pCoexDm->bPreIgnoreWlanAct, pCoexDm->bCurIgnoreWlanAct));
1091
1092 if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct)
1093 return;
1094 }
1095 halbtc8723a2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable);
1096
1097 pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct;
1098}
1099
1100VOID
1101halbtc8723a2ant_SetFwPstdma(
1102 IN PBTC_COEXIST pBtCoexist,
1103 IN u1Byte byte1,
1104 IN u1Byte byte2,
1105 IN u1Byte byte3,
1106 IN u1Byte byte4,
1107 IN u1Byte byte5
1108 )
1109{
1110 u1Byte H2C_Parameter[5] ={0};
1111
1112 H2C_Parameter[0] = byte1;
1113 H2C_Parameter[1] = byte2;
1114 H2C_Parameter[2] = byte3;
1115 H2C_Parameter[3] = byte4;
1116 H2C_Parameter[4] = byte5;
1117
1118 pCoexDm->psTdmaPara[0] = byte1;
1119 pCoexDm->psTdmaPara[1] = byte2;
1120 pCoexDm->psTdmaPara[2] = byte3;
1121 pCoexDm->psTdmaPara[3] = byte4;
1122 pCoexDm->psTdmaPara[4] = byte5;
1123
1124 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC, ("[BTCoex], FW write 0x3a(5bytes)=0x%x%08x\n",
1125 H2C_Parameter[0],
1126 H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4]));
1127
1128 pBtCoexist->btc_fill_h2c(pBtCoexist, 0x3a, 5, H2C_Parameter);
1129}
1130
1131VOID
1132halbtc8723a2ant_PsTdma(
1133 IN PBTC_COEXIST pBtCoexist,
1134 IN BOOLEAN bForceExec,
1135 IN BOOLEAN bTurnOn,
1136 IN u1Byte type
1137 )
1138{
1139 u4Byte btTxRxCnt=0;
1140
1141 btTxRxCnt = pCoexSta->highPriorityTx+pCoexSta->highPriorityRx+
1142 pCoexSta->lowPriorityTx+pCoexSta->lowPriorityRx;
1143
1144 if(btTxRxCnt > 3000)
1145 {
1146 pCoexDm->bCurPsTdmaOn = true;
1147 pCoexDm->curPsTdma = 8;
1148 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], turn ON PS TDMA, type=%d for BT tx/rx counters=%d(>3000)\n",
1149 pCoexDm->curPsTdma, btTxRxCnt));
1150 }
1151 else
1152 {
1153 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], %s turn %s PS TDMA, type=%d\n",
1154 (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type));
1155 pCoexDm->bCurPsTdmaOn = bTurnOn;
1156 pCoexDm->curPsTdma = type;
1157 }
1158
1159 if(!bForceExec)
1160 {
1161 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n",
1162 pCoexDm->bPrePsTdmaOn, pCoexDm->bCurPsTdmaOn));
1163 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n",
1164 pCoexDm->prePsTdma, pCoexDm->curPsTdma));
1165
1166 if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) &&
1167 (pCoexDm->prePsTdma == pCoexDm->curPsTdma) )
1168 return;
1169 }
1170 if(pCoexDm->bCurPsTdmaOn)
1171 {
1172 switch(pCoexDm->curPsTdma)
1173 {
1174 case 1:
1175 default:
1176 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x98);
1177 break;
1178 case 2:
1179 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x98);
1180 break;
1181 case 3:
1182 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x98);
1183 break;
1184 case 4:
1185 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x5, 0x5, 0xe1, 0x80);
1186 break;
1187 case 5:
1188 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x98);
1189 break;
1190 case 6:
1191 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x98);
1192 break;
1193 case 7:
1194 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x98);
1195 break;
1196 case 8:
1197 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x5, 0x5, 0x60, 0x80);
1198 break;
1199 case 9:
1200 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x98);
1201 break;
1202 case 10:
1203 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x98);
1204 break;
1205 case 11:
1206 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x98);
1207 break;
1208 case 12:
1209 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x98);
1210 break;
1211 case 13:
1212 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x98);
1213 break;
1214 case 14:
1215 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x98);
1216 break;
1217 case 15:
1218 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x98);
1219 break;
1220 case 16:
1221 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0x60, 0x98);
1222 break;
1223 case 17:
1224 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x2f, 0x2f, 0x60, 0x80);
1225 break;
1226 case 18:
1227 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x98);
1228 break;
1229 case 19:
1230 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x98);
1231 break;
1232 case 20:
1233 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x98);
1234 break;
1235 }
1236 }
1237 else
1238 {
1239 // disable PS tdma
1240 switch(pCoexDm->curPsTdma)
1241 {
1242 case 0:
1243 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0);
1244 break;
1245 case 1:
1246 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0);
1247 break;
1248 default:
1249 halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0);
1250 break;
1251 }
1252 }
1253
1254 // update pre state
1255 pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn;
1256 pCoexDm->prePsTdma = pCoexDm->curPsTdma;
1257}
1258
1259
1260VOID
1261halbtc8723a2ant_CoexAllOff(
1262 IN PBTC_COEXIST pBtCoexist
1263 )
1264{
1265 // fw all off
1266 halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
1267 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1268 halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
1269 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
1270
1271 // sw all off
1272 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1273 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1274 halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
1275 halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
1276 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
1277
1278 // hw all off
1279 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
1280}
1281
1282VOID
1283halbtc8723a2ant_InitCoexDm(
1284 IN PBTC_COEXIST pBtCoexist
1285 )
1286{
1287 // force to reset coex mechanism
1288 halbtc8723a2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0x55555555, 0xffff, 0x3);
1289 halbtc8723a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0);
1290 halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 0x20);
1291 halbtc8723a2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, FALSE);
1292 halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE);
1293
1294 halbtc8723a2ant_AgcTable(pBtCoexist, FORCE_EXEC, FALSE);
1295 halbtc8723a2ant_AdcBackOff(pBtCoexist, FORCE_EXEC, FALSE);
1296 halbtc8723a2ant_LowPenaltyRa(pBtCoexist, FORCE_EXEC, FALSE);
1297 halbtc8723a2ant_RfShrink(pBtCoexist, FORCE_EXEC, FALSE);
1298 halbtc8723a2ant_DacSwing(pBtCoexist, FORCE_EXEC, FALSE, 0xc0);
1299}
1300
1301VOID
1302halbtc8723a2ant_BtInquiryPage(
1303 IN PBTC_COEXIST pBtCoexist
1304 )
1305{
1306 BOOLEAN bLowPwrDisable=true;
1307
1308 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable);
1309
1310 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
1311 halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
1312 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 8);
1313}
1314
1315VOID
1316halbtc8723a2ant_BtEnableAction(
1317 IN PBTC_COEXIST pBtCoexist
1318 )
1319{
1320 BOOLEAN bWifiConnected=FALSE;
1321
1322 // Here we need to resend some wifi info to BT
1323 // because bt is reset and loss of the info.
1324 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
1325 if(bWifiConnected)
1326 {
1327 halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, BTC_MEDIA_CONNECT);
1328 }
1329 else
1330 {
1331 halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, BTC_MEDIA_DISCONNECT);
1332 }
1333
1334 halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE);
1335}
1336
1337VOID
1338halbtc8723a2ant_MonitorBtCtr(
1339 IN PBTC_COEXIST pBtCoexist
1340 )
1341{
1342 u4Byte regHPTxRx, regLPTxRx, u4Tmp;
1343 u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0;
1344 u1Byte u1Tmp;
1345
1346 regHPTxRx = 0x770;
1347 regLPTxRx = 0x774;
1348
1349 u4Tmp = pBtCoexist->btc_read_4byte(pBtCoexist, regHPTxRx);
1350 regHPTx = u4Tmp & MASKLWORD;
1351 regHPRx = (u4Tmp & MASKHWORD)>>16;
1352
1353 u4Tmp = pBtCoexist->btc_read_4byte(pBtCoexist, regLPTxRx);
1354 regLPTx = u4Tmp & MASKLWORD;
1355 regLPRx = (u4Tmp & MASKHWORD)>>16;
1356
1357 pCoexSta->highPriorityTx = regHPTx;
1358 pCoexSta->highPriorityRx = regHPRx;
1359 pCoexSta->lowPriorityTx = regLPTx;
1360 pCoexSta->lowPriorityRx = regLPRx;
1361
1362 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
1363 regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx));
1364 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
1365 regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx));
1366
1367 // reset counter
1368 pBtCoexist->btc_write_1byte(pBtCoexist, 0x76e, 0xc);
1369}
1370
1371VOID
1372halbtc8723a2ant_MonitorBtEnableDisable(
1373 IN PBTC_COEXIST pBtCoexist
1374 )
1375{
1376 static BOOLEAN bPreBtDisabled=FALSE;
1377 static u4Byte btDisableCnt=0;
1378 BOOLEAN bBtActive=true, bBtDisabled=FALSE;
1379
1380 // This function check if bt is disabled
1381
1382 if( pCoexSta->highPriorityTx == 0 &&
1383 pCoexSta->highPriorityRx == 0 &&
1384 pCoexSta->lowPriorityTx == 0 &&
1385 pCoexSta->lowPriorityRx == 0)
1386 {
1387 bBtActive = FALSE;
1388 }
1389 if( pCoexSta->highPriorityTx == 0xffff &&
1390 pCoexSta->highPriorityRx == 0xffff &&
1391 pCoexSta->lowPriorityTx == 0xffff &&
1392 pCoexSta->lowPriorityRx == 0xffff)
1393 {
1394 bBtActive = FALSE;
1395 }
1396 if(bBtActive)
1397 {
1398 btDisableCnt = 0;
1399 bBtDisabled = FALSE;
1400 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
1401 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is enabled !!\n"));
1402 }
1403 else
1404 {
1405 btDisableCnt++;
1406 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], bt all counters=0, %d times!!\n",
1407 btDisableCnt));
1408 if(btDisableCnt >= 2)
1409 {
1410 bBtDisabled = true;
1411 pBtCoexist->btc_set(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled);
1412 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is disabled !!\n"));
1413 }
1414 }
1415 if(bPreBtDisabled != bBtDisabled)
1416 {
1417 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR, ("[BTCoex], BT is from %s to %s!!\n",
1418 (bPreBtDisabled ? "disabled":"enabled"),
1419 (bBtDisabled ? "disabled":"enabled")));
1420 bPreBtDisabled = bBtDisabled;
1421 if(!bBtDisabled)
1422 {
1423 halbtc8723a2ant_BtEnableAction(pBtCoexist);
1424 }
1425 }
1426}
1427
1428BOOLEAN
1429halbtc8723a2ant_IsCommonAction(
1430 IN PBTC_COEXIST pBtCoexist
1431 )
1432{
1433 PBTC_STACK_INFO pStackInfo=&pBtCoexist->stack_info;
1434 BOOLEAN bCommon=FALSE, bWifiConnected=FALSE;
1435 BOOLEAN bLowPwrDisable=FALSE;
1436
1437 if(!pStackInfo->bBtLinkExist)
1438 {
1439 bLowPwrDisable = FALSE;
1440 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable);
1441 }
1442 else
1443 {
1444 bLowPwrDisable = true;
1445 pBtCoexist->btc_set(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable);
1446 }
1447
1448 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected);
1449
1450 if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) &&
1451 BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus)
1452 {
1453 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi idle + Bt idle!!\n"));
1454
1455 halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE);
1456 halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
1457 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
1458
1459 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1460 halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
1461 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
1462
1463 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1464 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1465 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
1466
1467 bCommon = true;
1468 }
1469 else if(!halbtc8723a2ant_IsWifiIdle(pBtCoexist) &&
1470 (BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus) )
1471 {
1472 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi non-idle + BT idle!!\n"));
1473
1474 halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, true);
1475 halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE);
1476 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
1477
1478 halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
1479 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1480 halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
1481 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
1482
1483 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1484 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1485 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
1486
1487 bCommon = true;
1488 }
1489 else if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) &&
1490 (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) )
1491 {
1492 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi idle + Bt connected idle!!\n"));
1493
1494 halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, true);
1495 halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, true);
1496 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
1497
1498 halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
1499 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1500 halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
1501 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
1502
1503 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1504 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1505 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
1506
1507 bCommon = true;
1508 }
1509 else if(!halbtc8723a2ant_IsWifiIdle(pBtCoexist) &&
1510 (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) )
1511 {
1512 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi non-idle + Bt connected idle!!\n"));
1513
1514 halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, true);
1515 halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, true);
1516 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
1517
1518 halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
1519 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1520 halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
1521 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
1522
1523 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1524 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1525 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
1526
1527 bCommon = true;
1528 }
1529 else if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) &&
1530 (BT_8723A_2ANT_BT_STATUS_NON_IDLE == pCoexDm->btStatus) )
1531 {
1532 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi idle + BT non-idle!!\n"));
1533
1534 halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, true);
1535 halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, true);
1536 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
1537
1538 halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
1539 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
1540 halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
1541 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
1542
1543 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
1544 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
1545 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
1546
1547 bCommon = true;
1548 }
1549 else
1550 {
1551 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Wifi non-idle + BT non-idle!!\n"));
1552 halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, true);
1553 halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, true);
1554 halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE);
1555 halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20);
1556
1557 bCommon = FALSE;
1558 }
1559
1560 return bCommon;
1561}
1562VOID
1563halbtc8723a2ant_TdmaDurationAdjust(
1564 IN PBTC_COEXIST pBtCoexist,
1565 IN BOOLEAN bScoHid,
1566 IN BOOLEAN bTxPause,
1567 IN u1Byte maxInterval
1568 )
1569{
1570 static s4Byte up,dn,m,n,WaitCount;
1571 s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration
1572 u1Byte retryCount=0;
1573
1574 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW, ("[BTCoex], TdmaDurationAdjust()\n"));
1575
1576 if(pCoexDm->bResetTdmaAdjust)
1577 {
1578 pCoexDm->bResetTdmaAdjust = FALSE;
1579 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], first run TdmaDurationAdjust()!!\n"));
1580 {
1581 if(bScoHid)
1582 {
1583 if(bTxPause)
1584 {
1585 if(maxInterval == 1)
1586 {
1587 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 13);
1588 pCoexDm->psTdmaDuAdjType = 13;
1589 }
1590 else if(maxInterval == 2)
1591 {
1592 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
1593 pCoexDm->psTdmaDuAdjType = 14;
1594 }
1595 else if(maxInterval == 3)
1596 {
1597 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
1598 pCoexDm->psTdmaDuAdjType = 15;
1599 }
1600 else
1601 {
1602 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
1603 pCoexDm->psTdmaDuAdjType = 15;
1604 }
1605 }
1606 else
1607 {
1608 if(maxInterval == 1)
1609 {
1610 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
1611 pCoexDm->psTdmaDuAdjType = 9;
1612 }
1613 else if(maxInterval == 2)
1614 {
1615 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
1616 pCoexDm->psTdmaDuAdjType = 10;
1617 }
1618 else if(maxInterval == 3)
1619 {
1620 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
1621 pCoexDm->psTdmaDuAdjType = 11;
1622 }
1623 else
1624 {
1625 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
1626 pCoexDm->psTdmaDuAdjType = 11;
1627 }
1628 }
1629 }
1630 else
1631 {
1632 if(bTxPause)
1633 {
1634 if(maxInterval == 1)
1635 {
1636 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 5);
1637 pCoexDm->psTdmaDuAdjType = 5;
1638 }
1639 else if(maxInterval == 2)
1640 {
1641 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
1642 pCoexDm->psTdmaDuAdjType = 6;
1643 }
1644 else if(maxInterval == 3)
1645 {
1646 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
1647 pCoexDm->psTdmaDuAdjType = 7;
1648 }
1649 else
1650 {
1651 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
1652 pCoexDm->psTdmaDuAdjType = 7;
1653 }
1654 }
1655 else
1656 {
1657 if(maxInterval == 1)
1658 {
1659 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 1);
1660 pCoexDm->psTdmaDuAdjType = 1;
1661 }
1662 else if(maxInterval == 2)
1663 {
1664 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
1665 pCoexDm->psTdmaDuAdjType = 2;
1666 }
1667 else if(maxInterval == 3)
1668 {
1669 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
1670 pCoexDm->psTdmaDuAdjType = 3;
1671 }
1672 else
1673 {
1674 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
1675 pCoexDm->psTdmaDuAdjType = 3;
1676 }
1677 }
1678 }
1679 }
1680 //============
1681 up = 0;
1682 dn = 0;
1683 m = 1;
1684 n= 3;
1685 result = 0;
1686 WaitCount = 0;
1687 }
1688 else
1689 {
1690 //accquire the BT TRx retry count from BT_Info byte2
1691 retryCount = pCoexSta->btRetryCnt;
1692 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], retryCount = %d\n", retryCount));
1693 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n",
1694 up, dn, m, n, WaitCount));
1695 result = 0;
1696 WaitCount++;
1697
1698 if(retryCount == 0) // no retry in the last 2-second duration
1699 {
1700 up++;
1701 dn--;
1702
1703 if (dn <= 0)
1704 dn = 0;
1705
1706 if(up >= n) // if ³sÄò n ­Ó2¬í retry count¬°0, «h½Õ¼eWiFi duration
1707 {
1708 WaitCount = 0;
1709 n = 3;
1710 up = 0;
1711 dn = 0;
1712 result = 1;
1713 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], Increase wifi duration!!\n"));
1714 }
1715 }
1716 else if (retryCount <= 3) // <=3 retry in the last 2-second duration
1717 {
1718 up--;
1719 dn++;
1720
1721 if (up <= 0)
1722 up = 0;
1723
1724 if (dn == 2) // if ³sÄò 2 ­Ó2¬í retry count< 3, «h½Õ¯¶WiFi duration
1725 {
1726 if (WaitCount <= 2)
1727 m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^
1728 else
1729 m = 1;
1730
1731 if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
1732 m = 20;
1733
1734 n = 3*m;
1735 up = 0;
1736 dn = 0;
1737 WaitCount = 0;
1738 result = -1;
1739 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n"));
1740 }
1741 }
1742 else //retry count > 3, ¥u­n1¦¸ retry count > 3, «h½Õ¯¶WiFi duration
1743 {
1744 if (WaitCount == 1)
1745 m++; // ÁקK¤@ª½¦b¨â­Ólevel¤¤¨Ó¦^
1746 else
1747 m = 1;
1748
1749 if ( m >= 20) //m ³Ì¤j­È = 20 ' ³Ì¤j120¬í recheck¬O§_½Õ¾ã WiFi duration.
1750 m = 20;
1751
1752 n = 3*m;
1753 up = 0;
1754 dn = 0;
1755 WaitCount = 0;
1756 result = -1;
1757 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n"));
1758 }
1759
1760 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], max Interval = %d\n", maxInterval));
1761 if(maxInterval == 1)
1762 {
1763 if(bTxPause)
1764 {
1765 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], TxPause = 1\n"));
1766
1767 if(pCoexDm->curPsTdma == 1)
1768 {
1769 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 5);
1770 pCoexDm->psTdmaDuAdjType = 5;
1771 }
1772 else if(pCoexDm->curPsTdma == 2)
1773 {
1774 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
1775 pCoexDm->psTdmaDuAdjType = 6;
1776 }
1777 else if(pCoexDm->curPsTdma == 3)
1778 {
1779 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
1780 pCoexDm->psTdmaDuAdjType = 7;
1781 }
1782 else if(pCoexDm->curPsTdma == 4)
1783 {
1784 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 8);
1785 pCoexDm->psTdmaDuAdjType = 8;
1786 }
1787 if(pCoexDm->curPsTdma == 9)
1788 {
1789 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 13);
1790 pCoexDm->psTdmaDuAdjType = 13;
1791 }
1792 else if(pCoexDm->curPsTdma == 10)
1793 {
1794 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
1795 pCoexDm->psTdmaDuAdjType = 14;
1796 }
1797 else if(pCoexDm->curPsTdma == 11)
1798 {
1799 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
1800 pCoexDm->psTdmaDuAdjType = 15;
1801 }
1802 else if(pCoexDm->curPsTdma == 12)
1803 {
1804 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 16);
1805 pCoexDm->psTdmaDuAdjType = 16;
1806 }
1807
1808 if(result == -1)
1809 {
1810 if(pCoexDm->curPsTdma == 5)
1811 {
1812 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
1813 pCoexDm->psTdmaDuAdjType = 6;
1814 }
1815 else if(pCoexDm->curPsTdma == 6)
1816 {
1817 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
1818 pCoexDm->psTdmaDuAdjType = 7;
1819 }
1820 else if(pCoexDm->curPsTdma == 7)
1821 {
1822 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 8);
1823 pCoexDm->psTdmaDuAdjType = 8;
1824 }
1825 else if(pCoexDm->curPsTdma == 13)
1826 {
1827 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
1828 pCoexDm->psTdmaDuAdjType = 14;
1829 }
1830 else if(pCoexDm->curPsTdma == 14)
1831 {
1832 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
1833 pCoexDm->psTdmaDuAdjType = 15;
1834 }
1835 else if(pCoexDm->curPsTdma == 15)
1836 {
1837 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 16);
1838 pCoexDm->psTdmaDuAdjType = 16;
1839 }
1840 }
1841 else if (result == 1)
1842 {
1843 if(pCoexDm->curPsTdma == 8)
1844 {
1845 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
1846 pCoexDm->psTdmaDuAdjType = 7;
1847 }
1848 else if(pCoexDm->curPsTdma == 7)
1849 {
1850 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
1851 pCoexDm->psTdmaDuAdjType = 6;
1852 }
1853 else if(pCoexDm->curPsTdma == 6)
1854 {
1855 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 5);
1856 pCoexDm->psTdmaDuAdjType = 5;
1857 }
1858 else if(pCoexDm->curPsTdma == 16)
1859 {
1860 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
1861 pCoexDm->psTdmaDuAdjType = 15;
1862 }
1863 else if(pCoexDm->curPsTdma == 15)
1864 {
1865 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
1866 pCoexDm->psTdmaDuAdjType = 14;
1867 }
1868 else if(pCoexDm->curPsTdma == 14)
1869 {
1870 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 13);
1871 pCoexDm->psTdmaDuAdjType = 13;
1872 }
1873 }
1874 }
1875 else
1876 {
1877 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], TxPause = 0\n"));
1878 if(pCoexDm->curPsTdma == 5)
1879 {
1880 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 1);
1881 pCoexDm->psTdmaDuAdjType = 1;
1882 }
1883 else if(pCoexDm->curPsTdma == 6)
1884 {
1885 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
1886 pCoexDm->psTdmaDuAdjType = 2;
1887 }
1888 else if(pCoexDm->curPsTdma == 7)
1889 {
1890 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
1891 pCoexDm->psTdmaDuAdjType = 3;
1892 }
1893 else if(pCoexDm->curPsTdma == 8)
1894 {
1895 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 4);
1896 pCoexDm->psTdmaDuAdjType = 4;
1897 }
1898 if(pCoexDm->curPsTdma == 13)
1899 {
1900 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
1901 pCoexDm->psTdmaDuAdjType = 9;
1902 }
1903 else if(pCoexDm->curPsTdma == 14)
1904 {
1905 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
1906 pCoexDm->psTdmaDuAdjType = 10;
1907 }
1908 else if(pCoexDm->curPsTdma == 15)
1909 {
1910 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
1911 pCoexDm->psTdmaDuAdjType = 11;
1912 }
1913 else if(pCoexDm->curPsTdma == 16)
1914 {
1915 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 12);
1916 pCoexDm->psTdmaDuAdjType = 12;
1917 }
1918
1919 if(result == -1)
1920 {
1921 if(pCoexDm->curPsTdma == 1)
1922 {
1923 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
1924 pCoexDm->psTdmaDuAdjType = 2;
1925 }
1926 else if(pCoexDm->curPsTdma == 2)
1927 {
1928 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
1929 pCoexDm->psTdmaDuAdjType = 3;
1930 }
1931 else if(pCoexDm->curPsTdma == 3)
1932 {
1933 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 4);
1934 pCoexDm->psTdmaDuAdjType = 4;
1935 }
1936 else if(pCoexDm->curPsTdma == 9)
1937 {
1938 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
1939 pCoexDm->psTdmaDuAdjType = 10;
1940 }
1941 else if(pCoexDm->curPsTdma == 10)
1942 {
1943 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
1944 pCoexDm->psTdmaDuAdjType = 11;
1945 }
1946 else if(pCoexDm->curPsTdma == 11)
1947 {
1948 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 12);
1949 pCoexDm->psTdmaDuAdjType = 12;
1950 }
1951 }
1952 else if (result == 1)
1953 {
1954 if(pCoexDm->curPsTdma == 4)
1955 {
1956 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
1957 pCoexDm->psTdmaDuAdjType = 3;
1958 }
1959 else if(pCoexDm->curPsTdma == 3)
1960 {
1961 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
1962 pCoexDm->psTdmaDuAdjType = 2;
1963 }
1964 else if(pCoexDm->curPsTdma == 2)
1965 {
1966 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 1);
1967 pCoexDm->psTdmaDuAdjType = 1;
1968 }
1969 else if(pCoexDm->curPsTdma == 12)
1970 {
1971 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
1972 pCoexDm->psTdmaDuAdjType = 11;
1973 }
1974 else if(pCoexDm->curPsTdma == 11)
1975 {
1976 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
1977 pCoexDm->psTdmaDuAdjType = 10;
1978 }
1979 else if(pCoexDm->curPsTdma == 10)
1980 {
1981 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
1982 pCoexDm->psTdmaDuAdjType = 9;
1983 }
1984 }
1985 }
1986 }
1987 else if(maxInterval == 2)
1988 {
1989 if(bTxPause)
1990 {
1991 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], TxPause = 1\n"));
1992 if(pCoexDm->curPsTdma == 1)
1993 {
1994 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
1995 pCoexDm->psTdmaDuAdjType = 6;
1996 }
1997 else if(pCoexDm->curPsTdma == 2)
1998 {
1999 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
2000 pCoexDm->psTdmaDuAdjType = 6;
2001 }
2002 else if(pCoexDm->curPsTdma == 3)
2003 {
2004 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2005 pCoexDm->psTdmaDuAdjType = 7;
2006 }
2007 else if(pCoexDm->curPsTdma == 4)
2008 {
2009 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 8);
2010 pCoexDm->psTdmaDuAdjType = 8;
2011 }
2012 if(pCoexDm->curPsTdma == 9)
2013 {
2014 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
2015 pCoexDm->psTdmaDuAdjType = 14;
2016 }
2017 else if(pCoexDm->curPsTdma == 10)
2018 {
2019 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
2020 pCoexDm->psTdmaDuAdjType = 14;
2021 }
2022 else if(pCoexDm->curPsTdma == 11)
2023 {
2024 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2025 pCoexDm->psTdmaDuAdjType = 15;
2026 }
2027 else if(pCoexDm->curPsTdma == 12)
2028 {
2029 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 16);
2030 pCoexDm->psTdmaDuAdjType = 16;
2031 }
2032 if(result == -1)
2033 {
2034 if(pCoexDm->curPsTdma == 5)
2035 {
2036 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
2037 pCoexDm->psTdmaDuAdjType = 6;
2038 }
2039 else if(pCoexDm->curPsTdma == 6)
2040 {
2041 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2042 pCoexDm->psTdmaDuAdjType = 7;
2043 }
2044 else if(pCoexDm->curPsTdma == 7)
2045 {
2046 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 8);
2047 pCoexDm->psTdmaDuAdjType = 8;
2048 }
2049 else if(pCoexDm->curPsTdma == 13)
2050 {
2051 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
2052 pCoexDm->psTdmaDuAdjType = 14;
2053 }
2054 else if(pCoexDm->curPsTdma == 14)
2055 {
2056 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2057 pCoexDm->psTdmaDuAdjType = 15;
2058 }
2059 else if(pCoexDm->curPsTdma == 15)
2060 {
2061 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 16);
2062 pCoexDm->psTdmaDuAdjType = 16;
2063 }
2064 }
2065 else if (result == 1)
2066 {
2067 if(pCoexDm->curPsTdma == 8)
2068 {
2069 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2070 pCoexDm->psTdmaDuAdjType = 7;
2071 }
2072 else if(pCoexDm->curPsTdma == 7)
2073 {
2074 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
2075 pCoexDm->psTdmaDuAdjType = 6;
2076 }
2077 else if(pCoexDm->curPsTdma == 6)
2078 {
2079 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
2080 pCoexDm->psTdmaDuAdjType = 6;
2081 }
2082 else if(pCoexDm->curPsTdma == 16)
2083 {
2084 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2085 pCoexDm->psTdmaDuAdjType = 15;
2086 }
2087 else if(pCoexDm->curPsTdma == 15)
2088 {
2089 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
2090 pCoexDm->psTdmaDuAdjType = 14;
2091 }
2092 else if(pCoexDm->curPsTdma == 14)
2093 {
2094 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
2095 pCoexDm->psTdmaDuAdjType = 14;
2096 }
2097 }
2098 }
2099 else
2100 {
2101 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], TxPause = 0\n"));
2102 if(pCoexDm->curPsTdma == 5)
2103 {
2104 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
2105 pCoexDm->psTdmaDuAdjType = 2;
2106 }
2107 else if(pCoexDm->curPsTdma == 6)
2108 {
2109 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
2110 pCoexDm->psTdmaDuAdjType = 2;
2111 }
2112 else if(pCoexDm->curPsTdma == 7)
2113 {
2114 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2115 pCoexDm->psTdmaDuAdjType = 3;
2116 }
2117 else if(pCoexDm->curPsTdma == 8)
2118 {
2119 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 4);
2120 pCoexDm->psTdmaDuAdjType = 4;
2121 }
2122 if(pCoexDm->curPsTdma == 13)
2123 {
2124 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
2125 pCoexDm->psTdmaDuAdjType = 10;
2126 }
2127 else if(pCoexDm->curPsTdma == 14)
2128 {
2129 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
2130 pCoexDm->psTdmaDuAdjType = 10;
2131 }
2132 else if(pCoexDm->curPsTdma == 15)
2133 {
2134 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2135 pCoexDm->psTdmaDuAdjType = 11;
2136 }
2137 else if(pCoexDm->curPsTdma == 16)
2138 {
2139 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 12);
2140 pCoexDm->psTdmaDuAdjType = 12;
2141 }
2142 if(result == -1)
2143 {
2144 if(pCoexDm->curPsTdma == 1)
2145 {
2146 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
2147 pCoexDm->psTdmaDuAdjType = 2;
2148 }
2149 else if(pCoexDm->curPsTdma == 2)
2150 {
2151 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2152 pCoexDm->psTdmaDuAdjType = 3;
2153 }
2154 else if(pCoexDm->curPsTdma == 3)
2155 {
2156 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 4);
2157 pCoexDm->psTdmaDuAdjType = 4;
2158 }
2159 else if(pCoexDm->curPsTdma == 9)
2160 {
2161 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
2162 pCoexDm->psTdmaDuAdjType = 10;
2163 }
2164 else if(pCoexDm->curPsTdma == 10)
2165 {
2166 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2167 pCoexDm->psTdmaDuAdjType = 11;
2168 }
2169 else if(pCoexDm->curPsTdma == 11)
2170 {
2171 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 12);
2172 pCoexDm->psTdmaDuAdjType = 12;
2173 }
2174 }
2175 else if (result == 1)
2176 {
2177 if(pCoexDm->curPsTdma == 4)
2178 {
2179 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2180 pCoexDm->psTdmaDuAdjType = 3;
2181 }
2182 else if(pCoexDm->curPsTdma == 3)
2183 {
2184 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
2185 pCoexDm->psTdmaDuAdjType = 2;
2186 }
2187 else if(pCoexDm->curPsTdma == 2)
2188 {
2189 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
2190 pCoexDm->psTdmaDuAdjType = 2;
2191 }
2192 else if(pCoexDm->curPsTdma == 12)
2193 {
2194 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2195 pCoexDm->psTdmaDuAdjType = 11;
2196 }
2197 else if(pCoexDm->curPsTdma == 11)
2198 {
2199 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
2200 pCoexDm->psTdmaDuAdjType = 10;
2201 }
2202 else if(pCoexDm->curPsTdma == 10)
2203 {
2204 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
2205 pCoexDm->psTdmaDuAdjType = 10;
2206 }
2207 }
2208 }
2209 }
2210 else if(maxInterval == 3)
2211 {
2212 if(bTxPause)
2213 {
2214 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], TxPause = 1\n"));
2215 if(pCoexDm->curPsTdma == 1)
2216 {
2217 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2218 pCoexDm->psTdmaDuAdjType = 7;
2219 }
2220 else if(pCoexDm->curPsTdma == 2)
2221 {
2222 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2223 pCoexDm->psTdmaDuAdjType = 7;
2224 }
2225 else if(pCoexDm->curPsTdma == 3)
2226 {
2227 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2228 pCoexDm->psTdmaDuAdjType = 7;
2229 }
2230 else if(pCoexDm->curPsTdma == 4)
2231 {
2232 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 8);
2233 pCoexDm->psTdmaDuAdjType = 8;
2234 }
2235 if(pCoexDm->curPsTdma == 9)
2236 {
2237 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2238 pCoexDm->psTdmaDuAdjType = 15;
2239 }
2240 else if(pCoexDm->curPsTdma == 10)
2241 {
2242 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2243 pCoexDm->psTdmaDuAdjType = 15;
2244 }
2245 else if(pCoexDm->curPsTdma == 11)
2246 {
2247 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2248 pCoexDm->psTdmaDuAdjType = 15;
2249 }
2250 else if(pCoexDm->curPsTdma == 12)
2251 {
2252 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 16);
2253 pCoexDm->psTdmaDuAdjType = 16;
2254 }
2255 if(result == -1)
2256 {
2257 if(pCoexDm->curPsTdma == 5)
2258 {
2259 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2260 pCoexDm->psTdmaDuAdjType = 7;
2261 }
2262 else if(pCoexDm->curPsTdma == 6)
2263 {
2264 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2265 pCoexDm->psTdmaDuAdjType = 7;
2266 }
2267 else if(pCoexDm->curPsTdma == 7)
2268 {
2269 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 8);
2270 pCoexDm->psTdmaDuAdjType = 8;
2271 }
2272 else if(pCoexDm->curPsTdma == 13)
2273 {
2274 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2275 pCoexDm->psTdmaDuAdjType = 15;
2276 }
2277 else if(pCoexDm->curPsTdma == 14)
2278 {
2279 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2280 pCoexDm->psTdmaDuAdjType = 15;
2281 }
2282 else if(pCoexDm->curPsTdma == 15)
2283 {
2284 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 16);
2285 pCoexDm->psTdmaDuAdjType = 16;
2286 }
2287 }
2288 else if (result == 1)
2289 {
2290 if(pCoexDm->curPsTdma == 8)
2291 {
2292 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2293 pCoexDm->psTdmaDuAdjType = 7;
2294 }
2295 else if(pCoexDm->curPsTdma == 7)
2296 {
2297 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2298 pCoexDm->psTdmaDuAdjType = 7;
2299 }
2300 else if(pCoexDm->curPsTdma == 6)
2301 {
2302 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 7);
2303 pCoexDm->psTdmaDuAdjType = 7;
2304 }
2305 else if(pCoexDm->curPsTdma == 16)
2306 {
2307 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2308 pCoexDm->psTdmaDuAdjType = 15;
2309 }
2310 else if(pCoexDm->curPsTdma == 15)
2311 {
2312 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2313 pCoexDm->psTdmaDuAdjType = 15;
2314 }
2315 else if(pCoexDm->curPsTdma == 14)
2316 {
2317 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2318 pCoexDm->psTdmaDuAdjType = 15;
2319 }
2320 }
2321 }
2322 else
2323 {
2324 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], TxPause = 0\n"));
2325 if(pCoexDm->curPsTdma == 5)
2326 {
2327 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2328 pCoexDm->psTdmaDuAdjType = 3;
2329 }
2330 else if(pCoexDm->curPsTdma == 6)
2331 {
2332 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2333 pCoexDm->psTdmaDuAdjType = 3;
2334 }
2335 else if(pCoexDm->curPsTdma == 7)
2336 {
2337 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2338 pCoexDm->psTdmaDuAdjType = 3;
2339 }
2340 else if(pCoexDm->curPsTdma == 8)
2341 {
2342 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 4);
2343 pCoexDm->psTdmaDuAdjType = 4;
2344 }
2345 if(pCoexDm->curPsTdma == 13)
2346 {
2347 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2348 pCoexDm->psTdmaDuAdjType = 11;
2349 }
2350 else if(pCoexDm->curPsTdma == 14)
2351 {
2352 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2353 pCoexDm->psTdmaDuAdjType = 11;
2354 }
2355 else if(pCoexDm->curPsTdma == 15)
2356 {
2357 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2358 pCoexDm->psTdmaDuAdjType = 11;
2359 }
2360 else if(pCoexDm->curPsTdma == 16)
2361 {
2362 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 12);
2363 pCoexDm->psTdmaDuAdjType = 12;
2364 }
2365 if(result == -1)
2366 {
2367 if(pCoexDm->curPsTdma == 1)
2368 {
2369 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2370 pCoexDm->psTdmaDuAdjType = 3;
2371 }
2372 else if(pCoexDm->curPsTdma == 2)
2373 {
2374 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2375 pCoexDm->psTdmaDuAdjType = 3;
2376 }
2377 else if(pCoexDm->curPsTdma == 3)
2378 {
2379 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 4);
2380 pCoexDm->psTdmaDuAdjType = 4;
2381 }
2382 else if(pCoexDm->curPsTdma == 9)
2383 {
2384 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2385 pCoexDm->psTdmaDuAdjType = 11;
2386 }
2387 else if(pCoexDm->curPsTdma == 10)
2388 {
2389 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2390 pCoexDm->psTdmaDuAdjType = 11;
2391 }
2392 else if(pCoexDm->curPsTdma == 11)
2393 {
2394 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 12);
2395 pCoexDm->psTdmaDuAdjType = 12;
2396 }
2397 }
2398 else if (result == 1)
2399 {
2400 if(pCoexDm->curPsTdma == 4)
2401 {
2402 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2403 pCoexDm->psTdmaDuAdjType = 3;
2404 }
2405 else if(pCoexDm->curPsTdma == 3)
2406 {
2407 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2408 pCoexDm->psTdmaDuAdjType = 3;
2409 }
2410 else if(pCoexDm->curPsTdma == 2)
2411 {
2412 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3);
2413 pCoexDm->psTdmaDuAdjType = 3;
2414 }
2415 else if(pCoexDm->curPsTdma == 12)
2416 {
2417 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2418 pCoexDm->psTdmaDuAdjType = 11;
2419 }
2420 else if(pCoexDm->curPsTdma == 11)
2421 {
2422 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2423 pCoexDm->psTdmaDuAdjType = 11;
2424 }
2425 else if(pCoexDm->curPsTdma == 10)
2426 {
2427 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2428 pCoexDm->psTdmaDuAdjType = 11;
2429 }
2430 }
2431 }
2432 }
2433 }
2434
2435 // if current PsTdma not match with the recorded one (when scan, dhcp...),
2436 // then we have to adjust it back to the previous record one.
2437 if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType)
2438 {
2439 BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE;
2440 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n",
2441 pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType));
2442
2443 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
2444 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
2445 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
2446
2447 if( !bScan && !bLink && !bRoam)
2448 {
2449 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, pCoexDm->psTdmaDuAdjType);
2450 }
2451 else
2452 {
2453 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n"));
2454 }
2455 }
2456}
2457
2458// SCO only or SCO+PAN(HS)
2459VOID
2460halbtc8723a2ant_ActionSco(
2461 IN PBTC_COEXIST pBtCoexist
2462 )
2463{
2464 u1Byte wifiRssiState, wifiRssiState1;
2465 u4Byte wifiBw;
2466
2467 if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
2468 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
2469 else
2470 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
2471 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
2472
2473 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2474 if(BTC_WIFI_BW_HT40 == wifiBw)
2475 {
2476 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
2477 // fw mechanism
2478 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2479 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2480 {
2481 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2482 }
2483 else
2484 {
2485 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2486 }
2487
2488 // sw mechanism
2489 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2490 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2491 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2492 }
2493 else
2494 {
2495 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
2496 wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
2497
2498 // fw mechanism
2499 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2500 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2501 {
2502 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 11);
2503 }
2504 else
2505 {
2506 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 15);
2507 }
2508
2509 // sw mechanism
2510 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
2511 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
2512 {
2513 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, true);
2514 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2515 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2516 }
2517 else
2518 {
2519 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2520 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
2521 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2522 }
2523 }
2524}
2525
2526
2527VOID
2528halbtc8723a2ant_ActionHid(
2529 IN PBTC_COEXIST pBtCoexist
2530 )
2531{
2532 u1Byte wifiRssiState, wifiRssiState1;
2533 u4Byte wifiBw;
2534
2535 if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
2536 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
2537 else
2538 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
2539 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
2540
2541 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2542 if(BTC_WIFI_BW_HT40 == wifiBw)
2543 {
2544 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
2545 // fw mechanism
2546 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2547 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2548 {
2549 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
2550 }
2551 else
2552 {
2553 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 13);
2554 }
2555
2556 // sw mechanism
2557 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2558 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
2559 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2560 }
2561 else
2562 {
2563 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
2564 wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
2565
2566 // fw mechanism
2567 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2568 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2569 {
2570 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9);
2571 }
2572 else
2573 {
2574 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 13);
2575 }
2576
2577 // sw mechanism
2578 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
2579 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
2580 {
2581 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, true);
2582 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2583 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2584 }
2585 else
2586 {
2587 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2588 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
2589 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2590 }
2591 }
2592}
2593
2594//A2DP only / PAN(EDR) only/ A2DP+PAN(HS)
2595VOID
2596halbtc8723a2ant_ActionA2dp(
2597 IN PBTC_COEXIST pBtCoexist
2598 )
2599{
2600 u1Byte wifiRssiState, wifiRssiState1, btInfoExt;
2601 u4Byte wifiBw;
2602
2603 btInfoExt = pCoexSta->btInfoExt;
2604
2605 if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
2606 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
2607 else
2608 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
2609 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
2610
2611 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2612 if(BTC_WIFI_BW_HT40 == wifiBw)
2613 {
2614 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
2615
2616 // fw mechanism
2617 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2618 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2619 {
2620 if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr
2621 {
2622 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3);
2623 }
2624 else
2625 {
2626 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1);
2627 }
2628 }
2629 else
2630 {
2631 if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr
2632 {
2633 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, true, 3);
2634 }
2635 else
2636 {
2637 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, true, 1);
2638 }
2639 }
2640
2641 // sw mechanism
2642 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2643 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2644 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2645 }
2646 else
2647 {
2648 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
2649 wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
2650
2651 // fw mechanism
2652 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2653 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2654 {
2655 if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr
2656 {
2657 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3);
2658 }
2659 else
2660 {
2661 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1);
2662 }
2663 }
2664 else
2665 {
2666 if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr
2667 {
2668 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, true, 3);
2669 }
2670 else
2671 {
2672 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, true, 1);
2673 }
2674 }
2675
2676 // sw mechanism
2677 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
2678 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
2679 {
2680 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, true);
2681 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2682 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2683 }
2684 else
2685 {
2686 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2687 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
2688 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2689 }
2690 }
2691}
2692
2693VOID
2694halbtc8723a2ant_ActionPanEdr(
2695 IN PBTC_COEXIST pBtCoexist
2696 )
2697{
2698 u1Byte wifiRssiState, wifiRssiState1, btInfoExt;
2699 u4Byte wifiBw;
2700
2701 btInfoExt = pCoexSta->btInfoExt;
2702
2703 if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
2704 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
2705 else
2706 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
2707 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
2708
2709 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2710 if(BTC_WIFI_BW_HT40 == wifiBw)
2711 {
2712 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
2713
2714 // fw mechanism
2715 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2716 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2717 {
2718 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
2719 }
2720 else
2721 {
2722 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
2723 }
2724
2725 // sw mechanism
2726 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2727 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2728 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2729 }
2730 else
2731 {
2732 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
2733 wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
2734
2735 // fw mechanism
2736 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2737 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2738 {
2739 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
2740 }
2741 else
2742 {
2743 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
2744 }
2745
2746 // sw mechanism
2747 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
2748 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
2749 {
2750 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, true);
2751 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2752 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2753 }
2754 else
2755 {
2756 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2757 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
2758 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2759 }
2760 }
2761}
2762
2763
2764//PAN(HS) only
2765VOID
2766halbtc8723a2ant_ActionPanHs(
2767 IN PBTC_COEXIST pBtCoexist
2768 )
2769{
2770 u1Byte wifiRssiState;
2771 u4Byte wifiBw;
2772
2773 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
2774
2775 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2776 if(BTC_WIFI_BW_HT40 == wifiBw)
2777 {
2778 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
2779
2780 // fw mechanism
2781 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2782 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2783 {
2784 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
2785 }
2786 else
2787 {
2788 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
2789 }
2790 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2791
2792 // sw mechanism
2793 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2794 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2795 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2796 }
2797 else
2798 {
2799 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
2800
2801 // fw mechanism
2802 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2803 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2804 {
2805 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
2806 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2807 }
2808 else
2809 {
2810 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
2811 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0);
2812 }
2813
2814 // sw mechanism
2815 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2816 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2817 {
2818 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, true);
2819 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2820 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2821 }
2822 else
2823 {
2824 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2825 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
2826 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2827 }
2828 }
2829}
2830
2831//PAN(EDR)+A2DP
2832VOID
2833halbtc8723a2ant_ActionPanEdrA2dp(
2834 IN PBTC_COEXIST pBtCoexist
2835 )
2836{
2837 u1Byte wifiRssiState, wifiRssiState1, btInfoExt;
2838 u4Byte wifiBw;
2839
2840 btInfoExt = pCoexSta->btInfoExt;
2841
2842 if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
2843 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
2844 else
2845 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
2846 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
2847
2848 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2849 if(BTC_WIFI_BW_HT40 == wifiBw)
2850 {
2851 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
2852
2853 // fw mechanism
2854 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2855 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2856 {
2857 if(btInfoExt&BIT0) //a2dp basic rate
2858 {
2859 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 4);
2860 }
2861 else //a2dp edr rate
2862 {
2863 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
2864 }
2865 }
2866 else
2867 {
2868 if(btInfoExt&BIT0) //a2dp basic rate
2869 {
2870 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 8);
2871 }
2872 else //a2dp edr rate
2873 {
2874 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
2875 }
2876 }
2877
2878 // sw mechanism
2879 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2880 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2881 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2882 }
2883 else
2884 {
2885 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
2886 wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0);
2887
2888 // fw mechanism
2889 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2890 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2891 {
2892 if(btInfoExt&BIT0) //a2dp basic rate
2893 {
2894 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 4);
2895 }
2896 else //a2dp edr rate
2897 {
2898 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 2);
2899 }
2900 }
2901 else
2902 {
2903 if(btInfoExt&BIT0) //a2dp basic rate
2904 {
2905 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 8);
2906 }
2907 else //a2dp edr rate
2908 {
2909 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 6);
2910 }
2911 }
2912
2913 // sw mechanism
2914 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
2915 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
2916 {
2917 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, true);
2918 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2919 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2920 }
2921 else
2922 {
2923 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2924 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
2925 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2926 }
2927 }
2928}
2929
2930VOID
2931halbtc8723a2ant_ActionPanEdrHid(
2932 IN PBTC_COEXIST pBtCoexist
2933 )
2934{
2935 u1Byte wifiRssiState, wifiRssiState1;
2936 u4Byte wifiBw;
2937
2938 if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
2939 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
2940 else
2941 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
2942 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
2943
2944 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
2945 if(BTC_WIFI_BW_HT40 == wifiBw)
2946 {
2947 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
2948
2949 // fw mechanism
2950 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2951 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2952 {
2953 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
2954 }
2955 else
2956 {
2957 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
2958 }
2959
2960 // sw mechanism
2961 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2962 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2963 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2964 }
2965 else
2966 {
2967 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
2968 wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
2969
2970 // fw mechanism
2971 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2972 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2973 {
2974 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
2975 }
2976 else
2977 {
2978 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
2979 }
2980
2981 // sw mechanism
2982 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
2983 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
2984 {
2985 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, true);
2986 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
2987 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2988 }
2989 else
2990 {
2991 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
2992 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
2993 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
2994 }
2995 }
2996}
2997
2998// HID+A2DP+PAN(EDR)
2999VOID
3000halbtc8723a2ant_ActionHidA2dpPanEdr(
3001 IN PBTC_COEXIST pBtCoexist
3002 )
3003{
3004 u1Byte wifiRssiState, wifiRssiState1, btInfoExt;
3005 u4Byte wifiBw;
3006
3007 btInfoExt = pCoexSta->btInfoExt;
3008
3009 if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
3010 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
3011 else
3012 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
3013 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
3014
3015 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
3016 if(BTC_WIFI_BW_HT40 == wifiBw)
3017 {
3018 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
3019
3020 // fw mechanism
3021 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
3022 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
3023 {
3024 if(btInfoExt&BIT0) //a2dp basic rate
3025 {
3026 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 12);
3027 }
3028 else //a2dp edr rate
3029 {
3030 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
3031 }
3032 }
3033 else
3034 {
3035 if(btInfoExt&BIT0) //a2dp basic rate
3036 {
3037 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 16);
3038 }
3039 else //a2dp edr rate
3040 {
3041 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
3042 }
3043 }
3044
3045 // sw mechanism
3046 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
3047 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
3048 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
3049 }
3050 else
3051 {
3052 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
3053 wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
3054
3055 // fw mechanism
3056 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
3057 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
3058 {
3059 if(btInfoExt&BIT0) //a2dp basic rate
3060 {
3061 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 12);
3062 }
3063 else //a2dp edr rate
3064 {
3065 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 10);
3066 }
3067 }
3068 else
3069 {
3070 if(btInfoExt&BIT0) //a2dp basic rate
3071 {
3072 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 16);
3073 }
3074 else //a2dp edr rate
3075 {
3076 halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 14);
3077 }
3078 }
3079
3080 // sw mechanism
3081 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
3082 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
3083 {
3084 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, true);
3085 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
3086 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
3087 }
3088 else
3089 {
3090 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
3091 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
3092 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
3093 }
3094 }
3095}
3096
3097VOID
3098halbtc8723a2ant_ActionHidA2dp(
3099 IN PBTC_COEXIST pBtCoexist
3100 )
3101{
3102 u1Byte wifiRssiState, wifiRssiState1, btInfoExt;
3103 u4Byte wifiBw;
3104
3105 btInfoExt = pCoexSta->btInfoExt;
3106
3107 if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist))
3108 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, true);
3109 else
3110 halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE);
3111 halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3);
3112
3113 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
3114 if(BTC_WIFI_BW_HT40 == wifiBw)
3115 {
3116 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0);
3117
3118 // fw mechanism
3119 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
3120 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
3121 {
3122 if(btInfoExt&BIT0) //a2dp basic rate
3123 {
3124 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, true, FALSE, 3);
3125 }
3126 else //a2dp edr rate
3127 {
3128 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, true, FALSE, 1);
3129 }
3130 }
3131 else
3132 {
3133 if(btInfoExt&BIT0) //a2dp basic rate
3134 {
3135 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, true, true, 3);
3136 }
3137 else //a2dp edr rate
3138 {
3139 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, true, true, 1);
3140 }
3141 }
3142
3143 // sw mechanism
3144 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
3145 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
3146 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
3147 }
3148 else
3149 {
3150 wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0);
3151 wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0);
3152
3153 // fw mechanism
3154 if( (wifiRssiState == BTC_RSSI_STATE_HIGH) ||
3155 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) )
3156 {
3157 if(btInfoExt&BIT0) //a2dp basic rate
3158 {
3159 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, true, FALSE, 3);
3160 }
3161 else //a2dp edr rate
3162 {
3163 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, true, FALSE, 1);
3164 }
3165 }
3166 else
3167 {
3168 if(btInfoExt&BIT0) //a2dp basic rate
3169 {
3170 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, true, true, 3);
3171 }
3172 else //a2dp edr rate
3173 {
3174 halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, true, true, 1);
3175 }
3176 }
3177
3178 // sw mechanism
3179 if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) ||
3180 (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) )
3181 {
3182 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, true);
3183 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, true);
3184 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
3185 }
3186 else
3187 {
3188 halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE);
3189 halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE);
3190 halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0);
3191 }
3192 }
3193}
3194
3195VOID
3196halbtc8723a2ant_RunCoexistMechanism(
3197 IN PBTC_COEXIST pBtCoexist
3198 )
3199{
3200 PBTC_STACK_INFO pStackInfo=&pBtCoexist->stack_info;
3201 u1Byte btInfoOriginal=0, btRetryCnt=0;
3202 u1Byte algorithm=0;
3203
3204 if(pBtCoexist->manual_control)
3205 {
3206 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Manual control!!!\n"));
3207 return;
3208 }
3209
3210 if(pStackInfo->bProfileNotified)
3211 {
3212 if(pCoexSta->bHoldForStackOperation)
3213 {
3214 // if bt inquiry/page/pair, do not execute.
3215 return;
3216 }
3217
3218 algorithm = halbtc8723a2ant_ActionAlgorithm(pBtCoexist);
3219 if(pCoexSta->bHoldPeriodCnt && (BT_8723A_2ANT_COEX_ALGO_PANHS!=algorithm))
3220 {
3221 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex],Hold BT inquiry/page scan setting (cnt = %d)!!\n",
3222 pCoexSta->bHoldPeriodCnt));
3223 if(pCoexSta->bHoldPeriodCnt >= 6)
3224 {
3225 pCoexSta->bHoldPeriodCnt = 0;
3226 // next time the coexist parameters should be reset again.
3227 }
3228 else
3229 pCoexSta->bHoldPeriodCnt++;
3230 return;
3231 }
3232
3233 pCoexDm->curAlgorithm = algorithm;
3234 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Algorithm = %d \n", pCoexDm->curAlgorithm));
3235 if(halbtc8723a2ant_IsCommonAction(pBtCoexist))
3236 {
3237 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant common.\n"));
3238 pCoexDm->bResetTdmaAdjust = true;
3239 }
3240 else
3241 {
3242 if(pCoexDm->curAlgorithm != pCoexDm->preAlgorithm)
3243 {
3244 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], preAlgorithm=%d, curAlgorithm=%d\n",
3245 pCoexDm->preAlgorithm, pCoexDm->curAlgorithm));
3246 pCoexDm->bResetTdmaAdjust = true;
3247 }
3248 switch(pCoexDm->curAlgorithm)
3249 {
3250 case BT_8723A_2ANT_COEX_ALGO_SCO:
3251 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant, algorithm = SCO.\n"));
3252 halbtc8723a2ant_ActionSco(pBtCoexist);
3253 break;
3254 case BT_8723A_2ANT_COEX_ALGO_HID:
3255 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant, algorithm = HID.\n"));
3256 halbtc8723a2ant_ActionHid(pBtCoexist);
3257 break;
3258 case BT_8723A_2ANT_COEX_ALGO_A2DP:
3259 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant, algorithm = A2DP.\n"));
3260 halbtc8723a2ant_ActionA2dp(pBtCoexist);
3261 break;
3262 case BT_8723A_2ANT_COEX_ALGO_PANEDR:
3263 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"));
3264 halbtc8723a2ant_ActionPanEdr(pBtCoexist);
3265 break;
3266 case BT_8723A_2ANT_COEX_ALGO_PANHS:
3267 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant, algorithm = HS mode.\n"));
3268 halbtc8723a2ant_ActionPanHs(pBtCoexist);
3269 break;
3270 case BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP:
3271 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"));
3272 halbtc8723a2ant_ActionPanEdrA2dp(pBtCoexist);
3273 break;
3274 case BT_8723A_2ANT_COEX_ALGO_PANEDR_HID:
3275 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"));
3276 halbtc8723a2ant_ActionPanEdrHid(pBtCoexist);
3277 break;
3278 case BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
3279 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"));
3280 halbtc8723a2ant_ActionHidA2dpPanEdr(pBtCoexist);
3281 break;
3282 case BT_8723A_2ANT_COEX_ALGO_HID_A2DP:
3283 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"));
3284 halbtc8723a2ant_ActionHidA2dp(pBtCoexist);
3285 break;
3286 default:
3287 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"));
3288 halbtc8723a2ant_CoexAllOff(pBtCoexist);
3289 break;
3290 }
3291 pCoexDm->preAlgorithm = pCoexDm->curAlgorithm;
3292 }
3293 }
3294}
3295
3296//============================================================
3297// work around function start with wa_halbtc8723a2ant_
3298//============================================================
3299VOID
3300wa_halbtc8723a2ant_MonitorC2h(
3301 IN PBTC_COEXIST pBtCoexist
3302 )
3303{
3304 u1Byte tmp1b=0x0;
3305 u4Byte curC2hTotalCnt=0x0;
3306 static u4Byte preC2hTotalCnt=0x0, sameCntPollingTime=0x0;
3307
3308 curC2hTotalCnt+=pCoexSta->btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_BT_RSP];
3309
3310 if(curC2hTotalCnt == preC2hTotalCnt)
3311 {
3312 sameCntPollingTime++;
3313 }
3314 else
3315 {
3316 preC2hTotalCnt = curC2hTotalCnt;
3317 sameCntPollingTime = 0;
3318 }
3319
3320 if(sameCntPollingTime >= 2)
3321 {
3322 tmp1b = pBtCoexist->btc_read_1byte(pBtCoexist, 0x1af);
3323 if(tmp1b != 0x0)
3324 {
3325 pCoexSta->c2hHangDetectCnt++;
3326 pBtCoexist->btc_write_1byte(pBtCoexist, 0x1af, 0x0);
3327 }
3328 }
3329}
3330
3331//============================================================
3332// extern function start with EXhalbtc8723a2ant_
3333//============================================================
3334VOID
3335EXhalbtc8723a2ant_InitHwConfig(
3336 IN PBTC_COEXIST pBtCoexist
3337 )
3338{
3339 u4Byte u4Tmp=0;
3340 u1Byte u1Tmp=0;
3341
3342 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], 2Ant Init HW Config!!\n"));
3343
3344 // backup rf 0x1e value
3345 pCoexDm->btRf0x1eBackup =
3346 pBtCoexist->btc_get_rf_reg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff);
3347
3348 // Enable counter statistics
3349 pBtCoexist->btc_write_1byte(pBtCoexist, 0x76e, 0x4);
3350 pBtCoexist->btc_write_1byte(pBtCoexist, 0x778, 0x3);
3351 pBtCoexist->btc_write_1byte(pBtCoexist, 0x40, 0x20);
3352}
3353
3354VOID
3355EXhalbtc8723a2ant_InitCoexDm(
3356 IN PBTC_COEXIST pBtCoexist
3357 )
3358{
3359 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT, ("[BTCoex], Coex Mechanism Init!!\n"));
3360
3361 halbtc8723a2ant_InitCoexDm(pBtCoexist);
3362}
3363
3364VOID
3365EXhalbtc8723a2ant_DisplayCoexInfo(
3366 IN PBTC_COEXIST pBtCoexist
3367 )
3368{
3369 struct btc_board_info * pBoardInfo=&pBtCoexist->board_info;
3370 PBTC_STACK_INFO pStackInfo=&pBtCoexist->stack_info;
3371 pu1Byte cliBuf=pBtCoexist->cli_buf;
3372 u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0;
3373 u4Byte u4Tmp[4];
3374 BOOLEAN bRoam=FALSE, bScan=FALSE, bLink=FALSE, bWifiUnder5G=FALSE;
3375 BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE;
3376 s4Byte wifiRssi=0, btHsRssi=0;
3377 u4Byte wifiBw, wifiTrafficDir;
3378 u1Byte wifiDot11Chnl, wifiHsChnl;
3379
3380 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============");
3381 CL_PRINTF(cliBuf);
3382
3383 if(!pBoardInfo->bt_exist)
3384 {
3385 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n BT not exists !!!");
3386 CL_PRINTF(cliBuf);
3387 return;
3388 }
3389
3390 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \
3391 pBoardInfo->pg_ant_num, pBoardInfo->btdm_ant_num);
3392 CL_PRINTF(cliBuf);
3393
3394 if(pBtCoexist->manual_control)
3395 {
3396 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!");
3397 CL_PRINTF(cliBuf);
3398 }
3399
3400 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \
3401 ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion);
3402 CL_PRINTF(cliBuf);
3403
3404 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
3405 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiDot11Chnl);
3406 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifiHsChnl);
3407 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d(%d)", "Dot11 channel / HsChnl(HsMode)", \
3408 wifiDot11Chnl, wifiHsChnl, bBtHsOn);
3409 CL_PRINTF(cliBuf);
3410
3411 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "H2C Wifi inform bt chnl Info", \
3412 pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1],
3413 pCoexDm->wifiChnlInfo[2]);
3414 CL_PRINTF(cliBuf);
3415
3416 pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi);
3417 pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_HS_RSSI, &btHsRssi);
3418 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "Wifi rssi/ HS rssi", \
3419 wifiRssi, btHsRssi);
3420 CL_PRINTF(cliBuf);
3421
3422 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan);
3423 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink);
3424 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam);
3425 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Wifi bLink/ bRoam/ bScan", \
3426 bLink, bRoam, bScan);
3427 CL_PRINTF(cliBuf);
3428
3429 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G);
3430 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw);
3431 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy);
3432 pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir);
3433 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s ", "Wifi status", \
3434 (bWifiUnder5G? "5G":"2.4G"),
3435 ((BTC_WIFI_BW_LEGACY==wifiBw)? "Legacy": (((BTC_WIFI_BW_HT40==wifiBw)? "HT40":"HT20"))),
3436 ((!bWifiBusy)? "idle": ((BTC_WIFI_TRAFFIC_TX==wifiTrafficDir)? "uplink":"downlink")));
3437 CL_PRINTF(cliBuf);
3438
3439 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \
3440 ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus)? "idle":( (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy"))),
3441 pCoexSta->btRssi, pCoexSta->btRetryCnt);
3442 CL_PRINTF(cliBuf);
3443
3444 if(pStackInfo->bProfileNotified)
3445 {
3446 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \
3447 pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist);
3448 CL_PRINTF(cliBuf);
3449
3450 pBtCoexist->btc_disp_dbg_msg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO);
3451 }
3452
3453 btInfoExt = pCoexSta->btInfoExt;
3454 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \
3455 (btInfoExt&BIT0)? "Basic rate":"EDR rate");
3456 CL_PRINTF(cliBuf);
3457
3458 for(i=0; i<BT_INFO_SRC_8723A_2ANT_MAX; i++)
3459 {
3460 if(pCoexSta->btInfoC2hCnt[i])
3461 {
3462 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723a2Ant[i], \
3463 pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1],
3464 pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3],
3465 pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5],
3466 pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]);
3467 CL_PRINTF(cliBuf);
3468 }
3469 }
3470
3471 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "write 0x1af=0x0 num", \
3472 pCoexSta->c2hHangDetectCnt);
3473 CL_PRINTF(cliBuf);
3474
3475 // Sw mechanism
3476 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============");
3477 CL_PRINTF(cliBuf);
3478 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "SM1[ShRf/ LpRA/ LimDig]", \
3479 pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->limited_dig);
3480 CL_PRINTF(cliBuf);
3481 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \
3482 pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl);
3483 CL_PRINTF(cliBuf);
3484
3485 // Fw mechanism
3486 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============");
3487 CL_PRINTF(cliBuf);
3488
3489 if(!pBtCoexist->manual_control)
3490 {
3491 psTdmaCase = pCoexDm->curPsTdma;
3492 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \
3493 pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1],
3494 pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3],
3495 pCoexDm->psTdmaPara[4], psTdmaCase);
3496 CL_PRINTF(cliBuf);
3497
3498 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \
3499 pCoexDm->bCurDecBtPwr, pCoexDm->bCurIgnoreWlanAct);
3500 CL_PRINTF(cliBuf);
3501 }
3502
3503 // Hw setting
3504 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============");
3505 CL_PRINTF(cliBuf);
3506
3507 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \
3508 pCoexDm->btRf0x1eBackup);
3509 CL_PRINTF(cliBuf);
3510
3511 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x778);
3512 u1Tmp[1] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x783);
3513 u1Tmp[2] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x796);
3514 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/ 0x783/ 0x796", \
3515 u1Tmp[0], u1Tmp[1], u1Tmp[2]);
3516 CL_PRINTF(cliBuf);
3517
3518 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x880);
3519 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x880", \
3520 u4Tmp[0]);
3521 CL_PRINTF(cliBuf);
3522
3523 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x40);
3524 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \
3525 u1Tmp[0]);
3526 CL_PRINTF(cliBuf);
3527
3528 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x550);
3529 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x522);
3530 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \
3531 u4Tmp[0], u1Tmp[0]);
3532 CL_PRINTF(cliBuf);
3533
3534 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x484);
3535 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x484(rate adaptive)", \
3536 u4Tmp[0]);
3537 CL_PRINTF(cliBuf);
3538
3539 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xc50);
3540 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \
3541 u4Tmp[0]);
3542 CL_PRINTF(cliBuf);
3543
3544 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xda0);
3545 u4Tmp[1] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xda4);
3546 u4Tmp[2] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xda8);
3547 u4Tmp[3] = pBtCoexist->btc_read_4byte(pBtCoexist, 0xdac);
3548 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0xda0/0xda4/0xda8/0xdac(FA cnt)", \
3549 u4Tmp[0], u4Tmp[1], u4Tmp[2], u4Tmp[3]);
3550 CL_PRINTF(cliBuf);
3551
3552 u4Tmp[0] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x6c0);
3553 u4Tmp[1] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x6c4);
3554 u4Tmp[2] = pBtCoexist->btc_read_4byte(pBtCoexist, 0x6c8);
3555 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x6cc);
3556 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \
3557 u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]);
3558 CL_PRINTF(cliBuf);
3559
3560 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770 (hp rx[31:16]/tx[15:0])", \
3561 pCoexSta->highPriorityRx, pCoexSta->highPriorityTx);
3562 CL_PRINTF(cliBuf);
3563 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \
3564 pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx);
3565 CL_PRINTF(cliBuf);
3566
3567 // Tx mgnt queue hang or not, 0x41b should = 0xf, ex: 0xd ==>hang
3568 u1Tmp[0] = pBtCoexist->btc_read_1byte(pBtCoexist, 0x41b);
3569 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x41b (mgntQ hang chk == 0xf)", \
3570 u1Tmp[0]);
3571 CL_PRINTF(cliBuf);
3572
3573 pBtCoexist->btc_disp_dbg_msg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS);
3574}
3575
3576
3577VOID
3578EXhalbtc8723a2ant_IpsNotify(
3579 IN PBTC_COEXIST pBtCoexist,
3580 IN u1Byte type
3581 )
3582{
3583 if(BTC_IPS_ENTER == type)
3584 {
3585 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], IPS ENTER notify\n"));
3586 halbtc8723a2ant_CoexAllOff(pBtCoexist);
3587 }
3588 else if(BTC_IPS_LEAVE == type)
3589 {
3590 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], IPS LEAVE notify\n"));
3591 //halbtc8723a2ant_InitCoexDm(pBtCoexist);
3592 }
3593}
3594
3595VOID
3596EXhalbtc8723a2ant_LpsNotify(
3597 IN PBTC_COEXIST pBtCoexist,
3598 IN u1Byte type
3599 )
3600{
3601 if(BTC_LPS_ENABLE == type)
3602 {
3603 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], LPS ENABLE notify\n"));
3604 }
3605 else if(BTC_LPS_DISABLE == type)
3606 {
3607 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], LPS DISABLE notify\n"));
3608 }
3609}
3610
3611VOID
3612EXhalbtc8723a2ant_ScanNotify(
3613 IN PBTC_COEXIST pBtCoexist,
3614 IN u1Byte type
3615 )
3616{
3617 if(BTC_SCAN_START == type)
3618 {
3619 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], SCAN START notify\n"));
3620 }
3621 else if(BTC_SCAN_FINISH == type)
3622 {
3623 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], SCAN FINISH notify\n"));
3624 }
3625}
3626
3627VOID
3628EXhalbtc8723a2ant_ConnectNotify(
3629 IN PBTC_COEXIST pBtCoexist,
3630 IN u1Byte type
3631 )
3632{
3633 if(BTC_ASSOCIATE_START == type)
3634 {
3635 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], CONNECT START notify\n"));
3636 }
3637 else if(BTC_ASSOCIATE_FINISH == type)
3638 {
3639 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], CONNECT FINISH notify\n"));
3640 }
3641}
3642
3643VOID
3644EXhalbtc8723a2ant_MediaStatusNotify(
3645 IN PBTC_COEXIST pBtCoexist,
3646 IN u1Byte type
3647 )
3648{
3649 if(BTC_MEDIA_CONNECT == type)
3650 {
3651 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], MEDIA connect notify\n"));
3652 }
3653 else
3654 {
3655 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], MEDIA disconnect notify\n"));
3656 }
3657
3658 halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, type);
3659}
3660
3661VOID
3662EXhalbtc8723a2ant_SpecialPacketNotify(
3663 IN PBTC_COEXIST pBtCoexist,
3664 IN u1Byte type
3665 )
3666{
3667 if(type == BTC_PACKET_DHCP)
3668 {
3669 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], DHCP Packet notify\n"));
3670 }
3671}
3672
3673VOID
3674EXhalbtc8723a2ant_BtInfoNotify(
3675 IN PBTC_COEXIST pBtCoexist,
3676 IN pu1Byte tmpBuf,
3677 IN u1Byte length
3678 )
3679{
3680 u1Byte btInfo=0;
3681 u1Byte i, rspSource=0;
3682 BOOLEAN bBtBusy=FALSE, limited_dig=FALSE;
3683 BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE;
3684
3685 pCoexSta->bC2hBtInfoReqSent = FALSE;
3686
3687 rspSource = BT_INFO_SRC_8723A_2ANT_BT_RSP;
3688 pCoexSta->btInfoC2hCnt[rspSource]++;
3689
3690 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length));
3691 for(i=0; i<length; i++)
3692 {
3693 pCoexSta->btInfoC2h[rspSource][i] = tmpBuf[i];
3694 if(i == 0)
3695 btInfo = tmpBuf[i];
3696 if(i == length-1)
3697 {
3698 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("0x%02x]\n", tmpBuf[i]));
3699 }
3700 else
3701 {
3702 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("0x%02x, ", tmpBuf[i]));
3703 }
3704 }
3705
3706 if(BT_INFO_SRC_8723A_2ANT_WIFI_FW != rspSource)
3707 {
3708 pCoexSta->btRetryCnt =
3709 pCoexSta->btInfoC2h[rspSource][1];
3710
3711 pCoexSta->btRssi =
3712 pCoexSta->btInfoC2h[rspSource][2]*2+10;
3713
3714 pCoexSta->btInfoExt =
3715 pCoexSta->btInfoC2h[rspSource][3];
3716 }
3717
3718 pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn);
3719 // check BIT2 first ==> check if bt is under inquiry or page scan
3720 if(btInfo & BT_INFO_8723A_2ANT_B_INQ_PAGE)
3721 {
3722 pCoexSta->bC2hBtInquiryPage = true;
3723 }
3724 else
3725 {
3726 pCoexSta->bC2hBtInquiryPage = FALSE;
3727 }
3728}
3729
3730VOID
3731EXhalbtc8723a2ant_StackOperationNotify(
3732 IN PBTC_COEXIST pBtCoexist,
3733 IN u1Byte type
3734 )
3735{
3736 if(BTC_STACK_OP_INQ_PAGE_PAIR_START == type)
3737 {
3738 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], StackOP Inquiry/page/pair start notify\n"));
3739 pCoexSta->bHoldForStackOperation = true;
3740 pCoexSta->bHoldPeriodCnt = 1;
3741 halbtc8723a2ant_BtInquiryPage(pBtCoexist);
3742 }
3743 else if(BTC_STACK_OP_INQ_PAGE_PAIR_FINISH == type)
3744 {
3745 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], StackOP Inquiry/page/pair finish notify\n"));
3746 pCoexSta->bHoldForStackOperation = FALSE;
3747 }
3748}
3749
3750VOID
3751EXhalbtc8723a2ant_HaltNotify(
3752 IN PBTC_COEXIST pBtCoexist
3753 )
3754{
3755 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], Halt notify\n"));
3756
3757 halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, true);
3758 EXhalbtc8723a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT);
3759}
3760
3761VOID
3762EXhalbtc8723a2ant_Periodical(
3763 IN PBTC_COEXIST pBtCoexist
3764 )
3765{
3766 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, ("[BTCoex], 2Ant Periodical!!\n"));
3767
3768 // work around for c2h hang
3769 wa_halbtc8723a2ant_MonitorC2h(pBtCoexist);
3770
3771 halbtc8723a2ant_QueryBtInfo(pBtCoexist);
3772 halbtc8723a2ant_MonitorBtCtr(pBtCoexist);
3773 halbtc8723a2ant_MonitorBtEnableDisable(pBtCoexist);
3774
3775 halbtc8723a2ant_RunCoexistMechanism(pBtCoexist);
3776}
3777
3778
3779#endif
3780
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtc8723a2ant.h b/drivers/staging/rtl8821ae/btcoexist/halbtc8723a2ant.h
new file mode 100644
index 000000000000..c07d3738aadc
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtc8723a2ant.h
@@ -0,0 +1,179 @@
1//===========================================
2// The following is for 8723A 2Ant BT Co-exist definition
3//===========================================
4#define BT_INFO_8723A_2ANT_B_FTP BIT7
5#define BT_INFO_8723A_2ANT_B_A2DP BIT6
6#define BT_INFO_8723A_2ANT_B_HID BIT5
7#define BT_INFO_8723A_2ANT_B_SCO_BUSY BIT4
8#define BT_INFO_8723A_2ANT_B_ACL_BUSY BIT3
9#define BT_INFO_8723A_2ANT_B_INQ_PAGE BIT2
10#define BT_INFO_8723A_2ANT_B_SCO_ESCO BIT1
11#define BT_INFO_8723A_2ANT_B_CONNECTION BIT0
12
13#define BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT 2
14
15typedef enum _BT_INFO_SRC_8723A_2ANT{
16 BT_INFO_SRC_8723A_2ANT_WIFI_FW = 0x0,
17 BT_INFO_SRC_8723A_2ANT_BT_RSP = 0x1,
18 BT_INFO_SRC_8723A_2ANT_BT_ACTIVE_SEND = 0x2,
19 BT_INFO_SRC_8723A_2ANT_MAX
20}BT_INFO_SRC_8723A_2ANT,*PBT_INFO_SRC_8723A_2ANT;
21
22typedef enum _BT_8723A_2ANT_BT_STATUS{
23 BT_8723A_2ANT_BT_STATUS_IDLE = 0x0,
24 BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
25 BT_8723A_2ANT_BT_STATUS_NON_IDLE = 0x2,
26 BT_8723A_2ANT_BT_STATUS_MAX
27}BT_8723A_2ANT_BT_STATUS,*PBT_8723A_2ANT_BT_STATUS;
28
29typedef enum _BT_8723A_2ANT_COEX_ALGO{
30 BT_8723A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
31 BT_8723A_2ANT_COEX_ALGO_SCO = 0x1,
32 BT_8723A_2ANT_COEX_ALGO_HID = 0x2,
33 BT_8723A_2ANT_COEX_ALGO_A2DP = 0x3,
34 BT_8723A_2ANT_COEX_ALGO_PANEDR = 0x4,
35 BT_8723A_2ANT_COEX_ALGO_PANHS = 0x5,
36 BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
37 BT_8723A_2ANT_COEX_ALGO_PANEDR_HID = 0x7,
38 BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
39 BT_8723A_2ANT_COEX_ALGO_HID_A2DP = 0x9,
40 BT_8723A_2ANT_COEX_ALGO_MAX
41}BT_8723A_2ANT_COEX_ALGO,*PBT_8723A_2ANT_COEX_ALGO;
42
43typedef struct _COEX_DM_8723A_2ANT{
44 // fw mechanism
45 BOOLEAN bPreDecBtPwr;
46 BOOLEAN bCurDecBtPwr;
47 //BOOLEAN bPreBtLnaConstrain;
48 //BOOLEAN bCurBtLnaConstrain;
49 //u1Byte bPreBtPsdMode;
50 //u1Byte bCurBtPsdMode;
51 u1Byte preFwDacSwingLvl;
52 u1Byte curFwDacSwingLvl;
53 BOOLEAN bCurIgnoreWlanAct;
54 BOOLEAN bPreIgnoreWlanAct;
55 u1Byte prePsTdma;
56 u1Byte curPsTdma;
57 u1Byte psTdmaPara[5];
58 u1Byte psTdmaDuAdjType;
59 BOOLEAN bResetTdmaAdjust;
60 BOOLEAN bPrePsTdmaOn;
61 BOOLEAN bCurPsTdmaOn;
62 //BOOLEAN bPreBtAutoReport;
63 //BOOLEAN bCurBtAutoReport;
64
65 // sw mechanism
66 BOOLEAN bPreRfRxLpfShrink;
67 BOOLEAN bCurRfRxLpfShrink;
68 u4Byte btRf0x1eBackup;
69 BOOLEAN bPreLowPenaltyRa;
70 BOOLEAN bCurLowPenaltyRa;
71 BOOLEAN bPreDacSwingOn;
72 u4Byte preDacSwingLvl;
73 BOOLEAN bCurDacSwingOn;
74 u4Byte curDacSwingLvl;
75 BOOLEAN bPreAdcBackOff;
76 BOOLEAN bCurAdcBackOff;
77 BOOLEAN bPreAgcTableEn;
78 BOOLEAN bCurAgcTableEn;
79 u4Byte preVal0x6c0;
80 u4Byte curVal0x6c0;
81 u4Byte preVal0x6c8;
82 u4Byte curVal0x6c8;
83 u1Byte preVal0x6cc;
84 u1Byte curVal0x6cc;
85 BOOLEAN limited_dig;
86
87 // algorithm related
88 u1Byte preAlgorithm;
89 u1Byte curAlgorithm;
90 u1Byte btStatus;
91 u1Byte wifiChnlInfo[3];
92} COEX_DM_8723A_2ANT, *PCOEX_DM_8723A_2ANT;
93
94typedef struct _COEX_STA_8723A_2ANT{
95 u4Byte highPriorityTx;
96 u4Byte highPriorityRx;
97 u4Byte lowPriorityTx;
98 u4Byte lowPriorityRx;
99 u1Byte btRssi;
100 u1Byte preBtRssiState;
101 u1Byte preBtRssiState1;
102 u1Byte preWifiRssiState[4];
103 BOOLEAN bC2hBtInfoReqSent;
104 u1Byte btInfoC2h[BT_INFO_SRC_8723A_2ANT_MAX][10];
105 u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_MAX];
106 BOOLEAN bC2hBtInquiryPage;
107 u1Byte btRetryCnt;
108 u1Byte btInfoExt;
109 BOOLEAN bHoldForStackOperation;
110 u1Byte bHoldPeriodCnt;
111 // this is for c2h hang work-around
112 u4Byte c2hHangDetectCnt;
113}COEX_STA_8723A_2ANT, *PCOEX_STA_8723A_2ANT;
114
115//===========================================
116// The following is interface which will notify coex module.
117//===========================================
118VOID
119EXhalbtc8723a2ant_InitHwConfig(
120 IN PBTC_COEXIST pBtCoexist
121 );
122VOID
123EXhalbtc8723a2ant_InitCoexDm(
124 IN PBTC_COEXIST pBtCoexist
125 );
126VOID
127EXhalbtc8723a2ant_IpsNotify(
128 IN PBTC_COEXIST pBtCoexist,
129 IN u1Byte type
130 );
131VOID
132EXhalbtc8723a2ant_LpsNotify(
133 IN PBTC_COEXIST pBtCoexist,
134 IN u1Byte type
135 );
136VOID
137EXhalbtc8723a2ant_ScanNotify(
138 IN PBTC_COEXIST pBtCoexist,
139 IN u1Byte type
140 );
141VOID
142EXhalbtc8723a2ant_ConnectNotify(
143 IN PBTC_COEXIST pBtCoexist,
144 IN u1Byte type
145 );
146VOID
147EXhalbtc8723a2ant_MediaStatusNotify(
148 IN PBTC_COEXIST pBtCoexist,
149 IN u1Byte type
150 );
151VOID
152EXhalbtc8723a2ant_SpecialPacketNotify(
153 IN PBTC_COEXIST pBtCoexist,
154 IN u1Byte type
155 );
156VOID
157EXhalbtc8723a2ant_HaltNotify(
158 IN PBTC_COEXIST pBtCoexist
159 );
160VOID
161EXhalbtc8723a2ant_Periodical(
162 IN PBTC_COEXIST pBtCoexist
163 );
164VOID
165EXhalbtc8723a2ant_BtInfoNotify(
166 IN PBTC_COEXIST pBtCoexist,
167 IN pu1Byte tmpBuf,
168 IN u1Byte length
169 );
170VOID
171EXhalbtc8723a2ant_StackOperationNotify(
172 IN PBTC_COEXIST pBtCoexist,
173 IN u1Byte type
174 );
175VOID
176EXhalbtc8723a2ant_DisplayCoexInfo(
177 IN PBTC_COEXIST pBtCoexist
178 );
179
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtc8723b1ant.c b/drivers/staging/rtl8821ae/btcoexist/halbtc8723b1ant.c
new file mode 100644
index 000000000000..3414ba78cc43
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtc8723b1ant.c
@@ -0,0 +1,4104 @@
1/***************************************************************
2 * Description:
3 *
4 * This file is for RTL8723B Co-exist mechanism
5 *
6 * History
7 * 2012/11/15 Cosa first check in.
8 *
9 ***************************************************************/
10
11
12/***************************************************************
13 * include files
14 ***************************************************************/
15#include "halbt_precomp.h"
16#if 1
17/***************************************************************
18 * Global variables, these are static variables
19 ***************************************************************/
20static struct coex_dm_8723b_1ant glcoex_dm_8723b_1ant;
21static struct coex_dm_8723b_1ant *coex_dm = &glcoex_dm_8723b_1ant;
22static struct coex_sta_8723b_1ant glcoex_sta_8723b_1ant;
23static struct coex_sta_8723b_1ant *coex_sta = &glcoex_sta_8723b_1ant;
24
25const char *const GLBtInfoSrc8723b1Ant[]={
26 "BT Info[wifi fw]",
27 "BT Info[bt rsp]",
28 "BT Info[bt auto report]",
29};
30
31u32 glcoex_ver_date_8723b_1ant = 20130906;
32u32 glcoex_ver_8723b_1ant = 0x45;
33
34/***************************************************************
35 * local function proto type if needed
36 ***************************************************************/
37/***************************************************************
38 * local function start with halbtc8723b1ant_
39 ***************************************************************/
40u8 halbtc8723b1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
41{
42 s32 bt_rssi=0;
43 u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
44
45 bt_rssi = coex_sta->bt_rssi;
46
47 if (level_num == 2){
48 if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
49 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
50 if (bt_rssi >= rssi_thresh +
51 BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT) {
52 bt_rssi_state = BTC_RSSI_STATE_HIGH;
53 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
54 "[BTCoex], BT Rssi state "
55 "switch to High\n");
56 } else {
57 bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
58 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
59 "[BTCoex], BT Rssi state "
60 "stay at Low\n");
61 }
62 } else {
63 if (bt_rssi < rssi_thresh) {
64 bt_rssi_state = BTC_RSSI_STATE_LOW;
65 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
66 "[BTCoex], BT Rssi state "
67 "switch to Low\n");
68 } else {
69 bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
70 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
71 "[BTCoex], BT Rssi state "
72 "stay at High\n");
73 }
74 }
75 } else if (level_num == 3) {
76 if (rssi_thresh > rssi_thresh1) {
77 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
78 "[BTCoex], BT Rssi thresh error!!\n");
79 return coex_sta->pre_bt_rssi_state;
80 }
81
82 if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
83 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
84 if (bt_rssi >= rssi_thresh +
85 BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT) {
86 bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
87 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
88 "[BTCoex], BT Rssi state "
89 "switch to Medium\n");
90 } else {
91 bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
92 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
93 "[BTCoex], BT Rssi state "
94 "stay at Low\n");
95 }
96 } else if ((coex_sta->pre_bt_rssi_state ==
97 BTC_RSSI_STATE_MEDIUM) ||
98 (coex_sta->pre_bt_rssi_state ==
99 BTC_RSSI_STATE_STAY_MEDIUM)) {
100 if (bt_rssi >= rssi_thresh1 +
101 BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT) {
102 bt_rssi_state = BTC_RSSI_STATE_HIGH;
103 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
104 "[BTCoex], BT Rssi state "
105 "switch to High\n");
106 } else if (bt_rssi < rssi_thresh) {
107 bt_rssi_state = BTC_RSSI_STATE_LOW;
108 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
109 "[BTCoex], BT Rssi state "
110 "switch to Low\n");
111 } else {
112 bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
113 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
114 "[BTCoex], BT Rssi state "
115 "stay at Medium\n");
116 }
117 } else {
118 if (bt_rssi < rssi_thresh1) {
119 bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
120 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
121 "[BTCoex], BT Rssi state "
122 "switch to Medium\n");
123 } else {
124 bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
125 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
126 "[BTCoex], BT Rssi state "
127 "stay at High\n");
128 }
129 }
130 }
131
132 coex_sta->pre_bt_rssi_state = bt_rssi_state;
133
134 return bt_rssi_state;
135}
136
137u8 halbtc8723b1ant_wifi_rssi_state(struct btc_coexist *btcoexist,
138 u8 index, u8 level_num,
139 u8 rssi_thresh, u8 rssi_thresh1)
140{
141 s32 wifi_rssi=0;
142 u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
143
144 btcoexist->btc_get(btcoexist,
145 BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
146
147 if (level_num == 2) {
148 if ((coex_sta->pre_wifi_rssi_state[index] ==
149 BTC_RSSI_STATE_LOW) ||
150 (coex_sta->pre_wifi_rssi_state[index] ==
151 BTC_RSSI_STATE_STAY_LOW)) {
152 if (wifi_rssi >= rssi_thresh +
153 BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT) {
154 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
155 BTC_PRINT(BTC_MSG_ALGORITHM,
156 ALGO_WIFI_RSSI_STATE,
157 "[BTCoex], wifi RSSI state "
158 "switch to High\n");
159 } else {
160 wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
161 BTC_PRINT(BTC_MSG_ALGORITHM,
162 ALGO_WIFI_RSSI_STATE,
163 "[BTCoex], wifi RSSI state "
164 "stay at Low\n");
165 }
166 } else {
167 if (wifi_rssi < rssi_thresh) {
168 wifi_rssi_state = BTC_RSSI_STATE_LOW;
169 BTC_PRINT(BTC_MSG_ALGORITHM,
170 ALGO_WIFI_RSSI_STATE,
171 "[BTCoex], wifi RSSI state "
172 "switch to Low\n");
173 } else {
174 wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
175 BTC_PRINT(BTC_MSG_ALGORITHM,
176 ALGO_WIFI_RSSI_STATE,
177 "[BTCoex], wifi RSSI state "
178 "stay at High\n");
179 }
180 }
181 } else if (level_num == 3) {
182 if (rssi_thresh > rssi_thresh1) {
183 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE,
184 "[BTCoex], wifi RSSI thresh error!!\n");
185 return coex_sta->pre_wifi_rssi_state[index];
186 }
187
188 if ((coex_sta->pre_wifi_rssi_state[index] ==
189 BTC_RSSI_STATE_LOW) ||
190 (coex_sta->pre_wifi_rssi_state[index] ==
191 BTC_RSSI_STATE_STAY_LOW)) {
192 if (wifi_rssi >= rssi_thresh +
193 BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT) {
194 wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
195 BTC_PRINT(BTC_MSG_ALGORITHM,
196 ALGO_WIFI_RSSI_STATE,
197 "[BTCoex], wifi RSSI state "
198 "switch to Medium\n");
199 } else {
200 wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
201 BTC_PRINT(BTC_MSG_ALGORITHM,
202 ALGO_WIFI_RSSI_STATE,
203 "[BTCoex], wifi RSSI state "
204 "stay at Low\n");
205 }
206 } else if ((coex_sta->pre_wifi_rssi_state[index] ==
207 BTC_RSSI_STATE_MEDIUM) ||
208 (coex_sta->pre_wifi_rssi_state[index] ==
209 BTC_RSSI_STATE_STAY_MEDIUM)) {
210 if (wifi_rssi >= rssi_thresh1 +
211 BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT) {
212 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
213 BTC_PRINT(BTC_MSG_ALGORITHM,
214 ALGO_WIFI_RSSI_STATE,
215 "[BTCoex], wifi RSSI state "
216 "switch to High\n");
217 } else if (wifi_rssi < rssi_thresh) {
218 wifi_rssi_state = BTC_RSSI_STATE_LOW;
219 BTC_PRINT(BTC_MSG_ALGORITHM,
220 ALGO_WIFI_RSSI_STATE,
221 "[BTCoex], wifi RSSI state "
222 "switch to Low\n");
223 } else {
224 wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
225 BTC_PRINT(BTC_MSG_ALGORITHM,
226 ALGO_WIFI_RSSI_STATE,
227 "[BTCoex], wifi RSSI state "
228 "stay at Medium\n");
229 }
230 } else {
231 if (wifi_rssi < rssi_thresh1) {
232 wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
233 BTC_PRINT(BTC_MSG_ALGORITHM,
234 ALGO_WIFI_RSSI_STATE,
235 "[BTCoex], wifi RSSI state "
236 "switch to Medium\n");
237 } else {
238 wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
239 BTC_PRINT(BTC_MSG_ALGORITHM,
240 ALGO_WIFI_RSSI_STATE,
241 "[BTCoex], wifi RSSI state "
242 "stay at High\n");
243 }
244 }
245 }
246
247 coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
248
249 return wifi_rssi_state;
250}
251
252void halbtc8723b1ant_updatera_mask(struct btc_coexist *btcoexist,
253 bool force_exec, u32 dis_rate_mask)
254{
255 coex_dm->curra_mask = dis_rate_mask;
256
257 if (force_exec || (coex_dm->prera_mask != coex_dm->curra_mask))
258 btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_ra_mask,
259 &coex_dm->curra_mask);
260
261 coex_dm->prera_mask = coex_dm->curra_mask;
262}
263
264void halbtc8723b1ant_auto_rate_fallback_retry(struct btc_coexist *btcoexist,
265 bool force_exec, u8 type)
266{
267 bool wifi_under_bmode = false;
268
269 coex_dm->cur_arfr_type = type;
270
271 if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
272 switch (coex_dm->cur_arfr_type) {
273 case 0: /* normal mode */
274 btcoexist->btc_write_4byte(btcoexist, 0x430,
275 coex_dm->backup_arfr_cnt1);
276 btcoexist->btc_write_4byte(btcoexist, 0x434,
277 coex_dm->backup_arfr_cnt2);
278 break;
279 case 1:
280 btcoexist->btc_get(btcoexist,
281 BTC_GET_BL_WIFI_UNDER_B_MODE,
282 &wifi_under_bmode);
283 if (wifi_under_bmode) {
284 btcoexist->btc_write_4byte(btcoexist,
285 0x430, 0x0);
286 btcoexist->btc_write_4byte(btcoexist,
287 0x434, 0x01010101);
288 } else {
289 btcoexist->btc_write_4byte(btcoexist,
290 0x430, 0x0);
291 btcoexist->btc_write_4byte(btcoexist,
292 0x434, 0x04030201);
293 }
294 break;
295 default:
296 break;
297 }
298 }
299
300 coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
301}
302
303void halbtc8723b1ant_retry_limit(struct btc_coexist *btcoexist,
304 bool force_exec, u8 type)
305{
306 coex_dm->cur_retry_limit_type = type;
307
308 if (force_exec || (coex_dm->pre_retry_limit_type !=
309 coex_dm->cur_retry_limit_type)) {
310
311 switch (coex_dm->cur_retry_limit_type) {
312 case 0: /* normal mode */
313 btcoexist->btc_write_2byte(btcoexist, 0x42a,
314 coex_dm->backup_retry_limit);
315 break;
316 case 1: /* retry limit=8 */
317 btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808);
318 break;
319 default:
320 break;
321 }
322 }
323
324 coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
325}
326
327void halbtc8723b1ant_ampdu_maxtime(struct btc_coexist *btcoexist,
328 bool force_exec, u8 type)
329{
330 coex_dm->cur_ampdu_time_type = type;
331
332 if (force_exec || (coex_dm->pre_ampdu_time_type !=
333 coex_dm->cur_ampdu_time_type)) {
334 switch (coex_dm->cur_ampdu_time_type) {
335 case 0: /* normal mode */
336 btcoexist->btc_write_1byte(btcoexist, 0x456,
337 coex_dm->backup_ampdu_max_time);
338 break;
339 case 1: /* AMPDU timw = 0x38 * 32us */
340 btcoexist->btc_write_1byte(btcoexist,
341 0x456, 0x38);
342 break;
343 default:
344 break;
345 }
346 }
347
348 coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
349}
350
351void halbtc8723b1ant_limited_tx(struct btc_coexist *btcoexist,
352 bool force_exec, u8 ra_maskType, u8 arfr_type,
353 u8 retry_limit_type, u8 ampdu_time_type)
354{
355 switch (ra_maskType) {
356 case 0: /* normal mode */
357 halbtc8723b1ant_updatera_mask(btcoexist, force_exec, 0x0);
358 break;
359 case 1: /* disable cck 1/2 */
360 halbtc8723b1ant_updatera_mask(btcoexist, force_exec,
361 0x00000003);
362 break;
363 /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4*/
364 case 2:
365 halbtc8723b1ant_updatera_mask(btcoexist, force_exec,
366 0x0001f1f7);
367 break;
368 default:
369 break;
370 }
371
372 halbtc8723b1ant_auto_rate_fallback_retry(btcoexist, force_exec,
373 arfr_type);
374 halbtc8723b1ant_retry_limit(btcoexist, force_exec, retry_limit_type);
375 halbtc8723b1ant_ampdu_maxtime(btcoexist, force_exec, ampdu_time_type);
376}
377
378void halbtc8723b1ant_limited_rx(struct btc_coexist *btcoexist,
379 bool force_exec, bool rej_ap_agg_pkt,
380 bool b_bt_ctrl_agg_buf_size, u8 agg_buf_size)
381{
382 bool reject_rx_agg = rej_ap_agg_pkt;
383 bool bt_ctrl_rx_agg_size = b_bt_ctrl_agg_buf_size;
384 u8 rxAggSize = agg_buf_size;
385
386 /**********************************************
387 * Rx Aggregation related setting
388 **********************************************/
389 btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
390 &reject_rx_agg);
391 /* decide BT control aggregation buf size or not */
392 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
393 &bt_ctrl_rx_agg_size);
394 /* aggregation buf size, only work
395 *when BT control Rx aggregation size. */
396 btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize);
397 /* real update aggregation setting */
398 btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
399}
400
401void halbtc8723b1ant_monitor_bt_ctr(struct btc_coexist *btcoexist)
402{
403 u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
404 u32 reg_hp_tx = 0, reg_hp_rx = 0;
405 u32 reg_lp_tx = 0, reg_lp_rx = 0;
406
407 reg_hp_txrx = 0x770;
408 reg_lp_txrx = 0x774;
409
410 u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
411 reg_hp_tx = u32tmp & MASKLWORD;
412 reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
413
414 u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
415 reg_lp_tx = u32tmp & MASKLWORD;
416 reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
417
418 coex_sta->high_priority_tx = reg_hp_tx;
419 coex_sta->high_priority_rx = reg_hp_rx;
420 coex_sta->low_priority_tx = reg_lp_tx;
421 coex_sta->low_priority_rx = reg_lp_rx;
422
423 /* reset counter */
424 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
425}
426
427void halbtc8723b1ant_query_bt_info(struct btc_coexist *btcoexist)
428{
429 u8 h2c_parameter[1] = {0};
430
431 coex_sta->c2h_bt_info_req_sent = true;
432
433 h2c_parameter[0] |= BIT0; /* trigger*/
434
435 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
436 "[BTCoex], Query Bt Info, FW write 0x61=0x%x\n",
437 h2c_parameter[0]);
438
439 btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
440}
441
442bool halbtc8723b1ant_is_wifi_status_changed(struct btc_coexist *btcoexist)
443{
444 static bool pre_wifi_busy = false;
445 static bool pre_under_4way = false, pre_bt_hs_on = false;
446 bool wifi_busy = false, under_4way = false, bt_hs_on = false;
447 bool wifi_connected = false;
448
449 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
450 &wifi_connected);
451 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
452 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
453 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
454 &under_4way);
455
456 if (wifi_connected) {
457 if (wifi_busy != pre_wifi_busy) {
458 pre_wifi_busy = wifi_busy;
459 return true;
460 }
461 if (under_4way != pre_under_4way) {
462 pre_under_4way = under_4way;
463 return true;
464 }
465 if (bt_hs_on != pre_bt_hs_on) {
466 pre_bt_hs_on = bt_hs_on;
467 return true;
468 }
469 }
470
471 return false;
472}
473
474void halbtc8723b1ant_update_bt_link_info(struct btc_coexist *btcoexist)
475{
476 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
477 bool bt_hs_on = false;
478
479 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
480
481 bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
482 bt_link_info->sco_exist = coex_sta->sco_exist;
483 bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
484 bt_link_info->pan_exist = coex_sta->pan_exist;
485 bt_link_info->hid_exist = coex_sta->hid_exist;
486
487 /* work around for HS mode. */
488 if (bt_hs_on) {
489 bt_link_info->pan_exist = true;
490 bt_link_info->bt_link_exist = true;
491 }
492
493 /* check if Sco only */
494 if (bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
495 !bt_link_info->pan_exist && !bt_link_info->hid_exist)
496 bt_link_info->sco_only = true;
497 else
498 bt_link_info->sco_only = false;
499
500 /* check if A2dp only */
501 if (!bt_link_info->sco_exist && bt_link_info->a2dp_exist &&
502 !bt_link_info->pan_exist && !bt_link_info->hid_exist)
503 bt_link_info->a2dp_only = true;
504 else
505 bt_link_info->a2dp_only = false;
506
507 /* check if Pan only */
508 if (!bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
509 bt_link_info->pan_exist && !bt_link_info->hid_exist)
510 bt_link_info->pan_only = true;
511 else
512 bt_link_info->pan_only = false;
513
514 /* check if Hid only */
515 if (!bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
516 !bt_link_info->pan_exist && bt_link_info->hid_exist )
517 bt_link_info->hid_only = true;
518 else
519 bt_link_info->hid_only = false;
520}
521
522u8 halbtc8723b1ant_action_algorithm(struct btc_coexist *btcoexist)
523{
524 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
525 bool bt_hs_on = false;
526 u8 algorithm = BT_8723B_1ANT_COEX_ALGO_UNDEFINED;
527 u8 numOfDiffProfile = 0;
528
529 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
530
531 if (!bt_link_info->bt_link_exist) {
532 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
533 "[BTCoex], No BT link exists!!!\n");
534 return algorithm;
535 }
536
537 if (bt_link_info->sco_exist)
538 numOfDiffProfile++;
539 if (bt_link_info->hid_exist)
540 numOfDiffProfile++;
541 if (bt_link_info->pan_exist)
542 numOfDiffProfile++;
543 if (bt_link_info->a2dp_exist)
544 numOfDiffProfile++;
545
546 if (numOfDiffProfile == 1) {
547 if (bt_link_info->sco_exist) {
548 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
549 "[BTCoex], BT Profile = SCO only\n");
550 algorithm = BT_8723B_1ANT_COEX_ALGO_SCO;
551 } else {
552 if (bt_link_info->hid_exist) {
553 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
554 "[BTCoex], BT Profile = HID only\n");
555 algorithm = BT_8723B_1ANT_COEX_ALGO_HID;
556 } else if (bt_link_info->a2dp_exist) {
557 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
558 "[BTCoex], BT Profile = A2DP only\n");
559 algorithm = BT_8723B_1ANT_COEX_ALGO_A2DP;
560 } else if (bt_link_info->pan_exist) {
561 if (bt_hs_on) {
562 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
563 "[BTCoex], BT Profile = "
564 "PAN(HS) only\n");
565 algorithm =
566 BT_8723B_1ANT_COEX_ALGO_PANHS;
567 } else {
568 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
569 "[BTCoex], BT Profile = "
570 "PAN(EDR) only\n");
571 algorithm =
572 BT_8723B_1ANT_COEX_ALGO_PANEDR;
573 }
574 }
575 }
576 } else if (numOfDiffProfile == 2) {
577 if (bt_link_info->sco_exist) {
578 if (bt_link_info->hid_exist) {
579 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
580 "[BTCoex], BT Profile = SCO + HID\n");
581 algorithm = BT_8723B_1ANT_COEX_ALGO_HID;
582 } else if (bt_link_info->a2dp_exist) {
583 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
584 "[BTCoex], BT Profile = "
585 "SCO + A2DP ==> SCO\n");
586 algorithm = BT_8723B_1ANT_COEX_ALGO_SCO;
587 } else if (bt_link_info->pan_exist) {
588 if (bt_hs_on) {
589 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
590 "[BTCoex], BT Profile "
591 "= SCO + PAN(HS)\n");
592 algorithm = BT_8723B_1ANT_COEX_ALGO_SCO;
593 } else {
594 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
595 "[BTCoex], BT Profile "
596 "= SCO + PAN(EDR)\n");
597 algorithm =
598 BT_8723B_1ANT_COEX_ALGO_PANEDR_HID;
599 }
600 }
601 } else {
602 if (bt_link_info->hid_exist &&
603 bt_link_info->a2dp_exist) {
604 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
605 "[BTCoex], BT Profile = "
606 "HID + A2DP\n");
607 algorithm = BT_8723B_1ANT_COEX_ALGO_HID_A2DP;
608 } else if (bt_link_info->hid_exist &&
609 bt_link_info->pan_exist) {
610 if (bt_hs_on) {
611 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
612 "[BTCoex], BT Profile = "
613 "HID + PAN(HS)\n");
614 algorithm =
615 BT_8723B_1ANT_COEX_ALGO_HID_A2DP;
616 } else {
617 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
618 "[BTCoex], BT Profile = "
619 "HID + PAN(EDR)\n");
620 algorithm =
621 BT_8723B_1ANT_COEX_ALGO_PANEDR_HID;
622 }
623 } else if (bt_link_info->pan_exist &&
624 bt_link_info->a2dp_exist) {
625 if (bt_hs_on) {
626 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
627 "[BTCoex], BT Profile = "
628 "A2DP + PAN(HS)\n");
629 algorithm =
630 BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS;
631 } else {
632 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
633 "[BTCoex], BT Profile = "
634 "A2DP + PAN(EDR)\n");
635 algorithm =
636 BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP;
637 }
638 }
639 }
640 } else if (numOfDiffProfile == 3) {
641 if (bt_link_info->sco_exist) {
642 if (bt_link_info->hid_exist &&
643 bt_link_info->a2dp_exist) {
644 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
645 "[BTCoex], BT Profile = "
646 "SCO + HID + A2DP ==> HID\n");
647 algorithm = BT_8723B_1ANT_COEX_ALGO_HID;
648 } else if (bt_link_info->hid_exist &&
649 bt_link_info->pan_exist) {
650 if (bt_hs_on) {
651 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
652 "[BTCoex], BT Profile = "
653 "SCO + HID + PAN(HS)\n");
654 algorithm =
655 BT_8723B_1ANT_COEX_ALGO_HID_A2DP;
656 } else {
657 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
658 "[BTCoex], BT Profile = "
659 "SCO + HID + PAN(EDR)\n");
660 algorithm =
661 BT_8723B_1ANT_COEX_ALGO_PANEDR_HID;
662 }
663 } else if (bt_link_info->pan_exist &&
664 bt_link_info->a2dp_exist) {
665 if (bt_hs_on) {
666 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
667 "[BTCoex], BT Profile = "
668 "SCO + A2DP + PAN(HS)\n");
669 algorithm = BT_8723B_1ANT_COEX_ALGO_SCO;
670 } else {
671 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
672 "[BTCoex], BT Profile = SCO + "
673 "A2DP + PAN(EDR) ==> HID\n");
674 algorithm =
675 BT_8723B_1ANT_COEX_ALGO_PANEDR_HID;
676 }
677 }
678 } else {
679 if (bt_link_info->hid_exist &&
680 bt_link_info->pan_exist &&
681 bt_link_info->a2dp_exist) {
682 if (bt_hs_on) {
683 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
684 "[BTCoex], BT Profile = "
685 "HID + A2DP + PAN(HS)\n");
686 algorithm =
687 BT_8723B_1ANT_COEX_ALGO_HID_A2DP;
688 } else {
689 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
690 "[BTCoex], BT Profile = "
691 "HID + A2DP + PAN(EDR)\n");
692 algorithm =
693 BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR;
694 }
695 }
696 }
697 } else if (numOfDiffProfile >= 3) {
698 if (bt_link_info->sco_exist) {
699 if (bt_link_info->hid_exist &&
700 bt_link_info->pan_exist &&
701 bt_link_info->a2dp_exist) {
702 if (bt_hs_on) {
703 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
704 "[BTCoex], Error!!! "
705 "BT Profile = SCO + "
706 "HID + A2DP + PAN(HS)\n");
707 } else {
708 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
709 "[BTCoex], BT Profile = "
710 "SCO + HID + A2DP + PAN(EDR)"
711 "==>PAN(EDR)+HID\n");
712 algorithm =
713 BT_8723B_1ANT_COEX_ALGO_PANEDR_HID;
714 }
715 }
716 }
717 }
718
719 return algorithm;
720}
721
722bool halbtc8723b1ant_need_to_dec_bt_pwr(struct btc_coexist *btcoexist)
723{
724 bool ret = false;
725 bool bt_hs_on = false, wifi_connected = false;
726 s32 bt_hs_rssi = 0;
727 u8 bt_rssi_state;
728
729 if (!btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on))
730 return false;
731 if (!btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
732 &wifi_connected))
733 return false;
734 if (!btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi))
735 return false;
736
737 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 35, 0);
738
739 if (wifi_connected) {
740 if (bt_hs_on) {
741 if (bt_hs_rssi > 37)
742 ret = true;
743 } else {
744 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
745 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
746 ret = true;
747 }
748 }
749
750 return ret;
751}
752
753void halbtc8723b1ant_set_fw_dac_swing_level(struct btc_coexist *btcoexist,
754 u8 dac_swing_lvl)
755{
756 u8 h2c_parameter[1] = {0};
757
758 /* There are several type of dacswing
759 * 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
760 h2c_parameter[0] = dac_swing_lvl;
761
762 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
763 "[BTCoex], Set Dac Swing Level=0x%x\n", dac_swing_lvl);
764 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
765 "[BTCoex], FW write 0x64=0x%x\n", h2c_parameter[0]);
766
767 btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
768}
769
770void halbtc8723b1ant_set_fw_dec_bt_pwr(struct btc_coexist *btcoexist,
771 bool dec_bt_pwr)
772{
773 u8 h2c_parameter[1] = {0};
774
775 h2c_parameter[0] = 0;
776
777 if (dec_bt_pwr)
778 h2c_parameter[0] |= BIT1;
779
780 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
781 "[BTCoex], decrease Bt Power : %s, FW write 0x62=0x%x\n",
782 (dec_bt_pwr? "Yes!!":"No!!"),h2c_parameter[0]);
783
784 btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
785}
786
787void halbtc8723b1ant_dec_bt_pwr(struct btc_coexist *btcoexist,
788 bool force_exec, bool dec_bt_pwr)
789{
790 return;
791 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
792 "[BTCoex], %s Dec BT power = %s\n",
793 (force_exec ? "force to" : ""), (dec_bt_pwr ? "ON" : "OFF"));
794 coex_dm->cur_dec_bt_pwr = dec_bt_pwr;
795
796 if (!force_exec) {
797 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
798 "[BTCoex], bPreDecBtPwr=%d, bCurDecBtPwr=%d\n",
799 coex_dm->pre_dec_bt_pwr, coex_dm->cur_dec_bt_pwr);
800
801 if (coex_dm->pre_dec_bt_pwr == coex_dm->cur_dec_bt_pwr)
802 return;
803 }
804 halbtc8723b1ant_set_fw_dec_bt_pwr(btcoexist, coex_dm->cur_dec_bt_pwr);
805
806 coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr;
807}
808
809void halbtc8723b1ant_set_bt_auto_report(struct btc_coexist *btcoexist,
810 bool enable_auto_report)
811{
812 u8 h2c_parameter[1] = {0};
813
814 h2c_parameter[0] = 0;
815
816 if (enable_auto_report)
817 h2c_parameter[0] |= BIT0;
818
819 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
820 "[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n",
821 (enable_auto_report? "Enabled!!":"Disabled!!"),
822 h2c_parameter[0]);
823
824 btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
825}
826
827void halbtc8723b1ant_bt_auto_report(struct btc_coexist *btcoexist,
828 bool force_exec, bool enable_auto_report)
829{
830 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
831 "[BTCoex], %s BT Auto report = %s\n",
832 (force_exec? "force to":""),
833 ((enable_auto_report)? "Enabled":"Disabled"));
834 coex_dm->cur_bt_auto_report = enable_auto_report;
835
836 if (!force_exec) {
837 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
838 "[BTCoex], bPreBtAutoReport=%d, "
839 "bCurBtAutoReport=%d\n",
840 coex_dm->pre_bt_auto_report,
841 coex_dm->cur_bt_auto_report);
842
843 if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
844 return;
845 }
846 halbtc8723b1ant_set_bt_auto_report(btcoexist,
847 coex_dm->cur_bt_auto_report);
848
849 coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
850}
851
852void halbtc8723b1ant_fw_dac_swing_lvl(struct btc_coexist *btcoexist,
853 bool force_exec, u8 fw_dac_swing_lvl)
854{
855 return;
856 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
857 "[BTCoex], %s set FW Dac Swing level = %d\n",
858 (force_exec? "force to":""), fw_dac_swing_lvl);
859 coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
860
861 if (!force_exec) {
862 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
863 "[BTCoex], preFwDacSwingLvl=%d, "
864 "curFwDacSwingLvl=%d\n",
865 coex_dm->pre_fw_dac_swing_lvl,
866 coex_dm->cur_fw_dac_swing_lvl);
867
868 if (coex_dm->pre_fw_dac_swing_lvl ==
869 coex_dm->cur_fw_dac_swing_lvl)
870 return;
871 }
872
873 halbtc8723b1ant_set_fw_dac_swing_level(btcoexist,
874 coex_dm->cur_fw_dac_swing_lvl);
875
876 coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
877}
878
879void halbtc8723b1ant_set_sw_rf_rx_lpf_corner(struct btc_coexist *btcoexist,
880 bool rx_rf_shrink_on)
881{
882 if (rx_rf_shrink_on) {
883 /*Shrink RF Rx LPF corner */
884 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
885 "[BTCoex], Shrink RF Rx LPF corner!!\n");
886 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
887 0xfffff, 0xffff7);
888 } else {
889 /*Resume RF Rx LPF corner
890 * After initialized, we can use coex_dm->btRf0x1eBackup */
891 if (btcoexist->initilized) {
892 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
893 "[BTCoex], Resume RF Rx LPF corner!!\n");
894 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
895 0x1e, 0xfffff,
896 coex_dm->bt_rf0x1e_backup);
897 }
898 }
899}
900
901void halbtc8723b1ant_rf_shrink(struct btc_coexist *btcoexist,
902 bool force_exec, bool rx_rf_shrink_on)
903{
904 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
905 "[BTCoex], %s turn Rx RF Shrink = %s\n",
906 (force_exec? "force to":""),
907 ((rx_rf_shrink_on)? "ON":"OFF"));
908 coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
909
910 if (!force_exec) {
911 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
912 "[BTCoex], bPreRfRxLpfShrink=%d, "
913 "bCurRfRxLpfShrink=%d\n",
914 coex_dm->pre_rf_rx_lpf_shrink,
915 coex_dm->cur_rf_rx_lpf_shrink);
916
917 if (coex_dm->pre_rf_rx_lpf_shrink ==
918 coex_dm->cur_rf_rx_lpf_shrink)
919 return;
920 }
921 halbtc8723b1ant_set_sw_rf_rx_lpf_corner(btcoexist,
922 coex_dm->cur_rf_rx_lpf_shrink);
923
924 coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
925}
926
927void halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(
928 struct btc_coexist *btcoexist,
929 bool low_penalty_ra)
930{
931 u8 h2c_parameter[6] = {0};
932
933 h2c_parameter[0] = 0x6; /* opCode, 0x6= Retry_Penalty */
934
935 if (low_penalty_ra) {
936 h2c_parameter[1] |= BIT0;
937 /*normal rate except MCS7/6/5, OFDM54/48/36 */
938 h2c_parameter[2] = 0x00;
939 h2c_parameter[3] = 0xf7; /*MCS7 or OFDM54 */
940 h2c_parameter[4] = 0xf8; /*MCS6 or OFDM48 */
941 h2c_parameter[5] = 0xf9; /*MCS5 or OFDM36 */
942 }
943
944 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
945 "[BTCoex], set WiFi Low-Penalty Retry: %s",
946 (low_penalty_ra ? "ON!!" : "OFF!!"));
947
948 btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
949}
950
951void halbtc8723b1ant_low_penalty_ra(struct btc_coexist *btcoexist,
952 bool force_exec, bool low_penalty_ra)
953{
954 coex_dm->cur_low_penalty_ra = low_penalty_ra;
955
956 if (!force_exec) {
957 if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
958 return;
959 }
960 halbtc8723b1ant_set_sw_penalty_tx_rate_adaptive(btcoexist,
961 coex_dm->cur_low_penalty_ra);
962
963 coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
964}
965
966void halbtc8723b1ant_set_dac_swing_reg(struct btc_coexist *btcoexist, u32 level)
967{
968 u8 val = (u8) level;
969
970 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
971 "[BTCoex], Write SwDacSwing = 0x%x\n", level);
972 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
973}
974
975void halbtc8723b1ant_set_sw_full_time_dac_swing(struct btc_coexist *btcoexist,
976 bool sw_dac_swing_on,
977 u32 sw_dac_swing_lvl)
978{
979 if (sw_dac_swing_on)
980 halbtc8723b1ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
981 else
982 halbtc8723b1ant_set_dac_swing_reg(btcoexist, 0x18);
983}
984
985
986void halbtc8723b1ant_dac_swing(struct btc_coexist *btcoexist, bool force_exec,
987 bool dac_swing_on, u32 dac_swing_lvl)
988{
989 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
990 "[BTCoex], %s turn DacSwing=%s, dac_swing_lvl=0x%x\n",
991 (force_exec ? "force to" : ""), (dac_swing_on ? "ON" : "OFF"),
992 dac_swing_lvl);
993
994 coex_dm->cur_dac_swing_on = dac_swing_on;
995 coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
996
997 if (!force_exec) {
998 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
999 "[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl=0x%x, "
1000 "bCurDacSwingOn=%d, curDacSwingLvl=0x%x\n",
1001 coex_dm->pre_dac_swing_on, coex_dm->pre_dac_swing_lvl,
1002 coex_dm->cur_dac_swing_on,
1003 coex_dm->cur_dac_swing_lvl);
1004
1005 if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
1006 (coex_dm->pre_dac_swing_lvl == coex_dm->cur_dac_swing_lvl))
1007 return;
1008 }
1009 mdelay(30);
1010 halbtc8723b1ant_set_sw_full_time_dac_swing(btcoexist, dac_swing_on,
1011 dac_swing_lvl);
1012
1013 coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
1014 coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
1015}
1016
1017void halbtc8723b1ant_set_adc_backoff(struct btc_coexist *btcoexist,
1018 bool adc_backoff)
1019{
1020 if (adc_backoff) {
1021 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1022 "[BTCoex], BB BackOff Level On!\n");
1023 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x3);
1024 } else {
1025 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1026 "[BTCoex], BB BackOff Level Off!\n");
1027 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x8db, 0x60, 0x1);
1028 }
1029}
1030
1031void halbtc8723b1ant_adc_backoff(struct btc_coexist *btcoexist,
1032 bool force_exec, bool adc_backoff)
1033{
1034 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
1035 "[BTCoex], %s turn AdcBackOff = %s\n",
1036 (force_exec ? "force to" : ""), (adc_backoff ? "ON" : "OFF"));
1037 coex_dm->cur_adc_backoff = adc_backoff;
1038
1039 if (!force_exec) {
1040 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1041 "[BTCoex], bPreAdcBackOff=%d, bCurAdcBackOff=%d\n",
1042 coex_dm->pre_adc_backoff, coex_dm->cur_adc_backoff);
1043
1044 if(coex_dm->pre_adc_backoff == coex_dm->cur_adc_backoff)
1045 return;
1046 }
1047 halbtc8723b1ant_set_adc_backoff(btcoexist, coex_dm->cur_adc_backoff);
1048
1049 coex_dm->pre_adc_backoff =
1050 coex_dm->cur_adc_backoff;
1051}
1052
1053void halbtc8723b1ant_set_agc_table(struct btc_coexist *btcoexist,
1054 bool adc_table_en)
1055{
1056 u8 rssi_adjust_val = 0;
1057
1058 btcoexist->btc_set_rf_reg(btcoexist,
1059 BTC_RF_A, 0xef, 0xfffff, 0x02000);
1060 if (adc_table_en) {
1061 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1062 "[BTCoex], Agc Table On!\n");
1063 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b,
1064 0xfffff, 0x3fa58);
1065 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b,
1066 0xfffff, 0x37a58);
1067 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b,
1068 0xfffff, 0x2fa58);
1069 rssi_adjust_val = 8;
1070 } else {
1071 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1072 "[BTCoex], Agc Table Off!\n");
1073 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b,
1074 0xfffff, 0x39258);
1075 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b,
1076 0xfffff, 0x31258);
1077 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b,
1078 0xfffff, 0x29258);
1079 }
1080 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
1081
1082 /* set rssi_adjust_val for wifi module. */
1083 btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
1084 &rssi_adjust_val);
1085}
1086
1087
1088void halbtc8723b1ant_agc_table(struct btc_coexist *btcoexist,
1089 bool force_exec, bool adc_table_en)
1090{
1091 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
1092 "[BTCoex], %s %s Agc Table\n",
1093 (force_exec ? "force to" : ""),
1094 (adc_table_en ? "Enable" : "Disable"));
1095 coex_dm->cur_agc_table_en = adc_table_en;
1096
1097 if (!force_exec) {
1098 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1099 "[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n",
1100 coex_dm->pre_agc_table_en,
1101 coex_dm->cur_agc_table_en);
1102
1103 if(coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
1104 return;
1105 }
1106 halbtc8723b1ant_set_agc_table(btcoexist, adc_table_en);
1107
1108 coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
1109}
1110
1111void halbtc8723b1ant_set_coex_table(struct btc_coexist *btcoexist,
1112 u32 val0x6c0, u32 val0x6c4,
1113 u32 val0x6c8, u8 val0x6cc)
1114{
1115 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1116 "[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0);
1117 btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
1118
1119 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1120 "[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4);
1121 btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
1122
1123 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1124 "[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8);
1125 btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
1126
1127 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1128 "[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc);
1129 btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
1130}
1131
1132void halbtc8723b1ant_coex_table(struct btc_coexist *btcoexist,
1133 bool force_exec, u32 val0x6c0,
1134 u32 val0x6c4, u32 val0x6c8,
1135 u8 val0x6cc)
1136{
1137 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
1138 "[BTCoex], %s write Coex Table 0x6c0=0x%x,"
1139 " 0x6c4=0x%x, 0x6cc=0x%x\n", (force_exec ? "force to" : ""),
1140 val0x6c0, val0x6c4, val0x6cc);
1141 coex_dm->cur_val0x6c0 = val0x6c0;
1142 coex_dm->cur_val0x6c4 = val0x6c4;
1143 coex_dm->cur_val0x6c8 = val0x6c8;
1144 coex_dm->cur_val0x6cc = val0x6cc;
1145
1146 if (!force_exec) {
1147 if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
1148 (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
1149 (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
1150 (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
1151 return;
1152 }
1153 halbtc8723b1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4,
1154 val0x6c8, val0x6cc);
1155
1156 coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
1157 coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
1158 coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
1159 coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
1160}
1161
1162void halbtc8723b1ant_coex_table_with_type(struct btc_coexist *btcoexist,
1163 bool force_exec, u8 type)
1164{
1165 switch (type) {
1166 case 0:
1167 halbtc8723b1ant_coex_table(btcoexist, force_exec, 0x55555555,
1168 0x55555555, 0xffffff, 0x3);
1169 break;
1170 case 1:
1171 halbtc8723b1ant_coex_table(btcoexist, force_exec, 0x55555555,
1172 0x5a5a5a5a, 0xffffff, 0x3);
1173 break;
1174 case 2:
1175 halbtc8723b1ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
1176 0x5a5a5a5a, 0xffffff, 0x3);
1177 break;
1178 case 3:
1179 halbtc8723b1ant_coex_table(btcoexist, force_exec, 0x55555555,
1180 0xaaaaaaaa, 0xffffff, 0x3);
1181 break;
1182 case 4:
1183 halbtc8723b1ant_coex_table(btcoexist, force_exec, 0x55555555,
1184 0x5aaa5aaa, 0xffffff, 0x3);
1185 break;
1186 case 5:
1187 halbtc8723b1ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
1188 0xaaaa5a5a, 0xffffff, 0x3);
1189 break;
1190 case 6:
1191 halbtc8723b1ant_coex_table(btcoexist, force_exec, 0x55555555,
1192 0xaaaa5a5a, 0xffffff, 0x3);
1193 break;
1194 case 7:
1195 halbtc8723b1ant_coex_table(btcoexist, force_exec, 0x5afa5afa,
1196 0x5afa5afa, 0xffffff, 0x3);
1197 break;
1198 default:
1199 break;
1200 }
1201}
1202
1203void halbtc8723b1ant_SetFwIgnoreWlanAct(struct btc_coexist *btcoexist,
1204 bool enable)
1205{
1206 u8 h2c_parameter[1] = {0};
1207
1208 if (enable)
1209 h2c_parameter[0] |= BIT0; /* function enable */
1210
1211 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
1212 "[BTCoex], set FW for BT Ignore Wlan_Act,"
1213 " FW write 0x63=0x%x\n", h2c_parameter[0]);
1214
1215 btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
1216}
1217
1218void halbtc8723b1ant_ignore_wlan_act(struct btc_coexist *btcoexist,
1219 bool force_exec, bool enable)
1220{
1221 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
1222 "[BTCoex], %s turn Ignore WlanAct %s\n",
1223 (force_exec ? "force to" : ""), (enable ? "ON" : "OFF"));
1224 coex_dm->cur_ignore_wlan_act = enable;
1225
1226 if (!force_exec) {
1227 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1228 "[BTCoex], bPreIgnoreWlanAct = %d, "
1229 "bCurIgnoreWlanAct = %d!!\n",
1230 coex_dm->pre_ignore_wlan_act,
1231 coex_dm->cur_ignore_wlan_act);
1232
1233 if (coex_dm->pre_ignore_wlan_act ==
1234 coex_dm->cur_ignore_wlan_act)
1235 return;
1236 }
1237 halbtc8723b1ant_SetFwIgnoreWlanAct(btcoexist, enable);
1238
1239 coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
1240}
1241
1242void halbtc8723b1ant_set_fw_ps_tdma(struct btc_coexist *btcoexist,
1243 u8 byte1, u8 byte2, u8 byte3,
1244 u8 byte4, u8 byte5)
1245{
1246 u8 h2c_parameter[5] = {0};
1247 u8 real_byte1 = byte1, real_byte5 = byte5;
1248 bool ap_enable = false;
1249
1250 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
1251 &ap_enable);
1252
1253 if (ap_enable) {
1254 if ((byte1 & BIT4) && !(byte1 & BIT5)) {
1255 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
1256 "[BTCoex], FW for 1Ant AP mode\n");
1257 real_byte1 &= ~BIT4;
1258 real_byte1 |= BIT5;
1259
1260 real_byte5 |= BIT5;
1261 real_byte5 &= ~BIT6;
1262 }
1263 }
1264
1265 h2c_parameter[0] = real_byte1;
1266 h2c_parameter[1] = byte2;
1267 h2c_parameter[2] = byte3;
1268 h2c_parameter[3] = byte4;
1269 h2c_parameter[4] = real_byte5;
1270
1271 coex_dm->ps_tdma_para[0] = real_byte1;
1272 coex_dm->ps_tdma_para[1] = byte2;
1273 coex_dm->ps_tdma_para[2] = byte3;
1274 coex_dm->ps_tdma_para[3] = byte4;
1275 coex_dm->ps_tdma_para[4] = real_byte5;
1276
1277 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
1278 "[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n",
1279 h2c_parameter[0],
1280 h2c_parameter[1] << 24 |
1281 h2c_parameter[2] << 16 |
1282 h2c_parameter[3] << 8 |
1283 h2c_parameter[4]);
1284
1285 btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
1286}
1287
1288void halbtc8723b1ant_SetLpsRpwm(struct btc_coexist *btcoexist,
1289 u8 lps_val, u8 rpwm_val)
1290{
1291 u8 lps = lps_val;
1292 u8 rpwm = rpwm_val;
1293
1294 btcoexist->btc_set(btcoexist, BTC_SET_U1_1ANT_LPS, &lps);
1295 btcoexist->btc_set(btcoexist, BTC_SET_U1_1ANT_RPWM, &rpwm);
1296}
1297
1298void halbtc8723b1ant_LpsRpwm(struct btc_coexist *btcoexist, bool force_exec,
1299 u8 lps_val, u8 rpwm_val)
1300{
1301
1302 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
1303 "[BTCoex], %s set lps/rpwm=0x%x/0x%x \n",
1304 (force_exec ? "force to" : ""), lps_val, rpwm_val);
1305 coex_dm->cur_lps = lps_val;
1306 coex_dm->cur_rpwm = rpwm_val;
1307
1308 if (!force_exec) {
1309 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1310 "[BTCoex], LPS-RxBeaconMode=0x%x , LPS-RPWM=0x%x!!\n",
1311 coex_dm->cur_lps, coex_dm->cur_rpwm);
1312
1313 if ((coex_dm->pre_lps == coex_dm->cur_lps) &&
1314 (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) {
1315 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1316 "[BTCoex], LPS-RPWM_Last=0x%x"
1317 " , LPS-RPWM_Now=0x%x!!\n",
1318 coex_dm->pre_rpwm, coex_dm->cur_rpwm);
1319
1320 return;
1321 }
1322 }
1323 halbtc8723b1ant_SetLpsRpwm(btcoexist, lps_val, rpwm_val);
1324
1325 coex_dm->pre_lps = coex_dm->cur_lps;
1326 coex_dm->pre_rpwm = coex_dm->cur_rpwm;
1327}
1328
1329void halbtc8723b1ant_sw_mechanism1(struct btc_coexist *btcoexist,
1330 bool shrink_rx_lpf, bool low_penalty_ra,
1331 bool limited_dig, bool bt_lna_constrain)
1332{
1333 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
1334 "[BTCoex], SM1[ShRf/ LpRA/ LimDig/ btLna] = %d %d %d %d\n",
1335 shrink_rx_lpf, low_penalty_ra, limited_dig, bt_lna_constrain);
1336
1337 halbtc8723b1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
1338}
1339
1340void halbtc8723b1ant_sw_mechanism2(struct btc_coexist *btcoexist,
1341 bool agc_table_shift, bool adc_backoff,
1342 bool sw_dac_swing, u32 dac_swing_lvl)
1343{
1344 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
1345 "[BTCoex], SM2[AgcT/ AdcB/ SwDacSwing(lvl)] = %d %d %d\n",
1346 agc_table_shift, adc_backoff, sw_dac_swing);
1347}
1348
1349void halbtc8723b1ant_SetAntPath(struct btc_coexist *btcoexist,
1350 u8 ant_pos_type, bool init_hw_cfg,
1351 bool wifi_off)
1352{
1353 struct btc_board_info *board_info = &btcoexist->board_info;
1354 u32 fw_ver = 0, u32tmp = 0;
1355 bool pg_ext_switch = false;
1356 bool use_ext_switch = false;
1357 u8 h2c_parameter[2] = {0};
1358
1359 btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch);
1360 /* [31:16]=fw ver, [15:0]=fw sub ver */
1361 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
1362
1363
1364 if ((fw_ver < 0xc0000) || pg_ext_switch)
1365 use_ext_switch = true;
1366
1367 if (init_hw_cfg){
1368 /*BT select s0/s1 is controlled by WiFi */
1369 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1);
1370
1371 /*Force GNT_BT to Normal */
1372 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x0);
1373 } else if (wifi_off) {
1374 /*Force GNT_BT to High */
1375 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3);
1376 /*BT select s0/s1 is controlled by BT */
1377 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x0);
1378
1379 /* 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL
1380 * BT Vendor 0xac=0xf002 */
1381 u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
1382 u32tmp &= ~BIT23;
1383 u32tmp &= ~BIT24;
1384 btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
1385 }
1386
1387 if (use_ext_switch) {
1388 if (init_hw_cfg) {
1389 /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */
1390 u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
1391 u32tmp &= ~BIT23;
1392 u32tmp |= BIT24;
1393 btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
1394
1395 if (board_info->btdm_ant_pos ==
1396 BTC_ANTENNA_AT_MAIN_PORT) {
1397 /* Main Ant to BT for IPS case 0x4c[23]=1 */
1398 btcoexist->btc_write_1byte_bitmask(btcoexist,
1399 0x64, 0x1,
1400 0x1);
1401
1402 /*tell firmware "no antenna inverse"*/
1403 h2c_parameter[0] = 0;
1404 h2c_parameter[1] = 1; /*ext switch type*/
1405 btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
1406 h2c_parameter);
1407 } else {
1408 /*Aux Ant to BT for IPS case 0x4c[23]=1 */
1409 btcoexist->btc_write_1byte_bitmask(btcoexist,
1410 0x64, 0x1,
1411 0x0);
1412
1413 /*tell firmware "antenna inverse"*/
1414 h2c_parameter[0] = 1;
1415 h2c_parameter[1] = 1; /*ext switch type*/
1416 btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
1417 h2c_parameter);
1418 }
1419 }
1420
1421 /* fixed internal switch first*/
1422 /* fixed internal switch S1->WiFi, S0->BT*/
1423 if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT)
1424 btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0);
1425 else/* fixed internal switch S0->WiFi, S1->BT*/
1426 btcoexist->btc_write_2byte(btcoexist, 0x948, 0x280);
1427
1428 /* ext switch setting */
1429 switch (ant_pos_type) {
1430 case BTC_ANT_PATH_WIFI:
1431 if (board_info->btdm_ant_pos ==
1432 BTC_ANTENNA_AT_MAIN_PORT)
1433 btcoexist->btc_write_1byte_bitmask(btcoexist,
1434 0x92c, 0x3,
1435 0x1);
1436 else
1437 btcoexist->btc_write_1byte_bitmask(btcoexist,
1438 0x92c, 0x3,
1439 0x2);
1440 break;
1441 case BTC_ANT_PATH_BT:
1442 if (board_info->btdm_ant_pos ==
1443 BTC_ANTENNA_AT_MAIN_PORT)
1444 btcoexist->btc_write_1byte_bitmask(btcoexist,
1445 0x92c, 0x3,
1446 0x2);
1447 else
1448 btcoexist->btc_write_1byte_bitmask(btcoexist,
1449 0x92c, 0x3,
1450 0x1);
1451 break;
1452 default:
1453 case BTC_ANT_PATH_PTA:
1454 if (board_info->btdm_ant_pos ==
1455 BTC_ANTENNA_AT_MAIN_PORT)
1456 btcoexist->btc_write_1byte_bitmask(btcoexist,
1457 0x92c, 0x3,
1458 0x1);
1459 else
1460 btcoexist->btc_write_1byte_bitmask(btcoexist,
1461 0x92c, 0x3,
1462 0x2);
1463 break;
1464 }
1465
1466 } else {
1467 if (init_hw_cfg) {
1468 /* 0x4c[23]=1, 0x4c[24]=0 Antenna control by 0x64*/
1469 u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
1470 u32tmp |= BIT23;
1471 u32tmp &= ~BIT24;
1472 btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
1473
1474 if (board_info->btdm_ant_pos ==
1475 BTC_ANTENNA_AT_MAIN_PORT) {
1476 /*Main Ant to WiFi for IPS case 0x4c[23]=1*/
1477 btcoexist->btc_write_1byte_bitmask(btcoexist,
1478 0x64, 0x1,
1479 0x0);
1480
1481 /*tell firmware "no antenna inverse"*/
1482 h2c_parameter[0] = 0;
1483 h2c_parameter[1] = 0; /*internal switch type*/
1484 btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
1485 h2c_parameter);
1486 } else {
1487 /*Aux Ant to BT for IPS case 0x4c[23]=1*/
1488 btcoexist->btc_write_1byte_bitmask(btcoexist,
1489 0x64, 0x1,
1490 0x1);
1491
1492 /*tell firmware "antenna inverse"*/
1493 h2c_parameter[0] = 1;
1494 h2c_parameter[1] = 0; /*internal switch type*/
1495 btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
1496 h2c_parameter);
1497 }
1498 }
1499
1500 /* fixed external switch first*/
1501 /*Main->WiFi, Aux->BT*/
1502 if(board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT)
1503 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x92c,
1504 0x3, 0x1);
1505 else/*Main->BT, Aux->WiFi */
1506 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x92c,
1507 0x3, 0x2);
1508
1509 /* internal switch setting*/
1510 switch (ant_pos_type) {
1511 case BTC_ANT_PATH_WIFI:
1512 if(board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT)
1513 btcoexist->btc_write_2byte(btcoexist, 0x948,
1514 0x0);
1515 else
1516 btcoexist->btc_write_2byte(btcoexist, 0x948,
1517 0x280);
1518 break;
1519 case BTC_ANT_PATH_BT:
1520 if(board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT)
1521 btcoexist->btc_write_2byte(btcoexist, 0x948,
1522 0x280);
1523 else
1524 btcoexist->btc_write_2byte(btcoexist, 0x948,
1525 0x0);
1526 break;
1527 default:
1528 case BTC_ANT_PATH_PTA:
1529 if(board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT)
1530 btcoexist->btc_write_2byte(btcoexist, 0x948,
1531 0x200);
1532 else
1533 btcoexist->btc_write_2byte(btcoexist, 0x948,
1534 0x80);
1535 break;
1536 }
1537 }
1538}
1539
1540void halbtc8723b1ant_ps_tdma(struct btc_coexist *btcoexist, bool force_exec,
1541 bool turn_on, u8 type)
1542{
1543 bool wifi_busy = false;
1544 u8 rssi_adjust_val = 0;
1545
1546 coex_dm->cur_ps_tdma_on = turn_on;
1547 coex_dm->cur_ps_tdma = type;
1548
1549 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
1550
1551 if (!force_exec) {
1552 if (coex_dm->cur_ps_tdma_on)
1553 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1554 "[BTCoex], ******** TDMA(on, %d) *********\n",
1555 coex_dm->cur_ps_tdma);
1556 else
1557 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1558 "[BTCoex], ******** TDMA(off, %d) ********\n",
1559 coex_dm->cur_ps_tdma);
1560
1561
1562 if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
1563 (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
1564 return;
1565 }
1566 if (turn_on) {
1567 switch (type) {
1568 default:
1569 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51, 0x1a,
1570 0x1a, 0x0, 0x50);
1571 break;
1572 case 1:
1573 if (wifi_busy)
1574 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51,
1575 0x3a, 0x03,
1576 0x10, 0x50);
1577 else
1578 halbtc8723b1ant_set_fw_ps_tdma(btcoexist,0x51,
1579 0x3a, 0x03,
1580 0x10, 0x51);
1581
1582 rssi_adjust_val = 11;
1583 break;
1584 case 2:
1585 if (wifi_busy)
1586 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51,
1587 0x2b, 0x03,
1588 0x10, 0x50);
1589 else
1590 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51,
1591 0x2b, 0x03,
1592 0x10, 0x51);
1593 rssi_adjust_val = 14;
1594 break;
1595 case 3:
1596 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51, 0x1d,
1597 0x1d, 0x0, 0x52);
1598 break;
1599 case 4:
1600 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x93, 0x15,
1601 0x3, 0x14, 0x0);
1602 rssi_adjust_val = 17;
1603 break;
1604 case 5:
1605 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x61, 0x15,
1606 0x3, 0x11, 0x10);
1607 break;
1608 case 6:
1609 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x61, 0x20,
1610 0x3, 0x11, 0x13);
1611 break;
1612 case 7:
1613 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x13, 0xc,
1614 0x5, 0x0, 0x0);
1615 break;
1616 case 8:
1617 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x93, 0x25,
1618 0x3, 0x10, 0x0);
1619 break;
1620 case 9:
1621 if(wifi_busy)
1622 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51,
1623 0x21, 0x3,
1624 0x10, 0x50);
1625 else
1626 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51,
1627 0x21, 0x3,
1628 0x10, 0x50);
1629 rssi_adjust_val = 18;
1630 break;
1631 case 10:
1632 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x13, 0xa,
1633 0xa, 0x0, 0x40);
1634 break;
1635 case 11:
1636 if (wifi_busy)
1637 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51,
1638 0x15, 0x03,
1639 0x10, 0x50);
1640 else
1641 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51,
1642 0x15, 0x03,
1643 0x10, 0x50);
1644 rssi_adjust_val = 20;
1645 break;
1646 case 12:
1647 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51, 0x0a,
1648 0x0a, 0x0, 0x50);
1649 break;
1650 case 13:
1651 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51, 0x15,
1652 0x15, 0x0, 0x50);
1653 break;
1654 case 14:
1655 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51, 0x21,
1656 0x3, 0x10, 0x52);
1657 break;
1658 case 15:
1659 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x13, 0xa,
1660 0x3, 0x8, 0x0);
1661 break;
1662 case 16:
1663 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x93, 0x15,
1664 0x3, 0x10, 0x0);
1665 rssi_adjust_val = 18;
1666 break;
1667 case 18:
1668 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x93, 0x25,
1669 0x3, 0x10, 0x0);
1670 rssi_adjust_val = 14;
1671 break;
1672 case 20:
1673 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x61, 0x35,
1674 0x03, 0x11, 0x10);
1675 break;
1676 case 21:
1677 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x61, 0x15,
1678 0x03, 0x11, 0x10);
1679 break;
1680 case 22:
1681 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x61, 0x25,
1682 0x03, 0x11, 0x10);
1683 break;
1684 case 23:
1685 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x25,
1686 0x3, 0x31, 0x18);
1687 rssi_adjust_val = 22;
1688 break;
1689 case 24:
1690 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x15,
1691 0x3, 0x31, 0x18);
1692 rssi_adjust_val = 22;
1693 break;
1694 case 25:
1695 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0xe3, 0xa,
1696 0x3, 0x31, 0x18);
1697 rssi_adjust_val = 22;
1698 break;
1699 case 26:
1700 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0xe3, 0xa,
1701 0x3, 0x31, 0x18);
1702 rssi_adjust_val = 22;
1703 break;
1704 case 27:
1705 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x25,
1706 0x3, 0x31, 0x98);
1707 rssi_adjust_val = 22;
1708 break;
1709 case 28:
1710 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x69, 0x25,
1711 0x3, 0x31, 0x0);
1712 break;
1713 case 29:
1714 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0xab, 0x1a,
1715 0x1a, 0x1, 0x10);
1716 break;
1717 case 30:
1718 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x51, 0x14,
1719 0x3, 0x10, 0x50);
1720 break;
1721 case 31:
1722 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0xd3, 0x1a,
1723 0x1a, 0, 0x58);
1724 break;
1725 case 32:
1726 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x61, 0xa,
1727 0x3, 0x10, 0x0);
1728 break;
1729 case 33:
1730 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0xa3, 0x25,
1731 0x3, 0x30, 0x90);
1732 break;
1733 case 34:
1734 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x53, 0x1a,
1735 0x1a, 0x0, 0x10);
1736 break;
1737 case 35:
1738 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x63, 0x1a,
1739 0x1a, 0x0, 0x10);
1740 break;
1741 case 36:
1742 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0xd3, 0x12,
1743 0x3, 0x14, 0x50);
1744 break;
1745 /* SoftAP only with no sta associated,BT disable ,
1746 * TDMA mode for power saving
1747 * here softap mode screen off will cost 70-80mA for phone */
1748 case 40:
1749 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x23, 0x18,
1750 0x00, 0x10, 0x24);
1751 break;
1752 }
1753 } else {
1754 switch (type) {
1755 case 8: /*PTA Control */
1756 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x8, 0x0,
1757 0x0, 0x0, 0x0);
1758 halbtc8723b1ant_SetAntPath(btcoexist, BTC_ANT_PATH_PTA,
1759 false, false);
1760 break;
1761 case 0:
1762 default: /*Software control, Antenna at BT side */
1763 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x0, 0x0,
1764 0x0, 0x0, 0x0);
1765 halbtc8723b1ant_SetAntPath(btcoexist, BTC_ANT_PATH_BT,
1766 false, false);
1767 break;
1768 case 9: /*Software control, Antenna at WiFi side */
1769 halbtc8723b1ant_set_fw_ps_tdma(btcoexist, 0x0, 0x0,
1770 0x0, 0x0, 0x0);
1771 halbtc8723b1ant_SetAntPath(btcoexist, BTC_ANT_PATH_WIFI,
1772 false, false);
1773 break;
1774 }
1775 }
1776 rssi_adjust_val = 0;
1777 btcoexist->btc_set(btcoexist,
1778 BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
1779 &rssi_adjust_val);
1780
1781 /* update pre state */
1782 coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
1783 coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
1784}
1785
1786void halbtc8723b1ant_coex_alloff(struct btc_coexist *btcoexist)
1787{
1788 /* fw all off */
1789 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
1790 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
1791
1792 /* sw all off */
1793 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false, false, false);
1794 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
1795
1796
1797 /* hw all off */
1798 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
1799}
1800
1801bool halbtc8723b1ant_is_common_action(struct btc_coexist *btcoexist)
1802{
1803 bool commom = false, wifi_connected = false;
1804 bool wifi_busy = false;
1805
1806 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
1807 &wifi_connected);
1808 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
1809
1810 if (!wifi_connected &&
1811 BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status) {
1812 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1813 "[BTCoex], Wifi non connected-idle + "
1814 "BT non connected-idle!!\n");
1815 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
1816 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
1817
1818 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
1819 false, false);
1820 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
1821 false, 0x18);
1822
1823 commom = true;
1824 } else if (wifi_connected &&
1825 (BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE ==
1826 coex_dm->bt_status)) {
1827 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1828 "[BTCoex], Wifi connected + "
1829 "BT non connected-idle!!\n");
1830 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
1831 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
1832
1833 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
1834 false, false);
1835 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
1836 false, 0x18);
1837
1838 commom = true;
1839 } else if (!wifi_connected &&
1840 (BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE ==
1841 coex_dm->bt_status)) {
1842 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1843 "[BTCoex], Wifi non connected-idle + "
1844 "BT connected-idle!!\n");
1845 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
1846 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
1847
1848 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
1849 false, false);
1850 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
1851 false, 0x18);
1852
1853 commom = true;
1854 } else if (wifi_connected &&
1855 (BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE ==
1856 coex_dm->bt_status)) {
1857 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1858 "[BTCoex], Wifi connected + BT connected-idle!!\n");
1859 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
1860 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
1861
1862 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
1863 false, false);
1864 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
1865 false, 0x18);
1866
1867 commom = true;
1868 } else if (!wifi_connected &&
1869 (BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE !=
1870 coex_dm->bt_status)) {
1871 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1872 ("[BTCoex], Wifi non connected-idle + BT Busy!!\n"));
1873 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
1874 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
1875
1876 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
1877 false, false);
1878 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
1879 false, 0x18);
1880
1881 commom = true;
1882 } else {
1883 if (wifi_busy)
1884 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1885 "[BTCoex], Wifi Connected-Busy"
1886 " + BT Busy!!\n");
1887 else
1888 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1889 "[BTCoex], Wifi Connected-Idle"
1890 " + BT Busy!!\n");
1891
1892 commom = false;
1893 }
1894
1895 return commom;
1896}
1897
1898
1899void halbtc8723b1ant_tdma_duration_adjust_for_acl(struct btc_coexist *btcoexist,
1900 u8 wifi_status)
1901{
1902 static s32 up, dn, m, n, wait_count;
1903 /* 0: no change, +1: increase WiFi duration,
1904 * -1: decrease WiFi duration */
1905 s32 result;
1906 u8 retry_count = 0, bt_info_ext;
1907 static bool pre_wifi_busy = false;
1908 bool wifi_busy = false;
1909
1910 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
1911 "[BTCoex], TdmaDurationAdjustForAcl()\n");
1912
1913 if (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifi_status)
1914 wifi_busy = true;
1915 else
1916 wifi_busy = false;
1917
1918 if ((BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN ==
1919 wifi_status) ||
1920 (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifi_status) ||
1921 (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == wifi_status)) {
1922 if (coex_dm->cur_ps_tdma != 1 && coex_dm->cur_ps_tdma != 2 &&
1923 coex_dm->cur_ps_tdma != 3 && coex_dm->cur_ps_tdma != 9) {
1924 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
1925 true, 9);
1926 coex_dm->ps_tdma_du_adj_type = 9;
1927
1928 up = 0;
1929 dn = 0;
1930 m = 1;
1931 n = 3;
1932 result = 0;
1933 wait_count = 0;
1934 }
1935 return;
1936 }
1937
1938 if (!coex_dm->auto_tdma_adjust) {
1939 coex_dm->auto_tdma_adjust = true;
1940 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1941 "[BTCoex], first run TdmaDurationAdjust()!!\n");
1942
1943 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 2);
1944 coex_dm->ps_tdma_du_adj_type = 2;
1945
1946 up = 0;
1947 dn = 0;
1948 m = 1;
1949 n = 3;
1950 result = 0;
1951 wait_count = 0;
1952 } else {
1953 /*accquire the BT TRx retry count from BT_Info byte2 */
1954 retry_count = coex_sta->bt_retry_cnt;
1955 bt_info_ext = coex_sta->bt_info_ext;
1956 result = 0;
1957 wait_count++;
1958 /* no retry in the last 2-second duration */
1959 if (retry_count == 0) {
1960 up++;
1961 dn--;
1962
1963 if (dn <= 0)
1964 dn = 0;
1965
1966 if (up >= n) {
1967 wait_count = 0;
1968 n = 3;
1969 up = 0;
1970 dn = 0;
1971 result = 1;
1972 BTC_PRINT(BTC_MSG_ALGORITHM,
1973 ALGO_TRACE_FW_DETAIL,
1974 "[BTCoex], Increase wifi "
1975 "duration!!\n");
1976 }
1977 } else if (retry_count <= 3) {
1978 up--;
1979 dn++;
1980
1981 if (up <= 0)
1982 up = 0;
1983
1984 if (dn == 2) {
1985 if (wait_count <= 2)
1986 m++;
1987 else
1988 m = 1;
1989
1990 if (m >= 20)
1991 m = 20;
1992
1993 n = 3 * m;
1994 up = 0;
1995 dn = 0;
1996 wait_count = 0;
1997 result = -1;
1998 BTC_PRINT(BTC_MSG_ALGORITHM,
1999 ALGO_TRACE_FW_DETAIL,
2000 "[BTCoex], Decrease wifi duration"
2001 " for retryCounter<3!!\n");
2002 }
2003 } else {
2004 if (wait_count == 1)
2005 m++;
2006 else
2007 m = 1;
2008
2009 if (m >= 20)
2010 m = 20;
2011
2012 n = 3 * m;
2013 up = 0;
2014 dn = 0;
2015 wait_count = 0;
2016 result = -1;
2017 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
2018 "[BTCoex], Decrease wifi duration"
2019 " for retryCounter>3!!\n");
2020 }
2021
2022 if (result == -1) {
2023 if ((BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
2024 ((coex_dm->cur_ps_tdma == 1) ||
2025 (coex_dm->cur_ps_tdma == 2))) {
2026 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2027 true, 9);
2028 coex_dm->ps_tdma_du_adj_type = 9;
2029 } else if (coex_dm->cur_ps_tdma == 1) {
2030 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2031 true, 2);
2032 coex_dm->ps_tdma_du_adj_type = 2;
2033 } else if (coex_dm->cur_ps_tdma == 2) {
2034 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2035 true, 9);
2036 coex_dm->ps_tdma_du_adj_type = 9;
2037 } else if (coex_dm->cur_ps_tdma == 9) {
2038 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2039 true, 11);
2040 coex_dm->ps_tdma_du_adj_type = 11;
2041 }
2042 } else if(result == 1) {
2043 if ((BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(bt_info_ext)) &&
2044 ((coex_dm->cur_ps_tdma == 1) ||
2045 (coex_dm->cur_ps_tdma == 2))) {
2046 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2047 true, 9);
2048 coex_dm->ps_tdma_du_adj_type = 9;
2049 } else if (coex_dm->cur_ps_tdma == 11) {
2050 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2051 true, 9);
2052 coex_dm->ps_tdma_du_adj_type = 9;
2053 } else if (coex_dm->cur_ps_tdma == 9) {
2054 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2055 true, 2);
2056 coex_dm->ps_tdma_du_adj_type = 2;
2057 } else if (coex_dm->cur_ps_tdma == 2) {
2058 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2059 true, 1);
2060 coex_dm->ps_tdma_du_adj_type = 1;
2061 }
2062 } else { /*no change */
2063 /*if busy / idle change */
2064 if (wifi_busy != pre_wifi_busy) {
2065 pre_wifi_busy = wifi_busy;
2066 halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC,
2067 true,
2068 coex_dm->cur_ps_tdma);
2069 }
2070
2071 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
2072 "[BTCoex],********* TDMA(on, %d) ********\n",
2073 coex_dm->cur_ps_tdma);
2074 }
2075
2076 if (coex_dm->cur_ps_tdma != 1 && coex_dm->cur_ps_tdma != 2 &&
2077 coex_dm->cur_ps_tdma != 9 && coex_dm->cur_ps_tdma != 11) {
2078 /* recover to previous adjust type */
2079 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
2080 coex_dm->ps_tdma_du_adj_type);
2081 }
2082 }
2083}
2084
2085u8 halbtc8723b1ant_ps_tdma_type_by_wifi_rssi(s32 wifi_rssi, s32 pre_wifi_rssi,
2086 u8 wifi_rssi_thresh)
2087{
2088 u8 ps_tdma_type=0;
2089
2090 if (wifi_rssi > pre_wifi_rssi) {
2091 if (wifi_rssi > (wifi_rssi_thresh + 5))
2092 ps_tdma_type = 26;
2093 else
2094 ps_tdma_type = 25;
2095 } else {
2096 if (wifi_rssi > wifi_rssi_thresh)
2097 ps_tdma_type = 26;
2098 else
2099 ps_tdma_type = 25;
2100 }
2101
2102 return ps_tdma_type;
2103}
2104
2105void halbtc8723b1ant_PsTdmaCheckForPowerSaveState(struct btc_coexist *btcoexist,
2106 bool new_ps_state)
2107{
2108 u8 lps_mode = 0x0;
2109
2110 btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode);
2111
2112 if (lps_mode) { /* already under LPS state */
2113 if (new_ps_state) {
2114 /* keep state under LPS, do nothing. */
2115 } else {
2116 /* will leave LPS state, turn off psTdma first */
2117 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2118 false, 0);
2119 }
2120 } else { /* NO PS state */
2121 if (new_ps_state) {
2122 /* will enter LPS state, turn off psTdma first */
2123 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2124 false, 0);
2125 } else {
2126 /* keep state under NO PS state, do nothing. */
2127 }
2128 }
2129}
2130
2131void halbtc8723b1ant_power_save_state(struct btc_coexist *btcoexist,
2132 u8 ps_type, u8 lps_val,
2133 u8 rpwm_val)
2134{
2135 bool low_pwr_disable = false;
2136
2137 switch (ps_type) {
2138 case BTC_PS_WIFI_NATIVE:
2139 /* recover to original 32k low power setting */
2140 low_pwr_disable = false;
2141 btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
2142 &low_pwr_disable);
2143 btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, NULL);
2144 break;
2145 case BTC_PS_LPS_ON:
2146 halbtc8723b1ant_PsTdmaCheckForPowerSaveState(btcoexist, true);
2147 halbtc8723b1ant_LpsRpwm(btcoexist, NORMAL_EXEC, lps_val,
2148 rpwm_val);
2149 /* when coex force to enter LPS, do not enter 32k low power. */
2150 low_pwr_disable = true;
2151 btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
2152 &low_pwr_disable);
2153 /* power save must executed before psTdma. */
2154 btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, NULL);
2155 break;
2156 case BTC_PS_LPS_OFF:
2157 halbtc8723b1ant_PsTdmaCheckForPowerSaveState(btcoexist, false);
2158 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, NULL);
2159 break;
2160 default:
2161 break;
2162 }
2163}
2164
2165void halbtc8723b1ant_action_wifi_only(struct btc_coexist *btcoexist)
2166{
2167 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
2168 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9);
2169}
2170
2171void halbtc8723b1ant_monitor_bt_enable_disable(struct btc_coexist *btcoexist)
2172{
2173 static bool pre_bt_disabled = false;
2174 static u32 bt_disable_cnt = 0;
2175 bool bt_active = true, bt_disabled = false;
2176
2177 /* This function check if bt is disabled */
2178
2179 if (coex_sta->high_priority_tx == 0 &&
2180 coex_sta->high_priority_rx == 0 &&
2181 coex_sta->low_priority_tx == 0 &&
2182 coex_sta->low_priority_rx == 0)
2183 bt_active = false;
2184
2185 if (coex_sta->high_priority_tx == 0xffff &&
2186 coex_sta->high_priority_rx == 0xffff &&
2187 coex_sta->low_priority_tx == 0xffff &&
2188 coex_sta->low_priority_rx == 0xffff)
2189 bt_active = false;
2190
2191 if (bt_active) {
2192 bt_disable_cnt = 0;
2193 bt_disabled = false;
2194 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
2195 &bt_disabled);
2196 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
2197 "[BTCoex], BT is enabled !!\n");
2198 } else {
2199 bt_disable_cnt++;
2200 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
2201 "[BTCoex], bt all counters=0, %d times!!\n",
2202 bt_disable_cnt);
2203 if (bt_disable_cnt >= 2) {
2204 bt_disabled = true;
2205 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
2206 &bt_disabled);
2207 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
2208 "[BTCoex], BT is disabled !!\n");
2209 halbtc8723b1ant_action_wifi_only(btcoexist);
2210 }
2211 }
2212 if (pre_bt_disabled != bt_disabled) {
2213 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
2214 "[BTCoex], BT is from %s to %s!!\n",
2215 (pre_bt_disabled ? "disabled" : "enabled"),
2216 (bt_disabled ? "disabled" : "enabled"));
2217 pre_bt_disabled = bt_disabled;
2218 if (!bt_disabled) {
2219 } else {
2220 btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS,
2221 NULL);
2222 btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS,
2223 NULL);
2224 }
2225 }
2226}
2227
2228/***************************************************
2229 *
2230 * Software Coex Mechanism start
2231 *
2232 ***************************************************/
2233/* SCO only or SCO+PAN(HS) */
2234void halbtc8723b1ant_action_sco(struct btc_coexist *btcoexist)
2235{
2236 u8 wifi_rssi_state;
2237 u32 wifi_bw;
2238
2239 wifi_rssi_state =
2240 halbtc8723b1ant_wifi_rssi_state(btcoexist, 0, 2, 25, 0);
2241
2242 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4);
2243
2244 if (halbtc8723b1ant_need_to_dec_bt_pwr(btcoexist))
2245 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2246 else
2247 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2248
2249 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2250
2251 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2252 /* sw mechanism */
2253 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2254 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2255 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2256 false, false);
2257 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2258 false, 0x18);
2259 } else {
2260 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2261 false, false);
2262 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2263 false, 0x18);
2264 }
2265 } else {
2266 /* sw mechanism */
2267 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2268 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2269 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2270 false, false);
2271 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2272 false, 0x18);
2273 } else {
2274 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2275 false, false);
2276 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2277 false, 0x18);
2278 }
2279 }
2280}
2281
2282
2283void halbtc8723b1ant_action_hid(struct btc_coexist *btcoexist)
2284{
2285 u8 wifi_rssi_state, bt_rssi_state;
2286 u32 wifi_bw;
2287
2288 wifi_rssi_state = halbtc8723b1ant_wifi_rssi_state(btcoexist,
2289 0, 2, 25, 0);
2290 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 50, 0);
2291
2292 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2293
2294 if (halbtc8723b1ant_need_to_dec_bt_pwr(btcoexist))
2295 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2296 else
2297 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2298
2299 btcoexist->btc_get(btcoexist,
2300 BTC_GET_U4_WIFI_BW, &wifi_bw);
2301
2302 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2303 /* sw mechanism */
2304 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2305 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2306 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2307 false, false);
2308 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2309 false, 0x18);
2310 } else {
2311 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2312 false, false);
2313 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2314 false, 0x18);
2315 }
2316 } else {
2317 /* sw mechanism */
2318 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2319 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2320 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2321 false, false);
2322 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2323 false, 0x18);
2324 } else {
2325 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2326 false, false);
2327 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2328 false, 0x18);
2329 }
2330 }
2331}
2332
2333/*A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
2334void halbtc8723b1ant_action_a2dp(struct btc_coexist *btcoexist)
2335{
2336 u8 wifi_rssi_state, bt_rssi_state;
2337 u32 wifi_bw;
2338
2339 wifi_rssi_state = halbtc8723b1ant_wifi_rssi_state(btcoexist,
2340 0, 2, 25, 0);
2341 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 50, 0);
2342
2343 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2344
2345 if (halbtc8723b1ant_need_to_dec_bt_pwr(btcoexist))
2346 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2347 else
2348 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2349
2350 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2351
2352 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2353 /* sw mechanism */
2354 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2355 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2356 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2357 false, false);
2358 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2359 false, 0x18);
2360 } else {
2361 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2362 false, false);
2363 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2364 false, 0x18);
2365 }
2366 } else {
2367 /* sw mechanism */
2368 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2369 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2370 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2371 false, false);
2372 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2373 false, 0x18);
2374 } else {
2375 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2376 false, false);
2377 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2378 false, 0x18);
2379 }
2380 }
2381}
2382
2383void halbtc8723b1ant_action_a2dp_pan_hs(struct btc_coexist *btcoexist)
2384{
2385 u8 wifi_rssi_state, bt_rssi_state, bt_info_ext;
2386 u32 wifi_bw;
2387
2388 bt_info_ext = coex_sta->bt_info_ext;
2389 wifi_rssi_state = halbtc8723b1ant_wifi_rssi_state(btcoexist,
2390 0, 2, 25, 0);
2391 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 50, 0);
2392
2393 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2394
2395 if (halbtc8723b1ant_need_to_dec_bt_pwr(btcoexist))
2396 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2397 else
2398 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2399
2400 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2401
2402 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2403 /* sw mechanism */
2404 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2405 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2406 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2407 false, false);
2408 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2409 false, 0x18);
2410 } else {
2411 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2412 false, false);
2413 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2414 false, 0x18);
2415 }
2416 } else {
2417 /* sw mechanism */
2418 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2419 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2420 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2421 false, false);
2422 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2423 false, 0x18);
2424 } else {
2425 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2426 false, false);
2427 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2428 false, 0x18);
2429 }
2430 }
2431}
2432
2433void halbtc8723b1ant_action_pan_edr(struct btc_coexist *btcoexist)
2434{
2435 u8 wifi_rssi_state, bt_rssi_state;
2436 u32 wifi_bw;
2437
2438 wifi_rssi_state = halbtc8723b1ant_wifi_rssi_state(btcoexist,
2439 0, 2, 25, 0);
2440 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 50, 0);
2441
2442 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2443
2444 if (halbtc8723b1ant_need_to_dec_bt_pwr(btcoexist))
2445 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2446 else
2447 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2448
2449 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2450
2451 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2452 /* sw mechanism */
2453 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2454 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2455 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2456 false, false);
2457 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2458 false, 0x18);
2459 } else {
2460 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2461 false, false);
2462 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2463 false, 0x18);
2464 }
2465 } else {
2466 /* sw mechanism */
2467 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2468 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2469 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2470 false, false);
2471 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2472 false, 0x18);
2473 } else {
2474 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2475 false, false);
2476 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2477 false, 0x18);
2478 }
2479 }
2480}
2481
2482
2483/* PAN(HS) only */
2484void halbtc8723b1ant_action_pan_hs(struct btc_coexist *btcoexist)
2485{
2486 u8 wifi_rssi_state, bt_rssi_state;
2487 u32 wifi_bw;
2488
2489 wifi_rssi_state = halbtc8723b1ant_wifi_rssi_state(btcoexist,
2490 0, 2, 25, 0);
2491 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 50, 0);
2492
2493 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2494
2495 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2496
2497 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2498 /* fw mechanism */
2499 if((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2500 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
2501 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC,
2502 false);
2503 else
2504 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC,
2505 false);
2506
2507 /* sw mechanism */
2508 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2509 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2510 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2511 false, false);
2512 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2513 false, 0x18);
2514 } else {
2515 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2516 false, false);
2517 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2518 false, 0x18);
2519 }
2520 } else {
2521 /* fw mechanism */
2522 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2523 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
2524 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC,
2525 false);
2526 else
2527 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC,
2528 false);
2529
2530 /* sw mechanism */
2531 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2532 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2533 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2534 false, false);
2535 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2536 false, 0x18);
2537 } else {
2538 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2539 false, false);
2540 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2541 false, 0x18);
2542 }
2543 }
2544}
2545
2546/*PAN(EDR)+A2DP */
2547void halbtc8723b1ant_action_pan_edr_a2dp(struct btc_coexist *btcoexist)
2548{
2549 u8 wifi_rssi_state, bt_rssi_state, bt_info_ext;
2550 u32 wifi_bw;
2551
2552 bt_info_ext = coex_sta->bt_info_ext;
2553 wifi_rssi_state = halbtc8723b1ant_wifi_rssi_state(btcoexist,
2554 0, 2, 25, 0);
2555 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 50, 0);
2556
2557 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2558
2559 if (halbtc8723b1ant_need_to_dec_bt_pwr(btcoexist))
2560 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2561 else
2562 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2563
2564 btcoexist->btc_get(btcoexist,
2565 BTC_GET_U4_WIFI_BW, &wifi_bw);
2566
2567 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2568 /* sw mechanism */
2569 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2570 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2571 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2572 false, false);
2573 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2574 false, 0x18);
2575 } else {
2576 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2577 false, false);
2578 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2579 false, 0x18);
2580 }
2581 } else {
2582 /* sw mechanism */
2583 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2584 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2585 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2586 false, false);
2587 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2588 false, 0x18);
2589 } else {
2590 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false,
2591 false, false);
2592 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2593 false, 0x18);
2594 }
2595 }
2596}
2597
2598void halbtc8723b1ant_action_pan_edr_hid(struct btc_coexist *btcoexist)
2599{
2600 u8 wifi_rssi_state, bt_rssi_state;
2601 u32 wifi_bw;
2602
2603 wifi_rssi_state = halbtc8723b1ant_wifi_rssi_state(btcoexist,
2604 0, 2, 25, 0);
2605 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 50, 0);
2606
2607 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2608
2609 if (halbtc8723b1ant_need_to_dec_bt_pwr(btcoexist))
2610 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2611 else
2612 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2613
2614 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2615
2616 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2617 /* sw mechanism */
2618 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2619 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2620 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2621 false, false);
2622 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2623 false, 0x18);
2624 } else {
2625 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2626 false, false);
2627 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2628 false, 0x18);
2629 }
2630 } else {
2631 /* sw mechanism */
2632 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2633 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2634 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2635 false, false);
2636 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2637 false, 0x18);
2638 } else {
2639 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2640 false, false);
2641 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2642 false, 0x18);
2643 }
2644 }
2645}
2646
2647/* HID+A2DP+PAN(EDR) */
2648void halbtc8723b1ant_action_hid_a2dp_pan_edr(struct btc_coexist *btcoexist)
2649{
2650 u8 wifi_rssi_state, bt_rssi_state, bt_info_ext;
2651 u32 wifi_bw;
2652
2653 bt_info_ext = coex_sta->bt_info_ext;
2654 wifi_rssi_state = halbtc8723b1ant_wifi_rssi_state(btcoexist,
2655 0, 2, 25, 0);
2656 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 50, 0);
2657
2658 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2659
2660 if (halbtc8723b1ant_need_to_dec_bt_pwr(btcoexist))
2661 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2662 else
2663 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2664
2665 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2666
2667 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2668 /* sw mechanism */
2669 if((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2670 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2671 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2672 false, false);
2673 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2674 false, 0x18);
2675 } else {
2676 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2677 false, false);
2678 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2679 false, 0x18);
2680 }
2681 } else {
2682 /* sw mechanism */
2683 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2684 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2685 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2686 false, false);
2687 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2688 false, 0x18);
2689 } else {
2690 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2691 false, false);
2692 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2693 false, 0x18);
2694 }
2695 }
2696}
2697
2698void halbtc8723b1ant_action_hid_a2dp(struct btc_coexist *btcoexist)
2699{
2700 u8 wifi_rssi_state, bt_rssi_state, bt_info_ext;
2701 u32 wifi_bw;
2702
2703 bt_info_ext = coex_sta->bt_info_ext;
2704 wifi_rssi_state = halbtc8723b1ant_wifi_rssi_state(btcoexist,
2705 0, 2, 25, 0);
2706 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 50, 0);
2707
2708 if (halbtc8723b1ant_need_to_dec_bt_pwr(btcoexist))
2709 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2710 else
2711 halbtc8723b1ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2712
2713 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2714
2715 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2716 /* sw mechanism */
2717 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2718 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2719 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2720 false, false);
2721 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2722 false, 0x18);
2723 } else {
2724 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2725 false, false);
2726 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2727 false, 0x18);
2728 }
2729 } else {
2730 /* sw mechanism */
2731 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2732 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2733 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2734 false, false);
2735 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2736 false, 0x18);
2737 } else {
2738 halbtc8723b1ant_sw_mechanism1(btcoexist, false, true,
2739 false, false);
2740 halbtc8723b1ant_sw_mechanism2(btcoexist, false, false,
2741 false, 0x18);
2742 }
2743 }
2744}
2745
2746/*****************************************************
2747 *
2748 * Non-Software Coex Mechanism start
2749 *
2750 *****************************************************/
2751void halbtc8723b1ant_action_hs(struct btc_coexist *btcoexist)
2752{
2753 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
2754 halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 2);
2755}
2756
2757void halbtc8723b1ant_action_bt_inquiry(struct btc_coexist *btcoexist)
2758{
2759 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
2760 bool wifi_connected = false, ap_enable = false;
2761
2762 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
2763 &ap_enable);
2764 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
2765 &wifi_connected);
2766
2767 if (!wifi_connected) {
2768 halbtc8723b1ant_power_save_state(btcoexist,
2769 BTC_PS_WIFI_NATIVE, 0x0, 0x0);
2770 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
2771 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
2772 } else if (bt_link_info->sco_exist || bt_link_info->hid_only) {
2773 /* SCO/HID-only busy */
2774 halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
2775 0x0, 0x0);
2776 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 32);
2777 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
2778 } else {
2779 if (ap_enable)
2780 halbtc8723b1ant_power_save_state(btcoexist,
2781 BTC_PS_WIFI_NATIVE,
2782 0x0, 0x0);
2783 else
2784 halbtc8723b1ant_power_save_state(btcoexist,
2785 BTC_PS_LPS_ON,
2786 0x50, 0x4);
2787
2788 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 30);
2789 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
2790 }
2791}
2792
2793void halbtc8723b1ant_action_bt_sco_hid_only_busy(struct btc_coexist * btcoexist,
2794 u8 wifi_status)
2795{
2796 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
2797 bool wifi_connected = false;
2798
2799 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
2800 &wifi_connected);
2801
2802 /* tdma and coex table */
2803
2804 if (bt_link_info->sco_exist) {
2805 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
2806 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
2807 } else { /* HID */
2808 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 6);
2809 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5);
2810 }
2811}
2812
2813void halbtc8723b1ant_action_wifi_connected_bt_acl_busy(
2814 struct btc_coexist *btcoexist,
2815 u8 wifi_status)
2816{
2817 u8 bt_rssi_state;
2818
2819 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
2820 bt_rssi_state = halbtc8723b1ant_bt_rssi_state(2, 28, 0);
2821
2822 if (bt_link_info->hid_only) { /*HID */
2823 halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
2824 wifi_status);
2825 coex_dm->auto_tdma_adjust = false;
2826 return;
2827 } else if (bt_link_info->a2dp_only) { /*A2DP */
2828 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
2829 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2830 halbtc8723b1ant_tdma_duration_adjust_for_acl(btcoexist,
2831 wifi_status);
2832 } else { /*for low BT RSSI */
2833 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2834 true, 11);
2835 coex_dm->auto_tdma_adjust = false;
2836 }
2837
2838 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
2839 } else if (bt_link_info->hid_exist &&
2840 bt_link_info->a2dp_exist) { /*HID+A2DP */
2841 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
2842 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2843 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2844 true, 14);
2845 coex_dm->auto_tdma_adjust = false;
2846 } else { /*for low BT RSSI*/
2847 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2848 true, 14);
2849 coex_dm->auto_tdma_adjust = false;
2850 }
2851
2852 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
2853 /*PAN(OPP,FTP), HID+PAN(OPP,FTP) */
2854 } else if (bt_link_info->pan_only ||
2855 (bt_link_info->hid_exist && bt_link_info->pan_exist)) {
2856 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
2857 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 6);
2858 coex_dm->auto_tdma_adjust = false;
2859 /*A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP)*/
2860 } else if ((bt_link_info->a2dp_exist && bt_link_info->pan_exist) ||
2861 (bt_link_info->hid_exist && bt_link_info->a2dp_exist &&
2862 bt_link_info->pan_exist)) {
2863 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
2864 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
2865 coex_dm->auto_tdma_adjust = false;
2866 } else {
2867 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 11);
2868 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
2869 coex_dm->auto_tdma_adjust = false;
2870 }
2871}
2872
2873void halbtc8723b1ant_action_wifi_not_connected(struct btc_coexist *btcoexist)
2874{
2875 /* power save state */
2876 halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
2877 0x0, 0x0);
2878
2879 /* tdma and coex table */
2880 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
2881 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
2882}
2883
2884void halbtc8723b1ant_action_wifi_not_connected_asso_auth_scan(
2885 struct btc_coexist *btcoexist)
2886{
2887 halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
2888 0x0, 0x0);
2889
2890 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 22);
2891 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
2892}
2893
2894void halbtc8723b1ant_ActionWifiConnectedScan(struct btc_coexist *btcoexist)
2895{
2896 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
2897
2898 halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
2899 0x0, 0x0);
2900
2901 /* tdma and coex table */
2902 if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
2903 if (bt_link_info->a2dp_exist &&
2904 bt_link_info->pan_exist) {
2905 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2906 true, 22);
2907 halbtc8723b1ant_coex_table_with_type(btcoexist,
2908 NORMAL_EXEC, 1);
2909 } else {
2910 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
2911 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
2912 }
2913 } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
2914 (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
2915 coex_dm->bt_status)) {
2916 halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
2917 BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN);
2918 } else {
2919 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
2920 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
2921 }
2922}
2923
2924void halbtc8723b1ant_action_wifi_connected_special_packet(
2925 struct btc_coexist *btcoexist)
2926{
2927 bool hs_connecting = false;
2928 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
2929
2930 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_CONNECTING, &hs_connecting);
2931
2932 halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
2933 0x0, 0x0);
2934
2935 /* tdma and coex table */
2936 if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
2937 if (bt_link_info->a2dp_exist && bt_link_info->pan_exist) {
2938 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2939 true, 22);
2940 halbtc8723b1ant_coex_table_with_type(btcoexist,
2941 NORMAL_EXEC, 1);
2942 } else {
2943 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
2944 true, 20);
2945 halbtc8723b1ant_coex_table_with_type(btcoexist,
2946 NORMAL_EXEC, 1);
2947 }
2948 } else {
2949 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 20);
2950 halbtc8723b1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1);
2951 }
2952}
2953
2954void halbtc8723b1ant_action_wifi_connected(struct btc_coexist *btcoexist)
2955{
2956 bool wifi_busy = false;
2957 bool scan = false, link = false, roam = false;
2958 bool under_4way = false, ap_enable = false;
2959
2960 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
2961 "[BTCoex], CoexForWifiConnect()===>\n");
2962
2963 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
2964 &under_4way);
2965 if (under_4way) {
2966 halbtc8723b1ant_action_wifi_connected_special_packet(btcoexist);
2967 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
2968 "[BTCoex], CoexForWifiConnect(), "
2969 "return for wifi is under 4way<===\n");
2970 return;
2971 }
2972
2973 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
2974 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
2975 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
2976
2977 if (scan || link || roam) {
2978 halbtc8723b1ant_ActionWifiConnectedScan(btcoexist);
2979 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
2980 "[BTCoex], CoexForWifiConnect(), "
2981 "return for wifi is under scan<===\n");
2982 return;
2983 }
2984
2985 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
2986 &ap_enable);
2987 /* power save state */
2988 if (!ap_enable &&
2989 BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status &&
2990 !btcoexist->bt_link_info.hid_only)
2991 halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_LPS_ON,
2992 0x50, 0x4);
2993 else
2994 halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
2995 0x0, 0x0);
2996
2997 /* tdma and coex table */
2998 btcoexist->btc_get(btcoexist,
2999 BTC_GET_BL_WIFI_BUSY, &wifi_busy);
3000 if (!wifi_busy) {
3001 if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
3002 halbtc8723b1ant_action_wifi_connected_bt_acl_busy(btcoexist,
3003 BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
3004 } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY ==
3005 coex_dm->bt_status) ||
3006 (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
3007 coex_dm->bt_status)) {
3008 halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
3009 BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE);
3010 } else {
3011 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC,
3012 false, 8);
3013 halbtc8723b1ant_coex_table_with_type(btcoexist,
3014 NORMAL_EXEC, 2);
3015 }
3016 } else {
3017 if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) {
3018 halbtc8723b1ant_action_wifi_connected_bt_acl_busy(btcoexist,
3019 BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
3020 } else if ((BT_8723B_1ANT_BT_STATUS_SCO_BUSY ==
3021 coex_dm->bt_status) ||
3022 (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY ==
3023 coex_dm->bt_status)) {
3024 halbtc8723b1ant_action_bt_sco_hid_only_busy(btcoexist,
3025 BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY);
3026 } else {
3027 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 8);
3028 halbtc8723b1ant_coex_table_with_type(btcoexist,
3029 NORMAL_EXEC, 2);
3030 }
3031 }
3032}
3033
3034void halbtc8723b1ant_run_sw_coexist_mechanism(struct btc_coexist *btcoexist)
3035{
3036 u8 algorithm = 0;
3037
3038 algorithm = halbtc8723b1ant_action_algorithm(btcoexist);
3039 coex_dm->cur_algorithm = algorithm;
3040
3041 if (halbtc8723b1ant_is_common_action(btcoexist)) {
3042 } else {
3043 switch (coex_dm->cur_algorithm) {
3044 case BT_8723B_1ANT_COEX_ALGO_SCO:
3045 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3046 "[BTCoex], Action algorithm = SCO.\n");
3047 halbtc8723b1ant_action_sco(btcoexist);
3048 break;
3049 case BT_8723B_1ANT_COEX_ALGO_HID:
3050 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3051 "[BTCoex], Action algorithm = HID.\n");
3052 halbtc8723b1ant_action_hid(btcoexist);
3053 break;
3054 case BT_8723B_1ANT_COEX_ALGO_A2DP:
3055 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3056 "[BTCoex], Action algorithm = A2DP.\n");
3057 halbtc8723b1ant_action_a2dp(btcoexist);
3058 break;
3059 case BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS:
3060 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3061 "[BTCoex], Action algorithm = "
3062 "A2DP+PAN(HS).\n");
3063 halbtc8723b1ant_action_a2dp_pan_hs(btcoexist);
3064 break;
3065 case BT_8723B_1ANT_COEX_ALGO_PANEDR:
3066 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3067 "[BTCoex], Action algorithm = PAN(EDR).\n");
3068 halbtc8723b1ant_action_pan_edr(btcoexist);
3069 break;
3070 case BT_8723B_1ANT_COEX_ALGO_PANHS:
3071 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3072 "[BTCoex], Action algorithm = HS mode.\n");
3073 halbtc8723b1ant_action_pan_hs(btcoexist);
3074 break;
3075 case BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP:
3076 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3077 "[BTCoex], Action algorithm = PAN+A2DP.\n");
3078 halbtc8723b1ant_action_pan_edr_a2dp(btcoexist);
3079 break;
3080 case BT_8723B_1ANT_COEX_ALGO_PANEDR_HID:
3081 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3082 "[BTCoex], Action algorithm = "
3083 "PAN(EDR)+HID.\n");
3084 halbtc8723b1ant_action_pan_edr_hid(btcoexist);
3085 break;
3086 case BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR:
3087 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3088 "[BTCoex], Action algorithm = "
3089 "HID+A2DP+PAN.\n");
3090 halbtc8723b1ant_action_hid_a2dp_pan_edr(btcoexist);
3091 break;
3092 case BT_8723B_1ANT_COEX_ALGO_HID_A2DP:
3093 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3094 "[BTCoex], Action algorithm = HID+A2DP.\n");
3095 halbtc8723b1ant_action_hid_a2dp(btcoexist);
3096 break;
3097 default:
3098 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3099 "[BTCoex], Action algorithm = "
3100 "coexist All Off!!\n");
3101 break;
3102 }
3103 coex_dm->pre_algorithm = coex_dm->cur_algorithm;
3104 }
3105}
3106
3107void halbtc8723b1ant_run_coexist_mechanism(struct btc_coexist *btcoexist)
3108{
3109 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
3110 bool wifi_connected = false, bt_hs_on = false;
3111 bool limited_dig = false, bIncreaseScanDevNum = false;
3112 bool b_bt_ctrl_agg_buf_size = false;
3113 u8 agg_buf_size = 5;
3114 u8 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
3115
3116 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3117 "[BTCoex], RunCoexistMechanism()===>\n");
3118
3119 if (btcoexist->manual_control) {
3120 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3121 "[BTCoex], RunCoexistMechanism(), "
3122 "return for Manual CTRL <===\n");
3123 return;
3124 }
3125
3126 if (btcoexist->stop_coex_dm) {
3127 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3128 "[BTCoex], RunCoexistMechanism(), "
3129 "return for Stop Coex DM <===\n");
3130 return;
3131 }
3132
3133 if (coex_sta->under_ips) {
3134 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3135 "[BTCoex], wifi is under IPS !!!\n");
3136 return;
3137 }
3138
3139 if ((BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
3140 (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
3141 (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
3142 limited_dig = true;
3143 bIncreaseScanDevNum = true;
3144 }
3145
3146 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
3147 btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM,
3148 &bIncreaseScanDevNum);
3149
3150 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
3151 &wifi_connected);
3152
3153 if (!bt_link_info->sco_exist && !bt_link_info->hid_exist) {
3154 halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
3155 } else {
3156 if (wifi_connected) {
3157 wifi_rssi_state =
3158 halbtc8723b1ant_wifi_rssi_state(btcoexist,
3159 1, 2, 30, 0);
3160 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3161 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3162 halbtc8723b1ant_limited_tx(btcoexist,
3163 NORMAL_EXEC,
3164 1, 1, 1, 1);
3165 } else {
3166 halbtc8723b1ant_limited_tx(btcoexist,
3167 NORMAL_EXEC,
3168 1, 1, 1, 1);
3169 }
3170 } else {
3171 halbtc8723b1ant_limited_tx(btcoexist, NORMAL_EXEC,
3172 0, 0, 0, 0);
3173 }
3174 }
3175
3176 if (bt_link_info->sco_exist) {
3177 b_bt_ctrl_agg_buf_size = true;
3178 agg_buf_size = 0x3;
3179 } else if (bt_link_info->hid_exist) {
3180 b_bt_ctrl_agg_buf_size = true;
3181 agg_buf_size = 0x5;
3182 } else if (bt_link_info->a2dp_exist || bt_link_info->pan_exist) {
3183 b_bt_ctrl_agg_buf_size = true;
3184 agg_buf_size = 0x8;
3185 }
3186 halbtc8723b1ant_limited_rx(btcoexist, NORMAL_EXEC, false,
3187 b_bt_ctrl_agg_buf_size, agg_buf_size);
3188
3189 halbtc8723b1ant_run_sw_coexist_mechanism(btcoexist);
3190
3191 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
3192
3193 if (coex_sta->c2h_bt_inquiry_page) {
3194 halbtc8723b1ant_action_bt_inquiry(btcoexist);
3195 return;
3196 } else if (bt_hs_on) {
3197 halbtc8723b1ant_action_hs(btcoexist);
3198 return;
3199 }
3200
3201
3202 if (!wifi_connected) {
3203 bool scan = false, link = false, roam = false;
3204
3205 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3206 "[BTCoex], wifi is non connected-idle !!!\n");
3207
3208 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
3209 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
3210 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
3211
3212 if (scan || link || roam)
3213 halbtc8723b1ant_action_wifi_not_connected_asso_auth_scan(btcoexist);
3214 else
3215 halbtc8723b1ant_action_wifi_not_connected(btcoexist);
3216 } else { /* wifi LPS/Busy */
3217 halbtc8723b1ant_action_wifi_connected(btcoexist);
3218 }
3219}
3220
3221void halbtc8723b1ant_init_coex_dm(struct btc_coexist *btcoexist)
3222{
3223 /* force to reset coex mechanism */
3224 halbtc8723b1ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
3225 halbtc8723b1ant_dec_bt_pwr(btcoexist, FORCE_EXEC, false);
3226
3227 /* sw all off */
3228 halbtc8723b1ant_sw_mechanism1(btcoexist, false, false, false, false);
3229 halbtc8723b1ant_sw_mechanism2(btcoexist,false, false, false, 0x18);
3230
3231 halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 8);
3232 halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
3233}
3234
3235void halbtc8723b1ant_init_hw_config(struct btc_coexist *btcoexist, bool backup)
3236{
3237 u32 u32tmp = 0;
3238 u8 u8tmp = 0;
3239 u32 cnt_bt_cal_chk = 0;
3240
3241 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
3242 "[BTCoex], 1Ant Init HW Config!!\n");
3243
3244 if (backup) {/* backup rf 0x1e value */
3245 coex_dm->bt_rf0x1e_backup =
3246 btcoexist->btc_get_rf_reg(btcoexist,
3247 BTC_RF_A, 0x1e, 0xfffff);
3248
3249 coex_dm->backup_arfr_cnt1 =
3250 btcoexist->btc_read_4byte(btcoexist, 0x430);
3251 coex_dm->backup_arfr_cnt2 =
3252 btcoexist->btc_read_4byte(btcoexist, 0x434);
3253 coex_dm->backup_retry_limit =
3254 btcoexist->btc_read_2byte(btcoexist, 0x42a);
3255 coex_dm->backup_ampdu_max_time =
3256 btcoexist->btc_read_1byte(btcoexist, 0x456);
3257 }
3258
3259 /* WiFi goto standby while GNT_BT 0-->1 */
3260 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x780);
3261 /* BT goto standby while GNT_BT 1-->0 */
3262 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x2, 0xfffff, 0x500);
3263
3264 btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
3265 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3);
3266 btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77);
3267
3268
3269 /* BT calibration check */
3270 while (cnt_bt_cal_chk <= 20) {
3271 u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x49d);
3272 cnt_bt_cal_chk++;
3273 if (u32tmp & BIT0) {
3274 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
3275 "[BTCoex], ########### BT "
3276 "calibration(cnt=%d) ###########\n",
3277 cnt_bt_cal_chk);
3278 mdelay(50);
3279 } else {
3280 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
3281 "[BTCoex], ********** BT NOT "
3282 "calibration (cnt=%d)**********\n",
3283 cnt_bt_cal_chk);
3284 break;
3285 }
3286 }
3287
3288 /* 0x790[5:0]=0x5 */
3289 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
3290 u8tmp &= 0xc0;
3291 u8tmp |= 0x5;
3292 btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
3293
3294 /* Enable counter statistics */
3295 /*0x76e[3] =1, WLAN_Act control by PTA */
3296 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
3297 btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1);
3298 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
3299
3300 /*Antenna config */
3301 halbtc8723b1ant_SetAntPath(btcoexist, BTC_ANT_PATH_PTA, true, false);
3302 /* PTA parameter */
3303 halbtc8723b1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
3304
3305}
3306
3307void halbtc8723b1ant_wifi_off_hw_cfg(struct btc_coexist *btcoexist)
3308{
3309 /* set wlan_act to low */
3310 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0);
3311}
3312
3313/**************************************************************
3314 * work around function start with wa_halbtc8723b1ant_
3315 **************************************************************/
3316/**************************************************************
3317 * extern function start with EXhalbtc8723b1ant_
3318 **************************************************************/
3319
3320void ex_halbtc8723b1ant_init_hwconfig(struct btc_coexist *btcoexist)
3321{
3322 halbtc8723b1ant_init_hw_config(btcoexist, true);
3323}
3324
3325void ex_halbtc8723b1ant_init_coex_dm(struct btc_coexist *btcoexist)
3326{
3327 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
3328 "[BTCoex], Coex Mechanism Init!!\n");
3329
3330 btcoexist->stop_coex_dm = false;
3331
3332 halbtc8723b1ant_init_coex_dm(btcoexist);
3333
3334 halbtc8723b1ant_query_bt_info(btcoexist);
3335}
3336
3337void ex_halbtc8723b1ant_display_coex_info(struct btc_coexist *btcoexist)
3338{
3339 struct btc_board_info *board_info = &btcoexist->board_info;
3340 struct btc_stack_info *stack_info = &btcoexist->stack_info;
3341 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
3342 u8 *cli_buf = btcoexist->cli_buf;
3343 u8 u8tmp[4], i, bt_info_ext, psTdmaCase=0;
3344 u16 u16tmp[4];
3345 u32 u32tmp[4];
3346 bool roam = false, scan = false;
3347 bool link = false, wifi_under_5g = false;
3348 bool bt_hs_on = false, wifi_busy = false;
3349 s32 wifi_rssi =0, bt_hs_rssi = 0;
3350 u32 wifi_bw, wifi_traffic_dir, fa_ofdm, fa_cck;
3351 u8 wifi_dot11_chnl, wifi_hs_chnl;
3352 u32 fw_ver = 0, bt_patch_ver = 0;
3353
3354 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3355 "\r\n ============[BT Coexist info]============");
3356 CL_PRINTF(cli_buf);
3357
3358 if (btcoexist->manual_control) {
3359 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3360 "\r\n ============[Under Manual Control]==========");
3361 CL_PRINTF(cli_buf);
3362 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3363 "\r\n ==========================================");
3364 CL_PRINTF(cli_buf);
3365 }
3366 if (btcoexist->stop_coex_dm) {
3367 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3368 "\r\n ============[Coex is STOPPED]============");
3369 CL_PRINTF(cli_buf);
3370 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3371 "\r\n ==========================================");
3372 CL_PRINTF(cli_buf);
3373 }
3374
3375 if (!board_info->bt_exist) {
3376 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n BT not exists !!!");
3377 CL_PRINTF(cli_buf);
3378 return;
3379 }
3380
3381 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
3382 "Ant PG Num/ Ant Mech/ Ant Pos:", \
3383 board_info->pg_ant_num, board_info->btdm_ant_num,
3384 board_info->btdm_ant_pos);
3385 CL_PRINTF(cli_buf);
3386
3387 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d",
3388 "BT stack/ hci ext ver", \
3389 ((stack_info->profile_notified)? "Yes":"No"),
3390 stack_info->hci_version);
3391 CL_PRINTF(cli_buf);
3392
3393 btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
3394 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
3395 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3396 "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)",
3397 "CoexVer/ FwVer/ PatchVer", \
3398 glcoex_ver_date_8723b_1ant, glcoex_ver_8723b_1ant,
3399 fw_ver, bt_patch_ver, bt_patch_ver);
3400 CL_PRINTF(cli_buf);
3401
3402 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
3403 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_DOT11_CHNL,
3404 &wifi_dot11_chnl);
3405 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifi_hs_chnl);
3406 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d(%d)",
3407 "Dot11 channel / HsChnl(HsMode)", \
3408 wifi_dot11_chnl, wifi_hs_chnl, bt_hs_on);
3409 CL_PRINTF(cli_buf);
3410
3411 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
3412 "H2C Wifi inform bt chnl Info", \
3413 coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1],
3414 coex_dm->wifi_chnl_info[2]);
3415 CL_PRINTF(cli_buf);
3416
3417 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
3418 btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi);
3419 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
3420 "Wifi rssi/ HS rssi", wifi_rssi, bt_hs_rssi);
3421 CL_PRINTF(cli_buf);
3422
3423 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
3424 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
3425 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
3426 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
3427 "Wifi link/ roam/ scan", link, roam, scan);
3428 CL_PRINTF(cli_buf);
3429
3430 btcoexist->btc_get(btcoexist,BTC_GET_BL_WIFI_UNDER_5G,
3431 &wifi_under_5g);
3432 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3433 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
3434 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
3435 &wifi_traffic_dir);
3436
3437 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s ",
3438 "Wifi status", (wifi_under_5g? "5G":"2.4G"),
3439 ((BTC_WIFI_BW_LEGACY==wifi_bw)? "Legacy":
3440 (((BTC_WIFI_BW_HT40==wifi_bw)? "HT40":"HT20"))),
3441 ((!wifi_busy)? "idle":
3442 ((BTC_WIFI_TRAFFIC_TX==wifi_traffic_dir)?
3443 "uplink":"downlink")));
3444 CL_PRINTF(cli_buf);
3445 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ",
3446 "BT [status/ rssi/ retryCnt]",
3447 ((btcoexist->bt_info.bt_disabled)? ("disabled"):
3448 ((coex_sta->c2h_bt_inquiry_page)?("inquiry/page scan"):
3449 ((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == coex_dm->bt_status)?
3450 "non-connected idle":
3451 ((BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status)?
3452 "connected-idle":"busy")))),
3453 coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
3454 CL_PRINTF(cli_buf);
3455
3456
3457 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
3458 "SCO/HID/PAN/A2DP", bt_link_info->sco_exist,
3459 bt_link_info->hid_exist, bt_link_info->pan_exist,
3460 bt_link_info->a2dp_exist);
3461 CL_PRINTF(cli_buf);
3462 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
3463
3464 bt_info_ext = coex_sta->bt_info_ext;
3465 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
3466 "BT Info A2DP rate",
3467 (bt_info_ext & BIT0) ? "Basic rate" : "EDR rate");
3468 CL_PRINTF(cli_buf);
3469
3470 for (i = 0; i < BT_INFO_SRC_8723B_1ANT_MAX; i++) {
3471 if (coex_sta->bt_info_c2h_cnt[i]) {
3472 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3473 "\r\n %-35s = %02x %02x %02x "
3474 "%02x %02x %02x %02x(%d)",
3475 GLBtInfoSrc8723b1Ant[i],
3476 coex_sta->bt_info_c2h[i][0],
3477 coex_sta->bt_info_c2h[i][1],
3478 coex_sta->bt_info_c2h[i][2],
3479 coex_sta->bt_info_c2h[i][3],
3480 coex_sta->bt_info_c2h[i][4],
3481 coex_sta->bt_info_c2h[i][5],
3482 coex_sta->bt_info_c2h[i][6],
3483 coex_sta->bt_info_c2h_cnt[i]);
3484 CL_PRINTF(cli_buf);
3485 }
3486 }
3487 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3488 "\r\n %-35s = %s/%s, (0x%x/0x%x)",
3489 "PS state, IPS/LPS, (lps/rpwm)", \
3490 ((coex_sta->under_ips? "IPS ON":"IPS OFF")),
3491 ((coex_sta->under_lps? "LPS ON":"LPS OFF")),
3492 btcoexist->bt_info.lps_1ant,
3493 btcoexist->bt_info.rpwm_1ant);
3494 CL_PRINTF(cli_buf);
3495 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD);
3496
3497 if (!btcoexist->manual_control) {
3498 /* Sw mechanism */
3499 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
3500 "============[Sw mechanism]============");
3501 CL_PRINTF(cli_buf);
3502
3503 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
3504 "SM1[ShRf/ LpRA/ LimDig]", \
3505 coex_dm->cur_rf_rx_lpf_shrink,
3506 coex_dm->cur_low_penalty_ra,
3507 btcoexist->bt_info.limited_dig);
3508 CL_PRINTF(cli_buf);
3509 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3510 "\r\n %-35s = %d/ %d/ %d(0x%x) ",
3511 "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \
3512 coex_dm->cur_agc_table_en,
3513 coex_dm->cur_adc_backoff,
3514 coex_dm->cur_dac_swing_on,
3515 coex_dm->cur_dac_swing_lvl);
3516 CL_PRINTF(cli_buf);
3517
3518
3519 CL_PRINTF(cli_buf);
3520 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ",
3521 "Rate Mask", btcoexist->bt_info.ra_mask);
3522 CL_PRINTF(cli_buf);
3523
3524 /* Fw mechanism */
3525 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
3526 "============[Fw mechanism]============");
3527 CL_PRINTF(cli_buf);
3528
3529 psTdmaCase = coex_dm->cur_ps_tdma;
3530 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3531 "\r\n %-35s = %02x %02x %02x %02x %02x "
3532 "case-%d (auto:%d)",
3533 "PS TDMA", coex_dm->ps_tdma_para[0],
3534 coex_dm->ps_tdma_para[1], coex_dm->ps_tdma_para[2],
3535 coex_dm->ps_tdma_para[3], coex_dm->ps_tdma_para[4],
3536 psTdmaCase, coex_dm->auto_tdma_adjust);
3537 CL_PRINTF(cli_buf);
3538
3539 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ",
3540 "Latest error condition(should be 0)", \
3541 coex_dm->error_condition);
3542 CL_PRINTF(cli_buf);
3543
3544 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
3545 "DecBtPwr/ IgnWlanAct", coex_dm->cur_dec_bt_pwr,
3546 coex_dm->cur_ignore_wlan_act);
3547 CL_PRINTF(cli_buf);
3548 }
3549
3550 /* Hw setting */
3551 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
3552 "============[Hw setting]============");
3553 CL_PRINTF(cli_buf);
3554
3555 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
3556 "RF-A, 0x1e initVal", coex_dm->bt_rf0x1e_backup);
3557 CL_PRINTF(cli_buf);
3558 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
3559 "backup ARFR1/ARFR2/RL/AMaxTime", coex_dm->backup_arfr_cnt1,
3560 coex_dm->backup_arfr_cnt2, coex_dm->backup_retry_limit,
3561 coex_dm->backup_ampdu_max_time);
3562 CL_PRINTF(cli_buf);
3563
3564 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
3565 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
3566 u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
3567 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
3568 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
3569 "0x430/0x434/0x42a/0x456",
3570 u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
3571 CL_PRINTF(cli_buf);
3572
3573 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
3574 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc);
3575 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x880);
3576 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
3577 "0x778/0x6cc/0x880[29:25]", u8tmp[0], u32tmp[0],
3578 (u32tmp[1] & 0x3e000000) >> 25);
3579 CL_PRINTF(cli_buf);
3580
3581 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
3582 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
3583 u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x765);
3584 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
3585 "0x948/ 0x67[5] / 0x765",
3586 u32tmp[0], ((u8tmp[0] & 0x20)>> 5), u8tmp[1]);
3587 CL_PRINTF(cli_buf);
3588
3589 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c);
3590 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930);
3591 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944);
3592 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
3593 "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]",
3594 u32tmp[0] & 0x3, u32tmp[1] & 0xff, u32tmp[2] & 0x3);
3595 CL_PRINTF(cli_buf);
3596
3597 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39);
3598 u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
3599 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
3600 u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
3601 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3602 "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
3603 "0x38[11]/0x40/0x4c[24:23]/0x64[0]",
3604 ((u8tmp[0] & 0x8)>>3), u8tmp[1],
3605 ((u32tmp[0] & 0x01800000) >> 23), u8tmp[2] & 0x1);
3606 CL_PRINTF(cli_buf);
3607
3608 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
3609 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
3610 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
3611 "0x550(bcn ctrl)/0x522", u32tmp[0], u8tmp[0]);
3612 CL_PRINTF(cli_buf);
3613
3614 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
3615 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c);
3616 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
3617 "0xc50(dig)/0x49c(null-drop)", u32tmp[0] & 0xff, u8tmp[0]);
3618 CL_PRINTF(cli_buf);
3619
3620 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
3621 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
3622 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
3623 u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
3624
3625 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
3626 u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
3627
3628 fa_ofdm = ((u32tmp[0] & 0xffff0000) >> 16) +
3629 ((u32tmp[1] & 0xffff0000) >> 16) +
3630 (u32tmp[1] & 0xffff) +
3631 (u32tmp[2] & 0xffff) + \
3632 ((u32tmp[3] & 0xffff0000) >> 16) +
3633 (u32tmp[3] & 0xffff) ;
3634 fa_cck = (u8tmp[0] << 8) + u8tmp[1];
3635
3636 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
3637 "OFDM-CCA/OFDM-FA/CCK-FA",
3638 u32tmp[0] & 0xffff, fa_ofdm, fa_cck);
3639 CL_PRINTF(cli_buf);
3640
3641 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
3642 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
3643 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
3644 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
3645 "0x6c0/0x6c4/0x6c8(coexTable)",
3646 u32tmp[0], u32tmp[1], u32tmp[2]);
3647 CL_PRINTF(cli_buf);
3648
3649 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
3650 "0x770(high-pri rx/tx)", coex_sta->high_priority_rx,
3651 coex_sta->high_priority_tx);
3652 CL_PRINTF(cli_buf);
3653 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
3654 "0x774(low-pri rx/tx)", coex_sta->low_priority_rx,
3655 coex_sta->low_priority_tx);
3656 CL_PRINTF(cli_buf);
3657#if(BT_AUTO_REPORT_ONLY_8723B_1ANT == 1)
3658 halbtc8723b1ant_monitor_bt_ctr(btcoexist);
3659#endif
3660 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
3661}
3662
3663
3664void ex_halbtc8723b1ant_ips_notify(struct btc_coexist *btcoexist, u8 type)
3665{
3666
3667 if (btcoexist->manual_control || btcoexist->stop_coex_dm)
3668 return;
3669
3670 if (BTC_IPS_ENTER == type) {
3671 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3672 "[BTCoex], IPS ENTER notify\n");
3673 coex_sta->under_ips = true;
3674
3675 halbtc8723b1ant_SetAntPath(btcoexist, BTC_ANT_PATH_BT,
3676 false, true);
3677 /* set PTA control */
3678 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
3679 halbtc8723b1ant_coex_table_with_type(btcoexist,
3680 NORMAL_EXEC, 0);
3681 } else if (BTC_IPS_LEAVE == type) {
3682 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3683 "[BTCoex], IPS LEAVE notify\n");
3684 coex_sta->under_ips = false;
3685
3686 halbtc8723b1ant_run_coexist_mechanism(btcoexist);
3687 }
3688}
3689
3690void ex_halbtc8723b1ant_lps_notify(struct btc_coexist *btcoexist, u8 type)
3691{
3692 if (btcoexist->manual_control || btcoexist->stop_coex_dm)
3693 return;
3694
3695 if (BTC_LPS_ENABLE == type) {
3696 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3697 "[BTCoex], LPS ENABLE notify\n");
3698 coex_sta->under_lps = true;
3699 } else if (BTC_LPS_DISABLE == type) {
3700 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3701 "[BTCoex], LPS DISABLE notify\n");
3702 coex_sta->under_lps = false;
3703 }
3704}
3705
3706void ex_halbtc8723b1ant_scan_notify(struct btc_coexist *btcoexist, u8 type)
3707{
3708 bool wifi_connected = false, bt_hs_on = false;
3709
3710 if (btcoexist->manual_control || btcoexist->stop_coex_dm ||
3711 btcoexist->bt_info.bt_disabled)
3712 return;
3713
3714 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
3715 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
3716 &wifi_connected);
3717
3718 halbtc8723b1ant_query_bt_info(btcoexist);
3719
3720 if (coex_sta->c2h_bt_inquiry_page) {
3721 halbtc8723b1ant_action_bt_inquiry(btcoexist);
3722 return;
3723 } else if (bt_hs_on) {
3724 halbtc8723b1ant_action_hs(btcoexist);
3725 return;
3726 }
3727
3728 if (BTC_SCAN_START == type) {
3729 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3730 "[BTCoex], SCAN START notify\n");
3731 if (!wifi_connected) /* non-connected scan */
3732 halbtc8723b1ant_action_wifi_not_connected_asso_auth_scan(btcoexist);
3733 else /* wifi is connected */
3734 halbtc8723b1ant_ActionWifiConnectedScan(btcoexist);
3735 } else if (BTC_SCAN_FINISH == type) {
3736 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3737 "[BTCoex], SCAN FINISH notify\n");
3738 if (!wifi_connected) /* non-connected scan */
3739 halbtc8723b1ant_action_wifi_not_connected(btcoexist);
3740 else
3741 halbtc8723b1ant_action_wifi_connected(btcoexist);
3742 }
3743}
3744
3745void ex_halbtc8723b1ant_connect_notify(struct btc_coexist *btcoexist, u8 type)
3746{
3747 bool wifi_connected = false, bt_hs_on = false;
3748
3749 if (btcoexist->manual_control || btcoexist->stop_coex_dm ||
3750 btcoexist->bt_info.bt_disabled)
3751 return;
3752
3753 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
3754 if (coex_sta->c2h_bt_inquiry_page) {
3755 halbtc8723b1ant_action_bt_inquiry(btcoexist);
3756 return;
3757 } else if (bt_hs_on) {
3758 halbtc8723b1ant_action_hs(btcoexist);
3759 return;
3760 }
3761
3762 if (BTC_ASSOCIATE_START == type) {
3763 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3764 "[BTCoex], CONNECT START notify\n");
3765 halbtc8723b1ant_action_wifi_not_connected_asso_auth_scan(btcoexist);
3766 } else if (BTC_ASSOCIATE_FINISH == type) {
3767 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3768 "[BTCoex], CONNECT FINISH notify\n");
3769
3770 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
3771 &wifi_connected);
3772 if (!wifi_connected) /* non-connected scan */
3773 halbtc8723b1ant_action_wifi_not_connected(btcoexist);
3774 else
3775 halbtc8723b1ant_action_wifi_connected(btcoexist);
3776 }
3777}
3778
3779void ex_halbtc8723b1ant_media_status_notify(struct btc_coexist *btcoexist,
3780 u8 type)
3781{
3782 u8 h2c_parameter[3] ={0};
3783 u32 wifi_bw;
3784 u8 wifiCentralChnl;
3785
3786 if (btcoexist->manual_control || btcoexist->stop_coex_dm ||
3787 btcoexist->bt_info.bt_disabled )
3788 return;
3789
3790 if (BTC_MEDIA_CONNECT == type)
3791 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3792 "[BTCoex], MEDIA connect notify\n");
3793 else
3794 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3795 "[BTCoex], MEDIA disconnect notify\n");
3796
3797 /* only 2.4G we need to inform bt the chnl mask */
3798 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
3799 &wifiCentralChnl);
3800
3801 if ((BTC_MEDIA_CONNECT == type) &&
3802 (wifiCentralChnl <= 14)) {
3803 h2c_parameter[0] = 0x0;
3804 h2c_parameter[1] = wifiCentralChnl;
3805 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3806 if (BTC_WIFI_BW_HT40 == wifi_bw)
3807 h2c_parameter[2] = 0x30;
3808 else
3809 h2c_parameter[2] = 0x20;
3810 }
3811
3812 coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
3813 coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
3814 coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
3815
3816 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
3817 "[BTCoex], FW write 0x66=0x%x\n",
3818 h2c_parameter[0] << 16 | h2c_parameter[1] << 8 |
3819 h2c_parameter[2]);
3820
3821 btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
3822}
3823
3824void ex_halbtc8723b1ant_special_packet_notify(struct btc_coexist *btcoexist,
3825 u8 type)
3826{
3827 bool bt_hs_on = false;
3828
3829 if (btcoexist->manual_control || btcoexist->stop_coex_dm ||
3830 btcoexist->bt_info.bt_disabled)
3831 return;
3832
3833 coex_sta->special_pkt_period_cnt = 0;
3834
3835 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
3836 if (coex_sta->c2h_bt_inquiry_page) {
3837 halbtc8723b1ant_action_bt_inquiry(btcoexist);
3838 return;
3839 } else if (bt_hs_on) {
3840 halbtc8723b1ant_action_hs(btcoexist);
3841 return;
3842 }
3843
3844 if (BTC_PACKET_DHCP == type ||
3845 BTC_PACKET_EAPOL == type) {
3846 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3847 "[BTCoex], special Packet(%d) notify\n", type);
3848 halbtc8723b1ant_action_wifi_connected_special_packet(btcoexist);
3849 }
3850}
3851
3852void ex_halbtc8723b1ant_bt_info_notify(struct btc_coexist *btcoexist,
3853 u8 *tmp_buf, u8 length)
3854{
3855 u8 bt_info = 0;
3856 u8 i, rsp_source = 0;
3857 bool wifi_connected = false;
3858 bool bt_busy = false;
3859
3860 coex_sta->c2h_bt_info_req_sent = false;
3861
3862 rsp_source = tmp_buf[0] & 0xf;
3863 if (rsp_source >= BT_INFO_SRC_8723B_1ANT_MAX)
3864 rsp_source = BT_INFO_SRC_8723B_1ANT_WIFI_FW;
3865 coex_sta->bt_info_c2h_cnt[rsp_source]++;
3866
3867 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3868 "[BTCoex], Bt info[%d], length=%d, hex data=[",
3869 rsp_source, length);
3870 for (i=0; i<length; i++) {
3871 coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
3872 if (i == 1)
3873 bt_info = tmp_buf[i];
3874 if (i == length - 1)
3875 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3876 "0x%02x]\n", tmp_buf[i]);
3877 else
3878 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3879 "0x%02x, ", tmp_buf[i]);
3880 }
3881
3882 if (BT_INFO_SRC_8723B_1ANT_WIFI_FW != rsp_source) {
3883 coex_sta->bt_retry_cnt = /* [3:0] */
3884 coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
3885
3886 coex_sta->bt_rssi =
3887 coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
3888
3889 coex_sta->bt_info_ext =
3890 coex_sta->bt_info_c2h[rsp_source][4];
3891
3892 /* Here we need to resend some wifi info to BT
3893 * because bt is reset and loss of the info.*/
3894 if(coex_sta->bt_info_ext & BIT1)
3895 {
3896 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3897 "[BTCoex], BT ext info bit1 check, "
3898 "send wifi BW&Chnl to BT!!\n");
3899 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
3900 &wifi_connected);
3901 if(wifi_connected)
3902 ex_halbtc8723b1ant_media_status_notify(btcoexist,
3903 BTC_MEDIA_CONNECT);
3904 else
3905 ex_halbtc8723b1ant_media_status_notify(btcoexist,
3906 BTC_MEDIA_DISCONNECT);
3907 }
3908
3909 if (coex_sta->bt_info_ext & BIT3) {
3910 if (!btcoexist->manual_control &&
3911 !btcoexist->stop_coex_dm) {
3912 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3913 "[BTCoex], BT ext info bit3 check, "
3914 "set BT NOT ignore Wlan active!!\n");
3915 halbtc8723b1ant_ignore_wlan_act(btcoexist,
3916 FORCE_EXEC,
3917 false);
3918 }
3919 } else {
3920 /* BT already NOT ignore Wlan active, do nothing here.*/
3921 }
3922#if(BT_AUTO_REPORT_ONLY_8723B_1ANT == 0)
3923 if (coex_sta->bt_info_ext & BIT4) {
3924 /* BT auto report already enabled, do nothing */
3925 } else {
3926 halbtc8723b1ant_bt_auto_report(btcoexist, FORCE_EXEC,
3927 true);
3928 }
3929#endif
3930 }
3931
3932 /* check BIT2 first ==> check if bt is under inquiry or page scan */
3933 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE)
3934 coex_sta->c2h_bt_inquiry_page = true;
3935 else
3936 coex_sta->c2h_bt_inquiry_page = false;
3937
3938 /* set link exist status */
3939 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) {
3940 coex_sta->bt_link_exist = false;
3941 coex_sta->pan_exist = false;
3942 coex_sta->a2dp_exist = false;
3943 coex_sta->hid_exist = false;
3944 coex_sta->sco_exist = false;
3945 } else { /* connection exists */
3946 coex_sta->bt_link_exist = true;
3947 if (bt_info & BT_INFO_8723B_1ANT_B_FTP)
3948 coex_sta->pan_exist = true;
3949 else
3950 coex_sta->pan_exist = false;
3951 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP)
3952 coex_sta->a2dp_exist = true;
3953 else
3954 coex_sta->a2dp_exist = false;
3955 if (bt_info & BT_INFO_8723B_1ANT_B_HID)
3956 coex_sta->hid_exist = true;
3957 else
3958 coex_sta->hid_exist = false;
3959 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO)
3960 coex_sta->sco_exist = true;
3961 else
3962 coex_sta->sco_exist = false;
3963 }
3964
3965 halbtc8723b1ant_update_bt_link_info(btcoexist);
3966
3967 if (!(bt_info&BT_INFO_8723B_1ANT_B_CONNECTION)) {
3968 coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE;
3969 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3970 "[BTCoex], BtInfoNotify(), "
3971 "BT Non-Connected idle!!!\n");
3972 /* connection exists but no busy */
3973 } else if (bt_info == BT_INFO_8723B_1ANT_B_CONNECTION) {
3974 coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE;
3975 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3976 "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
3977 } else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) ||
3978 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) {
3979 coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_SCO_BUSY;
3980 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3981 "[BTCoex], BtInfoNotify(), "
3982 "BT SCO busy!!!\n");
3983 } else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) {
3984 if (BT_8723B_1ANT_BT_STATUS_ACL_BUSY != coex_dm->bt_status)
3985 coex_dm->auto_tdma_adjust = false;
3986
3987 coex_dm->bt_status = BT_8723B_1ANT_BT_STATUS_ACL_BUSY;
3988 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3989 "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
3990 } else {
3991 coex_dm->bt_status =
3992 BT_8723B_1ANT_BT_STATUS_MAX;
3993 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3994 "[BTCoex], BtInfoNotify(), BT Non-Defined state!!\n");
3995 }
3996
3997 if ((BT_8723B_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
3998 (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
3999 (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status))
4000 bt_busy = true;
4001 else
4002 bt_busy = false;
4003 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
4004
4005 halbtc8723b1ant_run_coexist_mechanism(btcoexist);
4006}
4007
4008void ex_halbtc8723b1ant_halt_notify(struct btc_coexist *btcoexist)
4009{
4010 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, "[BTCoex], Halt notify\n");
4011
4012 btcoexist->stop_coex_dm = true;
4013
4014 halbtc8723b1ant_SetAntPath(btcoexist, BTC_ANT_PATH_BT, false, true);
4015
4016 halbtc8723b1ant_wifi_off_hw_cfg(btcoexist);
4017 halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
4018
4019 halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
4020 0x0, 0x0);
4021 halbtc8723b1ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
4022
4023 ex_halbtc8723b1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
4024}
4025
4026void ex_halbtc8723b1ant_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state)
4027{
4028 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, "[BTCoex], Pnp notify\n");
4029
4030 if (BTC_WIFI_PNP_SLEEP == pnp_state) {
4031 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
4032 "[BTCoex], Pnp notify to SLEEP\n");
4033 btcoexist->stop_coex_dm = true;
4034 halbtc8723b1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
4035 halbtc8723b1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE,
4036 0x0, 0x0);
4037 halbtc8723b1ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 9);
4038 } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) {
4039 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
4040 "[BTCoex], Pnp notify to WAKE UP\n");
4041 btcoexist->stop_coex_dm = false;
4042 halbtc8723b1ant_init_hw_config(btcoexist, false);
4043 halbtc8723b1ant_init_coex_dm(btcoexist);
4044 halbtc8723b1ant_query_bt_info(btcoexist);
4045 }
4046}
4047
4048void ex_halbtc8723b1ant_periodical(struct btc_coexist *btcoexist)
4049{
4050 struct btc_board_info *board_info = &btcoexist->board_info;
4051 struct btc_stack_info *stack_info = &btcoexist->stack_info;
4052 static u8 dis_ver_info_cnt = 0;
4053 u32 fw_ver = 0, bt_patch_ver = 0;
4054
4055 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4056 "[BTCoex], =========================="
4057 "Periodical===========================\n");
4058
4059 if (dis_ver_info_cnt <= 5) {
4060 dis_ver_info_cnt += 1;
4061 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4062 "[BTCoex], *************************"
4063 "***************************************\n");
4064 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4065 "[BTCoex], Ant PG Num/ Ant Mech/ "
4066 "Ant Pos = %d/ %d/ %d\n", \
4067 board_info->pg_ant_num, board_info->btdm_ant_num,
4068 board_info->btdm_ant_pos);
4069 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4070 "[BTCoex], BT stack/ hci ext ver = %s / %d\n", \
4071 ((stack_info->profile_notified)? "Yes":"No"),
4072 stack_info->hci_version);
4073 btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
4074 &bt_patch_ver);
4075 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
4076 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4077 "[BTCoex], CoexVer/ FwVer/ PatchVer "
4078 "= %d_%x/ 0x%x/ 0x%x(%d)\n", \
4079 glcoex_ver_date_8723b_1ant,
4080 glcoex_ver_8723b_1ant, fw_ver,
4081 bt_patch_ver, bt_patch_ver);
4082 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4083 "[BTCoex], *****************************"
4084 "***********************************\n");
4085 }
4086
4087#if(BT_AUTO_REPORT_ONLY_8723B_1ANT == 0)
4088 halbtc8723b1ant_query_bt_info(btcoexist);
4089 halbtc8723b1ant_monitor_bt_ctr(btcoexist);
4090 halbtc8723b1ant_monitor_bt_enable_disable(btcoexist);
4091#else
4092 if (halbtc8723b1ant_is_wifi_status_changed(btcoexist) ||
4093 coex_dm->auto_tdma_adjust) {
4094 if (coex_sta->special_pkt_period_cnt > 2)
4095 halbtc8723b1ant_run_coexist_mechanism(btcoexist);
4096 }
4097
4098 coex_sta->special_pkt_period_cnt++;
4099#endif
4100}
4101
4102
4103#endif
4104
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtc8723b1ant.h b/drivers/staging/rtl8821ae/btcoexist/halbtc8723b1ant.h
new file mode 100644
index 000000000000..5ce292f2e7c6
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtc8723b1ant.h
@@ -0,0 +1,175 @@
1/**********************************************************************
2 * The following is for 8723B 1ANT BT Co-exist definition
3 **********************************************************************/
4#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1
5
6#define BT_INFO_8723B_1ANT_B_FTP BIT7
7#define BT_INFO_8723B_1ANT_B_A2DP BIT6
8#define BT_INFO_8723B_1ANT_B_HID BIT5
9#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
10#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
11#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
12#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
13#define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
14
15#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
16 (((_BT_INFO_EXT_&BIT0))? true:false)
17
18#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2
19
20typedef enum _BT_INFO_SRC_8723B_1ANT{
21 BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0,
22 BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1,
23 BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2,
24 BT_INFO_SRC_8723B_1ANT_MAX
25}BT_INFO_SRC_8723B_1ANT,*PBT_INFO_SRC_8723B_1ANT;
26
27typedef enum _BT_8723B_1ANT_BT_STATUS{
28 BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
29 BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
30 BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
31 BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
32 BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
33 BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
34 BT_8723B_1ANT_BT_STATUS_MAX
35}BT_8723B_1ANT_BT_STATUS,*PBT_8723B_1ANT_BT_STATUS;
36
37typedef enum _BT_8723B_1ANT_WIFI_STATUS{
38 BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
39 BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
40 BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
41 BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
42 BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
43 BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
44 BT_8723B_1ANT_WIFI_STATUS_MAX
45}BT_8723B_1ANT_WIFI_STATUS,*PBT_8723B_1ANT_WIFI_STATUS;
46
47typedef enum _BT_8723B_1ANT_COEX_ALGO{
48 BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
49 BT_8723B_1ANT_COEX_ALGO_SCO = 0x1,
50 BT_8723B_1ANT_COEX_ALGO_HID = 0x2,
51 BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3,
52 BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
53 BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5,
54 BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6,
55 BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
56 BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
57 BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
58 BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
59 BT_8723B_1ANT_COEX_ALGO_MAX = 0xb,
60}BT_8723B_1ANT_COEX_ALGO,*PBT_8723B_1ANT_COEX_ALGO;
61
62struct coex_dm_8723b_1ant{
63 /* fw mechanism */
64 bool pre_dec_bt_pwr;
65 bool cur_dec_bt_pwr;
66 u8 pre_fw_dac_swing_lvl;
67 u8 cur_fw_dac_swing_lvl;
68 bool cur_ignore_wlan_act;
69 bool pre_ignore_wlan_act;
70 u8 pre_ps_tdma;
71 u8 cur_ps_tdma;
72 u8 ps_tdma_para[5];
73 u8 ps_tdma_du_adj_type;
74 bool auto_tdma_adjust;
75 bool pre_ps_tdma_on;
76 bool cur_ps_tdma_on;
77 bool pre_bt_auto_report;
78 bool cur_bt_auto_report;
79 u8 pre_lps;
80 u8 cur_lps;
81 u8 pre_rpwm;
82 u8 cur_rpwm;
83
84 /* sw mechanism */
85 bool pre_rf_rx_lpf_shrink;
86 bool cur_rf_rx_lpf_shrink;
87 u32 bt_rf0x1e_backup;
88 bool pre_low_penalty_ra;
89 bool cur_low_penalty_ra;
90 bool pre_dac_swing_on;
91 u32 pre_dac_swing_lvl;
92 bool cur_dac_swing_on;
93 u32 cur_dac_swing_lvl;
94 bool pre_adc_backoff;
95 bool cur_adc_backoff;
96 bool pre_agc_table_en;
97 bool cur_agc_table_en;
98 u32 pre_val0x6c0;
99 u32 cur_val0x6c0;
100 u32 pre_val0x6c4;
101 u32 cur_val0x6c4;
102 u32 pre_val0x6c8;
103 u32 cur_val0x6c8;
104 u8 pre_val0x6cc;
105 u8 cur_val0x6cc;
106 bool limited_dig;
107
108 u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
109 u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
110 u16 backup_retry_limit;
111 u8 backup_ampdu_max_time;
112
113 /* algorithm related */
114 u8 pre_algorithm;
115 u8 cur_algorithm;
116 u8 bt_status;
117 u8 wifi_chnl_info[3];
118
119 u32 prera_mask;
120 u32 curra_mask;
121 u8 pre_arfr_type;
122 u8 cur_arfr_type;
123 u8 pre_retry_limit_type;
124 u8 cur_retry_limit_type;
125 u8 pre_ampdu_time_type;
126 u8 cur_ampdu_time_type;
127
128 u8 error_condition;
129};
130
131struct coex_sta_8723b_1ant{
132 bool bt_link_exist;
133 bool sco_exist;
134 bool a2dp_exist;
135 bool hid_exist;
136 bool pan_exist;
137
138 bool under_lps;
139 bool under_ips;
140 u32 special_pkt_period_cnt;
141 u32 high_priority_tx;
142 u32 high_priority_rx;
143 u32 low_priority_tx;
144 u32 low_priority_rx;
145 u8 bt_rssi;
146 u8 pre_bt_rssi_state;
147 u8 pre_wifi_rssi_state[4];
148 bool c2h_bt_info_req_sent;
149 u8 bt_info_c2h[BT_INFO_SRC_8723B_1ANT_MAX][10];
150 u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_1ANT_MAX];
151 bool c2h_bt_inquiry_page;
152 u8 bt_retry_cnt;
153 u8 bt_info_ext;
154};
155
156/*************************************************************************
157 * The following is interface which will notify coex module.
158 *************************************************************************/
159void ex_halbtc8723b1ant_init_hwconfig(struct btc_coexist *btcoexist);
160void ex_halbtc8723b1ant_init_coex_dm(struct btc_coexist *btcoexist);
161void ex_halbtc8723b1ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
162void ex_halbtc8723b1ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
163void ex_halbtc8723b1ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
164void ex_halbtc8723b1ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
165void ex_halbtc8723b1ant_media_status_notify(struct btc_coexist *btcoexist,
166 u8 type);
167void ex_halbtc8723b1ant_special_packet_notify(struct btc_coexist *btcoexist,
168 u8 type);
169void ex_halbtc8723b1ant_bt_info_notify(struct btc_coexist *btcoexist,
170 u8 *tmpbuf, u8 length);
171void ex_halbtc8723b1ant_halt_notify(struct btc_coexist *btcoexist);
172void ex_halbtc8723b1ant_pnp_notify(struct btc_coexist *btcoexist, u8 pnpState);
173void ex_halbtc8723b1ant_periodical(struct btc_coexist *btcoexist);
174void ex_halbtc8723b1ant_display_coex_info(struct btc_coexist *btcoexist);
175
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtc8723b2ant.c b/drivers/staging/rtl8821ae/btcoexist/halbtc8723b2ant.c
new file mode 100644
index 000000000000..83b1b4218333
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtc8723b2ant.c
@@ -0,0 +1,4185 @@
1/***************************************************************
2 * Description:
3 *
4 * This file is for RTL8723B Co-exist mechanism
5 *
6 * History
7 * 2012/11/15 Cosa first check in.
8 *
9 **************************************************************/
10/**************************************************************
11 * include files
12 **************************************************************/
13#include "halbt_precomp.h"
14#if 1
15/**************************************************************
16 * Global variables, these are static variables
17 **************************************************************/
18static struct coex_dm_8723b_2ant glcoex_dm_8723b_2ant;
19static struct coex_dm_8723b_2ant *coex_dm = &glcoex_dm_8723b_2ant;
20static struct coex_sta_8723b_2ant glcoex_sta_8723b_2ant;
21static struct coex_sta_8723b_2ant *coex_sta = &glcoex_sta_8723b_2ant;
22
23const char *const glbt_info_src_8723b_2ant[] = {
24 "BT Info[wifi fw]",
25 "BT Info[bt rsp]",
26 "BT Info[bt auto report]",
27};
28
29u32 glcoex_ver_date_8723b_2ant = 20131113;
30u32 glcoex_ver_8723b_2ant = 0x3f;
31
32/**************************************************************
33 * local function proto type if needed
34 **************************************************************/
35/**************************************************************
36 * local function start with halbtc8723b2ant_
37 **************************************************************/
38u8 halbtc8723b2ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
39{
40 s32 bt_rssi = 0;
41 u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
42
43 bt_rssi = coex_sta->bt_rssi;
44
45 if (level_num == 2) {
46 if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
47 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
48 if (bt_rssi >= rssi_thresh +
49 BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT) {
50 bt_rssi_state = BTC_RSSI_STATE_HIGH;
51 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
52 "[BTCoex], BT Rssi state "
53 "switch to High\n");
54 } else {
55 bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
56 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
57 "[BTCoex], BT Rssi state "
58 "stay at Low\n");
59 }
60 } else {
61 if (bt_rssi < rssi_thresh) {
62 bt_rssi_state = BTC_RSSI_STATE_LOW;
63 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
64 "[BTCoex], BT Rssi state "
65 "switch to Low\n");
66 } else {
67 bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
68 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
69 "[BTCoex], BT Rssi state "
70 "stay at High\n");
71 }
72 }
73 } else if (level_num == 3) {
74 if (rssi_thresh > rssi_thresh1) {
75 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
76 "[BTCoex], BT Rssi thresh error!!\n");
77 return coex_sta->pre_bt_rssi_state;
78 }
79
80 if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
81 (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
82 if (bt_rssi >= rssi_thresh +
83 BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT) {
84 bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
85 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
86 "[BTCoex], BT Rssi state "
87 "switch to Medium\n");
88 } else {
89 bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
90 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
91 "[BTCoex], BT Rssi state "
92 "stay at Low\n");
93 }
94 } else if ((coex_sta->pre_bt_rssi_state ==
95 BTC_RSSI_STATE_MEDIUM) ||
96 (coex_sta->pre_bt_rssi_state ==
97 BTC_RSSI_STATE_STAY_MEDIUM)) {
98 if (bt_rssi >= rssi_thresh1 +
99 BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT) {
100 bt_rssi_state = BTC_RSSI_STATE_HIGH;
101 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
102 "[BTCoex], BT Rssi state "
103 "switch to High\n");
104 } else if (bt_rssi < rssi_thresh) {
105 bt_rssi_state = BTC_RSSI_STATE_LOW;
106 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
107 "[BTCoex], BT Rssi state "
108 "switch to Low\n");
109 } else {
110 bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
111 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
112 "[BTCoex], BT Rssi state "
113 "stay at Medium\n");
114 }
115 } else {
116 if (bt_rssi < rssi_thresh1) {
117 bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
118 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
119 "[BTCoex], BT Rssi state "
120 "switch to Medium\n");
121 } else {
122 bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
123 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_RSSI_STATE,
124 "[BTCoex], BT Rssi state "
125 "stay at High\n");
126 }
127 }
128 }
129
130 coex_sta->pre_bt_rssi_state = bt_rssi_state;
131
132 return bt_rssi_state;
133}
134
135u8 halbtc8723b2ant_wifi_rssi_state(struct btc_coexist *btcoexist,
136 u8 index, u8 level_num,
137 u8 rssi_thresh, u8 rssi_thresh1)
138{
139 s32 wifi_rssi=0;
140 u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
141
142 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
143
144 if (level_num == 2) {
145 if ((coex_sta->pre_wifi_rssi_state[index] ==
146 BTC_RSSI_STATE_LOW) ||
147 (coex_sta->pre_wifi_rssi_state[index] ==
148 BTC_RSSI_STATE_STAY_LOW)) {
149 if (wifi_rssi >= rssi_thresh +
150 BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT) {
151 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
152 BTC_PRINT(BTC_MSG_ALGORITHM,
153 ALGO_WIFI_RSSI_STATE,
154 "[BTCoex], wifi RSSI state "
155 "switch to High\n");
156 } else {
157 wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
158 BTC_PRINT(BTC_MSG_ALGORITHM,
159 ALGO_WIFI_RSSI_STATE,
160 "[BTCoex], wifi RSSI state "
161 "stay at Low\n");
162 }
163 } else {
164 if (wifi_rssi < rssi_thresh) {
165 wifi_rssi_state = BTC_RSSI_STATE_LOW;
166 BTC_PRINT(BTC_MSG_ALGORITHM,
167 ALGO_WIFI_RSSI_STATE,
168 "[BTCoex], wifi RSSI state "
169 "switch to Low\n");
170 } else {
171 wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
172 BTC_PRINT(BTC_MSG_ALGORITHM,
173 ALGO_WIFI_RSSI_STATE,
174 "[BTCoex], wifi RSSI state "
175 "stay at High\n");
176 }
177 }
178 } else if (level_num == 3) {
179 if (rssi_thresh > rssi_thresh1) {
180 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_WIFI_RSSI_STATE,
181 "[BTCoex], wifi RSSI thresh error!!\n");
182 return coex_sta->pre_wifi_rssi_state[index];
183 }
184
185 if ((coex_sta->pre_wifi_rssi_state[index] ==
186 BTC_RSSI_STATE_LOW) ||
187 (coex_sta->pre_wifi_rssi_state[index] ==
188 BTC_RSSI_STATE_STAY_LOW)) {
189 if(wifi_rssi >= rssi_thresh +
190 BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT) {
191 wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
192 BTC_PRINT(BTC_MSG_ALGORITHM,
193 ALGO_WIFI_RSSI_STATE,
194 "[BTCoex], wifi RSSI state "
195 "switch to Medium\n");
196 } else {
197 wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
198 BTC_PRINT(BTC_MSG_ALGORITHM,
199 ALGO_WIFI_RSSI_STATE,
200 "[BTCoex], wifi RSSI state "
201 "stay at Low\n");
202 }
203 } else if ((coex_sta->pre_wifi_rssi_state[index] ==
204 BTC_RSSI_STATE_MEDIUM) ||
205 (coex_sta->pre_wifi_rssi_state[index] ==
206 BTC_RSSI_STATE_STAY_MEDIUM)) {
207 if (wifi_rssi >= rssi_thresh1 +
208 BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT) {
209 wifi_rssi_state = BTC_RSSI_STATE_HIGH;
210 BTC_PRINT(BTC_MSG_ALGORITHM,
211 ALGO_WIFI_RSSI_STATE,
212 "[BTCoex], wifi RSSI state "
213 "switch to High\n");
214 } else if (wifi_rssi < rssi_thresh) {
215 wifi_rssi_state = BTC_RSSI_STATE_LOW;
216 BTC_PRINT(BTC_MSG_ALGORITHM,
217 ALGO_WIFI_RSSI_STATE,
218 "[BTCoex], wifi RSSI state "
219 "switch to Low\n");
220 } else {
221 wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
222 BTC_PRINT(BTC_MSG_ALGORITHM,
223 ALGO_WIFI_RSSI_STATE,
224 "[BTCoex], wifi RSSI state "
225 "stay at Medium\n");
226 }
227 } else {
228 if (wifi_rssi < rssi_thresh1) {
229 wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
230 BTC_PRINT(BTC_MSG_ALGORITHM,
231 ALGO_WIFI_RSSI_STATE,
232 "[BTCoex], wifi RSSI state "
233 "switch to Medium\n");
234 } else {
235 wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
236 BTC_PRINT(BTC_MSG_ALGORITHM,
237 ALGO_WIFI_RSSI_STATE,
238 "[BTCoex], wifi RSSI state "
239 "stay at High\n");
240 }
241 }
242 }
243
244 coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
245
246 return wifi_rssi_state;
247}
248
249void halbtc8723b2ant_monitor_bt_enable_disable(struct btc_coexist *btcoexist)
250{
251 static bool pre_bt_disabled = false;
252 static u32 bt_disable_cnt = 0;
253 bool bt_active = true, bt_disabled = false;
254
255 /* This function check if bt is disabled */
256 if (coex_sta->high_priority_tx == 0 &&
257 coex_sta->high_priority_rx == 0 &&
258 coex_sta->low_priority_tx == 0 &&
259 coex_sta->low_priority_rx == 0)
260 bt_active = false;
261
262 if (coex_sta->high_priority_tx == 0xffff &&
263 coex_sta->high_priority_rx == 0xffff &&
264 coex_sta->low_priority_tx == 0xffff &&
265 coex_sta->low_priority_rx == 0xffff)
266 bt_active = true;
267
268 if (bt_active) {
269 bt_disable_cnt = 0;
270 bt_disabled = false;
271 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
272 &bt_disabled);
273 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
274 "[BTCoex], BT is enabled !!\n");
275 } else {
276 bt_disable_cnt++;
277 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
278 "[BTCoex], bt all counters=0, %d times!!\n",
279 bt_disable_cnt);
280 if (bt_disable_cnt >= 2) {
281 bt_disabled = true;
282 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
283 &bt_disabled);
284 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
285 "[BTCoex], BT is disabled !!\n");
286 }
287 }
288
289 if (pre_bt_disabled != bt_disabled) {
290 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
291 "[BTCoex], BT is from %s to %s!!\n",
292 (pre_bt_disabled ? "disabled":"enabled"),
293 (bt_disabled ? "disabled":"enabled"));
294
295 pre_bt_disabled = bt_disabled;
296 if (!bt_disabled) {
297 } else {
298 }
299 }
300}
301
302void halbtc8723b2ant_monitor_bt_ctr(struct btc_coexist *btcoexist)
303{
304 u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
305 u32 reg_hp_tx = 0, reg_hp_rx = 0;
306 u32 reg_lp_tx = 0, reg_lp_rx = 0;
307
308 reg_hp_txrx = 0x770;
309 reg_lp_txrx = 0x774;
310
311 u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
312 reg_hp_tx = u32tmp & MASKLWORD;
313 reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
314
315 u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
316 reg_lp_tx = u32tmp & MASKLWORD;
317 reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
318
319 coex_sta->high_priority_tx = reg_hp_tx;
320 coex_sta->high_priority_rx = reg_hp_rx;
321 coex_sta->low_priority_tx = reg_lp_tx;
322 coex_sta->low_priority_rx = reg_lp_rx;
323
324 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
325 "[BTCoex], High Priority Tx/Rx(reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
326 reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
327 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_BT_MONITOR,
328 "[BTCoex], Low Priority Tx/Rx(reg 0x%x)=0x%x(%d)/0x%x(%d)\n",
329 reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
330
331 /* reset counter */
332 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
333}
334
335void halbtc8723b2ant_query_bt_info(struct btc_coexist *btcoexist)
336{
337 u8 h2c_parameter[1] ={0};
338
339 coex_sta->c2h_bt_info_req_sent = true;
340
341 h2c_parameter[0] |= BIT0; /* trigger */
342
343 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
344 "[BTCoex], Query Bt Info, FW write 0x61=0x%x\n",
345 h2c_parameter[0]);
346
347 btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
348}
349
350bool halbtc8723b2ant_is_wifi_status_changed(struct btc_coexist *btcoexist)
351{
352 static bool pre_wifi_busy = false;
353 static bool pre_under_4way = false;
354 static bool pre_bt_hs_on = false;
355 bool wifi_busy = false, under_4way = false, bt_hs_on = false;
356 bool wifi_connected = false;
357
358 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
359 &wifi_connected);
360 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
361 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
362 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS,
363 &under_4way);
364
365 if (wifi_connected) {
366 if (wifi_busy != pre_wifi_busy) {
367 pre_wifi_busy = wifi_busy;
368 return true;
369 }
370
371 if (under_4way != pre_under_4way) {
372 pre_under_4way = under_4way;
373 return true;
374 }
375
376 if (bt_hs_on != pre_bt_hs_on) {
377 pre_bt_hs_on = bt_hs_on;
378 return true;
379 }
380 }
381
382 return false;
383}
384
385void halbtc8723b2ant_update_bt_link_info(struct btc_coexist *btcoexist)
386{
387 /*struct btc_stack_info *stack_info = &btcoexist->stack_info;*/
388 struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
389 bool bt_hs_on = false;
390
391#if(BT_AUTO_REPORT_ONLY_8723B_2ANT == 1) /* profile from bt patch */
392 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
393
394 bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
395 bt_link_info->sco_exist = coex_sta->sco_exist;
396 bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
397 bt_link_info->pan_exist = coex_sta->pan_exist;
398 bt_link_info->hid_exist = coex_sta->hid_exist;
399
400 /* work around for HS mode. */
401 if (bt_hs_on) {
402 bt_link_info->pan_exist = true;
403 bt_link_info->bt_link_exist = true;
404 }
405#else /* profile from bt stack */
406 bt_link_info->bt_link_exist = stack_info->bt_link_exist;
407 bt_link_info->sco_exist = stack_info->sco_exist;
408 bt_link_info->a2dp_exist = stack_info->a2dp_exist;
409 bt_link_info->pan_exist = stack_info->pan_exist;
410 bt_link_info->hid_exist = stack_info->hid_exist;
411
412 /*for win-8 stack HID report error*/
413 if (!stack_info->hid_exist)
414 stack_info->hid_exist = coex_sta->hid_exist;
415 /*sync BTInfo with BT firmware and stack*/
416 /* when stack HID report error, here we use the info from bt fw.*/
417 if (!stack_info->bt_link_exist)
418 stack_info->bt_link_exist = coex_sta->bt_link_exist;
419#endif
420 /* check if Sco only */
421 if (bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
422 !bt_link_info->pan_exist && !bt_link_info->hid_exist)
423 bt_link_info->sco_only = true;
424 else
425 bt_link_info->sco_only = false;
426
427 /* check if A2dp only */
428 if (!bt_link_info->sco_exist && bt_link_info->a2dp_exist &&
429 !bt_link_info->pan_exist && !bt_link_info->hid_exist)
430 bt_link_info->a2dp_only = true;
431 else
432 bt_link_info->a2dp_only = false;
433
434 /* check if Pan only */
435 if (!bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
436 bt_link_info->pan_exist && !bt_link_info->hid_exist)
437 bt_link_info->pan_only = true;
438 else
439 bt_link_info->pan_only = false;
440
441 /* check if Hid only */
442 if (!bt_link_info->sco_exist && !bt_link_info->a2dp_exist &&
443 !bt_link_info->pan_exist && bt_link_info->hid_exist)
444 bt_link_info->hid_only = true;
445 else
446 bt_link_info->hid_only = false;
447}
448
449u8 halbtc8723b2ant_action_algorithm(struct btc_coexist *btcoexist)
450{
451 struct btc_bt_link_info *bt_link_info=&btcoexist->bt_link_info;
452 bool bt_hs_on = false;
453 u8 algorithm = BT_8723B_2ANT_COEX_ALGO_UNDEFINED;
454 u8 num_of_diff_profile = 0;
455
456 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
457
458 if (!bt_link_info->bt_link_exist) {
459 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
460 "[BTCoex], No BT link exists!!!\n");
461 return algorithm;
462 }
463
464 if (bt_link_info->sco_exist)
465 num_of_diff_profile++;
466 if (bt_link_info->hid_exist)
467 num_of_diff_profile++;
468 if (bt_link_info->pan_exist)
469 num_of_diff_profile++;
470 if (bt_link_info->a2dp_exist)
471 num_of_diff_profile++;
472
473 if (num_of_diff_profile == 1) {
474 if (bt_link_info->sco_exist) {
475 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
476 "[BTCoex], SCO only\n");
477 algorithm = BT_8723B_2ANT_COEX_ALGO_SCO;
478 } else {
479 if (bt_link_info->hid_exist) {
480 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
481 "[BTCoex], HID only\n");
482 algorithm = BT_8723B_2ANT_COEX_ALGO_HID;
483 } else if (bt_link_info->a2dp_exist) {
484 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
485 "[BTCoex], A2DP only\n");
486 algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP;
487 } else if (bt_link_info->pan_exist) {
488 if (bt_hs_on) {
489 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
490 "[BTCoex], PAN(HS) only\n");
491 algorithm =
492 BT_8723B_2ANT_COEX_ALGO_PANHS;
493 } else {
494 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
495 "[BTCoex], PAN(EDR) only\n");
496 algorithm =
497 BT_8723B_2ANT_COEX_ALGO_PANEDR;
498 }
499 }
500 }
501 } else if (num_of_diff_profile == 2) {
502 if (bt_link_info->sco_exist) {
503 if (bt_link_info->hid_exist) {
504 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
505 "[BTCoex], SCO + HID\n");
506 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
507 } else if (bt_link_info->a2dp_exist) {
508 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
509 "[BTCoex], SCO + A2DP ==> SCO\n");
510 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
511 } else if (bt_link_info->pan_exist) {
512 if (bt_hs_on) {
513 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
514 "[BTCoex], SCO + PAN(HS)\n");
515 algorithm = BT_8723B_2ANT_COEX_ALGO_SCO;
516 } else {
517 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
518 "[BTCoex], SCO + PAN(EDR)\n");
519 algorithm =
520 BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
521 }
522 }
523 } else {
524 if (bt_link_info->hid_exist &&
525 bt_link_info->a2dp_exist) {
526 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
527 "[BTCoex], HID + A2DP\n");
528 algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP;
529 } else if (bt_link_info->hid_exist &&
530 bt_link_info->pan_exist) {
531 if (bt_hs_on) {
532 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
533 "[BTCoex], HID + PAN(HS)\n");
534 algorithm = BT_8723B_2ANT_COEX_ALGO_HID;
535 } else {
536 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
537 "[BTCoex], HID + PAN(EDR)\n");
538 algorithm =
539 BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
540 }
541 } else if (bt_link_info->pan_exist &&
542 bt_link_info->a2dp_exist) {
543 if (bt_hs_on) {
544 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
545 "[BTCoex], A2DP + PAN(HS)\n");
546 algorithm =
547 BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS;
548 } else {
549 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
550 "[BTCoex],A2DP + PAN(EDR)\n");
551 algorithm =
552 BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP;
553 }
554 }
555 }
556 } else if (num_of_diff_profile == 3) {
557 if (bt_link_info->sco_exist) {
558 if (bt_link_info->hid_exist &&
559 bt_link_info->a2dp_exist) {
560 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
561 "[BTCoex], SCO + HID + A2DP"
562 " ==> HID\n");
563 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
564 } else if (bt_link_info->hid_exist &&
565 bt_link_info->pan_exist) {
566 if (bt_hs_on) {
567 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
568 "[BTCoex], SCO + HID + "
569 "PAN(HS)\n");
570 algorithm =
571 BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
572 } else {
573 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
574 "[BTCoex], SCO + HID + "
575 "PAN(EDR)\n");
576 algorithm =
577 BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
578 }
579 } else if (bt_link_info->pan_exist &&
580 bt_link_info->a2dp_exist) {
581 if (bt_hs_on) {
582 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
583 "[BTCoex], SCO + A2DP + "
584 "PAN(HS)\n");
585 algorithm =
586 BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
587 } else {
588 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
589 "[BTCoex], SCO + A2DP + "
590 "PAN(EDR) ==> HID\n");
591 algorithm =
592 BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
593 }
594 }
595 } else {
596 if (bt_link_info->hid_exist &&
597 bt_link_info->pan_exist &&
598 bt_link_info->a2dp_exist) {
599 if (bt_hs_on) {
600 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
601 "[BTCoex], HID + A2DP + "
602 "PAN(HS)\n");
603 algorithm =
604 BT_8723B_2ANT_COEX_ALGO_HID_A2DP;
605 } else {
606 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
607 "[BTCoex], HID + A2DP + "
608 "PAN(EDR)\n");
609 algorithm =
610 BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
611 }
612 }
613 }
614 } else if (num_of_diff_profile >= 3) {
615 if (bt_link_info->sco_exist) {
616 if (bt_link_info->hid_exist &&
617 bt_link_info->pan_exist &&
618 bt_link_info->a2dp_exist) {
619 if (bt_hs_on) {
620 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
621 "[BTCoex], Error!!! SCO + HID"
622 " + A2DP + PAN(HS)\n");
623 } else {
624 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
625 "[BTCoex], SCO + HID + A2DP +"
626 " PAN(EDR)==>PAN(EDR)+HID\n");
627 algorithm =
628 BT_8723B_2ANT_COEX_ALGO_PANEDR_HID;
629 }
630 }
631 }
632 }
633
634 return algorithm;
635}
636
637bool halbtc8723b2ant_need_to_dec_bt_pwr(struct btc_coexist *btcoexist)
638{
639 bool bRet = false;
640 bool bt_hs_on = false, wifi_connected = false;
641 s32 bt_hs_rssi=0;
642 u8 bt_rssi_state;
643
644 if (!btcoexist->btc_get(btcoexist,
645 BTC_GET_BL_HS_OPERATION, &bt_hs_on))
646 return false;
647 if (!btcoexist->btc_get(btcoexist,
648 BTC_GET_BL_WIFI_CONNECTED, &wifi_connected))
649 return false;
650 if (!btcoexist->btc_get(btcoexist,
651 BTC_GET_S4_HS_RSSI, &bt_hs_rssi))
652 return false;
653
654 bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0);
655
656 if (wifi_connected) {
657 if (bt_hs_on) {
658 if (bt_hs_rssi > 37) {
659 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
660 "[BTCoex], Need to decrease bt "
661 "power for HS mode!!\n");
662 bRet = true;
663 }
664 } else {
665 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
666 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
667 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
668 "[BTCoex], Need to decrease bt "
669 "power for Wifi is connected!!\n");
670 bRet = true;
671 }
672 }
673 }
674
675 return bRet;
676}
677
678void halbtc8723b2ant_set_fw_dac_swing_level(struct btc_coexist *btcoexist,
679 u8 dac_swing_lvl)
680{
681 u8 h2c_parameter[1] ={0};
682
683 /* There are several type of dacswing
684 * 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */
685 h2c_parameter[0] = dac_swing_lvl;
686
687 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
688 "[BTCoex], Set Dac Swing Level=0x%x\n", dac_swing_lvl);
689 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
690 "[BTCoex], FW write 0x64=0x%x\n", h2c_parameter[0]);
691
692 btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
693}
694
695void halbtc8723b2ant_set_fw_dec_bt_pwr(struct btc_coexist *btcoexist,
696 bool dec_bt_pwr)
697{
698 u8 h2c_parameter[1] = {0};
699
700 h2c_parameter[0] = 0;
701
702 if (dec_bt_pwr)
703 h2c_parameter[0] |= BIT1;
704
705 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
706 "[BTCoex], decrease Bt Power : %s, FW write 0x62=0x%x\n",
707 (dec_bt_pwr? "Yes!!":"No!!"), h2c_parameter[0]);
708
709 btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
710}
711
712void halbtc8723b2ant_dec_bt_pwr(struct btc_coexist *btcoexist,
713 bool force_exec, bool dec_bt_pwr)
714{
715 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
716 "[BTCoex], %s Dec BT power = %s\n",
717 (force_exec? "force to":""), (dec_bt_pwr? "ON":"OFF"));
718 coex_dm->cur_dec_bt_pwr = dec_bt_pwr;
719
720 if (!force_exec) {
721 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
722 "[BTCoex], bPreDecBtPwr=%d, bCurDecBtPwr=%d\n",
723 coex_dm->pre_dec_bt_pwr, coex_dm->cur_dec_bt_pwr);
724
725 if (coex_dm->pre_dec_bt_pwr == coex_dm->cur_dec_bt_pwr)
726 return;
727 }
728 halbtc8723b2ant_set_fw_dec_bt_pwr(btcoexist, coex_dm->cur_dec_bt_pwr);
729
730 coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr;
731}
732
733void halbtc8723b2ant_set_bt_auto_report(struct btc_coexist *btcoexist,
734 bool enable_auto_report)
735{
736 u8 h2c_parameter[1] = {0};
737 h2c_parameter[0] = 0;
738
739 if (enable_auto_report)
740 h2c_parameter[0] |= BIT0;
741
742 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
743 "[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n",
744 (enable_auto_report? "Enabled!!":"Disabled!!"),
745 h2c_parameter[0]);
746
747 btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
748}
749
750void halbtc8723b2ant_bt_auto_report(struct btc_coexist *btcoexist,
751 bool force_exec, bool enable_auto_report)
752{
753 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
754 "[BTCoex], %s BT Auto report = %s\n",
755 (force_exec? "force to":""),
756 ((enable_auto_report)? "Enabled":"Disabled"));
757 coex_dm->cur_bt_auto_report = enable_auto_report;
758
759 if (!force_exec) {
760 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
761 "[BTCoex], bPreBtAutoReport=%d, "
762 "bCurBtAutoReport=%d\n",
763 coex_dm->pre_bt_auto_report,
764 coex_dm->cur_bt_auto_report);
765
766 if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
767 return;
768 }
769 halbtc8723b2ant_set_bt_auto_report(btcoexist,
770 coex_dm->cur_bt_auto_report);
771
772 coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
773}
774
775void halbtc8723b2ant_fw_dac_swing_lvl(struct btc_coexist *btcoexist,
776 bool force_exec, u8 fw_dac_swing_lvl)
777{
778 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
779 "[BTCoex], %s set FW Dac Swing level = %d\n",
780 (force_exec? "force to":""), fw_dac_swing_lvl);
781 coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
782
783 if (!force_exec) {
784 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
785 "[BTCoex], preFwDacSwingLvl=%d, "
786 "curFwDacSwingLvl=%d\n",
787 coex_dm->pre_fw_dac_swing_lvl,
788 coex_dm->cur_fw_dac_swing_lvl);
789
790 if(coex_dm->pre_fw_dac_swing_lvl ==
791 coex_dm->cur_fw_dac_swing_lvl)
792 return;
793 }
794
795 halbtc8723b2ant_set_fw_dac_swing_level(btcoexist,
796 coex_dm->cur_fw_dac_swing_lvl);
797 coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
798}
799
800void halbtc8723b2ant_set_sw_rf_rx_lpf_corner(struct btc_coexist *btcoexist,
801 bool rx_rf_shrink_on)
802{
803 if (rx_rf_shrink_on) {
804 /* Shrink RF Rx LPF corner */
805 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
806 "[BTCoex], Shrink RF Rx LPF corner!!\n");
807 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
808 0xfffff, 0xffffc);
809 } else {
810 /* Resume RF Rx LPF corner */
811 /* After initialized, we can use coex_dm->btRf0x1eBackup */
812 if (btcoexist->initilized) {
813 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
814 "[BTCoex], Resume RF Rx LPF corner!!\n");
815 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
816 0xfffff,
817 coex_dm->bt_rf0x1e_backup);
818 }
819 }
820}
821
822void halbtc8723b2ant_rf_shrink(struct btc_coexist *btcoexist,
823 bool force_exec, bool rx_rf_shrink_on)
824{
825 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
826 "[BTCoex], %s turn Rx RF Shrink = %s\n",
827 (force_exec? "force to":""), (rx_rf_shrink_on? "ON":"OFF"));
828 coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
829
830 if (!force_exec) {
831 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
832 "[BTCoex], bPreRfRxLpfShrink=%d, "
833 "bCurRfRxLpfShrink=%d\n",
834 coex_dm->pre_rf_rx_lpf_shrink,
835 coex_dm->cur_rf_rx_lpf_shrink);
836
837 if (coex_dm->pre_rf_rx_lpf_shrink ==
838 coex_dm->cur_rf_rx_lpf_shrink)
839 return;
840 }
841 halbtc8723b2ant_set_sw_rf_rx_lpf_corner(btcoexist,
842 coex_dm->cur_rf_rx_lpf_shrink);
843
844 coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
845}
846
847void halbtc8723b2ant_set_sw_penalty_txrate_adaptive(
848 struct btc_coexist *btcoexist,
849 bool low_penalty_ra)
850{
851 u8 h2c_parameter[6] ={0};
852
853 h2c_parameter[0] = 0x6; /* opCode, 0x6= Retry_Penalty*/
854
855 if (low_penalty_ra) {
856 h2c_parameter[1] |= BIT0;
857 /*normal rate except MCS7/6/5, OFDM54/48/36*/
858 h2c_parameter[2] = 0x00;
859 h2c_parameter[3] = 0xf7; /*MCS7 or OFDM54*/
860 h2c_parameter[4] = 0xf8; /*MCS6 or OFDM48*/
861 h2c_parameter[5] = 0xf9; /*MCS5 or OFDM36*/
862 }
863
864 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
865 "[BTCoex], set WiFi Low-Penalty Retry: %s",
866 (low_penalty_ra? "ON!!":"OFF!!"));
867
868 btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, h2c_parameter);
869}
870
871void halbtc8723b2ant_low_penalty_ra(struct btc_coexist *btcoexist,
872 bool force_exec, bool low_penalty_ra)
873{
874 /*return; */
875 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
876 "[BTCoex], %s turn LowPenaltyRA = %s\n",
877 (force_exec? "force to":""), (low_penalty_ra? "ON":"OFF"));
878 coex_dm->cur_low_penalty_ra = low_penalty_ra;
879
880 if (!force_exec) {
881 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
882 "[BTCoex], bPreLowPenaltyRa=%d, "
883 "bCurLowPenaltyRa=%d\n",
884 coex_dm->pre_low_penalty_ra,
885 coex_dm->cur_low_penalty_ra);
886
887 if (coex_dm->pre_low_penalty_ra == coex_dm->cur_low_penalty_ra)
888 return;
889 }
890 halbtc8723b2ant_set_sw_penalty_txrate_adaptive(btcoexist,
891 coex_dm->cur_low_penalty_ra);
892
893 coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra;
894}
895
896void halbtc8723b2ant_set_dac_swing_reg(struct btc_coexist * btcoexist,
897 u32 level)
898{
899 u8 val = (u8) level;
900 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
901 "[BTCoex], Write SwDacSwing = 0x%x\n", level);
902 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
903}
904
905void halbtc8723b2ant_set_sw_fulltime_dac_swing(struct btc_coexist *btcoexist,
906 bool sw_dac_swing_on,
907 u32 sw_dac_swing_lvl)
908{
909 if(sw_dac_swing_on)
910 halbtc8723b2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
911 else
912 halbtc8723b2ant_set_dac_swing_reg(btcoexist, 0x18);
913}
914
915
916void halbtc8723b2ant_dac_swing(struct btc_coexist *btcoexist,
917 bool force_exec, bool dac_swing_on,
918 u32 dac_swing_lvl)
919{
920 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
921 "[BTCoex], %s turn DacSwing=%s, dac_swing_lvl=0x%x\n",
922 (force_exec? "force to":""),
923 (dac_swing_on? "ON":"OFF"), dac_swing_lvl);
924 coex_dm->cur_dac_swing_on = dac_swing_on;
925 coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
926
927 if (!force_exec) {
928 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
929 "[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl=0x%x,"
930 " bCurDacSwingOn=%d, curDacSwingLvl=0x%x\n",
931 coex_dm->pre_dac_swing_on, coex_dm->pre_dac_swing_lvl,
932 coex_dm->cur_dac_swing_on,
933 coex_dm->cur_dac_swing_lvl);
934
935 if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
936 (coex_dm->pre_dac_swing_lvl == coex_dm->cur_dac_swing_lvl))
937 return;
938 }
939 mdelay(30);
940 halbtc8723b2ant_set_sw_fulltime_dac_swing(btcoexist, dac_swing_on,
941 dac_swing_lvl);
942
943 coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
944 coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
945}
946
947void halbtc8723b2ant_set_adc_backoff(struct btc_coexist *btcoexist,
948 bool adc_backoff)
949{
950 if (adc_backoff) {
951 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
952 "[BTCoex], BB BackOff Level On!\n");
953 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x3);
954 } else {
955 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
956 "[BTCoex], BB BackOff Level Off!\n");
957 btcoexist->btc_write_1byte_bitmask(btcoexist, 0xc05, 0x30, 0x1);
958 }
959}
960
961void halbtc8723b2ant_adc_backoff(struct btc_coexist *btcoexist,
962 bool force_exec, bool adc_backoff)
963{
964 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
965 "[BTCoex], %s turn AdcBackOff = %s\n",
966 (force_exec? "force to":""), (adc_backoff? "ON":"OFF"));
967 coex_dm->cur_adc_back_off = adc_backoff;
968
969 if (!force_exec) {
970 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
971 "[BTCoex], bPreAdcBackOff=%d, bCurAdcBackOff=%d\n",
972 coex_dm->pre_adc_back_off,
973 coex_dm->cur_adc_back_off);
974
975 if (coex_dm->pre_adc_back_off == coex_dm->cur_adc_back_off)
976 return;
977 }
978 halbtc8723b2ant_set_adc_backoff(btcoexist, coex_dm->cur_adc_back_off);
979
980 coex_dm->pre_adc_back_off = coex_dm->cur_adc_back_off;
981}
982
983void halbtc8723b2ant_set_agc_table(struct btc_coexist *btcoexist,
984 bool agc_table_en)
985{
986 u8 rssi_adjust_val = 0;
987
988 /* BB AGC Gain Table */
989 if (agc_table_en) {
990 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
991 "[BTCoex], BB Agc Table On!\n");
992 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6e1A0001);
993 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6d1B0001);
994 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6c1C0001);
995 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6b1D0001);
996 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x6a1E0001);
997 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x691F0001);
998 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x68200001);
999 } else {
1000 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1001 "[BTCoex], BB Agc Table Off!\n");
1002 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
1003 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
1004 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
1005 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
1006 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
1007 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
1008 btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa4200001);
1009 }
1010
1011
1012 /* RF Gain */
1013 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000);
1014 if (agc_table_en) {
1015 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1016 "[BTCoex], Agc Table On!\n");
1017 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b,
1018 0xfffff, 0x38fff);
1019 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b,
1020 0xfffff, 0x38ffe);
1021 } else {
1022 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1023 "[BTCoex], Agc Table Off!\n");
1024 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b,
1025 0xfffff, 0x380c3);
1026 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x3b,
1027 0xfffff, 0x28ce6);
1028 }
1029 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xef, 0xfffff, 0x0);
1030
1031 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x1);
1032
1033 if (agc_table_en) {
1034 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1035 "[BTCoex], Agc Table On!\n");
1036 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40,
1037 0xfffff, 0x38fff);
1038 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40,
1039 0xfffff, 0x38ffe);
1040 } else {
1041 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1042 "[BTCoex], Agc Table Off!\n");
1043 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40,
1044 0xfffff, 0x380c3);
1045 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x40,
1046 0xfffff, 0x28ce6);
1047 }
1048 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0xed, 0xfffff, 0x0);
1049
1050 /* set rssiAdjustVal for wifi module. */
1051 if (agc_table_en)
1052 rssi_adjust_val = 8;
1053 btcoexist->btc_set(btcoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
1054 &rssi_adjust_val);
1055}
1056
1057void halbtc8723b2ant_agc_table(struct btc_coexist *btcoexist,
1058 bool force_exec, bool agc_table_en)
1059{
1060 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
1061 "[BTCoex], %s %s Agc Table\n",
1062 (force_exec? "force to":""),
1063 (agc_table_en? "Enable":"Disable"));
1064 coex_dm->cur_agc_table_en = agc_table_en;
1065
1066 if (!force_exec) {
1067 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1068 "[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n",
1069 coex_dm->pre_agc_table_en, coex_dm->cur_agc_table_en);
1070
1071 if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
1072 return;
1073 }
1074 halbtc8723b2ant_set_agc_table(btcoexist, agc_table_en);
1075
1076 coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
1077}
1078
1079void halbtc8723b2ant_set_coex_table(struct btc_coexist *btcoexist,
1080 u32 val0x6c0, u32 val0x6c4,
1081 u32 val0x6c8, u8 val0x6cc)
1082{
1083 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1084 "[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0);
1085 btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
1086
1087 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1088 "[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4);
1089 btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
1090
1091 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1092 "[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8);
1093 btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
1094
1095 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_EXEC,
1096 "[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc);
1097 btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
1098}
1099
1100void halbtc8723b2ant_coex_table(struct btc_coexist *btcoexist,
1101 bool force_exec, u32 val0x6c0,
1102 u32 val0x6c4, u32 val0x6c8,
1103 u8 val0x6cc)
1104{
1105 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW,
1106 "[BTCoex], %s write Coex Table 0x6c0=0x%x,"
1107 " 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n",
1108 (force_exec? "force to":""), val0x6c0,
1109 val0x6c4, val0x6c8, val0x6cc);
1110 coex_dm->cur_val0x6c0 = val0x6c0;
1111 coex_dm->cur_val0x6c4 = val0x6c4;
1112 coex_dm->cur_val0x6c8 = val0x6c8;
1113 coex_dm->cur_val0x6cc = val0x6cc;
1114
1115 if (!force_exec) {
1116 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1117 "[BTCoex], preVal0x6c0=0x%x, "
1118 "preVal0x6c4=0x%x, preVal0x6c8=0x%x, "
1119 "preVal0x6cc=0x%x !!\n",
1120 coex_dm->pre_val0x6c0, coex_dm->pre_val0x6c4,
1121 coex_dm->pre_val0x6c8, coex_dm->pre_val0x6cc);
1122 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_SW_DETAIL,
1123 "[BTCoex], curVal0x6c0=0x%x, "
1124 "curVal0x6c4=0x%x, curVal0x6c8=0x%x, "
1125 "curVal0x6cc=0x%x !!\n",
1126 coex_dm->cur_val0x6c0, coex_dm->cur_val0x6c4,
1127 coex_dm->cur_val0x6c8, coex_dm->cur_val0x6cc);
1128
1129 if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
1130 (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
1131 (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
1132 (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
1133 return;
1134 }
1135 halbtc8723b2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4,
1136 val0x6c8, val0x6cc);
1137
1138 coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
1139 coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
1140 coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
1141 coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
1142}
1143
1144void halbtc8723b2ant_coex_table_with_type(struct btc_coexist *btcoexist,
1145 bool force_exec, u8 type)
1146{
1147 switch (type) {
1148 case 0:
1149 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x55555555,
1150 0x55555555, 0xffff, 0x3);
1151 break;
1152 case 1:
1153 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x55555555,
1154 0x5afa5afa, 0xffff, 0x3);
1155 break;
1156 case 2:
1157 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
1158 0x5a5a5a5a, 0xffff, 0x3);
1159 break;
1160 case 3:
1161 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0xaaaaaaaa,
1162 0xaaaaaaaa, 0xffff, 0x3);
1163 break;
1164 case 4:
1165 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0xffffffff,
1166 0xffffffff, 0xffff, 0x3);
1167 break;
1168 case 5:
1169 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x5fff5fff,
1170 0x5fff5fff, 0xffff, 0x3);
1171 break;
1172 case 6:
1173 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x55ff55ff,
1174 0x5a5a5a5a, 0xffff, 0x3);
1175 break;
1176 case 7:
1177 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x55ff55ff,
1178 0x5afa5afa, 0xffff, 0x3);
1179 break;
1180 case 8:
1181 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x5aea5aea,
1182 0x5aea5aea, 0xffff, 0x3);
1183 break;
1184 case 9:
1185 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x55ff55ff,
1186 0x5aea5aea, 0xffff, 0x3);
1187 break;
1188 case 10:
1189 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x55ff55ff,
1190 0x5aff5aff, 0xffff, 0x3);
1191 break;
1192 case 11:
1193 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x55ff55ff,
1194 0x5a5f5a5f, 0xffff, 0x3);
1195 break;
1196 case 12:
1197 halbtc8723b2ant_coex_table(btcoexist, force_exec, 0x55ff55ff,
1198 0x5f5f5f5f, 0xffff, 0x3);
1199 break;
1200 default:
1201 break;
1202 }
1203}
1204
1205void halbtc8723b2ant_set_fw_ignore_wlan_act(struct btc_coexist *btcoexist,
1206 bool enable)
1207{
1208 u8 h2c_parameter[1] ={0};
1209
1210 if (enable)
1211 h2c_parameter[0] |= BIT0;/* function enable*/
1212
1213 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
1214 "[BTCoex], set FW for BT Ignore Wlan_Act, "
1215 "FW write 0x63=0x%x\n", h2c_parameter[0]);
1216
1217 btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
1218}
1219
1220void halbtc8723b2ant_ignore_wlan_act(struct btc_coexist *btcoexist,
1221 bool force_exec, bool enable)
1222{
1223 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
1224 "[BTCoex], %s turn Ignore WlanAct %s\n",
1225 (force_exec? "force to":""), (enable? "ON":"OFF"));
1226 coex_dm->cur_ignore_wlan_act = enable;
1227
1228 if (!force_exec) {
1229 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1230 "[BTCoex], bPreIgnoreWlanAct = %d, "
1231 "bCurIgnoreWlanAct = %d!!\n",
1232 coex_dm->pre_ignore_wlan_act,
1233 coex_dm->cur_ignore_wlan_act);
1234
1235 if (coex_dm->pre_ignore_wlan_act ==
1236 coex_dm->cur_ignore_wlan_act)
1237 return;
1238 }
1239 halbtc8723b2ant_set_fw_ignore_wlan_act(btcoexist, enable);
1240
1241 coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
1242}
1243
1244void halbtc8723b2ant_set_fw_ps_tdma(struct btc_coexist *btcoexist, u8 byte1,
1245 u8 byte2, u8 byte3, u8 byte4, u8 byte5)
1246{
1247 u8 h2c_parameter[5] ={0};
1248
1249 h2c_parameter[0] = byte1;
1250 h2c_parameter[1] = byte2;
1251 h2c_parameter[2] = byte3;
1252 h2c_parameter[3] = byte4;
1253 h2c_parameter[4] = byte5;
1254
1255 coex_dm->ps_tdma_para[0] = byte1;
1256 coex_dm->ps_tdma_para[1] = byte2;
1257 coex_dm->ps_tdma_para[2] = byte3;
1258 coex_dm->ps_tdma_para[3] = byte4;
1259 coex_dm->ps_tdma_para[4] = byte5;
1260
1261 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
1262 "[BTCoex], FW write 0x60(5bytes)=0x%x%08x\n",
1263 h2c_parameter[0],
1264 h2c_parameter[1] << 24 | h2c_parameter[2] << 16 |
1265 h2c_parameter[3] << 8 | h2c_parameter[4]);
1266
1267 btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
1268}
1269
1270void halbtc8723b2ant_sw_mechanism1(struct btc_coexist *btcoexist,
1271 bool shrink_rx_lpf, bool low_penalty_ra,
1272 bool limited_dig, bool bt_lna_constrain)
1273{
1274 /*
1275 u32 wifi_bw;
1276
1277 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
1278
1279 if(BTC_WIFI_BW_HT40 != wifi_bw) //only shrink RF Rx LPF for HT40
1280 {
1281 if (shrink_rx_lpf)
1282 shrink_rx_lpf = false;
1283 }
1284 */
1285
1286 halbtc8723b2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
1287 halbtc8723b2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, low_penalty_ra);
1288}
1289
1290void halbtc8723b2ant_sw_mechanism2(struct btc_coexist *btcoexist,
1291 bool agc_table_shift, bool adc_backoff,
1292 bool sw_dac_swing, u32 dac_swing_lvl)
1293{
1294 halbtc8723b2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift);
1295 /*halbtc8723b2ant_adc_backoff(btcoexist, NORMAL_EXEC, adc_backoff);*/
1296 halbtc8723b2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing,
1297 dac_swing_lvl);
1298}
1299
1300void halbtc8723b2ant_set_ant_path(struct btc_coexist *btcoexist,
1301 u8 antpos_type, bool init_hwcfg,
1302 bool wifi_off)
1303{
1304 struct btc_board_info *board_info = &btcoexist->board_info;
1305 u32 fw_ver = 0, u32tmp=0;
1306 bool pg_ext_switch = false;
1307 bool use_ext_switch = false;
1308 u8 h2c_parameter[2] ={0};
1309
1310 btcoexist->btc_get(btcoexist, BTC_GET_BL_EXT_SWITCH, &pg_ext_switch);
1311 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
1312
1313 if ((fw_ver<0xc0000) || pg_ext_switch)
1314 use_ext_switch = true;
1315
1316 if (init_hwcfg) {
1317 /* 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT */
1318 u32tmp = btcoexist->btc_read_4byte(btcoexist, 0x4c);
1319 u32tmp &= ~BIT23;
1320 u32tmp |= BIT24;
1321 btcoexist->btc_write_4byte(btcoexist, 0x4c, u32tmp);
1322
1323 btcoexist->btc_write_1byte(btcoexist, 0x974, 0xff);
1324 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x944, 0x3, 0x3);
1325 btcoexist->btc_write_1byte(btcoexist, 0x930, 0x77);
1326 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x1);
1327
1328 /* Force GNT_BT to low */
1329 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x0);
1330 btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0);
1331
1332 if (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT) {
1333 /* tell firmware "no antenna inverse" */
1334 h2c_parameter[0] = 0;
1335 h2c_parameter[1] = 1; /* ext switch type */
1336 btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
1337 h2c_parameter);
1338 } else {
1339 /* tell firmware "antenna inverse" */
1340 h2c_parameter[0] = 1;
1341 h2c_parameter[1] = 1; /* ext switch type */
1342 btcoexist->btc_fill_h2c(btcoexist, 0x65, 2,
1343 h2c_parameter);
1344 }
1345 }
1346
1347 /* ext switch setting */
1348 if (use_ext_switch) {
1349 /* fixed internal switch S1->WiFi, S0->BT */
1350 btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0);
1351 switch (antpos_type) {
1352 case BTC_ANT_WIFI_AT_MAIN:
1353 /* ext switch main at wifi */
1354 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x92c,
1355 0x3, 0x1);
1356 break;
1357 case BTC_ANT_WIFI_AT_AUX:
1358 /* ext switch aux at wifi */
1359 btcoexist->btc_write_1byte_bitmask(btcoexist,
1360 0x92c, 0x3, 0x2);
1361 break;
1362 }
1363 } else { /* internal switch */
1364 /* fixed ext switch */
1365 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x92c, 0x3, 0x1);
1366 switch (antpos_type) {
1367 case BTC_ANT_WIFI_AT_MAIN:
1368 /* fixed internal switch S1->WiFi, S0->BT */
1369 btcoexist->btc_write_2byte(btcoexist, 0x948, 0x0);
1370 break;
1371 case BTC_ANT_WIFI_AT_AUX:
1372 /* fixed internal switch S0->WiFi, S1->BT */
1373 btcoexist->btc_write_2byte(btcoexist, 0x948, 0x280);
1374 break;
1375 }
1376 }
1377}
1378
1379
1380void halbtc8723b2ant_ps_tdma(struct btc_coexist *btcoexist, bool force_exec,
1381 bool turn_on, u8 type)
1382{
1383
1384 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
1385 "[BTCoex], %s turn %s PS TDMA, type=%d\n",
1386 (force_exec? "force to":""), (turn_on? "ON":"OFF"), type);
1387 coex_dm->cur_ps_tdma_on = turn_on;
1388 coex_dm->cur_ps_tdma = type;
1389
1390 if (!force_exec) {
1391 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1392 "[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n",
1393 coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on);
1394 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1395 "[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n",
1396 coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma);
1397
1398 if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
1399 (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
1400 return;
1401 }
1402 if (turn_on) {
1403 switch (type) {
1404 case 1:
1405 default:
1406 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
1407 0x1a, 0xe1, 0x90);
1408 break;
1409 case 2:
1410 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
1411 0x12, 0xe1, 0x90);
1412 break;
1413 case 3:
1414 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1c,
1415 0x3, 0xf1, 0x90);
1416 break;
1417 case 4:
1418 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x10,
1419 0x03, 0xf1, 0x90);
1420 break;
1421 case 5:
1422 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
1423 0x1a, 0x60, 0x90);
1424 break;
1425 case 6:
1426 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
1427 0x12, 0x60, 0x90);
1428 break;
1429 case 7:
1430 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1c,
1431 0x3, 0x70, 0x90);
1432 break;
1433 case 8:
1434 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xa3, 0x10,
1435 0x3, 0x70, 0x90);
1436 break;
1437 case 9:
1438 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
1439 0x1a, 0xe1, 0x90);
1440 break;
1441 case 10:
1442 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
1443 0x12, 0xe1, 0x90);
1444 break;
1445 case 11:
1446 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0xa,
1447 0xa, 0xe1, 0x90);
1448 break;
1449 case 12:
1450 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x5,
1451 0x5, 0xe1, 0x90);
1452 break;
1453 case 13:
1454 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
1455 0x1a, 0x60, 0x90);
1456 break;
1457 case 14:
1458 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
1459 0x12, 0x60, 0x90);
1460 break;
1461 case 15:
1462 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0xa,
1463 0xa, 0x60, 0x90);
1464 break;
1465 case 16:
1466 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x5,
1467 0x5, 0x60, 0x90);
1468 break;
1469 case 17:
1470 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xa3, 0x2f,
1471 0x2f, 0x60, 0x90);
1472 break;
1473 case 18:
1474 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x5,
1475 0x5, 0xe1, 0x90);
1476 break;
1477 case 19:
1478 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x25,
1479 0x25, 0xe1, 0x90);
1480 break;
1481 case 20:
1482 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x25,
1483 0x25, 0x60, 0x90);
1484 break;
1485 case 21:
1486 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x15,
1487 0x03, 0x70, 0x90);
1488 break;
1489 case 71:
1490 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
1491 0x1a, 0xe1, 0x90);
1492 break;
1493 }
1494 } else {
1495 /* disable PS tdma */
1496 switch (type) {
1497 case 0:
1498 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0x0, 0x0, 0x0,
1499 0x40, 0x0);
1500 break;
1501 case 1:
1502 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0x0, 0x0, 0x0,
1503 0x48, 0x0);
1504 break;
1505 default:
1506 halbtc8723b2ant_set_fw_ps_tdma(btcoexist, 0x0, 0x0, 0x0,
1507 0x40, 0x0);
1508 break;
1509 }
1510 }
1511
1512 /* update pre state */
1513 coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
1514 coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
1515}
1516
1517void halbtc8723b2ant_coex_alloff(struct btc_coexist *btcoexist)
1518{
1519 /* fw all off */
1520 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
1521 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
1522 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
1523
1524 /* sw all off */
1525 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
1526 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
1527
1528 /* hw all off */
1529 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
1530 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
1531}
1532
1533void halbtc8723b2ant_init_coex_dm(struct btc_coexist *btcoexist)
1534{
1535 /* force to reset coex mechanism*/
1536
1537 halbtc8723b2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
1538 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
1539 halbtc8723b2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, false);
1540
1541 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
1542 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
1543}
1544
1545void halbtc8723b2ant_action_bt_inquiry(struct btc_coexist *btcoexist)
1546{
1547 bool wifi_connected = false;
1548 bool low_pwr_disable = true;
1549
1550 btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
1551 &low_pwr_disable);
1552 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
1553 &wifi_connected);
1554
1555 if (wifi_connected) {
1556 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
1557 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
1558 } else {
1559 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
1560 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
1561 }
1562 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
1563 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
1564
1565 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false, false);
1566 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
1567
1568 coex_dm->need_recover_0x948 = true;
1569 coex_dm->backup_0x948 = btcoexist->btc_read_2byte(btcoexist, 0x948);
1570
1571 halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_AUX,
1572 false, false);
1573}
1574
1575bool halbtc8723b2ant_is_common_action(struct btc_coexist *btcoexist)
1576{
1577 bool bCommon = false, wifi_connected = false;
1578 bool wifi_busy = false;
1579 bool bt_hs_on = false, low_pwr_disable = false;
1580
1581 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
1582 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
1583 &wifi_connected);
1584 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
1585
1586 if (!wifi_connected) {
1587 low_pwr_disable = false;
1588 btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
1589 &low_pwr_disable);
1590
1591 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1592 "[BTCoex], Wifi non-connected idle!!\n");
1593
1594 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
1595 0x0);
1596 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
1597 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
1598 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
1599 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
1600
1601 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false, false,
1602 false);
1603 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false, false,
1604 0x18);
1605
1606 bCommon = true;
1607 } else {
1608 if (BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
1609 coex_dm->bt_status) {
1610 low_pwr_disable = false;
1611 btcoexist->btc_set(btcoexist,
1612 BTC_SET_ACT_DISABLE_LOW_POWER,
1613 &low_pwr_disable);
1614
1615 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1616 "[BTCoex], Wifi connected + "
1617 "BT non connected-idle!!\n");
1618
1619 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
1620 0xfffff, 0x0);
1621 halbtc8723b2ant_coex_table_with_type(btcoexist,
1622 NORMAL_EXEC, 0);
1623 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
1624 1);
1625 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
1626 0xb);
1627 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC,
1628 false);
1629
1630 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
1631 false, false);
1632 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
1633 false, 0x18);
1634
1635 bCommon = true;
1636 } else if (BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE ==
1637 coex_dm->bt_status) {
1638 low_pwr_disable = true;
1639 btcoexist->btc_set(btcoexist,
1640 BTC_SET_ACT_DISABLE_LOW_POWER,
1641 &low_pwr_disable);
1642
1643 if(bt_hs_on)
1644 return false;
1645 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1646 "[BTCoex], Wifi connected + "
1647 "BT connected-idle!!\n");
1648
1649 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
1650 0xfffff, 0x0);
1651 halbtc8723b2ant_coex_table_with_type(btcoexist,
1652 NORMAL_EXEC, 0);
1653 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false,
1654 1);
1655 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
1656 0xb);
1657 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC,
1658 false);
1659
1660 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
1661 false, false);
1662 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
1663 false, 0x18);
1664
1665 bCommon = true;
1666 } else {
1667 low_pwr_disable = true;
1668 btcoexist->btc_set(btcoexist,
1669 BTC_SET_ACT_DISABLE_LOW_POWER,
1670 &low_pwr_disable);
1671
1672 if (wifi_busy) {
1673 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1674 "[BTCoex], Wifi Connected-Busy + "
1675 "BT Busy!!\n");
1676 bCommon = false;
1677 } else {
1678 if(bt_hs_on)
1679 return false;
1680
1681 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
1682 "[BTCoex], Wifi Connected-Idle + "
1683 "BT Busy!!\n");
1684
1685 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A,
1686 0x1, 0xfffff, 0x0);
1687 halbtc8723b2ant_coex_table_with_type(btcoexist,
1688 NORMAL_EXEC,
1689 7);
1690 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC,
1691 true, 21);
1692 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist,
1693 NORMAL_EXEC,
1694 0xb);
1695 if (halbtc8723b2ant_need_to_dec_bt_pwr(btcoexist))
1696 halbtc8723b2ant_dec_bt_pwr(btcoexist,
1697 NORMAL_EXEC,
1698 true);
1699 else
1700 halbtc8723b2ant_dec_bt_pwr(btcoexist,
1701 NORMAL_EXEC,
1702 false);
1703 halbtc8723b2ant_sw_mechanism1(btcoexist, false,
1704 false, false,
1705 false);
1706 halbtc8723b2ant_sw_mechanism2(btcoexist, false,
1707 false, false,
1708 0x18);
1709 bCommon = true;
1710 }
1711 }
1712 }
1713
1714 return bCommon;
1715}
1716void halbtc8723b2ant_tdma_duration_adjust(struct btc_coexist *btcoexist,
1717 bool sco_hid, bool tx_pause,
1718 u8 max_interval)
1719{
1720 static s32 up, dn, m, n, wait_count;
1721 /*0: no change, +1: increase WiFi duration, -1: decrease WiFi duration*/
1722 s32 result;
1723 u8 retryCount=0;
1724
1725 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW,
1726 "[BTCoex], TdmaDurationAdjust()\n");
1727
1728 if (!coex_dm->auto_tdma_adjust) {
1729 coex_dm->auto_tdma_adjust = true;
1730 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1731 "[BTCoex], first run TdmaDurationAdjust()!!\n");
1732 if (sco_hid) {
1733 if (tx_pause) {
1734 if (max_interval == 1) {
1735 halbtc8723b2ant_ps_tdma(btcoexist,
1736 NORMAL_EXEC,
1737 true, 13);
1738 coex_dm->ps_tdma_du_adj_type = 13;
1739 }else if (max_interval == 2) {
1740 halbtc8723b2ant_ps_tdma(btcoexist,
1741 NORMAL_EXEC,
1742 true, 14);
1743 coex_dm->ps_tdma_du_adj_type = 14;
1744 } else if (max_interval == 3) {
1745 halbtc8723b2ant_ps_tdma(btcoexist,
1746 NORMAL_EXEC,
1747 true, 15);
1748 coex_dm->ps_tdma_du_adj_type = 15;
1749 } else {
1750 halbtc8723b2ant_ps_tdma(btcoexist,
1751 NORMAL_EXEC,
1752 true, 15);
1753 coex_dm->ps_tdma_du_adj_type = 15;
1754 }
1755 } else {
1756 if(max_interval == 1) {
1757 halbtc8723b2ant_ps_tdma(btcoexist,
1758 NORMAL_EXEC,
1759 true, 9);
1760 coex_dm->ps_tdma_du_adj_type = 9;
1761 } else if (max_interval == 2) {
1762 halbtc8723b2ant_ps_tdma(btcoexist,
1763 NORMAL_EXEC,
1764 true, 10);
1765 coex_dm->ps_tdma_du_adj_type = 10;
1766 } else if (max_interval == 3) {
1767 halbtc8723b2ant_ps_tdma(btcoexist,
1768 NORMAL_EXEC,
1769 true, 11);
1770 coex_dm->ps_tdma_du_adj_type = 11;
1771 } else {
1772 halbtc8723b2ant_ps_tdma(btcoexist,
1773 NORMAL_EXEC,
1774 true, 11);
1775 coex_dm->ps_tdma_du_adj_type = 11;
1776 }
1777 }
1778 } else {
1779 if (tx_pause) {
1780 if (max_interval == 1) {
1781 halbtc8723b2ant_ps_tdma(btcoexist,
1782 NORMAL_EXEC,
1783 true, 5);
1784 coex_dm->ps_tdma_du_adj_type = 5;
1785 } else if (max_interval == 2) {
1786 halbtc8723b2ant_ps_tdma(btcoexist,
1787 NORMAL_EXEC,
1788 true, 6);
1789 coex_dm->ps_tdma_du_adj_type = 6;
1790 } else if (max_interval == 3) {
1791 halbtc8723b2ant_ps_tdma(btcoexist,
1792 NORMAL_EXEC,
1793 true, 7);
1794 coex_dm->ps_tdma_du_adj_type = 7;
1795 } else {
1796 halbtc8723b2ant_ps_tdma(btcoexist,
1797 NORMAL_EXEC,
1798 true, 7);
1799 coex_dm->ps_tdma_du_adj_type = 7;
1800 }
1801 } else {
1802 if (max_interval == 1) {
1803 halbtc8723b2ant_ps_tdma(btcoexist,
1804 NORMAL_EXEC,
1805 true, 1);
1806 coex_dm->ps_tdma_du_adj_type = 1;
1807 } else if (max_interval == 2) {
1808 halbtc8723b2ant_ps_tdma(btcoexist,
1809 NORMAL_EXEC,
1810 true, 2);
1811 coex_dm->ps_tdma_du_adj_type = 2;
1812 } else if (max_interval == 3) {
1813 halbtc8723b2ant_ps_tdma(btcoexist,
1814 NORMAL_EXEC,
1815 true, 3);
1816 coex_dm->ps_tdma_du_adj_type = 3;
1817 } else {
1818 halbtc8723b2ant_ps_tdma(btcoexist,
1819 NORMAL_EXEC,
1820 true, 3);
1821 coex_dm->ps_tdma_du_adj_type = 3;
1822 }
1823 }
1824 }
1825
1826 up = 0;
1827 dn = 0;
1828 m = 1;
1829 n= 3;
1830 result = 0;
1831 wait_count = 0;
1832 } else {
1833 /*accquire the BT TRx retry count from BT_Info byte2*/
1834 retryCount = coex_sta->bt_retry_cnt;
1835 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1836 "[BTCoex], retryCount = %d\n", retryCount);
1837 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1838 "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_count=%d\n",
1839 up, dn, m, n, wait_count);
1840 result = 0;
1841 wait_count++;
1842 /* no retry in the last 2-second duration*/
1843 if (retryCount == 0) {
1844 up++;
1845 dn--;
1846
1847 if (dn <= 0)
1848 dn = 0;
1849
1850 if (up >= n) {
1851 wait_count = 0;
1852 n = 3;
1853 up = 0;
1854 dn = 0;
1855 result = 1;
1856 BTC_PRINT(BTC_MSG_ALGORITHM,
1857 ALGO_TRACE_FW_DETAIL,
1858 "[BTCoex], Increase wifi "
1859 "duration!!\n");
1860 }/* <=3 retry in the last 2-second duration*/
1861 } else if (retryCount <= 3) {
1862 up--;
1863 dn++;
1864
1865 if (up <= 0)
1866 up = 0;
1867
1868 if (dn == 2) {
1869 if (wait_count <= 2)
1870 m++;
1871 else
1872 m = 1;
1873
1874 if (m >= 20)
1875 m = 20;
1876
1877 n = 3 * m;
1878 up = 0;
1879 dn = 0;
1880 wait_count = 0;
1881 result = -1;
1882 BTC_PRINT(BTC_MSG_ALGORITHM,
1883 ALGO_TRACE_FW_DETAIL,
1884 "[BTCoex], Decrease wifi duration "
1885 "for retryCounter<3!!\n");
1886 }
1887 } else {
1888 if (wait_count == 1)
1889 m++;
1890 else
1891 m = 1;
1892
1893 if (m >= 20)
1894 m = 20;
1895
1896 n = 3 * m;
1897 up = 0;
1898 dn = 0;
1899 wait_count = 0;
1900 result = -1;
1901 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1902 "[BTCoex], Decrease wifi duration "
1903 "for retryCounter>3!!\n");
1904 }
1905
1906 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
1907 "[BTCoex], max Interval = %d\n", max_interval);
1908 if (max_interval == 1) {
1909 if (tx_pause) {
1910 BTC_PRINT(BTC_MSG_ALGORITHM,
1911 ALGO_TRACE_FW_DETAIL,
1912 "[BTCoex], TxPause = 1\n");
1913
1914 if (coex_dm->cur_ps_tdma == 71) {
1915 halbtc8723b2ant_ps_tdma(btcoexist,
1916 NORMAL_EXEC,
1917 true, 5);
1918 coex_dm->ps_tdma_du_adj_type = 5;
1919 } else if (coex_dm->cur_ps_tdma == 1) {
1920 halbtc8723b2ant_ps_tdma(btcoexist,
1921 NORMAL_EXEC,
1922 true, 5);
1923 coex_dm->ps_tdma_du_adj_type = 5;
1924 } else if (coex_dm->cur_ps_tdma == 2) {
1925 halbtc8723b2ant_ps_tdma(btcoexist,
1926 NORMAL_EXEC,
1927 true, 6);
1928 coex_dm->ps_tdma_du_adj_type = 6;
1929 } else if (coex_dm->cur_ps_tdma == 3) {
1930 halbtc8723b2ant_ps_tdma(btcoexist,
1931 NORMAL_EXEC,
1932 true, 7);
1933 coex_dm->ps_tdma_du_adj_type = 7;
1934 } else if (coex_dm->cur_ps_tdma == 4) {
1935 halbtc8723b2ant_ps_tdma(btcoexist,
1936 NORMAL_EXEC,
1937 true, 8);
1938 coex_dm->ps_tdma_du_adj_type = 8;
1939 }
1940
1941 if (coex_dm->cur_ps_tdma == 9) {
1942 halbtc8723b2ant_ps_tdma(btcoexist,
1943 NORMAL_EXEC,
1944 true, 13);
1945 coex_dm->ps_tdma_du_adj_type = 13;
1946 } else if (coex_dm->cur_ps_tdma == 10) {
1947 halbtc8723b2ant_ps_tdma(btcoexist,
1948 NORMAL_EXEC,
1949 true, 14);
1950 coex_dm->ps_tdma_du_adj_type = 14;
1951 } else if (coex_dm->cur_ps_tdma == 11) {
1952 halbtc8723b2ant_ps_tdma(btcoexist,
1953 NORMAL_EXEC,
1954 true, 15);
1955 coex_dm->ps_tdma_du_adj_type = 15;
1956 } else if (coex_dm->cur_ps_tdma == 12) {
1957 halbtc8723b2ant_ps_tdma(btcoexist,
1958 NORMAL_EXEC,
1959 true, 16);
1960 coex_dm->ps_tdma_du_adj_type = 16;
1961 }
1962
1963 if (result == -1) {
1964 if (coex_dm->cur_ps_tdma == 5) {
1965 halbtc8723b2ant_ps_tdma(
1966 btcoexist,
1967 NORMAL_EXEC,
1968 true, 6);
1969 coex_dm->ps_tdma_du_adj_type =
1970 6;
1971 } else if (coex_dm->cur_ps_tdma == 6) {
1972 halbtc8723b2ant_ps_tdma(
1973 btcoexist,
1974 NORMAL_EXEC,
1975 true, 7);
1976 coex_dm->ps_tdma_du_adj_type =
1977 7;
1978 } else if (coex_dm->cur_ps_tdma == 7) {
1979 halbtc8723b2ant_ps_tdma(
1980 btcoexist,
1981 NORMAL_EXEC,
1982 true, 8);
1983 coex_dm->ps_tdma_du_adj_type =
1984 8;
1985 } else if (coex_dm->cur_ps_tdma == 13) {
1986 halbtc8723b2ant_ps_tdma(
1987 btcoexist,
1988 NORMAL_EXEC,
1989 true, 14);
1990 coex_dm->ps_tdma_du_adj_type =
1991 14;
1992 } else if(coex_dm->cur_ps_tdma == 14) {
1993 halbtc8723b2ant_ps_tdma(
1994 btcoexist,
1995 NORMAL_EXEC,
1996 true, 15);
1997 coex_dm->ps_tdma_du_adj_type =
1998 15;
1999 } else if(coex_dm->cur_ps_tdma == 15) {
2000 halbtc8723b2ant_ps_tdma(
2001 btcoexist,
2002 NORMAL_EXEC,
2003 true, 16);
2004 coex_dm->ps_tdma_du_adj_type =
2005 16;
2006 }
2007 } else if (result == 1) {
2008 if (coex_dm->cur_ps_tdma == 8) {
2009 halbtc8723b2ant_ps_tdma(
2010 btcoexist,
2011 NORMAL_EXEC,
2012 true, 7);
2013 coex_dm->ps_tdma_du_adj_type =
2014 7;
2015 } else if (coex_dm->cur_ps_tdma == 7) {
2016 halbtc8723b2ant_ps_tdma(
2017 btcoexist,
2018 NORMAL_EXEC,
2019 true, 6);
2020 coex_dm->ps_tdma_du_adj_type =
2021 6;
2022 } else if(coex_dm->cur_ps_tdma == 6) {
2023 halbtc8723b2ant_ps_tdma(
2024 btcoexist,
2025 NORMAL_EXEC,
2026 true, 5);
2027 coex_dm->ps_tdma_du_adj_type =
2028 5;
2029 } else if(coex_dm->cur_ps_tdma == 16) {
2030 halbtc8723b2ant_ps_tdma(
2031 btcoexist,
2032 NORMAL_EXEC,
2033 true, 15);
2034 coex_dm->ps_tdma_du_adj_type =
2035 15;
2036 } else if(coex_dm->cur_ps_tdma == 15) {
2037 halbtc8723b2ant_ps_tdma(
2038 btcoexist,
2039 NORMAL_EXEC,
2040 true, 14);
2041 coex_dm->ps_tdma_du_adj_type =
2042 14;
2043 } else if(coex_dm->cur_ps_tdma == 14) {
2044 halbtc8723b2ant_ps_tdma(
2045 btcoexist,
2046 NORMAL_EXEC,
2047 true, 13);
2048 coex_dm->ps_tdma_du_adj_type =
2049 13;
2050 }
2051 }
2052 } else {
2053 BTC_PRINT(BTC_MSG_ALGORITHM,
2054 ALGO_TRACE_FW_DETAIL,
2055 "[BTCoex], TxPause = 0\n");
2056 if (coex_dm->cur_ps_tdma == 5) {
2057 halbtc8723b2ant_ps_tdma(btcoexist,
2058 NORMAL_EXEC,
2059 true, 71);
2060 coex_dm->ps_tdma_du_adj_type = 71;
2061 } else if (coex_dm->cur_ps_tdma == 6) {
2062 halbtc8723b2ant_ps_tdma(btcoexist,
2063 NORMAL_EXEC,
2064 true, 2);
2065 coex_dm->ps_tdma_du_adj_type = 2;
2066 } else if (coex_dm->cur_ps_tdma == 7) {
2067 halbtc8723b2ant_ps_tdma(btcoexist,
2068 NORMAL_EXEC,
2069 true, 3);
2070 coex_dm->ps_tdma_du_adj_type = 3;
2071 } else if (coex_dm->cur_ps_tdma == 8) {
2072 halbtc8723b2ant_ps_tdma(btcoexist,
2073 NORMAL_EXEC,
2074 true, 4);
2075 coex_dm->ps_tdma_du_adj_type = 4;
2076 }
2077
2078 if (coex_dm->cur_ps_tdma == 13) {
2079 halbtc8723b2ant_ps_tdma(btcoexist,
2080 NORMAL_EXEC,
2081 true, 9);
2082 coex_dm->ps_tdma_du_adj_type = 9;
2083 } else if (coex_dm->cur_ps_tdma == 14) {
2084 halbtc8723b2ant_ps_tdma(btcoexist,
2085 NORMAL_EXEC,
2086 true, 10);
2087 coex_dm->ps_tdma_du_adj_type = 10;
2088 } else if (coex_dm->cur_ps_tdma == 15) {
2089 halbtc8723b2ant_ps_tdma(btcoexist,
2090 NORMAL_EXEC,
2091 true, 11);
2092 coex_dm->ps_tdma_du_adj_type = 11;
2093 } else if(coex_dm->cur_ps_tdma == 16) {
2094 halbtc8723b2ant_ps_tdma(btcoexist,
2095 NORMAL_EXEC,
2096 true, 12);
2097 coex_dm->ps_tdma_du_adj_type = 12;
2098 }
2099
2100 if (result == -1) {
2101 if (coex_dm->cur_ps_tdma == 71) {
2102 halbtc8723b2ant_ps_tdma(
2103 btcoexist,
2104 NORMAL_EXEC,
2105 true, 1);
2106 coex_dm->ps_tdma_du_adj_type =
2107 1;
2108 } else if (coex_dm->cur_ps_tdma == 1) {
2109 halbtc8723b2ant_ps_tdma(
2110 btcoexist,
2111 NORMAL_EXEC,
2112 true, 2);
2113 coex_dm->ps_tdma_du_adj_type =
2114 2;
2115 } else if (coex_dm->cur_ps_tdma == 2) {
2116 halbtc8723b2ant_ps_tdma(
2117 btcoexist,
2118 NORMAL_EXEC,
2119 true, 3);
2120 coex_dm->ps_tdma_du_adj_type =
2121 3;
2122 } else if(coex_dm->cur_ps_tdma == 3) {
2123 halbtc8723b2ant_ps_tdma(
2124 btcoexist,
2125 NORMAL_EXEC,
2126 true, 4);
2127 coex_dm->ps_tdma_du_adj_type =
2128 4;
2129 } else if(coex_dm->cur_ps_tdma == 9) {
2130 halbtc8723b2ant_ps_tdma(
2131 btcoexist,
2132 NORMAL_EXEC,
2133 true, 10);
2134 coex_dm->ps_tdma_du_adj_type =
2135 10;
2136 } else if (coex_dm->cur_ps_tdma == 10) {
2137 halbtc8723b2ant_ps_tdma(
2138 btcoexist,
2139 NORMAL_EXEC,
2140 true, 11);
2141 coex_dm->ps_tdma_du_adj_type =
2142 11;
2143 } else if (coex_dm->cur_ps_tdma == 11) {
2144 halbtc8723b2ant_ps_tdma(
2145 btcoexist,
2146 NORMAL_EXEC,
2147 true, 12);
2148 coex_dm->ps_tdma_du_adj_type =
2149 12;
2150 }
2151 } else if (result == 1) {
2152 if (coex_dm->cur_ps_tdma == 4) {
2153 halbtc8723b2ant_ps_tdma(
2154 btcoexist,
2155 NORMAL_EXEC,
2156 true, 3);
2157 coex_dm->ps_tdma_du_adj_type =
2158 3;
2159 } else if (coex_dm->cur_ps_tdma == 3) {
2160 halbtc8723b2ant_ps_tdma(
2161 btcoexist,
2162 NORMAL_EXEC,
2163 true, 2);
2164 coex_dm->ps_tdma_du_adj_type =
2165 2;
2166 } else if (coex_dm->cur_ps_tdma == 2) {
2167 halbtc8723b2ant_ps_tdma(
2168 btcoexist,
2169 NORMAL_EXEC,
2170 true, 1);
2171 coex_dm->ps_tdma_du_adj_type =
2172 1;
2173 } else if (coex_dm->cur_ps_tdma == 1) {
2174 halbtc8723b2ant_ps_tdma(
2175 btcoexist,
2176 NORMAL_EXEC,
2177 true, 71);
2178 coex_dm->ps_tdma_du_adj_type =
2179 71;
2180 } else if (coex_dm->cur_ps_tdma == 12) {
2181 halbtc8723b2ant_ps_tdma(
2182 btcoexist,
2183 NORMAL_EXEC,
2184 true, 11);
2185 coex_dm->ps_tdma_du_adj_type =
2186 11;
2187 } else if (coex_dm->cur_ps_tdma == 11) {
2188 halbtc8723b2ant_ps_tdma(
2189 btcoexist,
2190 NORMAL_EXEC,
2191 true, 10);
2192 coex_dm->ps_tdma_du_adj_type =
2193 10;
2194 } else if (coex_dm->cur_ps_tdma == 10) {
2195 halbtc8723b2ant_ps_tdma(
2196 btcoexist,
2197 NORMAL_EXEC,
2198 true, 9);
2199 coex_dm->ps_tdma_du_adj_type =
2200 9;
2201 }
2202 }
2203 }
2204 } else if(max_interval == 2) {
2205 if (tx_pause) {
2206 BTC_PRINT(BTC_MSG_ALGORITHM,
2207 ALGO_TRACE_FW_DETAIL,
2208 "[BTCoex], TxPause = 1\n");
2209 if (coex_dm->cur_ps_tdma == 1) {
2210 halbtc8723b2ant_ps_tdma(btcoexist,
2211 NORMAL_EXEC,
2212 true, 6);
2213 coex_dm->ps_tdma_du_adj_type = 6;
2214 } else if (coex_dm->cur_ps_tdma == 2) {
2215 halbtc8723b2ant_ps_tdma(btcoexist,
2216 NORMAL_EXEC,
2217 true, 6);
2218 coex_dm->ps_tdma_du_adj_type = 6;
2219 } else if (coex_dm->cur_ps_tdma == 3) {
2220 halbtc8723b2ant_ps_tdma(btcoexist,
2221 NORMAL_EXEC,
2222 true, 7);
2223 coex_dm->ps_tdma_du_adj_type = 7;
2224 } else if (coex_dm->cur_ps_tdma == 4) {
2225 halbtc8723b2ant_ps_tdma(btcoexist,
2226 NORMAL_EXEC,
2227 true, 8);
2228 coex_dm->ps_tdma_du_adj_type = 8;
2229 }
2230 if (coex_dm->cur_ps_tdma == 9) {
2231 halbtc8723b2ant_ps_tdma(btcoexist,
2232 NORMAL_EXEC,
2233 true, 14);
2234 coex_dm->ps_tdma_du_adj_type = 14;
2235 } else if (coex_dm->cur_ps_tdma == 10) {
2236 halbtc8723b2ant_ps_tdma(btcoexist,
2237 NORMAL_EXEC,
2238 true, 14);
2239 coex_dm->ps_tdma_du_adj_type = 14;
2240 } else if (coex_dm->cur_ps_tdma == 11) {
2241 halbtc8723b2ant_ps_tdma(btcoexist,
2242 NORMAL_EXEC,
2243 true, 15);
2244 coex_dm->ps_tdma_du_adj_type = 15;
2245 } else if (coex_dm->cur_ps_tdma == 12) {
2246 halbtc8723b2ant_ps_tdma(btcoexist,
2247 NORMAL_EXEC,
2248 true, 16);
2249 coex_dm->ps_tdma_du_adj_type = 16;
2250 }
2251 if (result == -1) {
2252 if (coex_dm->cur_ps_tdma == 5) {
2253 halbtc8723b2ant_ps_tdma(
2254 btcoexist,
2255 NORMAL_EXEC,
2256 true, 6);
2257 coex_dm->ps_tdma_du_adj_type =
2258 6;
2259 } else if (coex_dm->cur_ps_tdma == 6) {
2260 halbtc8723b2ant_ps_tdma(
2261 btcoexist,
2262 NORMAL_EXEC,
2263 true, 7);
2264 coex_dm->ps_tdma_du_adj_type =
2265 7;
2266 } else if (coex_dm->cur_ps_tdma == 7) {
2267 halbtc8723b2ant_ps_tdma(
2268 btcoexist,
2269 NORMAL_EXEC,
2270 true, 8);
2271 coex_dm->ps_tdma_du_adj_type =
2272 8;
2273 } else if (coex_dm->cur_ps_tdma == 13) {
2274 halbtc8723b2ant_ps_tdma(
2275 btcoexist,
2276 NORMAL_EXEC,
2277 true, 14);
2278 coex_dm->ps_tdma_du_adj_type =
2279 14;
2280 } else if (coex_dm->cur_ps_tdma == 14) {
2281 halbtc8723b2ant_ps_tdma(
2282 btcoexist,
2283 NORMAL_EXEC,
2284 true, 15);
2285 coex_dm->ps_tdma_du_adj_type =
2286 15;
2287 } else if (coex_dm->cur_ps_tdma == 15) {
2288 halbtc8723b2ant_ps_tdma(
2289 btcoexist,
2290 NORMAL_EXEC,
2291 true, 16);
2292 coex_dm->ps_tdma_du_adj_type =
2293 16;
2294 }
2295 } else if (result == 1) {
2296 if (coex_dm->cur_ps_tdma == 8) {
2297 halbtc8723b2ant_ps_tdma(
2298 btcoexist,
2299 NORMAL_EXEC,
2300 true, 7);
2301 coex_dm->ps_tdma_du_adj_type =
2302 7;
2303 } else if (coex_dm->cur_ps_tdma == 7) {
2304 halbtc8723b2ant_ps_tdma(
2305 btcoexist,
2306 NORMAL_EXEC,
2307 true, 6);
2308 coex_dm->ps_tdma_du_adj_type =
2309 6;
2310 } else if (coex_dm->cur_ps_tdma == 6) {
2311 halbtc8723b2ant_ps_tdma(
2312 btcoexist,
2313 NORMAL_EXEC,
2314 true, 6);
2315 coex_dm->ps_tdma_du_adj_type =
2316 6;
2317 } else if (coex_dm->cur_ps_tdma == 16) {
2318 halbtc8723b2ant_ps_tdma(
2319 btcoexist,
2320 NORMAL_EXEC,
2321 true, 15);
2322 coex_dm->ps_tdma_du_adj_type =
2323 15;
2324 } else if (coex_dm->cur_ps_tdma == 15) {
2325 halbtc8723b2ant_ps_tdma(
2326 btcoexist,
2327 NORMAL_EXEC,
2328 true, 14);
2329 coex_dm->ps_tdma_du_adj_type =
2330 14;
2331 } else if (coex_dm->cur_ps_tdma == 14) {
2332 halbtc8723b2ant_ps_tdma(
2333 btcoexist,
2334 NORMAL_EXEC,
2335 true, 14);
2336 coex_dm->ps_tdma_du_adj_type =
2337 14;
2338 }
2339 }
2340 } else {
2341 BTC_PRINT(BTC_MSG_ALGORITHM,
2342 ALGO_TRACE_FW_DETAIL,
2343 "[BTCoex], TxPause = 0\n");
2344 if (coex_dm->cur_ps_tdma == 5) {
2345 halbtc8723b2ant_ps_tdma(btcoexist,
2346 NORMAL_EXEC,
2347 true, 2);
2348 coex_dm->ps_tdma_du_adj_type = 2;
2349 } else if (coex_dm->cur_ps_tdma == 6) {
2350 halbtc8723b2ant_ps_tdma(btcoexist,
2351 NORMAL_EXEC,
2352 true, 2);
2353 coex_dm->ps_tdma_du_adj_type = 2;
2354 } else if (coex_dm->cur_ps_tdma == 7) {
2355 halbtc8723b2ant_ps_tdma(btcoexist,
2356 NORMAL_EXEC,
2357 true, 3);
2358 coex_dm->ps_tdma_du_adj_type = 3;
2359 } else if (coex_dm->cur_ps_tdma == 8) {
2360 halbtc8723b2ant_ps_tdma(btcoexist,
2361 NORMAL_EXEC,
2362 true, 4);
2363 coex_dm->ps_tdma_du_adj_type = 4;
2364 }
2365 if (coex_dm->cur_ps_tdma == 13) {
2366 halbtc8723b2ant_ps_tdma(btcoexist,
2367 NORMAL_EXEC,
2368 true, 10);
2369 coex_dm->ps_tdma_du_adj_type = 10;
2370 } else if (coex_dm->cur_ps_tdma == 14){
2371 halbtc8723b2ant_ps_tdma(btcoexist,
2372 NORMAL_EXEC,
2373 true, 10);
2374 coex_dm->ps_tdma_du_adj_type = 10;
2375 } else if (coex_dm->cur_ps_tdma == 15) {
2376 halbtc8723b2ant_ps_tdma(btcoexist,
2377 NORMAL_EXEC,
2378 true, 11);
2379 coex_dm->ps_tdma_du_adj_type = 11;
2380 } else if (coex_dm->cur_ps_tdma == 16) {
2381 halbtc8723b2ant_ps_tdma(btcoexist,
2382 NORMAL_EXEC,
2383 true, 12);
2384 coex_dm->ps_tdma_du_adj_type = 12;
2385 }
2386 if (result == -1) {
2387 if (coex_dm->cur_ps_tdma == 1) {
2388 halbtc8723b2ant_ps_tdma(
2389 btcoexist,
2390 NORMAL_EXEC,
2391 true, 2);
2392 coex_dm->ps_tdma_du_adj_type =
2393 2;
2394 } else if (coex_dm->cur_ps_tdma == 2) {
2395 halbtc8723b2ant_ps_tdma(
2396 btcoexist,
2397 NORMAL_EXEC,
2398 true, 3);
2399 coex_dm->ps_tdma_du_adj_type =
2400 3;
2401 } else if (coex_dm->cur_ps_tdma == 3) {
2402 halbtc8723b2ant_ps_tdma(
2403 btcoexist,
2404 NORMAL_EXEC,
2405 true, 4);
2406 coex_dm->ps_tdma_du_adj_type =
2407 4;
2408 } else if (coex_dm->cur_ps_tdma == 9) {
2409 halbtc8723b2ant_ps_tdma(
2410 btcoexist,
2411 NORMAL_EXEC,
2412 true, 10);
2413 coex_dm->ps_tdma_du_adj_type =
2414 10;
2415 } else if (coex_dm->cur_ps_tdma == 10) {
2416 halbtc8723b2ant_ps_tdma(
2417 btcoexist,
2418 NORMAL_EXEC,
2419 true, 11);
2420 coex_dm->ps_tdma_du_adj_type =
2421 11;
2422 } else if (coex_dm->cur_ps_tdma == 11) {
2423 halbtc8723b2ant_ps_tdma(
2424 btcoexist,
2425 NORMAL_EXEC,
2426 true, 12);
2427 coex_dm->ps_tdma_du_adj_type =
2428 12;
2429 }
2430 } else if (result == 1) {
2431 if (coex_dm->cur_ps_tdma == 4) {
2432 halbtc8723b2ant_ps_tdma(
2433 btcoexist,
2434 NORMAL_EXEC,
2435 true, 3);
2436 coex_dm->ps_tdma_du_adj_type =
2437 3;
2438 } else if (coex_dm->cur_ps_tdma == 3) {
2439 halbtc8723b2ant_ps_tdma(
2440 btcoexist,
2441 NORMAL_EXEC,
2442 true, 2);
2443 coex_dm->ps_tdma_du_adj_type =
2444 2;
2445 } else if (coex_dm->cur_ps_tdma == 2) {
2446 halbtc8723b2ant_ps_tdma(
2447 btcoexist,
2448 NORMAL_EXEC,
2449 true, 2);
2450 coex_dm->ps_tdma_du_adj_type =
2451 2;
2452 } else if (coex_dm->cur_ps_tdma == 12) {
2453 halbtc8723b2ant_ps_tdma(
2454 btcoexist,
2455 NORMAL_EXEC,
2456 true, 11);
2457 coex_dm->ps_tdma_du_adj_type =
2458 11;
2459 } else if (coex_dm->cur_ps_tdma == 11) {
2460 halbtc8723b2ant_ps_tdma(
2461 btcoexist,
2462 NORMAL_EXEC,
2463 true, 10);
2464 coex_dm->ps_tdma_du_adj_type =
2465 10;
2466 } else if (coex_dm->cur_ps_tdma == 10) {
2467 halbtc8723b2ant_ps_tdma(
2468 btcoexist,
2469 NORMAL_EXEC,
2470 true, 10);
2471 coex_dm->ps_tdma_du_adj_type =
2472 10;
2473 }
2474 }
2475 }
2476 } else if (max_interval == 3) {
2477 if (tx_pause) {
2478 BTC_PRINT(BTC_MSG_ALGORITHM,
2479 ALGO_TRACE_FW_DETAIL,
2480 "[BTCoex], TxPause = 1\n");
2481 if (coex_dm->cur_ps_tdma == 1) {
2482 halbtc8723b2ant_ps_tdma(btcoexist,
2483 NORMAL_EXEC,
2484 true, 7);
2485 coex_dm->ps_tdma_du_adj_type = 7;
2486 } else if (coex_dm->cur_ps_tdma == 2) {
2487 halbtc8723b2ant_ps_tdma(btcoexist,
2488 NORMAL_EXEC,
2489 true, 7);
2490 coex_dm->ps_tdma_du_adj_type = 7;
2491 } else if (coex_dm->cur_ps_tdma == 3) {
2492 halbtc8723b2ant_ps_tdma(btcoexist,
2493 NORMAL_EXEC,
2494 true, 7);
2495 coex_dm->ps_tdma_du_adj_type = 7;
2496 } else if (coex_dm->cur_ps_tdma == 4) {
2497 halbtc8723b2ant_ps_tdma(btcoexist,
2498 NORMAL_EXEC,
2499 true, 8);
2500 coex_dm->ps_tdma_du_adj_type = 8;
2501 }
2502 if (coex_dm->cur_ps_tdma == 9) {
2503 halbtc8723b2ant_ps_tdma(btcoexist,
2504 NORMAL_EXEC,
2505 true, 15);
2506 coex_dm->ps_tdma_du_adj_type = 15;
2507 } else if (coex_dm->cur_ps_tdma == 10) {
2508 halbtc8723b2ant_ps_tdma(btcoexist,
2509 NORMAL_EXEC,
2510 true, 15);
2511 coex_dm->ps_tdma_du_adj_type = 15;
2512 } else if (coex_dm->cur_ps_tdma == 11) {
2513 halbtc8723b2ant_ps_tdma(btcoexist,
2514 NORMAL_EXEC,
2515 true, 15);
2516 coex_dm->ps_tdma_du_adj_type = 15;
2517 } else if (coex_dm->cur_ps_tdma == 12) {
2518 halbtc8723b2ant_ps_tdma(btcoexist,
2519 NORMAL_EXEC,
2520 true, 16);
2521 coex_dm->ps_tdma_du_adj_type = 16;
2522 }
2523 if (result == -1) {
2524 if (coex_dm->cur_ps_tdma == 5) {
2525 halbtc8723b2ant_ps_tdma(
2526 btcoexist,
2527 NORMAL_EXEC,
2528 true, 7);
2529 coex_dm->ps_tdma_du_adj_type =
2530 7;
2531 } else if (coex_dm->cur_ps_tdma == 6) {
2532 halbtc8723b2ant_ps_tdma(
2533 btcoexist,
2534 NORMAL_EXEC,
2535 true, 7);
2536 coex_dm->ps_tdma_du_adj_type =
2537 7;
2538 } else if (coex_dm->cur_ps_tdma == 7) {
2539 halbtc8723b2ant_ps_tdma(
2540 btcoexist,
2541 NORMAL_EXEC,
2542 true, 8);
2543 coex_dm->ps_tdma_du_adj_type =
2544 8;
2545 } else if (coex_dm->cur_ps_tdma == 13) {
2546 halbtc8723b2ant_ps_tdma(
2547 btcoexist,
2548 NORMAL_EXEC,
2549 true, 15);
2550 coex_dm->ps_tdma_du_adj_type =
2551 15;
2552 } else if (coex_dm->cur_ps_tdma == 14) {
2553 halbtc8723b2ant_ps_tdma(
2554 btcoexist,
2555 NORMAL_EXEC,
2556 true, 15);
2557 coex_dm->ps_tdma_du_adj_type =
2558 15;
2559 } else if (coex_dm->cur_ps_tdma == 15) {
2560 halbtc8723b2ant_ps_tdma(
2561 btcoexist,
2562 NORMAL_EXEC,
2563 true, 16);
2564 coex_dm->ps_tdma_du_adj_type =
2565 16;
2566 }
2567 } else if (result == 1) {
2568 if (coex_dm->cur_ps_tdma == 8) {
2569 halbtc8723b2ant_ps_tdma(
2570 btcoexist,
2571 NORMAL_EXEC,
2572 true, 7);
2573 coex_dm->ps_tdma_du_adj_type =
2574 7;
2575 } else if (coex_dm->cur_ps_tdma == 7) {
2576 halbtc8723b2ant_ps_tdma(
2577 btcoexist,
2578 NORMAL_EXEC,
2579 true, 7);
2580 coex_dm->ps_tdma_du_adj_type =
2581 7;
2582 } else if (coex_dm->cur_ps_tdma == 6) {
2583 halbtc8723b2ant_ps_tdma(
2584 btcoexist,
2585 NORMAL_EXEC,
2586 true, 7);
2587 coex_dm->ps_tdma_du_adj_type =
2588 7;
2589 } else if (coex_dm->cur_ps_tdma == 16) {
2590 halbtc8723b2ant_ps_tdma(
2591 btcoexist,
2592 NORMAL_EXEC,
2593 true, 15);
2594 coex_dm->ps_tdma_du_adj_type =
2595 15;
2596 } else if (coex_dm->cur_ps_tdma == 15) {
2597 halbtc8723b2ant_ps_tdma(
2598 btcoexist,
2599 NORMAL_EXEC,
2600 true, 15);
2601 coex_dm->ps_tdma_du_adj_type =
2602 15;
2603 } else if (coex_dm->cur_ps_tdma == 14) {
2604 halbtc8723b2ant_ps_tdma(
2605 btcoexist,
2606 NORMAL_EXEC,
2607 true, 15);
2608 coex_dm->ps_tdma_du_adj_type =
2609 15;
2610 }
2611 }
2612 } else {
2613 BTC_PRINT(BTC_MSG_ALGORITHM,
2614 ALGO_TRACE_FW_DETAIL,
2615 "[BTCoex], TxPause = 0\n");
2616 if (coex_dm->cur_ps_tdma == 5) {
2617 halbtc8723b2ant_ps_tdma(btcoexist,
2618 NORMAL_EXEC,
2619 true, 3);
2620 coex_dm->ps_tdma_du_adj_type = 3;
2621 } else if (coex_dm->cur_ps_tdma == 6) {
2622 halbtc8723b2ant_ps_tdma(btcoexist,
2623 NORMAL_EXEC,
2624 true, 3);
2625 coex_dm->ps_tdma_du_adj_type = 3;
2626 } else if (coex_dm->cur_ps_tdma == 7) {
2627 halbtc8723b2ant_ps_tdma(btcoexist,
2628 NORMAL_EXEC,
2629 true, 3);
2630 coex_dm->ps_tdma_du_adj_type = 3;
2631 } else if (coex_dm->cur_ps_tdma == 8) {
2632 halbtc8723b2ant_ps_tdma(btcoexist,
2633 NORMAL_EXEC,
2634 true, 4);
2635 coex_dm->ps_tdma_du_adj_type = 4;
2636 }
2637 if (coex_dm->cur_ps_tdma == 13) {
2638 halbtc8723b2ant_ps_tdma(btcoexist,
2639 NORMAL_EXEC,
2640 true, 11);
2641 coex_dm->ps_tdma_du_adj_type = 11;
2642 } else if (coex_dm->cur_ps_tdma == 14) {
2643 halbtc8723b2ant_ps_tdma(btcoexist,
2644 NORMAL_EXEC,
2645 true, 11);
2646 coex_dm->ps_tdma_du_adj_type = 11;
2647 } else if (coex_dm->cur_ps_tdma == 15) {
2648 halbtc8723b2ant_ps_tdma(btcoexist,
2649 NORMAL_EXEC,
2650 true, 11);
2651 coex_dm->ps_tdma_du_adj_type = 11;
2652 } else if (coex_dm->cur_ps_tdma == 16) {
2653 halbtc8723b2ant_ps_tdma(btcoexist,
2654 NORMAL_EXEC,
2655 true, 12);
2656 coex_dm->ps_tdma_du_adj_type = 12;
2657 }
2658 if (result == -1) {
2659 if (coex_dm->cur_ps_tdma == 1) {
2660 halbtc8723b2ant_ps_tdma(
2661 btcoexist,
2662 NORMAL_EXEC,
2663 true, 3);
2664 coex_dm->ps_tdma_du_adj_type =
2665 3;
2666 } else if (coex_dm->cur_ps_tdma == 2) {
2667 halbtc8723b2ant_ps_tdma(
2668 btcoexist,
2669 NORMAL_EXEC,
2670 true, 3);
2671 coex_dm->ps_tdma_du_adj_type =
2672 3;
2673 } else if (coex_dm->cur_ps_tdma == 3) {
2674 halbtc8723b2ant_ps_tdma(
2675 btcoexist,
2676 NORMAL_EXEC,
2677 true, 4);
2678 coex_dm->ps_tdma_du_adj_type =
2679 4;
2680 } else if (coex_dm->cur_ps_tdma == 9) {
2681 halbtc8723b2ant_ps_tdma(
2682 btcoexist,
2683 NORMAL_EXEC,
2684 true, 11);
2685 coex_dm->ps_tdma_du_adj_type =
2686 11;
2687 } else if (coex_dm->cur_ps_tdma == 10) {
2688 halbtc8723b2ant_ps_tdma(
2689 btcoexist,
2690 NORMAL_EXEC,
2691 true, 11);
2692 coex_dm->ps_tdma_du_adj_type =
2693 11;
2694 } else if (coex_dm->cur_ps_tdma == 11) {
2695 halbtc8723b2ant_ps_tdma(
2696 btcoexist,
2697 NORMAL_EXEC,
2698 true, 12);
2699 coex_dm->ps_tdma_du_adj_type =
2700 12;
2701 }
2702 } else if (result == 1) {
2703 if (coex_dm->cur_ps_tdma == 4) {
2704 halbtc8723b2ant_ps_tdma(
2705 btcoexist,
2706 NORMAL_EXEC,
2707 true, 3);
2708 coex_dm->ps_tdma_du_adj_type =
2709 3;
2710 } else if (coex_dm->cur_ps_tdma == 3) {
2711 halbtc8723b2ant_ps_tdma(
2712 btcoexist,
2713 NORMAL_EXEC,
2714 true, 3);
2715 coex_dm->ps_tdma_du_adj_type =
2716 3;
2717 } else if (coex_dm->cur_ps_tdma == 2) {
2718 halbtc8723b2ant_ps_tdma(
2719 btcoexist,
2720 NORMAL_EXEC,
2721 true, 3);
2722 coex_dm->ps_tdma_du_adj_type =
2723 3;
2724 } else if (coex_dm->cur_ps_tdma == 12) {
2725 halbtc8723b2ant_ps_tdma(
2726 btcoexist,
2727 NORMAL_EXEC,
2728 true, 11);
2729 coex_dm->ps_tdma_du_adj_type =
2730 11;
2731 } else if (coex_dm->cur_ps_tdma == 11) {
2732 halbtc8723b2ant_ps_tdma(
2733 btcoexist,
2734 NORMAL_EXEC,
2735 true, 11);
2736 coex_dm->ps_tdma_du_adj_type =
2737 11;
2738 } else if (coex_dm->cur_ps_tdma == 10) {
2739 halbtc8723b2ant_ps_tdma(
2740 btcoexist,
2741 NORMAL_EXEC,
2742 true, 11);
2743 coex_dm->ps_tdma_du_adj_type =
2744 11;
2745 }
2746 }
2747 }
2748 }
2749 }
2750
2751 /*if current PsTdma not match with the recorded one (when scan, dhcp..),
2752 *then we have to adjust it back to the previous record one.*/
2753 if (coex_dm->cur_ps_tdma != coex_dm->ps_tdma_du_adj_type) {
2754 bool scan = false, link = false, roam = false;
2755 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
2756 "[BTCoex], PsTdma type dismatch!!!, "
2757 "curPsTdma=%d, recordPsTdma=%d\n",
2758 coex_dm->cur_ps_tdma, coex_dm->ps_tdma_du_adj_type);
2759
2760 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
2761 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
2762 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
2763
2764 if (!scan && !link && !roam)
2765 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true,
2766 coex_dm->ps_tdma_du_adj_type);
2767 else
2768 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_DETAIL,
2769 "[BTCoex], roaming/link/scan is under"
2770 " progress, will adjust next time!!!\n");
2771 }
2772}
2773
2774/* SCO only or SCO+PAN(HS) */
2775void halbtc8723b2ant_action_sco(struct btc_coexist *btcoexist)
2776{
2777 u8 wifi_rssi_state;
2778 u32 wifi_bw;
2779
2780 wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
2781 0, 2, 15, 0);
2782
2783 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
2784
2785 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 4);
2786
2787 if (halbtc8723b2ant_need_to_dec_bt_pwr(btcoexist))
2788 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
2789 else
2790 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2791
2792 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2793
2794 /*for SCO quality at 11b/g mode*/
2795 if (BTC_WIFI_BW_LEGACY == wifi_bw)
2796 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
2797 else /*for SCO quality & wifi performance balance at 11n mode*/
2798 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8);
2799
2800 /*for voice quality */
2801 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
2802
2803 /* sw mechanism */
2804 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2805 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2806 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2807 halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
2808 false, false);
2809 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
2810 true, 0x4);
2811 } else {
2812 halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
2813 false, false);
2814 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
2815 true, 0x4);
2816 }
2817 } else {
2818 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2819 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2820 halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
2821 false, false);
2822 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
2823 true, 0x4);
2824 } else {
2825 halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
2826 false, false);
2827 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
2828 true, 0x4);
2829 }
2830 }
2831}
2832
2833
2834void halbtc8723b2ant_action_hid(struct btc_coexist *btcoexist)
2835{
2836 u8 wifi_rssi_state, bt_rssi_state;
2837 u32 wifi_bw;
2838
2839 wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
2840 0, 2, 15, 0);
2841 bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0);
2842
2843 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
2844
2845 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2846
2847 if (halbtc8723b2ant_need_to_dec_bt_pwr(btcoexist))
2848 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
2849 else
2850 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2851
2852 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2853
2854 if (BTC_WIFI_BW_LEGACY == wifi_bw) /*/for HID at 11b/g mode*/
2855 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
2856 else /*for HID quality & wifi performance balance at 11n mode*/
2857 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 9);
2858
2859 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
2860 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
2861 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
2862 else
2863 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
2864
2865 /* sw mechanism */
2866 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2867 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2868 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2869 halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
2870 false, false);
2871 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
2872 false, 0x18);
2873 } else {
2874 halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
2875 false, false);
2876 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
2877 false, 0x18);
2878 }
2879 } else {
2880 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2881 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2882 halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
2883 false, false);
2884 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
2885 false, 0x18);
2886 } else {
2887 halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
2888 false, false);
2889 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
2890 false, 0x18);
2891 }
2892 }
2893}
2894
2895/*A2DP only / PAN(EDR) only/ A2DP+PAN(HS)*/
2896void halbtc8723b2ant_action_a2dp(struct btc_coexist *btcoexist)
2897{
2898 u8 wifi_rssi_state, wifi_rssi_state1, bt_rssi_state;
2899 u32 wifi_bw;
2900 u8 ap_num = 0;
2901
2902 wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
2903 0, 2, 15, 0);
2904 wifi_rssi_state1 = halbtc8723b2ant_wifi_rssi_state(btcoexist,
2905 1, 2, 40, 0);
2906 bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0);
2907
2908 btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
2909
2910 /* define the office environment */
2911 /* driver don't know AP num in Linux, so we will never enter this if */
2912 if (ap_num >= 10 && BTC_RSSI_HIGH(wifi_rssi_state1)) {
2913 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
2914 0x0);
2915 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2916 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2917 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
2918 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
2919
2920 /* sw mechanism */
2921 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2922 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2923 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
2924 false, false);
2925 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
2926 true, 0x18);
2927 } else {
2928 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
2929 false, false);
2930 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
2931 true, 0x18);
2932 }
2933 return;
2934 }
2935
2936 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
2937
2938 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2939
2940 if (halbtc8723b2ant_need_to_dec_bt_pwr(btcoexist))
2941 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
2942 else
2943 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
2944
2945 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
2946
2947 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
2948 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
2949 halbtc8723b2ant_tdma_duration_adjust(btcoexist,false, false, 1);
2950 else
2951 halbtc8723b2ant_tdma_duration_adjust(btcoexist,false, true, 1);
2952
2953 /* sw mechanism */
2954 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
2955 if (BTC_WIFI_BW_HT40 == wifi_bw) {
2956 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2957 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2958 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
2959 false, false);
2960 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
2961 false, 0x18);
2962 } else {
2963 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
2964 false, false);
2965 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
2966 false, 0x18);
2967 }
2968 } else {
2969 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
2970 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
2971 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
2972 false, false);
2973 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
2974 false, 0x18);
2975 } else {
2976 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
2977 false, false);
2978 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
2979 false, 0x18);
2980 }
2981 }
2982}
2983
2984void halbtc8723b2ant_action_a2dp_pan_hs(struct btc_coexist *btcoexist)
2985{
2986 u8 wifi_rssi_state;
2987 u32 wifi_bw;
2988
2989 wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
2990 0, 2, 15, 0);
2991
2992 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
2993
2994 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
2995
2996 if (halbtc8723b2ant_need_to_dec_bt_pwr(btcoexist))
2997 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
2998 else
2999 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
3000
3001 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
3002
3003 halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 2);
3004
3005 /* sw mechanism */
3006 btcoexist->btc_get(btcoexist,
3007 BTC_GET_U4_WIFI_BW, &wifi_bw);
3008 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3009 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3010 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3011 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
3012 false, false);
3013 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3014 false, 0x18);
3015 } else {
3016 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
3017 false, false);
3018 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3019 false, 0x18);
3020 }
3021 } else {
3022 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3023 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3024 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
3025 false, false);
3026 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3027 false,0x18);
3028 } else {
3029 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
3030 false, false);
3031 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3032 false, 0x18);
3033 }
3034 }
3035}
3036
3037void halbtc8723b2ant_action_pan_edr(struct btc_coexist *btcoexist)
3038{
3039 u8 wifi_rssi_state, bt_rssi_state;
3040 u32 wifi_bw;
3041
3042 wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
3043 0, 2, 15, 0);
3044 bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0);
3045
3046 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
3047
3048 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
3049
3050 if (halbtc8723b2ant_need_to_dec_bt_pwr(btcoexist))
3051 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
3052 else
3053 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
3054
3055 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 10);
3056
3057 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
3058 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
3059 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
3060 else
3061 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
3062
3063 /* sw mechanism */
3064 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3065 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3066 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3067 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3068 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
3069 false, false);
3070 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3071 false, 0x18);
3072 } else {
3073 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
3074 false, false);
3075 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3076 false, 0x18);
3077 }
3078 } else {
3079 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3080 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3081 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
3082 false, false);
3083 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3084 false, 0x18);
3085 } else {
3086 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
3087 false, false);
3088 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3089 false, 0x18);
3090 }
3091 }
3092}
3093
3094
3095/*PAN(HS) only*/
3096void halbtc8723b2ant_action_pan_hs(struct btc_coexist *btcoexist)
3097{
3098 u8 wifi_rssi_state;
3099 u32 wifi_bw;
3100
3101 wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
3102 0, 2, 15, 0);
3103
3104 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
3105
3106 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
3107
3108 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3109 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH) )
3110 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
3111 else
3112 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
3113
3114 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
3115
3116 halbtc8723b2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
3117
3118 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3119 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3120 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3121 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3122 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
3123 false, false);
3124 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3125 false, 0x18);
3126 } else {
3127 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
3128 false, false);
3129 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3130 false, 0x18);
3131 }
3132 } else {
3133 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3134 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3135 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
3136 false, false);
3137 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3138 false, 0x18);
3139 } else {
3140 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
3141 false, false);
3142 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3143 false, 0x18);
3144 }
3145 }
3146}
3147
3148/*PAN(EDR)+A2DP*/
3149void halbtc8723b2ant_action_pan_edr_a2dp(struct btc_coexist *btcoexist)
3150{
3151 u8 wifi_rssi_state, bt_rssi_state;
3152 u32 wifi_bw;
3153
3154 wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
3155 0, 2, 15, 0);
3156 bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0);
3157
3158 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
3159
3160 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
3161
3162 if (halbtc8723b2ant_need_to_dec_bt_pwr(btcoexist))
3163 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
3164 else
3165 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
3166
3167 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3168
3169 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
3170 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3171 halbtc8723b2ant_coex_table_with_type(btcoexist,NORMAL_EXEC, 12);
3172 if (BTC_WIFI_BW_HT40 == wifi_bw)
3173 halbtc8723b2ant_tdma_duration_adjust(btcoexist, false,
3174 true, 3);
3175 else
3176 halbtc8723b2ant_tdma_duration_adjust(btcoexist, false,
3177 false, 3);
3178 } else {
3179 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
3180 halbtc8723b2ant_tdma_duration_adjust(btcoexist, false, true, 3);
3181 }
3182
3183 /* sw mechanism */
3184 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3185 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3186 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3187 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
3188 false, false);
3189 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3190 false, 0x18);
3191 } else {
3192 halbtc8723b2ant_sw_mechanism1(btcoexist, true, false,
3193 false, false);
3194 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3195 false, 0x18);
3196 }
3197 } else {
3198 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3199 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3200 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
3201 false, false);
3202 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3203 false, 0x18);
3204 } else {
3205 halbtc8723b2ant_sw_mechanism1(btcoexist, false, false,
3206 false, false);
3207 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3208 false, 0x18);
3209 }
3210 }
3211}
3212
3213void halbtc8723b2ant_action_pan_edr_hid(struct btc_coexist *btcoexist)
3214{
3215 u8 wifi_rssi_state, bt_rssi_state;
3216 u32 wifi_bw;
3217
3218 wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
3219 0, 2, 15, 0);
3220 bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0);
3221 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3222
3223 if (halbtc8723b2ant_need_to_dec_bt_pwr(btcoexist))
3224 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
3225 else
3226 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
3227
3228 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
3229 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3230 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3231 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
3232 3);
3233 halbtc8723b2ant_coex_table_with_type(btcoexist,
3234 NORMAL_EXEC, 11);
3235 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
3236 0xfffff, 0x780);
3237 } else {
3238 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC,
3239 6);
3240 halbtc8723b2ant_coex_table_with_type(btcoexist,
3241 NORMAL_EXEC, 7);
3242 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1,
3243 0xfffff, 0x0);
3244 }
3245 halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 2);
3246 } else {
3247 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
3248 halbtc8723b2ant_coex_table_with_type(btcoexist,NORMAL_EXEC, 11);
3249 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff,
3250 0x0);
3251 halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 2);
3252 }
3253
3254 /* sw mechanism */
3255 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3256 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3257 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3258 halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
3259 false, false);
3260 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3261 false, 0x18);
3262 } else {
3263 halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
3264 false, false);
3265 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3266 false, 0x18);
3267 }
3268 } else {
3269 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3270 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)){
3271 halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
3272 false, false);
3273 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3274 false, 0x18);
3275 } else {
3276 halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
3277 false, false);
3278 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3279 false, 0x18);
3280 }
3281 }
3282}
3283
3284/* HID+A2DP+PAN(EDR) */
3285void halbtc8723b2ant_action_hid_a2dp_pan_edr(struct btc_coexist *btcoexist)
3286{
3287 u8 wifi_rssi_state, bt_rssi_state;
3288 u32 wifi_bw;
3289
3290 wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
3291 0, 2, 15, 0);
3292 bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0);
3293
3294 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
3295
3296 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
3297
3298 if (halbtc8723b2ant_need_to_dec_bt_pwr(btcoexist))
3299 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
3300 else
3301 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
3302
3303 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3304
3305 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
3306
3307 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
3308 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3309 if (BTC_WIFI_BW_HT40 == wifi_bw)
3310 halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
3311 true, 2);
3312 else
3313 halbtc8723b2ant_tdma_duration_adjust(btcoexist, true,
3314 false, 3);
3315 } else {
3316 halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 3);
3317 }
3318
3319 /* sw mechanism */
3320 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3321 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3322 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3323 halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
3324 false, false);
3325 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3326 false, 0x18);
3327 } else {
3328 halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
3329 false, false);
3330 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3331 false, 0x18);
3332 }
3333 } else {
3334 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3335 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3336 halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
3337 false, false);
3338 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3339 false, 0x18);
3340 } else {
3341 halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
3342 false, false);
3343 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3344 false, 0x18);
3345 }
3346 }
3347}
3348
3349void halbtc8723b2ant_action_hid_a2dp(struct btc_coexist *btcoexist)
3350{
3351 u8 wifi_rssi_state, bt_rssi_state;
3352 u32 wifi_bw;
3353
3354 wifi_rssi_state = halbtc8723b2ant_wifi_rssi_state(btcoexist,
3355 0, 2, 15, 0);
3356 bt_rssi_state = halbtc8723b2ant_bt_rssi_state(2, 29, 0);
3357
3358 btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0xfffff, 0x0);
3359
3360 halbtc8723b2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
3361
3362 if (halbtc8723b2ant_need_to_dec_bt_pwr(btcoexist))
3363 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, true);
3364 else
3365 halbtc8723b2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, false);
3366
3367 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3368
3369 halbtc8723b2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7);
3370
3371 if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
3372 (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH))
3373 halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, false, 2);
3374 else
3375 halbtc8723b2ant_tdma_duration_adjust(btcoexist, true, true, 2);
3376
3377 /* sw mechanism */
3378 if (BTC_WIFI_BW_HT40 == wifi_bw) {
3379 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3380 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3381 halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
3382 false, false);
3383 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3384 false, 0x18);
3385 } else {
3386 halbtc8723b2ant_sw_mechanism1(btcoexist, true, true,
3387 false, false);
3388 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3389 false, 0x18);
3390 }
3391 } else {
3392 if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
3393 (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
3394 halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
3395 false, false);
3396 halbtc8723b2ant_sw_mechanism2(btcoexist, true, false,
3397 false, 0x18);
3398 } else {
3399 halbtc8723b2ant_sw_mechanism1(btcoexist, false, true,
3400 false, false);
3401 halbtc8723b2ant_sw_mechanism2(btcoexist, false, false,
3402 false, 0x18);
3403 }
3404 }
3405}
3406
3407void halbtc8723b2ant_run_coexist_mechanism(struct btc_coexist *btcoexist)
3408{
3409 u8 algorithm = 0;
3410
3411 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3412 "[BTCoex], RunCoexistMechanism()===>\n");
3413
3414 if (btcoexist->manual_control) {
3415 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3416 "[BTCoex], RunCoexistMechanism(), "
3417 "return for Manual CTRL <===\n");
3418 return;
3419 }
3420
3421 if (coex_sta->under_ips) {
3422 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3423 "[BTCoex], wifi is under IPS !!!\n");
3424 return;
3425 }
3426
3427 algorithm = halbtc8723b2ant_action_algorithm(btcoexist);
3428 if (coex_sta->c2h_bt_inquiry_page &&
3429 (BT_8723B_2ANT_COEX_ALGO_PANHS != algorithm)) {
3430 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3431 "[BTCoex], BT is under inquiry/page scan !!\n");
3432 halbtc8723b2ant_action_bt_inquiry(btcoexist);
3433 return;
3434 } else {
3435 if (coex_dm->need_recover_0x948) {
3436 coex_dm->need_recover_0x948 = false;
3437 btcoexist->btc_write_2byte(btcoexist, 0x948,
3438 coex_dm->backup_0x948);
3439 }
3440 }
3441
3442 coex_dm->cur_algorithm = algorithm;
3443 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, "[BTCoex], Algorithm = %d \n",
3444 coex_dm->cur_algorithm);
3445
3446 if (halbtc8723b2ant_is_common_action(btcoexist)) {
3447 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3448 "[BTCoex], Action 2-Ant common.\n");
3449 coex_dm->auto_tdma_adjust = false;
3450 } else {
3451 if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
3452 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3453 "[BTCoex], preAlgorithm=%d, "
3454 "curAlgorithm=%d\n", coex_dm->pre_algorithm,
3455 coex_dm->cur_algorithm);
3456 coex_dm->auto_tdma_adjust = false;
3457 }
3458 switch (coex_dm->cur_algorithm) {
3459 case BT_8723B_2ANT_COEX_ALGO_SCO:
3460 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3461 "[BTCoex], Action 2-Ant, algorithm = SCO.\n");
3462 halbtc8723b2ant_action_sco(btcoexist);
3463 break;
3464 case BT_8723B_2ANT_COEX_ALGO_HID:
3465 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3466 "[BTCoex], Action 2-Ant, algorithm = HID.\n");
3467 halbtc8723b2ant_action_hid(btcoexist);
3468 break;
3469 case BT_8723B_2ANT_COEX_ALGO_A2DP:
3470 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3471 "[BTCoex], Action 2-Ant, "
3472 "algorithm = A2DP.\n");
3473 halbtc8723b2ant_action_a2dp(btcoexist);
3474 break;
3475 case BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS:
3476 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3477 "[BTCoex], Action 2-Ant, "
3478 "algorithm = A2DP+PAN(HS).\n");
3479 halbtc8723b2ant_action_a2dp_pan_hs(btcoexist);
3480 break;
3481 case BT_8723B_2ANT_COEX_ALGO_PANEDR:
3482 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3483 "[BTCoex], Action 2-Ant, "
3484 "algorithm = PAN(EDR).\n");
3485 halbtc8723b2ant_action_pan_edr(btcoexist);
3486 break;
3487 case BT_8723B_2ANT_COEX_ALGO_PANHS:
3488 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3489 "[BTCoex], Action 2-Ant, "
3490 "algorithm = HS mode.\n");
3491 halbtc8723b2ant_action_pan_hs(btcoexist);
3492 break;
3493 case BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP:
3494 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3495 "[BTCoex], Action 2-Ant, "
3496 "algorithm = PAN+A2DP.\n");
3497 halbtc8723b2ant_action_pan_edr_a2dp(btcoexist);
3498 break;
3499 case BT_8723B_2ANT_COEX_ALGO_PANEDR_HID:
3500 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3501 "[BTCoex], Action 2-Ant, "
3502 "algorithm = PAN(EDR)+HID.\n");
3503 halbtc8723b2ant_action_pan_edr_hid(btcoexist);
3504 break;
3505 case BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
3506 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3507 "[BTCoex], Action 2-Ant, "
3508 "algorithm = HID+A2DP+PAN.\n");
3509 halbtc8723b2ant_action_hid_a2dp_pan_edr(btcoexist);
3510 break;
3511 case BT_8723B_2ANT_COEX_ALGO_HID_A2DP:
3512 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3513 "[BTCoex], Action 2-Ant, "
3514 "algorithm = HID+A2DP.\n");
3515 halbtc8723b2ant_action_hid_a2dp(btcoexist);
3516 break;
3517 default:
3518 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3519 "[BTCoex], Action 2-Ant, "
3520 "algorithm = coexist All Off!!\n");
3521 halbtc8723b2ant_coex_alloff(btcoexist);
3522 break;
3523 }
3524 coex_dm->pre_algorithm = coex_dm->cur_algorithm;
3525 }
3526}
3527
3528void halbtc8723b2ant_wifioff_hwcfg(struct btc_coexist *btcoexist)
3529{
3530 /* set wlan_act to low */
3531 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
3532 /* Force GNT_BT to High */
3533 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x765, 0x18, 0x3);
3534 /* BT select s0/s1 is controlled by BT */
3535 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, 0x0);
3536}
3537
3538/*********************************************************************
3539 * work around function start with wa_halbtc8723b2ant_
3540 *********************************************************************/
3541/*********************************************************************
3542 * extern function start with EXhalbtc8723b2ant_
3543 *********************************************************************/
3544void ex_halbtc8723b2ant_init_hwconfig(struct btc_coexist *btcoexist)
3545{
3546 u8 u8tmp = 0;
3547
3548 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
3549 "[BTCoex], 2Ant Init HW Config!!\n");
3550 coex_dm->bt_rf0x1e_backup =
3551 btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A, 0x1e, 0xfffff);
3552
3553 /* 0x790[5:0]=0x5 */
3554 u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
3555 u8tmp &= 0xc0;
3556 u8tmp |= 0x5;
3557 btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
3558
3559
3560 /*Antenna config */
3561 halbtc8723b2ant_set_ant_path(btcoexist, BTC_ANT_WIFI_AT_MAIN,
3562 true, false);
3563
3564
3565
3566
3567 /* PTA parameter */
3568 halbtc8723b2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
3569
3570 /* Enable counter statistics */
3571 /*0x76e[3] =1, WLAN_Act control by PTA*/
3572 btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
3573 btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
3574 btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1);
3575}
3576
3577void ex_halbtc8723b2ant_init_coex_dm(struct btc_coexist *btcoexist)
3578{
3579 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
3580 "[BTCoex], Coex Mechanism Init!!\n");
3581 halbtc8723b2ant_init_coex_dm(btcoexist);
3582}
3583
3584void ex_halbtc8723b2ant_display_coex_info(struct btc_coexist *btcoexist)
3585{
3586 struct btc_board_info *board_info = &btcoexist->board_info;
3587 struct btc_stack_info *stack_info = &btcoexist->stack_info;
3588 struct btc_bt_link_info* bt_link_info = &btcoexist->bt_link_info;
3589 u8 *cli_buf = btcoexist->cli_buf;
3590 u8 u8tmp[4], i, bt_info_ext, ps_tdma_case=0;
3591 u32 u32tmp[4];
3592 bool roam = false, scan = false;
3593 bool link = false, wifi_under_5g = false;
3594 bool bt_hs_on = false, wifi_busy = false;
3595 s32 wifi_rssi = 0, bt_hs_rssi = 0;
3596 u32 wifi_bw, wifi_traffic_dir, fa_ofdm, fa_cck;
3597 u8 wifi_dot11_chnl, wifi_hs_chnl;
3598 u32 fw_ver = 0, bt_patch_ver = 0;
3599 u8 ap_num = 0;
3600
3601 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3602 "\r\n ============[BT Coexist info]============");
3603 CL_PRINTF(cli_buf);
3604
3605 if (btcoexist->manual_control) {
3606 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3607 "\r\n ==========[Under Manual Control]============");
3608 CL_PRINTF(cli_buf);
3609 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3610 "\r\n ==========================================");
3611 CL_PRINTF(cli_buf);
3612 }
3613
3614 if (!board_info->bt_exist) {
3615 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n BT not exists !!!");
3616 CL_PRINTF(cli_buf);
3617 return;
3618 }
3619
3620 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
3621 "Ant PG number/ Ant mechanism:",
3622 board_info->pg_ant_num, board_info->btdm_ant_num);
3623 CL_PRINTF(cli_buf);
3624
3625 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d",
3626 "BT stack/ hci ext ver",
3627 ((stack_info->profile_notified)? "Yes":"No"),
3628 stack_info->hci_version);
3629 CL_PRINTF(cli_buf);
3630
3631 btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
3632 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
3633 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3634 "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)",
3635 "CoexVer/ fw_ver/ PatchVer",
3636 glcoex_ver_date_8723b_2ant, glcoex_ver_8723b_2ant,
3637 fw_ver, bt_patch_ver, bt_patch_ver);
3638 CL_PRINTF(cli_buf);
3639
3640 btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
3641 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_DOT11_CHNL,
3642 &wifi_dot11_chnl);
3643 btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifi_hs_chnl);
3644
3645 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d(%d)",
3646 "Dot11 channel / HsChnl(HsMode)",
3647 wifi_dot11_chnl, wifi_hs_chnl, bt_hs_on);
3648 CL_PRINTF(cli_buf);
3649
3650 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ",
3651 "H2C Wifi inform bt chnl Info", coex_dm->wifi_chnl_info[0],
3652 coex_dm->wifi_chnl_info[1], coex_dm->wifi_chnl_info[2]);
3653 CL_PRINTF(cli_buf);
3654
3655 btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
3656 btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi);
3657 btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, &ap_num);
3658 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d",
3659 "Wifi rssi/ HS rssi/ AP#", wifi_rssi, bt_hs_rssi, ap_num);
3660 CL_PRINTF(cli_buf);
3661
3662 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
3663 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
3664 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
3665 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
3666 "Wifi link/ roam/ scan", link, roam, scan);
3667 CL_PRINTF(cli_buf);
3668
3669 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
3670 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
3671 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
3672 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
3673 &wifi_traffic_dir);
3674 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s ",
3675 "Wifi status", (wifi_under_5g? "5G":"2.4G"),
3676 ((BTC_WIFI_BW_LEGACY == wifi_bw)? "Legacy":
3677 (((BTC_WIFI_BW_HT40 == wifi_bw)? "HT40":"HT20"))),
3678 ((!wifi_busy)? "idle":
3679 ((BTC_WIFI_TRAFFIC_TX ==wifi_traffic_dir)?\
3680 "uplink":"downlink")));
3681 CL_PRINTF(cli_buf);
3682
3683
3684 CL_PRINTF(cli_buf);
3685
3686 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d",
3687 "SCO/HID/PAN/A2DP",
3688 bt_link_info->sco_exist, bt_link_info->hid_exist,
3689 bt_link_info->pan_exist, bt_link_info->a2dp_exist);
3690 CL_PRINTF(cli_buf);
3691 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
3692
3693 bt_info_ext = coex_sta->bt_info_ext;
3694 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s",
3695 "BT Info A2DP rate",
3696 (bt_info_ext&BIT0)? "Basic rate":"EDR rate");
3697 CL_PRINTF(cli_buf);
3698
3699 for (i=0; i<BT_INFO_SRC_8723B_2ANT_MAX; i++) {
3700 if (coex_sta->bt_info_c2h_cnt[i]) {
3701 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3702 "\r\n %-35s = %02x %02x %02x "
3703 "%02x %02x %02x %02x(%d)",
3704 glbt_info_src_8723b_2ant[i], \
3705 coex_sta->bt_info_c2h[i][0],
3706 coex_sta->bt_info_c2h[i][1],
3707 coex_sta->bt_info_c2h[i][2],
3708 coex_sta->bt_info_c2h[i][3],
3709 coex_sta->bt_info_c2h[i][4],
3710 coex_sta->bt_info_c2h[i][5],
3711 coex_sta->bt_info_c2h[i][6],
3712 coex_sta->bt_info_c2h_cnt[i]);
3713 CL_PRINTF(cli_buf);
3714 }
3715 }
3716
3717 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/%s",
3718 "PS state, IPS/LPS",
3719 ((coex_sta->under_ips? "IPS ON":"IPS OFF")),
3720 ((coex_sta->under_lps? "LPS ON":"LPS OFF")));
3721 CL_PRINTF(cli_buf);
3722 btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD);
3723
3724 /* Sw mechanism */
3725 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3726 "\r\n %-35s", "============[Sw mechanism]============");
3727 CL_PRINTF(cli_buf);
3728 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ",
3729 "SM1[ShRf/ LpRA/ LimDig]", coex_dm->cur_rf_rx_lpf_shrink,
3730 coex_dm->cur_low_penalty_ra, coex_dm->limited_dig);
3731 CL_PRINTF(cli_buf);
3732 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
3733 "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
3734 coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
3735 coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
3736 CL_PRINTF(cli_buf);
3737
3738 /* Fw mechanism */
3739 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
3740 "============[Fw mechanism]============");
3741 CL_PRINTF(cli_buf);
3742
3743 ps_tdma_case = coex_dm->cur_ps_tdma;
3744 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3745 "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)",
3746 "PS TDMA", coex_dm->ps_tdma_para[0],
3747 coex_dm->ps_tdma_para[1], coex_dm->ps_tdma_para[2],
3748 coex_dm->ps_tdma_para[3], coex_dm->ps_tdma_para[4],
3749 ps_tdma_case, coex_dm->auto_tdma_adjust);
3750 CL_PRINTF(cli_buf);
3751
3752 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ",
3753 "DecBtPwr/ IgnWlanAct", coex_dm->cur_dec_bt_pwr,
3754 coex_dm->cur_ignore_wlan_act);
3755 CL_PRINTF(cli_buf);
3756
3757 /* Hw setting */
3758 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s",
3759 "============[Hw setting]============");
3760 CL_PRINTF(cli_buf);
3761
3762 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x",
3763 "RF-A, 0x1e initVal", coex_dm->bt_rf0x1e_backup);
3764 CL_PRINTF(cli_buf);
3765
3766 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
3767 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x880);
3768 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
3769 "0x778/0x880[29:25]", u8tmp[0],
3770 (u32tmp[0]&0x3e000000) >> 25);
3771 CL_PRINTF(cli_buf);
3772
3773
3774 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x948);
3775 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x67);
3776 u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x765);
3777 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
3778 "0x948/ 0x67[5] / 0x765",
3779 u32tmp[0], ((u8tmp[0]&0x20)>> 5), u8tmp[1]);
3780 CL_PRINTF(cli_buf);
3781
3782 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x92c);
3783 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x930);
3784 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x944);
3785 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
3786 "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]",
3787 u32tmp[0]&0x3, u32tmp[1]&0xff, u32tmp[2]&0x3);
3788 CL_PRINTF(cli_buf);
3789
3790
3791 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x39);
3792 u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40);
3793 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c);
3794 u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64);
3795 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
3796 "0x38[11]/0x40/0x4c[24:23]/0x64[0]",
3797 ((u8tmp[0] & 0x8)>>3), u8tmp[1],
3798 ((u32tmp[0]&0x01800000)>>23), u8tmp[2]&0x1);
3799 CL_PRINTF(cli_buf);
3800
3801 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
3802 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
3803 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
3804 "0x550(bcn ctrl)/0x522", u32tmp[0], u8tmp[0]);
3805 CL_PRINTF(cli_buf);
3806
3807 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
3808 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x49c);
3809 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x",
3810 "0xc50(dig)/0x49c(null-drop)", u32tmp[0]&0xff, u8tmp[0]);
3811 CL_PRINTF(cli_buf);
3812
3813 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xda0);
3814 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xda4);
3815 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0xda8);
3816 u32tmp[3] = btcoexist->btc_read_4byte(btcoexist, 0xcf0);
3817
3818 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xa5b);
3819 u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0xa5c);
3820
3821 fa_ofdm = ((u32tmp[0]&0xffff0000) >> 16) +
3822 ((u32tmp[1]&0xffff0000) >> 16) +
3823 (u32tmp[1] & 0xffff) +
3824 (u32tmp[2] & 0xffff) +
3825 ((u32tmp[3]&0xffff0000) >> 16) +
3826 (u32tmp[3] & 0xffff) ;
3827 fa_cck = (u8tmp[0] << 8) + u8tmp[1];
3828
3829 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
3830 "OFDM-CCA/OFDM-FA/CCK-FA", \
3831 u32tmp[0]&0xffff, fa_ofdm, fa_cck);
3832 CL_PRINTF(cli_buf);
3833
3834 u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
3835 u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
3836 u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
3837 u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
3838 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE,
3839 "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
3840 "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \
3841 u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
3842 CL_PRINTF(cli_buf);
3843
3844 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
3845 "0x770(high-pri rx/tx)",
3846 coex_sta->high_priority_rx, coex_sta->high_priority_tx);
3847 CL_PRINTF(cli_buf);
3848 CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d",
3849 "0x774(low-pri rx/tx)", coex_sta->low_priority_rx,
3850 coex_sta->low_priority_tx);
3851 CL_PRINTF(cli_buf);
3852#if(BT_AUTO_REPORT_ONLY_8723B_2ANT == 1)
3853 halbtc8723b2ant_monitor_bt_ctr(btcoexist);
3854#endif
3855 btcoexist->btc_disp_dbg_msg(btcoexist,
3856 BTC_DBG_DISP_COEX_STATISTICS);
3857}
3858
3859
3860void ex_halbtc8723b2ant_ips_notify(struct btc_coexist *btcoexist, u8 type)
3861{
3862 if (BTC_IPS_ENTER == type) {
3863 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3864 "[BTCoex], IPS ENTER notify\n");
3865 coex_sta->under_ips = true;
3866 halbtc8723b2ant_wifioff_hwcfg(btcoexist);
3867 halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
3868 halbtc8723b2ant_coex_alloff(btcoexist);
3869 } else if (BTC_IPS_LEAVE == type) {
3870 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3871 "[BTCoex], IPS LEAVE notify\n");
3872 coex_sta->under_ips = false;
3873 ex_halbtc8723b2ant_init_hwconfig(btcoexist);
3874 halbtc8723b2ant_init_coex_dm(btcoexist);
3875 halbtc8723b2ant_query_bt_info(btcoexist);
3876 }
3877}
3878
3879void ex_halbtc8723b2ant_lps_notify(struct btc_coexist *btcoexist, u8 type)
3880{
3881 if (BTC_LPS_ENABLE == type) {
3882 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3883 "[BTCoex], LPS ENABLE notify\n");
3884 coex_sta->under_lps = true;
3885 } else if (BTC_LPS_DISABLE == type) {
3886 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3887 "[BTCoex], LPS DISABLE notify\n");
3888 coex_sta->under_lps = false;
3889 }
3890}
3891
3892void ex_halbtc8723b2ant_scan_notify(struct btc_coexist *btcoexist, u8 type)
3893{
3894 if (BTC_SCAN_START == type)
3895 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3896 "[BTCoex], SCAN START notify\n");
3897 else if (BTC_SCAN_FINISH == type)
3898 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3899 "[BTCoex], SCAN FINISH notify\n");
3900}
3901
3902void ex_halbtc8723b2ant_connect_notify(struct btc_coexist *btcoexist, u8 type)
3903{
3904 if (BTC_ASSOCIATE_START == type)
3905 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3906 "[BTCoex], CONNECT START notify\n");
3907 else if (BTC_ASSOCIATE_FINISH == type)
3908 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3909 "[BTCoex], CONNECT FINISH notify\n");
3910}
3911
3912void ex_halbtc8723b2ant_media_status_notify(struct btc_coexist *btcoexist,
3913 u8 type)
3914{
3915 u8 h2c_parameter[3] ={0};
3916 u32 wifi_bw;
3917 u8 wifi_central_chnl;
3918
3919 if (BTC_MEDIA_CONNECT == type)
3920 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3921 "[BTCoex], MEDIA connect notify\n");
3922 else
3923 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3924 "[BTCoex], MEDIA disconnect notify\n");
3925
3926 /* only 2.4G we need to inform bt the chnl mask */
3927 btcoexist->btc_get(btcoexist,
3928 BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifi_central_chnl);
3929 if ((BTC_MEDIA_CONNECT == type) &&
3930 (wifi_central_chnl <= 14)) {
3931 h2c_parameter[0] = 0x1;
3932 h2c_parameter[1] = wifi_central_chnl;
3933 btcoexist->btc_get(btcoexist,
3934 BTC_GET_U4_WIFI_BW, &wifi_bw);
3935 if (BTC_WIFI_BW_HT40 == wifi_bw)
3936 h2c_parameter[2] = 0x30;
3937 else
3938 h2c_parameter[2] = 0x20;
3939 }
3940
3941 coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
3942 coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
3943 coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
3944
3945 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE_FW_EXEC,
3946 "[BTCoex], FW write 0x66=0x%x\n",
3947 h2c_parameter[0] << 16 | h2c_parameter[1] << 8 |
3948 h2c_parameter[2]);
3949
3950 btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
3951}
3952
3953void ex_halbtc8723b2ant_special_packet_notify(struct btc_coexist *btcoexist,
3954 u8 type)
3955{
3956 if (type == BTC_PACKET_DHCP)
3957 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3958 "[BTCoex], DHCP Packet notify\n");
3959}
3960
3961void ex_halbtc8723b2ant_bt_info_notify(struct btc_coexist *btcoexist,
3962 u8 *tmpbuf, u8 length)
3963{
3964 u8 btInfo = 0;
3965 u8 i, rsp_source = 0;
3966 bool bt_busy = false, limited_dig = false;
3967 bool wifi_connected = false;
3968
3969 coex_sta->c2h_bt_info_req_sent = false;
3970
3971 rsp_source = tmpbuf[0]&0xf;
3972 if(rsp_source >= BT_INFO_SRC_8723B_2ANT_MAX)
3973 rsp_source = BT_INFO_SRC_8723B_2ANT_WIFI_FW;
3974 coex_sta->bt_info_c2h_cnt[rsp_source]++;
3975
3976 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3977 "[BTCoex], Bt info[%d], length=%d, hex data=[",
3978 rsp_source, length);
3979 for (i = 0; i < length; i++) {
3980 coex_sta->bt_info_c2h[rsp_source][i] = tmpbuf[i];
3981 if (i == 1)
3982 btInfo = tmpbuf[i];
3983 if (i == length-1)
3984 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3985 "0x%02x]\n", tmpbuf[i]);
3986 else
3987 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY,
3988 "0x%02x, ", tmpbuf[i]);
3989 }
3990
3991 if (btcoexist->manual_control) {
3992 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
3993 "[BTCoex], BtInfoNotify(), "
3994 "return for Manual CTRL<===\n");
3995 return;
3996 }
3997
3998 if (BT_INFO_SRC_8723B_2ANT_WIFI_FW != rsp_source) {
3999 coex_sta->bt_retry_cnt = /* [3:0]*/
4000 coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
4001
4002 coex_sta->bt_rssi =
4003 coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
4004
4005 coex_sta->bt_info_ext =
4006 coex_sta->bt_info_c2h[rsp_source][4];
4007
4008 /* Here we need to resend some wifi info to BT
4009 because bt is reset and loss of the info.*/
4010 if ((coex_sta->bt_info_ext & BIT1)) {
4011 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4012 "[BTCoex], BT ext info bit1 check,"
4013 " send wifi BW&Chnl to BT!!\n");
4014 btcoexist->btc_get(btcoexist,BTC_GET_BL_WIFI_CONNECTED,
4015 &wifi_connected);
4016 if (wifi_connected)
4017 ex_halbtc8723b2ant_media_status_notify(
4018 btcoexist,
4019 BTC_MEDIA_CONNECT);
4020 else
4021 ex_halbtc8723b2ant_media_status_notify(
4022 btcoexist,
4023 BTC_MEDIA_DISCONNECT);
4024 }
4025
4026 if ((coex_sta->bt_info_ext & BIT3)) {
4027 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4028 "[BTCoex], BT ext info bit3 check, "
4029 "set BT NOT to ignore Wlan active!!\n");
4030 halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC,
4031 false);
4032 } else {
4033 /* BT already NOT ignore Wlan active, do nothing here.*/
4034 }
4035#if(BT_AUTO_REPORT_ONLY_8723B_2ANT == 0)
4036 if ((coex_sta->bt_info_ext & BIT4)) {
4037 /* BT auto report already enabled, do nothing*/
4038 } else {
4039 halbtc8723b2ant_bt_auto_report(btcoexist, FORCE_EXEC,
4040 true);
4041 }
4042#endif
4043 }
4044
4045 /* check BIT2 first ==> check if bt is under inquiry or page scan*/
4046 if (btInfo & BT_INFO_8723B_2ANT_B_INQ_PAGE)
4047 coex_sta->c2h_bt_inquiry_page = true;
4048 else
4049 coex_sta->c2h_bt_inquiry_page = false;
4050
4051 /* set link exist status*/
4052 if (!(btInfo & BT_INFO_8723B_2ANT_B_CONNECTION)) {
4053 coex_sta->bt_link_exist = false;
4054 coex_sta->pan_exist = false;
4055 coex_sta->a2dp_exist = false;
4056 coex_sta->hid_exist = false;
4057 coex_sta->sco_exist = false;
4058 } else {// connection exists
4059 coex_sta->bt_link_exist = true;
4060 if (btInfo & BT_INFO_8723B_2ANT_B_FTP)
4061 coex_sta->pan_exist = true;
4062 else
4063 coex_sta->pan_exist = false;
4064 if (btInfo & BT_INFO_8723B_2ANT_B_A2DP)
4065 coex_sta->a2dp_exist = true;
4066 else
4067 coex_sta->a2dp_exist = false;
4068 if (btInfo & BT_INFO_8723B_2ANT_B_HID)
4069 coex_sta->hid_exist = true;
4070 else
4071 coex_sta->hid_exist = false;
4072 if (btInfo & BT_INFO_8723B_2ANT_B_SCO_ESCO)
4073 coex_sta->sco_exist = true;
4074 else
4075 coex_sta->sco_exist = false;
4076 }
4077
4078 halbtc8723b2ant_update_bt_link_info(btcoexist);
4079
4080 if (!(btInfo & BT_INFO_8723B_2ANT_B_CONNECTION)) {
4081 coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
4082 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4083 "[BTCoex], BtInfoNotify(), "
4084 "BT Non-Connected idle!!!\n");
4085 /* connection exists but no busy */
4086 } else if (btInfo == BT_INFO_8723B_2ANT_B_CONNECTION) {
4087 coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE;
4088 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4089 "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n");
4090 } else if ((btInfo & BT_INFO_8723B_2ANT_B_SCO_ESCO) ||
4091 (btInfo & BT_INFO_8723B_2ANT_B_SCO_BUSY)) {
4092 coex_dm->bt_status =
4093 BT_8723B_2ANT_BT_STATUS_SCO_BUSY;
4094 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4095 "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n");
4096 } else if (btInfo&BT_INFO_8723B_2ANT_B_ACL_BUSY) {
4097 coex_dm->bt_status =
4098 BT_8723B_2ANT_BT_STATUS_ACL_BUSY;
4099 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4100 "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n");
4101 } else {
4102 coex_dm->bt_status = BT_8723B_2ANT_BT_STATUS_MAX;
4103 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4104 "[BTCoex], BtInfoNotify(), "
4105 "BT Non-Defined state!!!\n");
4106 }
4107
4108 if ((BT_8723B_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
4109 (BT_8723B_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
4110 (BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
4111 bt_busy = true;
4112 limited_dig = true;
4113 } else {
4114 bt_busy = false;
4115 limited_dig = false;
4116 }
4117
4118 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
4119
4120 coex_dm->limited_dig = limited_dig;
4121 btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
4122
4123 halbtc8723b2ant_run_coexist_mechanism(btcoexist);
4124}
4125
4126void ex_halbtc8723b2ant_halt_notify(struct btc_coexist *btcoexist)
4127{
4128 BTC_PRINT(BTC_MSG_INTERFACE, INTF_NOTIFY, "[BTCoex], Halt notify\n");
4129
4130 halbtc8723b2ant_wifioff_hwcfg(btcoexist);
4131 halbtc8723b2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
4132 ex_halbtc8723b2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
4133}
4134
4135void ex_halbtc8723b2ant_periodical(struct btc_coexist *btcoexist)
4136{
4137 struct btc_board_info *board_info = &btcoexist->board_info;
4138 struct btc_stack_info *stack_info = &btcoexist->stack_info;
4139 static u8 dis_ver_info_cnt = 0;
4140 u32 fw_ver = 0, bt_patch_ver = 0;
4141
4142 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
4143 "[BTCoex], =========================="
4144 "Periodical===========================\n");
4145
4146 if (dis_ver_info_cnt <= 5) {
4147 dis_ver_info_cnt += 1;
4148 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4149 "[BTCoex], ****************************"
4150 "************************************\n");
4151 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4152 "[BTCoex], Ant PG Num/ Ant Mech/ "
4153 "Ant Pos = %d/ %d/ %d\n", board_info->pg_ant_num,
4154 board_info->btdm_ant_num, board_info->btdm_ant_pos);
4155 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4156 "[BTCoex], BT stack/ hci ext ver = %s / %d\n",
4157 ((stack_info->profile_notified)? "Yes":"No"),
4158 stack_info->hci_version);
4159 btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
4160 &bt_patch_ver);
4161 btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
4162 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4163 "[BTCoex], CoexVer/ fw_ver/ PatchVer = "
4164 "%d_%x/ 0x%x/ 0x%x(%d)\n",
4165 glcoex_ver_date_8723b_2ant, glcoex_ver_8723b_2ant,
4166 fw_ver, bt_patch_ver, bt_patch_ver);
4167 BTC_PRINT(BTC_MSG_INTERFACE, INTF_INIT,
4168 "[BTCoex], *****************************"
4169 "***********************************\n");
4170 }
4171
4172#if(BT_AUTO_REPORT_ONLY_8723B_2ANT == 0)
4173 halbtc8723b2ant_query_bt_info(btcoexist);
4174 halbtc8723b2ant_monitor_bt_ctr(btcoexist);
4175 halbtc8723b2ant_monitor_bt_enable_disable(btcoexist);
4176#else
4177 if (halbtc8723b2ant_is_wifi_status_changed(btcoexist) ||
4178 coex_dm->auto_tdma_adjust)
4179 halbtc8723b2ant_run_coexist_mechanism(btcoexist);
4180#endif
4181}
4182
4183
4184#endif
4185
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtc8723b2ant.h b/drivers/staging/rtl8821ae/btcoexist/halbtc8723b2ant.h
new file mode 100644
index 000000000000..fa3784aa70cd
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtc8723b2ant.h
@@ -0,0 +1,145 @@
1/************************************************************************
2 * The following is for 8723B 2Ant BT Co-exist definition
3 ************************************************************************/
4#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1
5
6
7#define BT_INFO_8723B_2ANT_B_FTP BIT7
8#define BT_INFO_8723B_2ANT_B_A2DP BIT6
9#define BT_INFO_8723B_2ANT_B_HID BIT5
10#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
11#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
12#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
13#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
14#define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
15
16#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2
17
18typedef enum _BT_INFO_SRC_8723B_2ANT{
19 BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0,
20 BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1,
21 BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2,
22 BT_INFO_SRC_8723B_2ANT_MAX
23}BT_INFO_SRC_8723B_2ANT,*PBT_INFO_SRC_8723B_2ANT;
24
25typedef enum _BT_8723B_2ANT_BT_STATUS{
26 BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
27 BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
28 BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
29 BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
30 BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
31 BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
32 BT_8723B_2ANT_BT_STATUS_MAX
33}BT_8723B_2ANT_BT_STATUS,*PBT_8723B_2ANT_BT_STATUS;
34
35typedef enum _BT_8723B_2ANT_COEX_ALGO{
36 BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
37 BT_8723B_2ANT_COEX_ALGO_SCO = 0x1,
38 BT_8723B_2ANT_COEX_ALGO_HID = 0x2,
39 BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3,
40 BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
41 BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5,
42 BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6,
43 BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
44 BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
45 BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
46 BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
47 BT_8723B_2ANT_COEX_ALGO_MAX = 0xb,
48}BT_8723B_2ANT_COEX_ALGO,*PBT_8723B_2ANT_COEX_ALGO;
49
50struct coex_dm_8723b_2ant{
51 /* fw mechanism */
52 bool pre_dec_bt_pwr;
53 bool cur_dec_bt_pwr;
54 u8 pre_fw_dac_swing_lvl;
55 u8 cur_fw_dac_swing_lvl;
56 bool cur_ignore_wlan_act;
57 bool pre_ignore_wlan_act;
58 u8 pre_ps_tdma;
59 u8 cur_ps_tdma;
60 u8 ps_tdma_para[5];
61 u8 ps_tdma_du_adj_type;
62 bool reset_tdma_adjust;
63 bool auto_tdma_adjust;
64 bool pre_ps_tdma_on;
65 bool cur_ps_tdma_on;
66 bool pre_bt_auto_report;
67 bool cur_bt_auto_report;
68
69 /* sw mechanism */
70 bool pre_rf_rx_lpf_shrink;
71 bool cur_rf_rx_lpf_shrink;
72 u32 bt_rf0x1e_backup;
73 bool pre_low_penalty_ra;
74 bool cur_low_penalty_ra;
75 bool pre_dac_swing_on;
76 u32 pre_dac_swing_lvl;
77 bool cur_dac_swing_on;
78 u32 cur_dac_swing_lvl;
79 bool pre_adc_back_off;
80 bool cur_adc_back_off;
81 bool pre_agc_table_en;
82 bool cur_agc_table_en;
83 u32 pre_val0x6c0;
84 u32 cur_val0x6c0;
85 u32 pre_val0x6c4;
86 u32 cur_val0x6c4;
87 u32 pre_val0x6c8;
88 u32 cur_val0x6c8;
89 u8 pre_val0x6cc;
90 u8 cur_val0x6cc;
91 bool limited_dig;
92
93 /* algorithm related */
94 u8 pre_algorithm;
95 u8 cur_algorithm;
96 u8 bt_status;
97 u8 wifi_chnl_info[3];
98
99 bool need_recover_0x948;
100 u16 backup_0x948;
101};
102
103struct coex_sta_8723b_2ant{
104 bool bt_link_exist;
105 bool sco_exist;
106 bool a2dp_exist;
107 bool hid_exist;
108 bool pan_exist;
109
110 bool under_lps;
111 bool under_ips;
112 u32 high_priority_tx;
113 u32 high_priority_rx;
114 u32 low_priority_tx;
115 u32 low_priority_rx;
116 u8 bt_rssi;
117 u8 pre_bt_rssi_state;
118 u8 pre_wifi_rssi_state[4];
119 bool c2h_bt_info_req_sent;
120 u8 bt_info_c2h[BT_INFO_SRC_8723B_2ANT_MAX][10];
121 u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_2ANT_MAX];
122 bool c2h_bt_inquiry_page;
123 u8 bt_retry_cnt;
124 u8 bt_info_ext;
125};
126
127/*********************************************************************
128 * The following is interface which will notify coex module.
129 *********************************************************************/
130void ex_halbtc8723b2ant_init_hwconfig(struct btc_coexist *btcoexist);
131void ex_halbtc8723b2ant_init_coex_dm(struct btc_coexist *btcoexist);
132void ex_halbtc8723b2ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
133void ex_halbtc8723b2ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
134void ex_halbtc8723b2ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
135void ex_halbtc8723b2ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
136void ex_halbtc8723b2ant_media_status_notify(struct btc_coexist *btcoexist,
137 u8 type);
138void ex_halbtc8723b2ant_special_packet_notify(struct btc_coexist *btcoexist,
139 u8 type);
140void ex_halbtc8723b2ant_bt_info_notify(struct btc_coexist *btcoexist,
141 u8 *tmpbuf, u8 length);
142void ex_halbtc8723b2ant_halt_notify(struct btc_coexist *btcoexist);
143void ex_halbtc8723b2ant_periodical(struct btc_coexist * btcoexist);
144void ex_halbtc8723b2ant_display_coex_info(struct btc_coexist *btcoexist);
145
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtcoutsrc.c b/drivers/staging/rtl8821ae/btcoexist/halbtcoutsrc.c
new file mode 100644
index 000000000000..9d9fa4d7575d
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtcoutsrc.c
@@ -0,0 +1,1181 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20
21#include "halbt_precomp.h"
22
23/*#if(BT_30_SUPPORT == 1)*/
24#if 1
25/***********************************************
26 * Global variables
27 ***********************************************/
28const char *const bt_profile_string[]={
29 "NONE",
30 "A2DP",
31 "PAN",
32 "HID",
33 "SCO",
34};
35
36const char *const bt_spec_string[]={
37 "1.0b",
38 "1.1",
39 "1.2",
40 "2.0+EDR",
41 "2.1+EDR",
42 "3.0+HS",
43 "4.0",
44};
45
46const char *const bt_link_role_string[]={
47 "Master",
48 "Slave",
49};
50
51const char *const h2c_state_string[]={
52 "successful",
53 "h2c busy",
54 "rf off",
55 "fw not read",
56};
57
58const char *const io_state_string[]={
59 "IO_STATUS_SUCCESS",
60 "IO_STATUS_FAIL_CANNOT_IO",
61 "IO_STATUS_FAIL_RF_OFF",
62 "IO_STATUS_FAIL_FW_READ_CLEAR_TIMEOUT",
63 "IO_STATUS_FAIL_WAIT_IO_EVENT_TIMEOUT",
64 "IO_STATUS_INVALID_LEN",
65 "IO_STATUS_IO_IDLE_QUEUE_EMPTY",
66 "IO_STATUS_IO_INSERT_WAIT_QUEUE_FAIL",
67 "IO_STATUS_UNKNOWN_FAIL",
68 "IO_STATUS_WRONG_LEVEL",
69 "IO_STATUS_H2C_STOPPED",
70};
71
72struct btc_coexist gl_bt_coexist;
73
74u32 btc_dbg_type[BTC_MSG_MAX];
75u8 btc_dbg_buf[100];
76
77/***************************************************
78 * Debug related function
79 ***************************************************/
80bool halbtc_is_bt_coexist_available(struct btc_coexist *btcoexist)
81{
82 if (!btcoexist->binded || NULL == btcoexist->adapter)
83 return false;
84
85 return true;
86}
87
88bool halbtc_is_wifi_busy(struct rtl_priv *rtlpriv)
89{
90
91 if (rtlpriv->link_info.b_busytraffic)
92 return true;
93 else
94 return false;
95}
96
97
98void halbtc_dbg_init(void)
99{
100 u8 i;
101
102 for (i = 0; i < BTC_MSG_MAX; i++)
103 btc_dbg_type[i] = 0;
104
105 btc_dbg_type[BTC_MSG_INTERFACE] = \
106// INTF_INIT |
107// INTF_NOTIFY |
108 0;
109
110 btc_dbg_type[BTC_MSG_ALGORITHM] = \
111// ALGO_BT_RSSI_STATE |
112// ALGO_WIFI_RSSI_STATE |
113// ALGO_BT_MONITOR |
114// ALGO_TRACE |
115// ALGO_TRACE_FW |
116// ALGO_TRACE_FW_DETAIL |
117// ALGO_TRACE_FW_EXEC |
118// ALGO_TRACE_SW |
119// ALGO_TRACE_SW_DETAIL |
120// ALGO_TRACE_SW_EXEC |
121 0;
122}
123
124bool halbtc_is_hw_mailbox_exist(struct btc_coexist *btcoexist)
125{
126 return true;
127}
128
129bool halbtc_is_bt40(struct rtl_priv *adapter)
130{
131 struct rtl_priv *rtlpriv = adapter;
132 struct rtl_phy *rtlphy = &(rtlpriv->phy);
133 bool is_ht40 = true;
134 enum ht_channel_width bw = rtlphy->current_chan_bw;
135
136
137 if (bw == HT_CHANNEL_WIDTH_20)
138 is_ht40 = false;
139 else if (bw == HT_CHANNEL_WIDTH_20_40)
140 is_ht40 = true;
141
142 return is_ht40;
143}
144
145bool halbtc_legacy(struct rtl_priv *adapter)
146{
147 struct rtl_priv *rtlpriv = adapter;
148 struct rtl_mac *mac = rtl_mac(rtlpriv);
149
150 bool is_legacy = false;
151
152 if ((mac->mode == WIRELESS_MODE_B) || (mac->mode == WIRELESS_MODE_B))
153 is_legacy = true;
154
155 return is_legacy;
156}
157
158bool halbtc_is_wifi_uplink(struct rtl_priv *adapter)
159{
160 struct rtl_priv *rtlpriv = adapter;
161
162 if (rtlpriv->link_info.b_tx_busy_traffic)
163 return true;
164 else
165 return false;
166}
167
168u32 halbtc_get_wifi_bw(struct btc_coexist *btcoexist)
169{
170 struct rtl_priv *rtlpriv =
171 (struct rtl_priv *)btcoexist->adapter;
172 u32 wifi_bw = BTC_WIFI_BW_HT20;
173
174 if (halbtc_is_bt40(rtlpriv)){
175 wifi_bw = BTC_WIFI_BW_HT40;
176 } else {
177 if(halbtc_legacy(rtlpriv))
178 wifi_bw = BTC_WIFI_BW_LEGACY;
179 else
180 wifi_bw = BTC_WIFI_BW_HT20;
181 }
182 return wifi_bw;
183}
184
185u8 halbtc_get_wifi_central_chnl(struct btc_coexist *btcoexist)
186{
187 struct rtl_priv *rtlpriv = btcoexist->adapter;
188 struct rtl_phy *rtlphy = &(rtlpriv->phy);
189 u8 chnl = 1;
190
191
192 if (rtlphy->current_channel != 0)
193 chnl = rtlphy->current_channel;
194 BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE,
195 "halbtc_get_wifi_central_chnl:%d\n",chnl);
196 return chnl;
197}
198
199void halbtc_leave_lps(struct btc_coexist *btcoexist)
200{
201 struct rtl_priv *rtlpriv;
202 struct rtl_ps_ctl *ppsc;
203 bool ap_enable = false;
204
205 rtlpriv = btcoexist->adapter;
206 ppsc = rtl_psc(rtlpriv);
207
208 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
209 &ap_enable);
210
211 if (ap_enable) {
212 printk("halbtc_leave_lps()<--dont leave lps under AP mode\n");
213 return;
214 }
215
216 btcoexist->bt_info.bt_ctrl_lps = true;
217 btcoexist->bt_info.bt_lps_on = false;
218}
219
220void halbtc_enter_lps(struct btc_coexist *btcoexist)
221{
222 struct rtl_priv *rtlpriv;
223 struct rtl_ps_ctl *ppsc;
224 bool ap_enable = false;
225
226 rtlpriv = btcoexist->adapter;
227 ppsc = rtl_psc(rtlpriv);
228
229 btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE,
230 &ap_enable);
231
232 if (ap_enable) {
233 printk("halbtc_enter_lps()<--dont enter lps under AP mode\n");
234 return;
235 }
236
237 btcoexist->bt_info.bt_ctrl_lps = true;
238 btcoexist->bt_info.bt_lps_on = false;
239}
240
241void halbtc_normal_lps(struct btc_coexist *btcoexist)
242{
243 if (btcoexist->bt_info.bt_ctrl_lps) {
244 btcoexist->bt_info.bt_lps_on = false;
245 btcoexist->bt_info.bt_ctrl_lps = false;
246 }
247
248}
249
250void halbtc_leave_low_power(void)
251{
252}
253
254void halbtc_nomal_low_power(void)
255{
256}
257
258void halbtc_disable_low_power(void)
259{
260}
261
262void halbtc_aggregation_check(void)
263{
264}
265
266
267u32 halbtc_get_bt_patch_version(struct btc_coexist *btcoexist)
268{
269 return 0;
270}
271
272s32 halbtc_get_wifi_rssi(struct rtl_priv *adapter)
273{
274 struct rtl_priv *rtlpriv = adapter;
275 s32 undecorated_smoothed_pwdb = 0;
276
277 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED)
278 undecorated_smoothed_pwdb =
279 rtlpriv->dm.undecorated_smoothed_pwdb;
280 else /* associated entry pwdb */
281 undecorated_smoothed_pwdb =
282 rtlpriv->dm.undecorated_smoothed_pwdb;
283 return undecorated_smoothed_pwdb;
284}
285
286bool halbtc_get(void *void_btcoexist, u8 get_type, void *out_buf)
287{
288 struct btc_coexist *btcoexist = (struct btc_coexist *)void_btcoexist;
289 struct rtl_priv *rtlpriv = btcoexist->adapter;
290 struct rtl_phy *rtlphy = &(rtlpriv->phy);
291 struct rtl_mac *mac = rtl_mac(rtlpriv);
292 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
293 bool *bool_tmp = (bool*)out_buf;
294 int *s32_tmp = (int*)out_buf;
295 u32 *u32_tmp = (u32*)out_buf;
296 u8 *u8_tmp = (u8*)out_buf;
297 bool tmp = false;
298
299
300 if (!halbtc_is_bt_coexist_available(btcoexist))
301 return false;
302
303
304 switch (get_type){
305 case BTC_GET_BL_HS_OPERATION:
306 *bool_tmp = false;
307 break;
308 case BTC_GET_BL_HS_CONNECTING:
309 *bool_tmp = false;
310 break;
311 case BTC_GET_BL_WIFI_CONNECTED:
312 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED)
313 tmp = true;
314
315 *bool_tmp = tmp;
316 break;
317 case BTC_GET_BL_WIFI_BUSY:
318 if(halbtc_is_wifi_busy(rtlpriv))
319 *bool_tmp = true;
320 else
321 *bool_tmp = false;
322 break;
323 case BTC_GET_BL_WIFI_SCAN:
324 if (mac->act_scanning == true)
325 *bool_tmp = true;
326 else
327 *bool_tmp = false;
328 break;
329 case BTC_GET_BL_WIFI_LINK:
330 if (mac->link_state == MAC80211_LINKING)
331 *bool_tmp = true;
332 else
333 *bool_tmp = false;
334 break;
335 case BTC_GET_BL_WIFI_ROAM: /*TODO*/
336 if (mac->link_state == MAC80211_LINKING)
337 *bool_tmp = true;
338 else
339 *bool_tmp = false;
340 break;
341 case BTC_GET_BL_WIFI_4_WAY_PROGRESS: /*TODO*/
342 *bool_tmp = false;
343
344 break;
345 case BTC_GET_BL_WIFI_UNDER_5G:
346 *bool_tmp = false; /*TODO*/
347
348 case BTC_GET_BL_WIFI_DHCP: /*TODO*/
349 break;
350 case BTC_GET_BL_WIFI_SOFTAP_IDLE:
351 *bool_tmp = true;
352 break;
353 case BTC_GET_BL_WIFI_SOFTAP_LINKING:
354 *bool_tmp = false;
355 break;
356 case BTC_GET_BL_WIFI_IN_EARLY_SUSPEND:
357 *bool_tmp = false;
358 break;
359 case BTC_GET_BL_WIFI_AP_MODE_ENABLE:
360 *bool_tmp = false;
361 break;
362 case BTC_GET_BL_WIFI_ENABLE_ENCRYPTION:
363 if (NO_ENCRYPTION == rtlpriv->sec.pairwise_enc_algorithm)
364 *bool_tmp = false;
365 else
366 *bool_tmp = true;
367 break;
368 case BTC_GET_BL_WIFI_UNDER_B_MODE:
369 *bool_tmp = false; /*TODO*/
370 break;
371 case BTC_GET_BL_EXT_SWITCH:
372 *bool_tmp = false;
373 break;
374 case BTC_GET_S4_WIFI_RSSI:
375 *s32_tmp = halbtc_get_wifi_rssi(rtlpriv);
376 break;
377 case BTC_GET_S4_HS_RSSI: /*TODO*/
378 *s32_tmp = halbtc_get_wifi_rssi(rtlpriv);
379 break;
380 case BTC_GET_U4_WIFI_BW:
381 *u32_tmp = halbtc_get_wifi_bw(btcoexist);
382 break;
383 case BTC_GET_U4_WIFI_TRAFFIC_DIRECTION:
384 if (halbtc_is_wifi_uplink(rtlpriv))
385 *u32_tmp = BTC_WIFI_TRAFFIC_TX;
386 else
387 *u32_tmp = BTC_WIFI_TRAFFIC_RX;
388 break;
389 case BTC_GET_U4_WIFI_FW_VER:
390 *u32_tmp = rtlhal->fw_version;
391 break;
392 case BTC_GET_U4_BT_PATCH_VER:
393 *u32_tmp = halbtc_get_bt_patch_version(btcoexist);
394 break;
395 case BTC_GET_U1_WIFI_DOT11_CHNL:
396 *u8_tmp = rtlphy->current_channel;
397 break;
398 case BTC_GET_U1_WIFI_CENTRAL_CHNL:
399 *u8_tmp = halbtc_get_wifi_central_chnl(btcoexist);
400 break;
401 case BTC_GET_U1_WIFI_HS_CHNL:
402 *u8_tmp = 1;/* BT_OperateChnl(rtlpriv); */
403 break;
404 case BTC_GET_U1_MAC_PHY_MODE:
405 *u8_tmp = BTC_MP_UNKNOWN;
406 break;
407 case BTC_GET_U1_AP_NUM:
408 /* driver don't know AP num in Linux,
409 * So, the return value here is not right */
410 *u8_tmp = 1;/* pDefMgntInfo->NumBssDesc4Query; */
411 break;
412
413 /************* 1Ant **************/
414 case BTC_GET_U1_LPS_MODE:
415 *u8_tmp = btcoexist->pwr_mode_val[0];
416 break;
417
418 default:
419 break;
420 }
421
422 return true;
423}
424
425bool halbtc_set(void *void_btcoexist, u8 set_type, void *in_buf)
426{
427 struct btc_coexist *btcoexist = (struct btc_coexist *)void_btcoexist;
428 bool *bool_tmp = (bool *)in_buf;
429 u8 *u8_tmp = (u8 *)in_buf;
430 u32 *u32_tmp = (u32 *)in_buf;
431
432
433 if (!halbtc_is_bt_coexist_available(btcoexist))
434 return false;
435
436 switch (set_type) {
437 /* set some bool type variables. */
438 case BTC_SET_BL_BT_DISABLE:
439 btcoexist->bt_info.bt_disabled = *bool_tmp;
440 break;
441 case BTC_SET_BL_BT_TRAFFIC_BUSY:
442 btcoexist->bt_info.bt_busy = *bool_tmp;
443 break;
444 case BTC_SET_BL_BT_LIMITED_DIG:
445 btcoexist->bt_info.limited_dig = *bool_tmp;
446 break;
447 case BTC_SET_BL_FORCE_TO_ROAM:
448 btcoexist->bt_info.force_to_roam = *bool_tmp;
449 break;
450 case BTC_SET_BL_TO_REJ_AP_AGG_PKT:
451 btcoexist->bt_info.reject_agg_pkt = *bool_tmp;
452 break;
453 case BTC_SET_BL_BT_CTRL_AGG_SIZE:
454 btcoexist->bt_info.b_bt_ctrl_buf_size = *bool_tmp;
455 break;
456 case BTC_SET_BL_INC_SCAN_DEV_NUM:
457 btcoexist->bt_info.increase_scan_dev_num = *bool_tmp;
458 break;
459 /* set some u1Byte type variables. */
460 case BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON:
461 btcoexist->bt_info.rssi_adjust_for_agc_table_on = *u8_tmp;
462 break;
463 case BTC_SET_U1_AGG_BUF_SIZE:
464 btcoexist->bt_info.agg_buf_size = *u8_tmp;
465 break;
466 /* the following are some action which will be triggered */
467 case BTC_SET_ACT_GET_BT_RSSI:
468 /*BTHCI_SendGetBtRssiEvent(rtlpriv);*/
469 break;
470 case BTC_SET_ACT_AGGREGATE_CTRL:
471 halbtc_aggregation_check();
472 break;
473
474 /* 1Ant */
475 case BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE:
476 btcoexist->bt_info.rssi_adjust_for_1ant_coex_type = *u8_tmp;
477 break;
478 case BTC_SET_UI_SCAN_SIG_COMPENSATION:
479 /* rtlpriv->mlmepriv.scan_compensation = *u8_tmp; */
480 break;
481 case BTC_SET_U1_1ANT_LPS:
482 btcoexist->bt_info.lps_1ant = *u8_tmp;
483 break;
484 case BTC_SET_U1_1ANT_RPWM:
485 btcoexist->bt_info.rpwm_1ant = *u8_tmp;
486 break;
487 /* the following are some action which will be triggered */
488 case BTC_SET_ACT_LEAVE_LPS:
489 halbtc_leave_lps(btcoexist);
490 break;
491 case BTC_SET_ACT_ENTER_LPS:
492 halbtc_enter_lps(btcoexist);
493 break;
494 case BTC_SET_ACT_NORMAL_LPS:
495 halbtc_normal_lps(btcoexist);
496 break;
497 case BTC_SET_ACT_DISABLE_LOW_POWER:
498 halbtc_disable_low_power();
499 break;
500 case BTC_SET_ACT_UPDATE_ra_mask:
501 btcoexist->bt_info.ra_mask = *u32_tmp;
502 break;
503 case BTC_SET_ACT_SEND_MIMO_PS:
504 break;
505 case BTC_SET_ACT_INC_FORCE_EXEC_PWR_CMD_CNT:
506 btcoexist->bt_info.force_exec_pwr_cmd_cnt++;
507 break;
508 case BTC_SET_ACT_CTRL_BT_INFO: /*wait for 8812/8821*/
509 break;
510 case BTC_SET_ACT_CTRL_BT_COEX:
511 break;
512 default:
513 break;
514 }
515
516 return true;
517}
518
519void halbtc_display_coex_statistics(struct btc_coexist *btcoexist)
520{
521}
522
523void halbtc_display_bt_link_info(struct btc_coexist *btcoexist)
524{
525}
526
527void halbtc_display_bt_fw_info(struct btc_coexist *btcoexist)
528{
529}
530
531void halbtc_display_fw_pwr_mode_cmd(struct btc_coexist *btcoexist)
532{
533}
534
535/************************************************************
536 * IO related function
537 ************************************************************/
538u8 halbtc_read_1byte(void *bt_context, u32 reg_addr)
539{
540 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
541 struct rtl_priv *rtlpriv = btcoexist->adapter;
542
543 return rtl_read_byte(rtlpriv, reg_addr);
544}
545
546
547u16 halbtc_read_2byte(void *bt_context, u32 reg_addr)
548{
549 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
550 struct rtl_priv *rtlpriv = btcoexist->adapter;
551
552 return rtl_read_word(rtlpriv, reg_addr);
553}
554
555
556u32 halbtc_read_4byte(void *bt_context, u32 reg_addr)
557{
558 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
559 struct rtl_priv *rtlpriv = btcoexist->adapter;
560
561 return rtl_read_dword(rtlpriv, reg_addr);
562}
563
564
565void halbtc_write_1byte(void *bt_context, u32 reg_addr, u8 data)
566{
567 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
568 struct rtl_priv *rtlpriv = btcoexist->adapter;
569
570 rtl_write_byte(rtlpriv, reg_addr, data);
571}
572
573void halbtc_bitmask_write_1byte(void *bt_context, u32 reg_addr,
574 u8 bit_mask, u8 data)
575{
576 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
577 struct rtl_priv *rtlpriv = btcoexist->adapter;
578 u8 original_value, bit_shift = 0;
579 u8 i;
580
581 if (bit_mask != MASKDWORD) {/*if not "double word" write*/
582 original_value = rtl_read_byte(rtlpriv, reg_addr);
583 for (i=0; i<=7; i++) {
584 if((bit_mask>>i)&0x1)
585 break;
586 }
587 bit_shift = i;
588 data = (original_value & (~bit_mask)) |
589 ((data << bit_shift) & bit_mask);
590 }
591 rtl_write_byte(rtlpriv, reg_addr, data);
592}
593
594
595void halbtc_write_2byte(void *bt_context, u32 reg_addr, u16 data)
596{
597 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
598 struct rtl_priv *rtlpriv = btcoexist->adapter;
599
600 rtl_write_word(rtlpriv, reg_addr, data);
601}
602
603
604void halbtc_write_4byte(void *bt_context, u32 reg_addr, u32 data)
605{
606 struct btc_coexist *btcoexist =
607 (struct btc_coexist *)bt_context;
608 struct rtl_priv *rtlpriv = btcoexist->adapter;
609
610 rtl_write_dword(rtlpriv, reg_addr, data);
611}
612
613
614void halbtc_set_macreg(void *bt_context, u32 reg_addr, u32 bit_mask, u32 data)
615{
616 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
617 struct rtl_priv *rtlpriv = btcoexist->adapter;
618
619 rtl_set_bbreg(rtlpriv->mac80211.hw, reg_addr, bit_mask, data);
620}
621
622
623u32 halbtc_get_macreg(void *bt_context, u32 reg_addr, u32 bit_mask)
624{
625 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
626 struct rtl_priv *rtlpriv = btcoexist->adapter;
627
628 return rtl_get_bbreg(rtlpriv->mac80211.hw, reg_addr, bit_mask);
629}
630
631
632void halbtc_set_bbreg(void *bt_context, u32 reg_addr, u32 bit_mask, u32 data)
633{
634 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
635 struct rtl_priv *rtlpriv = btcoexist->adapter;
636
637 rtl_set_bbreg(rtlpriv->mac80211.hw, reg_addr, bit_mask, data);
638}
639
640
641u32 halbtc_get_bbreg(void *bt_context, u32 reg_addr, u32 bit_mask)
642{
643 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
644 struct rtl_priv *rtlpriv = btcoexist->adapter;
645
646 return rtl_get_bbreg(rtlpriv->mac80211.hw,reg_addr, bit_mask);
647}
648
649
650void halbtc_set_rfreg(void *bt_context, u8 rf_path, u32 reg_addr,
651 u32 bit_mask, u32 data)
652{
653 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
654 struct rtl_priv *rtlpriv = btcoexist->adapter;
655
656 rtl_set_rfreg(rtlpriv->mac80211.hw, rf_path, reg_addr, bit_mask, data);
657}
658
659
660u32 halbtc_get_rfreg(void *bt_context, u8 rf_path, u32 reg_addr, u32 bit_mask)
661{
662 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
663 struct rtl_priv *rtlpriv = btcoexist->adapter;
664
665 return rtl_get_rfreg(rtlpriv->mac80211.hw, rf_path, reg_addr, bit_mask);
666}
667
668
669void halbtc_fill_h2c_cmd(void *bt_context, u8 element_id,
670 u32 cmd_len, u8 *cmd_buf)
671{
672 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
673 struct rtl_priv *rtlpriv = btcoexist->adapter;
674
675 rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->mac80211.hw, element_id,
676 cmd_len, cmd_buf);
677}
678
679void halbtc_display_dbg_msg(void *bt_context, u8 disp_type)
680{
681 struct btc_coexist *btcoexist = (struct btc_coexist *)bt_context;
682 switch (disp_type) {
683 case BTC_DBG_DISP_COEX_STATISTICS:
684 halbtc_display_coex_statistics(btcoexist);
685 break;
686 case BTC_DBG_DISP_BT_LINK_INFO:
687 halbtc_display_bt_link_info(btcoexist);
688 break;
689 case BTC_DBG_DISP_BT_FW_VER:
690 halbtc_display_bt_fw_info(btcoexist);
691 break;
692 case BTC_DBG_DISP_FW_PWR_MODE_CMD:
693 halbtc_display_fw_pwr_mode_cmd(btcoexist);
694 break;
695 default:
696 break;
697 }
698}
699
700bool halbtc_under_ips(struct btc_coexist *btcoexist)
701{
702 struct rtl_priv *rtlpriv = btcoexist->adapter;
703 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
704 enum rf_pwrstate rtstate;
705
706 if (ppsc->b_inactiveps) {
707 rtstate = ppsc->rfpwr_state;
708
709 if (rtstate != ERFON &&
710 ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
711
712 return true;
713 }
714 }
715
716 return false;
717}
718
719/*****************************************************************
720 * Extern functions called by other module
721 *****************************************************************/
722bool exhalbtc_initlize_variables(struct rtl_priv *adapter)
723{
724 struct btc_coexist *btcoexist = &gl_bt_coexist;
725
726 btcoexist->statistics.cnt_bind++;
727
728 halbtc_dbg_init();
729
730 if (btcoexist->binded)
731 return false;
732 else
733 btcoexist->binded = true;
734
735#if ( defined(CONFIG_PCI_HCI))
736 btcoexist->chip_interface = BTC_INTF_PCI;
737#elif ( defined(CONFIG_USB_HCI))
738 btcoexist->chip_interface = BTC_INTF_USB;
739#elif ( defined(CONFIG_SDIO_HCI))
740 btcoexist->chip_interface = BTC_INTF_SDIO;
741#elif ( defined(CONFIG_GSPI_HCI))
742 btcoexist->chip_interface = BTC_INTF_GSPI;
743#else
744 btcoexist->chip_interface = BTC_INTF_UNKNOWN;
745#endif
746
747 if (NULL == btcoexist->adapter)
748 btcoexist->adapter = adapter;
749
750 btcoexist->stack_info.profile_notified = false;
751
752 btcoexist->btc_read_1byte = halbtc_read_1byte;
753 btcoexist->btc_write_1byte = halbtc_write_1byte;
754 btcoexist->btc_write_1byte_bitmask = halbtc_bitmask_write_1byte;
755 btcoexist->btc_read_2byte = halbtc_read_2byte;
756 btcoexist->btc_write_2byte = halbtc_write_2byte;
757 btcoexist->btc_read_4byte = halbtc_read_4byte;
758 btcoexist->btc_write_4byte = halbtc_write_4byte;
759
760 btcoexist->btc_set_bb_reg = halbtc_set_bbreg;
761 btcoexist->btc_get_bb_reg = halbtc_get_bbreg;
762
763 btcoexist->btc_set_rf_reg = halbtc_set_rfreg;
764 btcoexist->btc_get_rf_reg = halbtc_get_rfreg;
765
766 btcoexist->btc_fill_h2c = halbtc_fill_h2c_cmd;
767 btcoexist->btc_disp_dbg_msg = halbtc_display_dbg_msg;
768
769 btcoexist->btc_get = halbtc_get;
770 btcoexist->btc_set = halbtc_set;
771
772 btcoexist->cli_buf = &btc_dbg_buf[0];
773
774 btcoexist->bt_info.b_bt_ctrl_buf_size = false;
775 btcoexist->bt_info.agg_buf_size = 5;
776
777 btcoexist->bt_info.increase_scan_dev_num = false;
778 return true;
779}
780
781void exhalbtc_init_hw_config(struct btc_coexist *btcoexist)
782{
783 struct rtl_priv *rtlpriv = btcoexist->adapter;
784 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
785
786 if (!halbtc_is_bt_coexist_available(btcoexist))
787 return;
788
789 btcoexist->statistics.cnt_init_hw_config++;
790
791 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
792 if (btcoexist->board_info.btdm_ant_num == 2)
793 ex_halbtc8723b2ant_init_hwconfig(btcoexist);
794 else if(btcoexist->board_info.btdm_ant_num == 1)
795 ex_halbtc8723b1ant_init_hwconfig(btcoexist);
796 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) {
797 ex_halbtc8192e2ant_init_hwconfig(btcoexist);
798 }
799
800}
801
802void exhalbtc_init_coex_dm(struct btc_coexist *btcoexist)
803{
804 struct rtl_priv *rtlpriv = btcoexist->adapter;
805 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
806
807 if (!halbtc_is_bt_coexist_available(btcoexist))
808 return;
809
810 btcoexist->statistics.cnt_init_coex_dm++;
811
812 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
813 if (btcoexist->board_info.btdm_ant_num == 2)
814 ex_halbtc8723b2ant_init_coex_dm(btcoexist);
815 else if(btcoexist->board_info.btdm_ant_num == 1)
816 ex_halbtc8723b1ant_init_coex_dm(btcoexist);
817 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) {
818 ex_halbtc8192e2ant_init_coex_dm(btcoexist);
819 }
820
821 btcoexist->initilized = true;
822}
823
824void exhalbtc_ips_notify(struct btc_coexist *btcoexist, u8 type)
825{
826 struct rtl_priv *rtlpriv = btcoexist->adapter;
827 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
828 u8 ips_type;
829
830 if (!halbtc_is_bt_coexist_available(btcoexist))
831 return;
832 btcoexist->statistics.cnt_ips_notify++;
833 if (btcoexist->manual_control)
834 return;
835
836 if (ERFOFF == type)
837 ips_type = BTC_IPS_ENTER;
838 else
839 ips_type = BTC_IPS_LEAVE;
840
841 halbtc_leave_low_power();
842
843 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
844 if (btcoexist->board_info.btdm_ant_num == 2)
845 ex_halbtc8723b2ant_ips_notify(btcoexist, ips_type);
846 else if(btcoexist->board_info.btdm_ant_num == 1)
847 ex_halbtc8723b1ant_ips_notify(btcoexist, ips_type);
848 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) {
849 ex_halbtc8192e2ant_ips_notify(btcoexist, ips_type);
850 }
851
852 halbtc_nomal_low_power();
853}
854
855void exhalbtc_lps_notify(struct btc_coexist *btcoexist, u8 type)
856{
857 struct rtl_priv *rtlpriv = btcoexist->adapter;
858 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
859 u8 lps_type;
860
861 if (!halbtc_is_bt_coexist_available(btcoexist))
862 return;
863 btcoexist->statistics.cnt_lps_notify++;
864 if (btcoexist->manual_control)
865 return;
866
867 if (EACTIVE == type)
868 lps_type = BTC_LPS_DISABLE;
869 else
870 lps_type = BTC_LPS_ENABLE;
871
872 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
873 if (btcoexist->board_info.btdm_ant_num == 2)
874 ex_halbtc8723b2ant_lps_notify(btcoexist, lps_type);
875 else if(btcoexist->board_info.btdm_ant_num == 1)
876 ex_halbtc8723b1ant_lps_notify(btcoexist, lps_type);
877 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) {
878 ex_halbtc8192e2ant_lps_notify(btcoexist, lps_type);
879 }
880}
881
882void exhalbtc_scan_notify(struct btc_coexist *btcoexist, u8 type)
883{
884 struct rtl_priv *rtlpriv = btcoexist->adapter;
885 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
886 u8 scan_type;
887
888 if (!halbtc_is_bt_coexist_available(btcoexist))
889 return;
890 btcoexist->statistics.cnt_scan_notify++;
891 if (btcoexist->manual_control)
892 return;
893
894 if (type)
895 scan_type = BTC_SCAN_START;
896 else
897 scan_type = BTC_SCAN_FINISH;
898
899 halbtc_leave_low_power();
900
901 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
902 if (btcoexist->board_info.btdm_ant_num == 2)
903 ex_halbtc8723b2ant_scan_notify(btcoexist, scan_type);
904 else if(btcoexist->board_info.btdm_ant_num == 1)
905 ex_halbtc8723b1ant_scan_notify(btcoexist, scan_type);
906 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) {
907 ex_halbtc8192e2ant_scan_notify(btcoexist, scan_type);
908 }
909
910 halbtc_nomal_low_power();
911}
912
913void exhalbtc_connect_notify(struct btc_coexist *btcoexist, u8 action)
914{
915 struct rtl_priv *rtlpriv = btcoexist->adapter;
916 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
917 u8 asso_type;
918
919 if (!halbtc_is_bt_coexist_available(btcoexist))
920 return;
921 btcoexist->statistics.cnt_connect_notify++;
922 if (btcoexist->manual_control)
923 return;
924
925 if (action)
926 asso_type = BTC_ASSOCIATE_START;
927 else
928 asso_type = BTC_ASSOCIATE_FINISH;
929
930 halbtc_leave_low_power();
931
932 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
933 if (btcoexist->board_info.btdm_ant_num == 2)
934 ex_halbtc8723b2ant_connect_notify(btcoexist, asso_type);
935 else if(btcoexist->board_info.btdm_ant_num == 1)
936 ex_halbtc8723b1ant_connect_notify(btcoexist, asso_type);
937 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) {
938 ex_halbtc8192e2ant_connect_notify(btcoexist, asso_type);
939 }
940
941 halbtc_nomal_low_power();
942}
943
944void exhalbtc_mediastatus_notify(struct btc_coexist *btcoexist,
945 enum rt_media_status media_status)
946{
947 struct rtl_priv *rtlpriv = btcoexist->adapter;
948 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
949 u8 status;
950
951 if (!halbtc_is_bt_coexist_available(btcoexist))
952 return;
953 btcoexist->statistics.cnt_media_status_notify++;
954 if (btcoexist->manual_control)
955 return;
956
957 if (RT_MEDIA_CONNECT == media_status)
958 status = BTC_MEDIA_CONNECT;
959 else
960 status = BTC_MEDIA_DISCONNECT;
961
962 halbtc_leave_low_power();
963
964 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
965 if (btcoexist->board_info.btdm_ant_num == 2)
966 ex_halbtc8723b2ant_media_status_notify(btcoexist, status);
967 else if(btcoexist->board_info.btdm_ant_num == 1)
968 ex_halbtc8723b1ant_media_status_notify(btcoexist, status);
969 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) {
970 ex_halbtc8192e2ant_media_status_notify(btcoexist, status);
971 }
972
973 halbtc_nomal_low_power();
974}
975
976void exhalbtc_special_packet_notify(struct btc_coexist *btcoexist, u8 pkt_type)
977{
978 u8 packet_type;
979
980 if (!halbtc_is_bt_coexist_available(btcoexist))
981 return;
982 btcoexist->statistics.cnt_special_packet_notify++;
983 if (btcoexist->manual_control)
984 return;
985
986 /*if(PACKET_DHCP == pkt_type)*/
987 packet_type = BTC_PACKET_DHCP;
988 /*else if(PACKET_EAPOL == pkt_type)
989 packet_type = BTC_PACKET_EAPOL;
990 else
991 packet_type = BTC_PACKET_UNKNOWN;*/
992
993 halbtc_leave_low_power();
994
995 if (btcoexist->board_info.btdm_ant_num == 2)
996 ex_halbtc8723b2ant_special_packet_notify(btcoexist,
997 packet_type);
998 else if (btcoexist->board_info.btdm_ant_num == 1)
999 ex_halbtc8723b1ant_special_packet_notify(btcoexist,
1000 packet_type);
1001
1002 halbtc_nomal_low_power();
1003}
1004
1005void exhalbtc_bt_info_notify(struct btc_coexist *btcoexist,
1006 u8 *tmp_buf, u8 length)
1007{
1008 struct rtl_priv *rtlpriv = btcoexist->adapter;
1009 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1010 if (!halbtc_is_bt_coexist_available(btcoexist))
1011 return;
1012 btcoexist->statistics.cnt_bt_info_notify++;
1013
1014 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1015 if (btcoexist->board_info.btdm_ant_num == 2)
1016 ex_halbtc8723b2ant_bt_info_notify(btcoexist, tmp_buf, length);
1017 else if(btcoexist->board_info.btdm_ant_num == 1)
1018 ex_halbtc8723b1ant_bt_info_notify(btcoexist, tmp_buf, length);
1019 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) {
1020 // ex_halbtc8192e2ant_bt_info_notify(btcoexist, tmp_buf, length);
1021 }
1022}
1023
1024void exhalbtc_stack_operation_notify(struct btc_coexist *btcoexist, u8 type)
1025{
1026 u8 stack_op_type;
1027
1028 if (!halbtc_is_bt_coexist_available(btcoexist))
1029 return;
1030 btcoexist->statistics.cnt_stack_operation_notify++;
1031 if (btcoexist->manual_control)
1032 return;
1033
1034 stack_op_type = BTC_STACK_OP_NONE;
1035}
1036
1037void exhalbtc_halt_notify(struct btc_coexist *btcoexist)
1038{
1039 struct rtl_priv *rtlpriv = btcoexist->adapter;
1040 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1041 if (!halbtc_is_bt_coexist_available(btcoexist))
1042 return;
1043
1044 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1045 if (btcoexist->board_info.btdm_ant_num == 2)
1046 ex_halbtc8723b2ant_halt_notify(btcoexist);
1047 else if(btcoexist->board_info.btdm_ant_num == 1)
1048 ex_halbtc8723b1ant_halt_notify(btcoexist);
1049 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) {
1050 ex_halbtc8192e2ant_halt_notify(btcoexist);
1051 }
1052}
1053
1054void exhalbtc_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state)
1055{
1056 if (!halbtc_is_bt_coexist_available(btcoexist))
1057 return;
1058}
1059
1060void exhalbtc_periodical(struct btc_coexist *btcoexist)
1061{
1062 struct rtl_priv *rtlpriv = btcoexist->adapter;
1063 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1064 if (!halbtc_is_bt_coexist_available(btcoexist))
1065 return;
1066 btcoexist->statistics.cnt_periodical++;
1067
1068 halbtc_leave_low_power();
1069
1070 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1071 if (btcoexist->board_info.btdm_ant_num == 2)
1072 ex_halbtc8723b2ant_periodical(btcoexist);
1073 else if(btcoexist->board_info.btdm_ant_num == 1)
1074 ex_halbtc8723b1ant_periodical(btcoexist);
1075 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) {
1076 ex_halbtc8192e2ant_periodical(btcoexist);
1077 }
1078
1079 halbtc_nomal_low_power();
1080}
1081
1082void exhalbtc_dbg_control(struct btc_coexist *btcoexist,
1083 u8 code, u8 len, u8 *data)
1084{
1085 if (!halbtc_is_bt_coexist_available(btcoexist))
1086 return;
1087 btcoexist->statistics.cnt_dbg_ctrl++;
1088}
1089
1090void exhalbtc_stack_update_profile_info()
1091{
1092}
1093
1094void exhalbtc_update_min_bt_rssi(char bt_rssi)
1095{
1096 struct btc_coexist *btcoexist = &gl_bt_coexist;
1097
1098 if (!halbtc_is_bt_coexist_available(btcoexist))
1099 return;
1100
1101 btcoexist->stack_info.min_bt_rssi = bt_rssi;
1102}
1103
1104
1105void exhalbtc_set_hci_version(u16 hci_version)
1106{
1107 struct btc_coexist *btcoexist = &gl_bt_coexist;
1108
1109 if (!halbtc_is_bt_coexist_available(btcoexist))
1110 return;
1111
1112 btcoexist->stack_info.hci_version = hci_version;
1113}
1114
1115void exhalbtc_set_bt_patch_version(u16 bt_hci_version, u16 bt_patch_version)
1116{
1117 struct btc_coexist *btcoexist = &gl_bt_coexist;
1118
1119 if (!halbtc_is_bt_coexist_available(btcoexist))
1120 return;
1121
1122 btcoexist->bt_info.bt_real_fw_ver = bt_patch_version;
1123 btcoexist->bt_info.bt_hci_ver = bt_hci_version;
1124}
1125
1126void exhalbtc_set_bt_exist(bool bt_exist)
1127{
1128 gl_bt_coexist.board_info.bt_exist = bt_exist;
1129}
1130
1131void exhalbtc_set_chip_type(u8 chip_type)
1132{
1133 switch (chip_type) {
1134 default:
1135 case BT_2WIRE:
1136 case BT_ISSC_3WIRE:
1137 case BT_ACCEL:
1138 case BT_RTL8756:
1139 gl_bt_coexist.board_info.bt_chip_type = BTC_CHIP_UNDEF;
1140 break;
1141 case BT_CSR_BC4:
1142 gl_bt_coexist.board_info.bt_chip_type = BTC_CHIP_CSR_BC4;
1143 break;
1144 case BT_CSR_BC8:
1145 gl_bt_coexist.board_info.bt_chip_type = BTC_CHIP_CSR_BC8;
1146 break;
1147 case BT_RTL8723A:
1148 gl_bt_coexist.board_info.bt_chip_type = BTC_CHIP_RTL8723A;
1149 break;
1150 case BT_RTL8821A:
1151 gl_bt_coexist.board_info.bt_chip_type = BTC_CHIP_RTL8821;
1152 break;
1153 case BT_RTL8723B:
1154 gl_bt_coexist.board_info.bt_chip_type = BTC_CHIP_RTL8723B;
1155 break;
1156 }
1157}
1158
1159void exhalbtc_set_ant_num(u8 type, u8 ant_num)
1160{
1161 if (BT_COEX_ANT_TYPE_PG == type) {
1162 gl_bt_coexist.board_info.pg_ant_num = ant_num;
1163 gl_bt_coexist.board_info.btdm_ant_num = ant_num;
1164 } else if (BT_COEX_ANT_TYPE_ANTDIV == type) {
1165 gl_bt_coexist.board_info.btdm_ant_num = ant_num;
1166 }
1167}
1168
1169void exhalbtc_display_bt_coex_info(struct btc_coexist *btcoexist)
1170{
1171 if (!halbtc_is_bt_coexist_available(btcoexist))
1172 return;
1173
1174 if (btcoexist->board_info.btdm_ant_num == 2)
1175 ex_halbtc8723b2ant_display_coex_info(btcoexist);
1176 else if (btcoexist->board_info.btdm_ant_num == 1)
1177 ex_halbtc8723b1ant_display_coex_info(btcoexist);
1178}
1179
1180#endif
1181
diff --git a/drivers/staging/rtl8821ae/btcoexist/halbtcoutsrc.h b/drivers/staging/rtl8821ae/btcoexist/halbtcoutsrc.h
new file mode 100644
index 000000000000..787798e76217
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/halbtcoutsrc.h
@@ -0,0 +1,549 @@
1#ifndef __HALBTC_OUT_SRC_H__
2#define __HALBTC_OUT_SRC_H__
3
4#include "../wifi.h"
5
6#define NORMAL_EXEC false
7#define FORCE_EXEC true
8
9#define BTC_RF_A RF90_PATH_A
10#define BTC_RF_B RF90_PATH_B
11#define BTC_RF_C RF90_PATH_C
12#define BTC_RF_D RF90_PATH_D
13
14#define BTC_SMSP SINGLEMAC_SINGLEPHY
15#define BTC_DMDP DUALMAC_DUALPHY
16#define BTC_DMSP DUALMAC_SINGLEPHY
17#define BTC_MP_UNKNOWN 0xff
18
19#define IN
20#define OUT
21
22#define BT_TMP_BUF_SIZE 100
23
24#define BT_COEX_ANT_TYPE_PG 0
25#define BT_COEX_ANT_TYPE_ANTDIV 1
26#define BT_COEX_ANT_TYPE_DETECTED 2
27
28#define BTC_MIMO_PS_STATIC 0
29#define BTC_MIMO_PS_DYNAMIC 1
30
31#define BTC_RATE_DISABLE 0
32#define BTC_RATE_ENABLE 1
33
34/* single Antenna definition */
35#define BTC_ANT_PATH_WIFI 0
36#define BTC_ANT_PATH_BT 1
37#define BTC_ANT_PATH_PTA 2
38/* dual Antenna definition */
39#define BTC_ANT_WIFI_AT_MAIN 0
40#define BTC_ANT_WIFI_AT_AUX 1
41/* coupler Antenna definition */
42#define BTC_ANT_WIFI_AT_CPL_MAIN 0
43#define BTC_ANT_WIFI_AT_CPL_AUX 1
44
45enum btc_chip_interface{
46 BTC_INTF_UNKNOWN = 0,
47 BTC_INTF_PCI = 1,
48 BTC_INTF_USB = 2,
49 BTC_INTF_SDIO = 3,
50 BTC_INTF_GSPI = 4,
51 BTC_INTF_MAX
52};
53
54enum btc_chip_type{
55 BTC_CHIP_UNDEF = 0,
56 BTC_CHIP_CSR_BC4 = 1,
57 BTC_CHIP_CSR_BC8 = 2,
58 BTC_CHIP_RTL8723A = 3,
59 BTC_CHIP_RTL8821 = 4,
60 BTC_CHIP_RTL8723B = 5,
61 BTC_CHIP_MAX
62};
63
64enum btc_msg_type{
65 BTC_MSG_INTERFACE = 0x0,
66 BTC_MSG_ALGORITHM = 0x1,
67 BTC_MSG_MAX
68};
69
70extern u32 btc_dbg_type[];
71
72/* following is for BTC_MSG_INTERFACE */
73#define INTF_INIT BIT0
74#define INTF_NOTIFY BIT2
75
76/* following is for BTC_ALGORITHM */
77#define ALGO_BT_RSSI_STATE BIT0
78#define ALGO_WIFI_RSSI_STATE BIT1
79#define ALGO_BT_MONITOR BIT2
80#define ALGO_TRACE BIT3
81#define ALGO_TRACE_FW BIT4
82#define ALGO_TRACE_FW_DETAIL BIT5
83#define ALGO_TRACE_FW_EXEC BIT6
84#define ALGO_TRACE_SW BIT7
85#define ALGO_TRACE_SW_DETAIL BIT8
86#define ALGO_TRACE_SW_EXEC BIT9
87
88
89
90#define CL_SPRINTF snprintf
91#define CL_PRINTF printk
92
93#define BTC_PRINT(dbgtype, dbgflag, printstr, ...) \
94 do { \
95 if (unlikely(btc_dbg_type[dbgtype] & dbgflag)) {\
96 printk(printstr, ##__VA_ARGS__); \
97 } \
98 } while(0)
99
100#define BTC_PRINT_F(dbgtype, dbgflag, printstr, ...) \
101 do { \
102 if (unlikely(btc_dbg_type[dbgtype] & dbgflag)) {\
103 printk(KERN_DEBUG "%s: ", __func__); \
104 printk(printstr, ##__VA_ARGS__); \
105 } \
106 } while(0)
107
108#define BTC_PRINT_ADDR(dbgtype, dbgflag, printstr, _ptr) \
109 do { \
110 if(unlikely(btc_dbg_type[dbgtype] & dbgflag)) { \
111 int __i; \
112 u8* __ptr = (u8*)_Ptr; \
113 printk printstr; \
114 for( __i = 0; __i < 6; __i++ ) \
115 printk("%02X%s", __ptr[__i], (__i==5)?"":"-");\
116 printk(KERN_DEBUG "\n"); \
117 }\
118 } while(0)
119
120#define BTC_PRINT_DATA(dbgtype, dbgflag, _titlestring, _hexdata, _hexdatalen) \
121 do { \
122 if(unlikely(btc_dbg_type[dbgtype] & dbgflag) ) { \
123 int __i; \
124 u8 *__ptr = (u8*)_hexdata; \
125 printk(_titlestring); \
126 for( __i = 0; __i < (int)_hexdatalen; __i++ ) { \
127 printk("%02X%s", __ptr[__i], (((__i + 1) % 4) \
128 == 0)?" ":" ");\
129 if (((__i + 1) % 16) == 0) \
130 printk("\n"); \
131 } \
132 printk(KERN_DEBUG "\n"); \
133 } \
134 } while(0)
135
136
137#define BTC_RSSI_HIGH(_rssi_) \
138 ((_rssi_==BTC_RSSI_STATE_HIGH || _rssi_==BTC_RSSI_STATE_STAY_HIGH) ? \
139 true : false)
140
141#define BTC_RSSI_MEDIUM(_rssi_) \
142 ((_rssi_==BTC_RSSI_STATE_MEDIUM || _rssi_==BTC_RSSI_STATE_STAY_MEDIUM) \
143 ? true : false)
144
145#define BTC_RSSI_LOW(_rssi_) \
146 ((_rssi_==BTC_RSSI_STATE_LOW || _rssi_==BTC_RSSI_STATE_STAY_LOW) ? \
147 true : false)
148
149
150enum btc_power_save_type {
151 BTC_PS_WIFI_NATIVE = 0,
152 BTC_PS_LPS_ON = 1,
153 BTC_PS_LPS_OFF = 2,
154 BTC_PS_LPS_MAX
155};
156
157struct btc_board_info {
158 /* The following is some board information */
159 u8 bt_chip_type;
160 u8 pg_ant_num; /* pg ant number */
161 u8 btdm_ant_num; /* ant number for btdm */
162 u8 btdm_ant_pos;
163 bool bt_exist;
164};
165
166enum btc_dbg_opcode{
167 BTC_DBG_SET_COEX_NORMAL = 0x0,
168 BTC_DBG_SET_COEX_WIFI_ONLY = 0x1,
169 BTC_DBG_SET_COEX_BT_ONLY = 0x2,
170 BTC_DBG_MAX
171};
172
173enum btc_rssi_state{
174 BTC_RSSI_STATE_HIGH = 0x0,
175 BTC_RSSI_STATE_MEDIUM = 0x1,
176 BTC_RSSI_STATE_LOW = 0x2,
177 BTC_RSSI_STATE_STAY_HIGH = 0x3,
178 BTC_RSSI_STATE_STAY_MEDIUM = 0x4,
179 BTC_RSSI_STATE_STAY_LOW = 0x5,
180 BTC_RSSI_MAX
181};
182
183enum btc_wifi_role{
184 BTC_ROLE_STATION = 0x0,
185 BTC_ROLE_AP = 0x1,
186 BTC_ROLE_IBSS = 0x2,
187 BTC_ROLE_HS_MODE = 0x3,
188 BTC_ROLE_MAX
189};
190
191enum btc_wifi_bw_mode{
192 BTC_WIFI_BW_LEGACY = 0x0,
193 BTC_WIFI_BW_HT20 = 0x1,
194 BTC_WIFI_BW_HT40 = 0x2,
195 BTC_WIFI_BW_MAX
196};
197
198enum btc_wifi_traffic_dir{
199 BTC_WIFI_TRAFFIC_TX = 0x0,
200 BTC_WIFI_TRAFFIC_RX = 0x1,
201 BTC_WIFI_TRAFFIC_MAX
202};
203
204enum btc_wifi_pnp{
205 BTC_WIFI_PNP_WAKE_UP = 0x0,
206 BTC_WIFI_PNP_SLEEP = 0x1,
207 BTC_WIFI_PNP_MAX
208};
209
210
211enum btc_get_type{
212 /* type bool */
213 BTC_GET_BL_HS_OPERATION,
214 BTC_GET_BL_HS_CONNECTING,
215 BTC_GET_BL_WIFI_CONNECTED,
216 BTC_GET_BL_WIFI_BUSY,
217 BTC_GET_BL_WIFI_SCAN,
218 BTC_GET_BL_WIFI_LINK,
219 BTC_GET_BL_WIFI_DHCP,
220 BTC_GET_BL_WIFI_SOFTAP_IDLE,
221 BTC_GET_BL_WIFI_SOFTAP_LINKING,
222 BTC_GET_BL_WIFI_IN_EARLY_SUSPEND,
223 BTC_GET_BL_WIFI_ROAM,
224 BTC_GET_BL_WIFI_4_WAY_PROGRESS,
225 BTC_GET_BL_WIFI_UNDER_5G,
226 BTC_GET_BL_WIFI_AP_MODE_ENABLE,
227 BTC_GET_BL_WIFI_ENABLE_ENCRYPTION,
228 BTC_GET_BL_WIFI_UNDER_B_MODE,
229 BTC_GET_BL_EXT_SWITCH,
230
231 /* type s4Byte */
232 BTC_GET_S4_WIFI_RSSI,
233 BTC_GET_S4_HS_RSSI,
234
235 /* type u32 */
236 BTC_GET_U4_WIFI_BW,
237 BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
238 BTC_GET_U4_WIFI_FW_VER,
239 BTC_GET_U4_BT_PATCH_VER,
240
241 /* type u1Byte */
242 BTC_GET_U1_WIFI_DOT11_CHNL,
243 BTC_GET_U1_WIFI_CENTRAL_CHNL,
244 BTC_GET_U1_WIFI_HS_CHNL,
245 BTC_GET_U1_MAC_PHY_MODE,
246 BTC_GET_U1_AP_NUM,
247
248 /* for 1Ant */
249 BTC_GET_U1_LPS_MODE,
250 BTC_GET_BL_BT_SCO_BUSY,
251
252 /* for test mode */
253 BTC_GET_DRIVER_TEST_CFG,
254#if 0
255 BTC_GET_U1_LPS,
256 BTC_GET_U1_RPWM,
257#endif
258 BTC_GET_MAX
259};
260
261
262enum btc_set_type{
263 /* type bool */
264 BTC_SET_BL_BT_DISABLE,
265 BTC_SET_BL_BT_TRAFFIC_BUSY,
266 BTC_SET_BL_BT_LIMITED_DIG,
267 BTC_SET_BL_FORCE_TO_ROAM,
268 BTC_SET_BL_TO_REJ_AP_AGG_PKT,
269 BTC_SET_BL_BT_CTRL_AGG_SIZE,
270 BTC_SET_BL_INC_SCAN_DEV_NUM,
271
272 /* type u1Byte */
273 BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
274 BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
275 BTC_SET_UI_SCAN_SIG_COMPENSATION,
276 BTC_SET_U1_AGG_BUF_SIZE,
277
278 /* type trigger some action */
279 BTC_SET_ACT_GET_BT_RSSI,
280 BTC_SET_ACT_AGGREGATE_CTRL,
281
282 /********* for 1Ant **********/
283 /* type bool */
284 BTC_SET_BL_BT_SCO_BUSY,
285 /* type u1Byte */
286 BTC_SET_U1_1ANT_LPS,
287 BTC_SET_U1_1ANT_RPWM,
288 /* type trigger some action */
289 BTC_SET_ACT_LEAVE_LPS,
290 BTC_SET_ACT_ENTER_LPS,
291 BTC_SET_ACT_NORMAL_LPS,
292 BTC_SET_ACT_INC_FORCE_EXEC_PWR_CMD_CNT,
293 BTC_SET_ACT_DISABLE_LOW_POWER,
294 BTC_SET_ACT_UPDATE_ra_mask,
295 BTC_SET_ACT_SEND_MIMO_PS,
296 /* BT Coex related */
297 BTC_SET_ACT_CTRL_BT_INFO,
298 BTC_SET_ACT_CTRL_BT_COEX,
299 /***************************/
300 BTC_SET_MAX
301};
302
303enum btc_dbg_disp_type{
304 BTC_DBG_DISP_COEX_STATISTICS = 0x0,
305 BTC_DBG_DISP_BT_LINK_INFO = 0x1,
306 BTC_DBG_DISP_BT_FW_VER = 0x2,
307 BTC_DBG_DISP_FW_PWR_MODE_CMD = 0x3,
308 BTC_DBG_DISP_MAX
309};
310
311enum btc_notify_type_ips{
312 BTC_IPS_LEAVE = 0x0,
313 BTC_IPS_ENTER = 0x1,
314 BTC_IPS_MAX
315};
316
317enum btc_notify_type_lps{
318 BTC_LPS_DISABLE = 0x0,
319 BTC_LPS_ENABLE = 0x1,
320 BTC_LPS_MAX
321};
322
323enum btc_notify_type_scan{
324 BTC_SCAN_FINISH = 0x0,
325 BTC_SCAN_START = 0x1,
326 BTC_SCAN_MAX
327};
328
329enum btc_notify_type_associate{
330 BTC_ASSOCIATE_FINISH = 0x0,
331 BTC_ASSOCIATE_START = 0x1,
332 BTC_ASSOCIATE_MAX
333};
334
335enum btc_notify_type_media_status{
336 BTC_MEDIA_DISCONNECT = 0x0,
337 BTC_MEDIA_CONNECT = 0x1,
338 BTC_MEDIA_MAX
339};
340
341enum btc_notify_type_special_packet{
342 BTC_PACKET_UNKNOWN = 0x0,
343 BTC_PACKET_DHCP = 0x1,
344 BTC_PACKET_ARP = 0x2,
345 BTC_PACKET_EAPOL = 0x3,
346 BTC_PACKET_MAX
347};
348
349enum btc_notify_type_stack_operation{
350 BTC_STACK_OP_NONE = 0x0,
351 BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1,
352 BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2,
353 BTC_STACK_OP_MAX
354};
355
356
357typedef u8 (*bfp_btc_r1)(void *btc_context, u32 reg_addr);
358
359typedef u16 (*bfp_btc_r2)(void *btc_context, u32 reg_addr);
360
361typedef u32 (*bfp_btc_r4)(void *btc_context, u32 reg_addr);
362
363typedef void (*bfp_btc_w1)(void *btc_context, u32 reg_addr, u8 data);
364
365typedef void (*bfp_btc_w1_bit_mak)(void *btc_context, u32 reg_addr,
366 u8 bit_mask, u8 data1b);
367
368typedef void (*bfp_btc_w2)(void *btc_context, u32 reg_addr, u16 data);
369
370typedef void (*bfp_btc_w4)(void *btc_context, u32 reg_addr, u32 data);
371
372typedef void (*bfp_btc_wr_1byte_bit_mask)(void *btc_context, u32 reg_addr,
373 u8 bit_mask, u8 data);
374
375typedef void (*bfp_btc_set_bb_reg)(void *btc_context, u32 reg_addr,
376 u32 bit_mask, u32 data);
377
378typedef u32 (*bfp_btc_get_bb_reg)(void *btc_context, u32 reg_addr,
379 u32 bit_mask);
380
381typedef void (*bfp_btc_set_rf_reg)(void *btc_context, u8 rf_path, u32 reg_addr,
382 u32 bit_mask, u32 data);
383
384typedef u32 (*bfp_btc_get_rf_reg)(void *btc_context, u8 rf_path,
385 u32 reg_addr, u32 bit_mask);
386
387typedef void (*bfp_btc_fill_h2c)(void *btc_context, u8 element_id,
388 u32 cmd_len, u8 *cmd_buffer);
389
390typedef bool (*bfp_btc_get)(void *btcoexist, u8 get_type, void *out_buf);
391
392typedef bool (*bfp_btc_set)(void *btcoexist, u8 set_type, void *in_buf);
393
394typedef void (*bfp_btc_disp_dbg_msg)(void *btcoexist, u8 disp_type);
395
396struct btc_bt_info {
397 bool bt_disabled;
398 u8 rssi_adjust_for_agc_table_on;
399 u8 rssi_adjust_for_1ant_coex_type;
400 bool bt_busy;
401 u8 agg_buf_size;
402 bool limited_dig;
403 bool reject_agg_pkt;
404 bool b_bt_ctrl_buf_size;
405 bool increase_scan_dev_num;
406 u16 bt_hci_ver;
407 u16 bt_real_fw_ver;
408 u8 bt_fw_ver;
409
410 /* the following is for 1Ant solution */
411 bool bt_ctrl_lps;
412 bool bt_pwr_save_mode;
413 bool bt_lps_on;
414 bool force_to_roam;
415 u8 force_exec_pwr_cmd_cnt;
416 u8 lps_1ant;
417 u8 rpwm_1ant;
418 u32 ra_mask;
419};
420
421struct btc_stack_info {
422 bool profile_notified;
423 u16 hci_version; /* stack hci version */
424 u8 num_of_link;
425 bool bt_link_exist;
426 bool sco_exist;
427 bool acl_exist;
428 bool a2dp_exist;
429 bool hid_exist;
430 u8 num_of_hid;
431 bool pan_exist;
432 bool unknown_acl_exist;
433 char min_bt_rssi;
434};
435
436struct btc_statistics {
437 u32 cnt_bind;
438 u32 cnt_init_hw_config;
439 u32 cnt_init_coex_dm;
440 u32 cnt_ips_notify;
441 u32 cnt_lps_notify;
442 u32 cnt_scan_notify;
443 u32 cnt_connect_notify;
444 u32 cnt_media_status_notify;
445 u32 cnt_special_packet_notify;
446 u32 cnt_bt_info_notify;
447 u32 cnt_periodical;
448 u32 cnt_stack_operation_notify;
449 u32 cnt_dbg_ctrl;
450};
451
452struct btc_bt_link_info {
453 bool bt_link_exist;
454 bool sco_exist;
455 bool sco_only;
456 bool a2dp_exist;
457 bool a2dp_only;
458 bool hid_exist;
459 bool hid_only;
460 bool pan_exist;
461 bool pan_only;
462};
463
464enum btc_antenna_pos {
465 BTC_ANTENNA_AT_MAIN_PORT = 0x1,
466 BTC_ANTENNA_AT_AUX_PORT = 0x2,
467};
468
469struct btc_coexist {
470 /* make sure only one adapter can bind the data context */
471 bool binded;
472 /* default adapter */
473 void *adapter;
474 struct btc_board_info board_info;
475 /* some bt info referenced by non-bt module */
476 struct btc_bt_info bt_info;
477 struct btc_stack_info stack_info;
478 enum btc_chip_interface chip_interface;
479 struct btc_bt_link_info bt_link_info;
480
481 bool initilized;
482 bool stop_coex_dm;
483 bool manual_control;
484 u8 *cli_buf;
485 struct btc_statistics statistics;
486 u8 pwr_mode_val[10];
487
488 /* function pointers
489 * io related */
490 bfp_btc_r1 btc_read_1byte;
491 bfp_btc_w1 btc_write_1byte;
492 bfp_btc_w1_bit_mak btc_write_1byte_bitmask;
493 bfp_btc_r2 btc_read_2byte;
494 bfp_btc_w2 btc_write_2byte;
495 bfp_btc_r4 btc_read_4byte;
496 bfp_btc_w4 btc_write_4byte;
497
498 bfp_btc_set_bb_reg btc_set_bb_reg;
499 bfp_btc_get_bb_reg btc_get_bb_reg;
500
501
502 bfp_btc_set_rf_reg btc_set_rf_reg;
503 bfp_btc_get_rf_reg btc_get_rf_reg;
504
505
506 bfp_btc_fill_h2c btc_fill_h2c;
507
508 bfp_btc_disp_dbg_msg btc_disp_dbg_msg;
509
510 bfp_btc_get btc_get;
511 bfp_btc_set btc_set;
512};
513
514bool halbtc_is_wifi_uplink(struct rtl_priv *adapter);
515
516
517extern struct btc_coexist gl_bt_coexist;
518
519bool exhalbtc_initlize_variables(struct rtl_priv* adapter);
520void exhalbtc_init_hw_config(struct btc_coexist *btcoexist);
521void exhalbtc_init_coex_dm(struct btc_coexist *btcoexist);
522void exhalbtc_ips_notify(struct btc_coexist *btcoexist, u8 type);
523void exhalbtc_lps_notify(struct btc_coexist *btcoexist, u8 type);
524void exhalbtc_scan_notify(struct btc_coexist *btcoexist, u8 type);
525void exhalbtc_connect_notify(struct btc_coexist *btcoexist, u8 action);
526void exhalbtc_mediastatus_notify(struct btc_coexist *btcoexist,
527 enum rt_media_status media_status);
528void exhalbtc_special_packet_notify(struct btc_coexist *btcoexist, u8 pkt_type);
529void exhalbtc_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
530 u8 length);
531void exhalbtc_stack_operation_notify(struct btc_coexist *btcoexist, u8 type);
532void exhalbtc_halt_notify(struct btc_coexist *btcoexist);
533void exhalbtc_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state);
534void exhalbtc_periodical(struct btc_coexist *btcoexist);
535void exhalbtc_dbg_control(struct btc_coexist *btcoexist, u8 code, u8 len,
536 u8 *data);
537void exhalbtc_stack_update_profile_info(void);
538void exhalbtc_set_hci_version(u16 hci_version);
539void exhalbtc_set_bt_patch_version(u16 bt_hci_version, u16 bt_patch_version);
540void exhalbtc_update_min_bt_rssi(char bt_rssi);
541void exhalbtc_set_bt_exist(bool bt_exist);
542void exhalbtc_set_chip_type(u8 chip_type);
543void exhalbtc_set_ant_num(u8 type, u8 ant_num);
544void exhalbtc_display_bt_coex_info(struct btc_coexist *btcoexist);
545void exhalbtc_signal_compensation(struct btc_coexist *btcoexist,
546 u8 *rssi_wifi, u8 *rssi_bt);
547void exhalbtc_lps_leave(struct btc_coexist *btcoexist);
548void exhalbtc_low_wifi_traffic_notify(struct btc_coexist *btcoexist);
549#endif
diff --git a/drivers/staging/rtl8821ae/btcoexist/rtl_btc.c b/drivers/staging/rtl8821ae/btcoexist/rtl_btc.c
new file mode 100644
index 000000000000..6653f147757c
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/rtl_btc.c
@@ -0,0 +1,236 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29#include <linux/vmalloc.h>
30#include <linux/module.h>
31
32#include "rtl_btc.h"
33#include "halbt_precomp.h"
34
35struct rtl_btc_ops rtl_btc_operation ={
36 .btc_init_variables = rtl_btc_init_variables,
37 .btc_init_hal_vars = rtl_btc_init_hal_vars,
38 .btc_init_hw_config = rtl_btc_init_hw_config,
39 .btc_ips_notify = rtl_btc_ips_notify,
40 .btc_scan_notify = rtl_btc_scan_notify,
41 .btc_connect_notify = rtl_btc_connect_notify,
42 .btc_mediastatus_notify = rtl_btc_mediastatus_notify,
43 .btc_periodical = rtl_btc_periodical,
44 .btc_halt_notify = rtl_btc_halt_notify,
45 .btc_btinfo_notify = rtl_btc_btinfo_notify,
46 .btc_is_limited_dig = rtl_btc_is_limited_dig,
47 .btc_is_disable_edca_turbo = rtl_btc_is_disable_edca_turbo,
48 .btc_is_bt_disabled = rtl_btc_is_bt_disabled,
49};
50
51
52void rtl_btc_init_variables(struct rtl_priv *rtlpriv)
53{
54
55 exhalbtc_initlize_variables(rtlpriv);
56}
57
58void rtl_btc_init_hal_vars(struct rtl_priv *rtlpriv)
59{
60 u8 ant_num;
61 u8 bt_exist;
62 u8 bt_type;
63 ant_num = rtl_get_hwpg_ant_num(rtlpriv);
64 RT_TRACE(COMP_INIT, DBG_DMESG, ("%s, antNum is %d\n", __func__, ant_num));
65
66 bt_exist = rtl_get_hwpg_bt_exist(rtlpriv);
67 RT_TRACE(COMP_INIT, DBG_DMESG, ("%s, bt_exist is %d\n", __func__, bt_exist));
68 exhalbtc_set_bt_exist(bt_exist);
69
70 bt_type = rtl_get_hwpg_bt_type(rtlpriv);
71 RT_TRACE(COMP_INIT, DBG_DMESG, ("%s, bt_type is %d\n", __func__, bt_type));
72 exhalbtc_set_chip_type(bt_type);
73
74 exhalbtc_set_ant_num(BT_COEX_ANT_TYPE_PG, ant_num);
75
76}
77
78
79void rtl_btc_init_hw_config(struct rtl_priv *rtlpriv)
80{
81 exhalbtc_init_hw_config(&gl_bt_coexist);
82 exhalbtc_init_coex_dm(&gl_bt_coexist);
83}
84
85
86void rtl_btc_ips_notify(struct rtl_priv *rtlpriv, u8 type)
87{
88 exhalbtc_ips_notify(&gl_bt_coexist, type);
89}
90
91
92void rtl_btc_scan_notify(struct rtl_priv *rtlpriv, u8 scantype)
93{
94 exhalbtc_scan_notify(&gl_bt_coexist, scantype);
95}
96
97
98void rtl_btc_connect_notify(struct rtl_priv *rtlpriv, u8 action)
99{
100 exhalbtc_connect_notify(&gl_bt_coexist, action);
101}
102
103
104void rtl_btc_mediastatus_notify(struct rtl_priv *rtlpriv, enum rt_media_status mstatus)
105{
106 exhalbtc_mediastatus_notify(&gl_bt_coexist, mstatus);
107}
108
109void rtl_btc_periodical(struct rtl_priv *rtlpriv)
110{
111// rtl_bt_dm_monitor();
112 exhalbtc_periodical(&gl_bt_coexist);
113}
114
115void rtl_btc_halt_notify(void)
116{
117 exhalbtc_halt_notify(&gl_bt_coexist);
118}
119
120void rtl_btc_btinfo_notify(struct rtl_priv *rtlpriv, u8 * tmp_buf, u8 length)
121{
122 exhalbtc_bt_info_notify(&gl_bt_coexist, tmp_buf, length);
123}
124
125bool rtl_btc_is_limited_dig(struct rtl_priv *rtlpriv)
126{
127 return gl_bt_coexist.bt_info.limited_dig;
128}
129
130bool rtl_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv)
131{
132 bool bt_change_edca = false;
133 u32 cur_edca_val;
134 u32 edca_bt_hs_uplink = 0x5ea42b, edca_bt_hs_downlink = 0x5ea42b;
135 u32 edca_hs;
136 u32 edca_addr = 0x504;
137
138 cur_edca_val = rtl_read_dword(rtlpriv, edca_addr);
139 if (halbtc_is_wifi_uplink(rtlpriv)){
140 if (cur_edca_val != edca_bt_hs_uplink){
141 edca_hs = edca_bt_hs_uplink;
142 bt_change_edca = true;
143 }
144 }else{
145 if (cur_edca_val != edca_bt_hs_downlink){
146 edca_hs = edca_bt_hs_downlink;
147 bt_change_edca = true;
148 }
149 }
150
151 if(bt_change_edca)
152 rtl_write_dword(rtlpriv, edca_addr, edca_hs);
153
154 return true;
155}
156
157bool rtl_btc_is_bt_disabled(struct rtl_priv *rtlpriv)
158{
159 if (gl_bt_coexist.bt_info.bt_disabled)
160 return true;
161 else
162 return false;
163}
164
165struct rtl_btc_ops *rtl_btc_get_ops_pointer(void)
166{
167 return &rtl_btc_operation;
168}
169//EXPORT_SYMBOL(rtl_btc_get_ops_pointer);
170
171u8 rtl_get_hwpg_ant_num(struct rtl_priv *rtlpriv)
172{
173 u8 num;
174
175 if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2)
176 num = 2;
177 else
178 num = 1;
179
180 return num;
181}
182
183#if 0
184enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw)
185{
186 struct rtl_priv *rtlpriv = rtl_priv(hw);
187 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
188 enum rt_media_status m_status = RT_MEDIA_DISCONNECT;
189
190 u8 bibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ? 1 : 0;
191
192 if(bibss || rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
193 m_status = RT_MEDIA_CONNECT;
194 }
195
196 return m_status;
197}
198#endif
199
200u8 rtl_get_hwpg_bt_exist(struct rtl_priv *rtlpriv)
201{
202 return rtlpriv->btcoexist.btc_info.btcoexist;
203}
204
205u8 rtl_get_hwpg_bt_type(struct rtl_priv *rtlpriv)
206{
207 return rtlpriv->btcoexist.btc_info.bt_type;
208}
209
210
211#if 0
212
213MODULE_AUTHOR("Page He <page_he@realsil.com.cn>");
214MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
215MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
216MODULE_LICENSE("GPL");
217MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
218
219static int __init rtl_btcoexist_module_init(void)
220{
221
222 //printk("%s, rtlpriv->btc_ops.btc_init_variables addr is %p\n", __func__, rtlpriv->btc_ops.btc_init_variables);
223
224 return 0;
225}
226
227static void __exit rtl_btcoexist_module_exit(void)
228{
229 return;
230}
231
232module_init(rtl_btcoexist_module_init);
233module_exit(rtl_btcoexist_module_exit);
234
235#endif
236
diff --git a/drivers/staging/rtl8821ae/btcoexist/rtl_btc.h b/drivers/staging/rtl8821ae/btcoexist/rtl_btc.h
new file mode 100644
index 000000000000..452fbf1e6d1e
--- /dev/null
+++ b/drivers/staging/rtl8821ae/btcoexist/rtl_btc.h
@@ -0,0 +1,66 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 * Larry Finger <Larry.Finger@lwfinger.net>
26 *
27 *****************************************************************************/
28
29#ifndef __RTL_BTC_H__
30#define __RTL_BTC_H__
31
32#include "halbt_precomp.h"
33
34
35
36void rtl_btc_init_variables(struct rtl_priv *rtlpriv);
37void rtl_btc_init_hal_vars(struct rtl_priv *rtlpriv);
38void rtl_btc_init_hw_config(struct rtl_priv *rtlpriv);
39void rtl_btc_ips_notify(struct rtl_priv *rtlpriv, u8 type);
40void rtl_btc_scan_notify(struct rtl_priv *rtlpriv, u8 scantype);
41void rtl_btc_connect_notify(struct rtl_priv *rtlpriv, u8 action);
42void rtl_btc_mediastatus_notify(struct rtl_priv *rtlpriv, enum rt_media_status mstatus);
43void rtl_btc_periodical(struct rtl_priv *rtlpriv);
44void rtl_btc_halt_notify(void);
45void rtl_btc_btinfo_notify(struct rtl_priv *rtlpriv, u8 * tmpBuf, u8 length);
46bool rtl_btc_is_limited_dig(struct rtl_priv *rtlpriv);
47bool rtl_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv);
48bool rtl_btc_is_bt_disabled(struct rtl_priv *rtlpriv);
49
50
51//extern struct rtl_btc_ops rtl_btc_operation;
52extern struct rtl_btc_ops *rtl_btc_get_ops_pointer(void);
53
54u8 rtl_get_hwpg_ant_num(struct rtl_priv *rtlpriv);
55u8 rtl_get_hwpg_bt_exist(struct rtl_priv *rtlpriv);
56u8 rtl_get_hwpg_bt_type(struct rtl_priv *rtlpriv);
57//enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw);
58
59
60
61
62
63
64
65
66#endif
diff --git a/drivers/staging/rtl8821ae/cam.c b/drivers/staging/rtl8821ae/cam.c
new file mode 100644
index 000000000000..72743e78954b
--- /dev/null
+++ b/drivers/staging/rtl8821ae/cam.c
@@ -0,0 +1,354 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29#include "wifi.h"
30#include "cam.h"
31#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
32#include <linux/export.h>
33#endif
34
35void rtl_cam_reset_sec_info(struct ieee80211_hw *hw)
36{
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
38
39 rtlpriv->sec.use_defaultkey = false;
40 rtlpriv->sec.pairwise_enc_algorithm = NO_ENCRYPTION;
41 rtlpriv->sec.group_enc_algorithm = NO_ENCRYPTION;
42 memset(rtlpriv->sec.key_buf, 0, KEY_BUF_SIZE * MAX_KEY_LEN);
43 memset(rtlpriv->sec.key_len, 0, KEY_BUF_SIZE);
44 rtlpriv->sec.pairwise_key = NULL;
45}
46
47static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no,
48 u8 *mac_addr, u8 *key_cont_128, u16 us_config)
49{
50 struct rtl_priv *rtlpriv = rtl_priv(hw);
51
52 u32 target_command;
53 u32 target_content = 0;
54 u8 entry_i;
55
56 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_DMESG, "Key content :",
57 key_cont_128, 16);
58
59 for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
60 target_command = entry_i + CAM_CONTENT_COUNT * entry_no;
61 target_command = target_command | BIT(31) | BIT(16);
62
63 if (entry_i == 0) {
64 target_content = (u32) (*(mac_addr + 0)) << 16 |
65 (u32) (*(mac_addr + 1)) << 24 | (u32) us_config;
66
67 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
68 target_content);
69 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
70 target_command);
71
72 RT_TRACE(COMP_SEC, DBG_LOUD,
73 ("WRITE %x: %x \n",
74 rtlpriv->cfg->maps[WCAMI], target_content));
75 RT_TRACE(COMP_SEC, DBG_LOUD,
76 ("The Key ID is %d\n", entry_no));
77 RT_TRACE(COMP_SEC, DBG_LOUD,
78 ("WRITE %x: %x \n",
79 rtlpriv->cfg->maps[RWCAM], target_command));
80
81 } else if (entry_i == 1) {
82
83 target_content = (u32) (*(mac_addr + 5)) << 24 |
84 (u32) (*(mac_addr + 4)) << 16 |
85 (u32) (*(mac_addr + 3)) << 8 |
86 (u32) (*(mac_addr + 2));
87
88 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
89 target_content);
90 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
91 target_command);
92
93 RT_TRACE(COMP_SEC, DBG_LOUD,
94 ("WRITE A4: %x \n", target_content));
95 RT_TRACE(COMP_SEC, DBG_LOUD,
96 ("WRITE A0: %x \n", target_command));
97
98 } else {
99
100 target_content =
101 (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 3)) <<
102 24 | (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 2))
103 << 16 |
104 (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 1)) << 8
105 | (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 0));
106
107 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
108 target_content);
109 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
110 target_command);
111 udelay(100);
112
113 RT_TRACE(COMP_SEC, DBG_LOUD,
114 ("WRITE A4: %x \n", target_content));
115 RT_TRACE(COMP_SEC, DBG_LOUD,
116 ("WRITE A0: %x \n", target_command));
117 }
118 }
119
120 RT_TRACE(COMP_SEC, DBG_LOUD,
121 ("after set key, usconfig:%x\n", us_config));
122}
123
124u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
125 u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
126 u32 ul_default_key, u8 *key_content)
127{
128 u32 us_config;
129 struct rtl_priv *rtlpriv = rtl_priv(hw);
130
131 RT_TRACE(COMP_SEC, DBG_DMESG,
132 ("EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, "
133 "ulUseDK=%x MacAddr %pM\n",
134 ul_entry_idx, ul_key_id, ul_enc_alg,
135 ul_default_key, mac_addr));
136
137 if (ul_key_id == TOTAL_CAM_ENTRY) {
138 RT_TRACE(COMP_ERR, DBG_WARNING,
139 ("ulKeyId exceed!\n"));
140 return 0;
141 }
142
143 if (ul_default_key == 1) {
144 us_config = CFG_VALID | ((u16) (ul_enc_alg) << 2);
145 } else {
146 us_config = CFG_VALID | ((ul_enc_alg) << 2) | ul_key_id;
147 }
148
149 rtl_cam_program_entry(hw, ul_entry_idx, mac_addr,
150 (u8 *) key_content, us_config);
151
152 RT_TRACE(COMP_SEC, DBG_DMESG, ("end \n"));
153
154 return 1;
155
156}
157//EXPORT_SYMBOL(rtl_cam_add_one_entry);
158
159int rtl_cam_delete_one_entry(struct ieee80211_hw *hw,
160 u8 *mac_addr, u32 ul_key_id)
161{
162 u32 ul_command;
163 struct rtl_priv *rtlpriv = rtl_priv(hw);
164
165 RT_TRACE(COMP_SEC, DBG_DMESG, ("key_idx:%d\n", ul_key_id));
166
167 ul_command = ul_key_id * CAM_CONTENT_COUNT;
168 ul_command = ul_command | BIT(31) | BIT(16);
169
170 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], 0);
171 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
172
173 RT_TRACE(COMP_SEC, DBG_DMESG,
174 ("rtl_cam_delete_one_entry(): WRITE A4: %x \n", 0));
175 RT_TRACE(COMP_SEC, DBG_DMESG,
176 ("rtl_cam_delete_one_entry(): WRITE A0: %x \n", ul_command));
177
178 return 0;
179
180}
181//EXPORT_SYMBOL(rtl_cam_delete_one_entry);
182
183void rtl_cam_reset_all_entry(struct ieee80211_hw *hw)
184{
185 u32 ul_command;
186 struct rtl_priv *rtlpriv = rtl_priv(hw);
187
188 ul_command = BIT(31) | BIT(30);
189 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
190}
191//EXPORT_SYMBOL(rtl_cam_reset_all_entry);
192
193void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index)
194{
195 struct rtl_priv *rtlpriv = rtl_priv(hw);
196
197 u32 ul_command;
198 u32 ul_content;
199 u32 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
200
201 switch (rtlpriv->sec.pairwise_enc_algorithm) {
202 case WEP40_ENCRYPTION:
203 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
204 break;
205 case WEP104_ENCRYPTION:
206 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
207 break;
208 case TKIP_ENCRYPTION:
209 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
210 break;
211 case AESCCMP_ENCRYPTION:
212 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
213 break;
214 default:
215 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
216 }
217
218 ul_content = (uc_index & 3) | ((u16) (ul_enc_algo) << 2);
219
220 ul_content |= BIT(15);
221 ul_command = CAM_CONTENT_COUNT * uc_index;
222 ul_command = ul_command | BIT(31) | BIT(16);
223
224 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
225 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
226
227 RT_TRACE(COMP_SEC, DBG_DMESG,
228 ("rtl_cam_mark_invalid(): WRITE A4: %x \n", ul_content));
229 RT_TRACE(COMP_SEC, DBG_DMESG,
230 ("rtl_cam_mark_invalid(): WRITE A0: %x \n", ul_command));
231}
232//EXPORT_SYMBOL(rtl_cam_mark_invalid);
233
234void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index)
235{
236 struct rtl_priv *rtlpriv = rtl_priv(hw);
237
238 u32 ul_command;
239 u32 ul_content;
240 u32 ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
241 u8 entry_i;
242
243 switch (rtlpriv->sec.pairwise_enc_algorithm) {
244 case WEP40_ENCRYPTION:
245 ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
246 break;
247 case WEP104_ENCRYPTION:
248 ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
249 break;
250 case TKIP_ENCRYPTION:
251 ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
252 break;
253 case AESCCMP_ENCRYPTION:
254 ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
255 break;
256 default:
257 ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
258 }
259
260 for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
261
262 if (entry_i == 0) {
263 ul_content =
264 (uc_index & 0x03) | ((u16) (ul_encalgo) << 2);
265 ul_content |= BIT(15);
266
267 } else {
268 ul_content = 0;
269 }
270
271 ul_command = CAM_CONTENT_COUNT * uc_index + entry_i;
272 ul_command = ul_command | BIT(31) | BIT(16);
273
274 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
275 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
276
277 RT_TRACE(COMP_SEC, DBG_LOUD,
278 ("rtl_cam_empty_entry(): WRITE A4: %x \n",
279 ul_content));
280 RT_TRACE(COMP_SEC, DBG_LOUD,
281 ("rtl_cam_empty_entry(): WRITE A0: %x \n",
282 ul_command));
283 }
284
285}
286//EXPORT_SYMBOL(rtl_cam_empty_entry);
287
288u8 rtl_cam_get_free_entry(struct ieee80211_hw *hw, u8 *sta_addr)
289{
290 struct rtl_priv *rtlpriv = rtl_priv(hw);
291 u32 bitmap = (rtlpriv->sec.hwsec_cam_bitmap) >> 4;
292 u8 entry_idx = 0;
293 u8 i, *addr;
294
295 if (NULL == sta_addr) {
296 RT_TRACE(COMP_SEC, DBG_EMERG,
297 ("sta_addr is NULL.\n"));
298 return TOTAL_CAM_ENTRY;
299 }
300 /* Does STA already exist? */
301 for (i = 4; i < TOTAL_CAM_ENTRY; i++) {
302 addr = rtlpriv->sec.hwsec_cam_sta_addr[i];
303 if(memcmp(addr, sta_addr, ETH_ALEN) == 0)
304 return i;
305 }
306 /* Get a free CAM entry. */
307 for (entry_idx = 4; entry_idx < TOTAL_CAM_ENTRY; entry_idx++) {
308 if ((bitmap & BIT(0)) == 0) {
309 RT_TRACE(COMP_SEC, DBG_EMERG,
310 ("-----hwsec_cam_bitmap: 0x%x entry_idx=%d\n",
311 rtlpriv->sec.hwsec_cam_bitmap, entry_idx));
312 rtlpriv->sec.hwsec_cam_bitmap |= BIT(0) << entry_idx;
313 memcpy(rtlpriv->sec.hwsec_cam_sta_addr[entry_idx],
314 sta_addr, ETH_ALEN);
315 return entry_idx;
316 }
317 bitmap = bitmap >>1;
318 }
319 return TOTAL_CAM_ENTRY;
320}
321//EXPORT_SYMBOL(rtl_cam_get_free_entry);
322
323void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr)
324{
325 struct rtl_priv *rtlpriv = rtl_priv(hw);
326 u32 bitmap;
327 u8 i, *addr;
328
329 if (NULL == sta_addr) {
330 RT_TRACE(COMP_SEC, DBG_EMERG,
331 ("sta_addr is NULL.\n"));
332 }
333
334 if ((sta_addr[0]|sta_addr[1]|sta_addr[2]|sta_addr[3]|\
335 sta_addr[4]|sta_addr[5]) == 0) {
336 RT_TRACE(COMP_SEC, DBG_EMERG,
337 ("sta_addr is 00:00:00:00:00:00.\n"));
338 return;
339 }
340 /* Does STA already exist? */
341 for (i = 4; i < TOTAL_CAM_ENTRY; i++) {
342 addr = rtlpriv->sec.hwsec_cam_sta_addr[i];
343 bitmap = (rtlpriv->sec.hwsec_cam_bitmap) >> i;
344 if (((bitmap & BIT(0)) == BIT(0)) &&
345 (memcmp(addr, sta_addr, ETH_ALEN) == 0)) {
346 /* Remove from HW Security CAM */
347 memset(rtlpriv->sec.hwsec_cam_sta_addr[i], 0, ETH_ALEN);
348 rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i);
349 printk("&&&&&&&&&del entry %d\n",i);
350 }
351 }
352 return;
353}
354//EXPORT_SYMBOL(rtl_cam_del_entry);
diff --git a/drivers/staging/rtl8821ae/cam.h b/drivers/staging/rtl8821ae/cam.h
new file mode 100644
index 000000000000..326fa6784ae5
--- /dev/null
+++ b/drivers/staging/rtl8821ae/cam.h
@@ -0,0 +1,56 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_CAM_H_
31#define __RTL_CAM_H_
32
33#define CAM_CONTENT_COUNT 8
34
35#define CFG_DEFAULT_KEY BIT(5)
36#define CFG_VALID BIT(15)
37
38#define PAIRWISE_KEYIDX 0
39#define CAM_PAIRWISE_KEY_POSITION 4
40
41#define CAM_CONFIG_USEDK 1
42#define CAM_CONFIG_NO_USEDK 0
43
44extern void rtl_cam_reset_all_entry(struct ieee80211_hw *hw);
45extern u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
46 u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
47 u32 ul_default_key, u8 *key_content);
48int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
49 u32 ul_key_id);
50void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index);
51void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index);
52void rtl_cam_reset_sec_info(struct ieee80211_hw *hw);
53u8 rtl_cam_get_free_entry(struct ieee80211_hw *hw, u8 *sta_addr);
54void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr);
55
56#endif
diff --git a/drivers/staging/rtl8821ae/compat.h b/drivers/staging/rtl8821ae/compat.h
new file mode 100644
index 000000000000..68269cc2d477
--- /dev/null
+++ b/drivers/staging/rtl8821ae/compat.h
@@ -0,0 +1,125 @@
1#ifndef __RTL_COMPAT_H__
2#define __RTL_COMPAT_H__
3
4#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29))
5/*
6 * Use this if you want to use the same suspend and resume callbacks for suspend
7 * to RAM and hibernation.
8 */
9#define SIMPLE_DEV_PM_OPS(name, suspend_fn, resume_fn) \
10struct dev_pm_ops name = { \
11 .suspend = suspend_fn, \
12 .resume = resume_fn, \
13 .freeze = suspend_fn, \
14 .thaw = resume_fn, \
15 .poweroff = suspend_fn, \
16 .restore = resume_fn, \
17}
18
19#define compat_pci_suspend(fn) \
20 int fn##_compat(struct pci_dev *pdev, pm_message_t state) \
21 { \
22 int r; \
23 \
24 r = fn(&pdev->dev); \
25 if (r) \
26 return r; \
27 \
28 pci_save_state(pdev); \
29 pci_disable_device(pdev); \
30 pci_set_power_state(pdev, PCI_D3hot); \
31 \
32 return 0; \
33 }
34
35#define compat_pci_resume(fn) \
36 int fn##_compat(struct pci_dev *pdev) \
37 { \
38 int r; \
39 \
40 pci_set_power_state(pdev, PCI_D0); \
41 r = pci_enable_device(pdev); \
42 if (r) \
43 return r; \
44 pci_restore_state(pdev); \
45 \
46 return fn(&pdev->dev); \
47 }
48#endif
49
50#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39))
51#define RX_FLAG_MACTIME_MPDU RX_FLAG_TSFT
52#else
53#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0))
54#define RX_FLAG_MACTIME_MPDU RX_FLAG_MACTIME_START
55#else
56#endif
57//#define NETDEV_TX_OK
58#endif
59
60#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
61#define IEEE80211_KEY_FLAG_SW_MGMT IEEE80211_KEY_FLAG_SW_MGMT_TX
62#endif
63
64struct ieee80211_mgmt_compat {
65 __le16 frame_control;
66 __le16 duration;
67 u8 da[6];
68 u8 sa[6];
69 u8 bssid[6];
70 __le16 seq_ctrl;
71 union {
72 struct {
73 u8 category;
74 union {
75 struct {
76 u8 action_code;
77 u8 dialog_token;
78 u8 status_code;
79 u8 variable[0];
80 } __attribute__ ((packed)) wme_action;
81 struct{
82 u8 action_code;
83 u8 dialog_token;
84 __le16 capab;
85 __le16 timeout;
86 __le16 start_seq_num;
87 } __attribute__((packed)) addba_req;
88 struct{
89 u8 action_code;
90 u8 dialog_token;
91 __le16 status;
92 __le16 capab;
93 __le16 timeout;
94 } __attribute__((packed)) addba_resp;
95 struct{
96 u8 action_code;
97 __le16 params;
98 __le16 reason_code;
99 } __attribute__((packed)) delba;
100 struct{
101 u8 action_code;
102 /* capab_info for open and confirm,
103 * reason for close
104 */
105 __le16 aux;
106 /* Followed in plink_confirm by status
107 * code, AID and supported rates,
108 * and directly by supported rates in
109 * plink_open and plink_close
110 */
111 u8 variable[0];
112 } __attribute__((packed)) plink_action;
113 struct{
114 u8 action_code;
115 u8 variable[0];
116 } __attribute__((packed)) mesh_action;
117 struct {
118 u8 action;
119 u8 smps_control;
120 } __attribute__ ((packed)) ht_smps;
121 } u;
122 } __attribute__ ((packed)) action;
123 } u;
124} __attribute__ ((packed));
125#endif
diff --git a/drivers/staging/rtl8821ae/core.c b/drivers/staging/rtl8821ae/core.c
new file mode 100644
index 000000000000..40de6089039e
--- /dev/null
+++ b/drivers/staging/rtl8821ae/core.c
@@ -0,0 +1,1464 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "core.h"
32#include "cam.h"
33#include "base.h"
34#include "ps.h"
35
36#include "btcoexist/rtl_btc.h"
37
38/*mutex for start & stop is must here. */
39static int rtl_op_start(struct ieee80211_hw *hw)
40{
41 int err = 0;
42 struct rtl_priv *rtlpriv = rtl_priv(hw);
43 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
44
45 if (!is_hal_stop(rtlhal))
46 return 0;
47 if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
48 return 0;
49 mutex_lock(&rtlpriv->locks.conf_mutex);
50 err = rtlpriv->intf_ops->adapter_start(hw);
51 if (err)
52 goto out;
53 rtl_watch_dog_timer_callback((unsigned long)hw);
54
55out:
56 mutex_unlock(&rtlpriv->locks.conf_mutex);
57 return err;
58}
59
60static void rtl_op_stop(struct ieee80211_hw *hw)
61{
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
64 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
65 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
66
67 if (is_hal_stop(rtlhal))
68 return;
69
70 /* here is must, because adhoc do stop and start,
71 * but stop with RFOFF may cause something wrong,
72 * like adhoc TP */
73 if (unlikely(ppsc->rfpwr_state == ERFOFF))
74 rtl_ips_nic_on(hw);
75
76 mutex_lock(&rtlpriv->locks.conf_mutex);
77
78 mac->link_state = MAC80211_NOLINK;
79 memset(mac->bssid, 0, 6);
80 mac->vendor = PEER_UNKNOWN;
81
82 /*reset sec info */
83 rtl_cam_reset_sec_info(hw);
84
85 rtl_deinit_deferred_work(hw);
86 rtlpriv->intf_ops->adapter_stop(hw);
87
88 mutex_unlock(&rtlpriv->locks.conf_mutex);
89}
90
91/*<delete in kernel start>*/
92#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39))
93static int rtl_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
94{
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
96 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
97 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
98 struct rtl_tcb_desc tcb_desc;
99 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
100
101 if (unlikely(is_hal_stop(rtlhal) || ppsc->rfpwr_state != ERFON))
102 goto err_free;
103
104 if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
105 goto err_free;
106
107 if (!rtlpriv->intf_ops->waitq_insert(hw, skb))
108 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
109
110 return NETDEV_TX_OK;
111
112err_free:
113 dev_kfree_skb_any(skb);
114 return NETDEV_TX_OK;
115}
116#else
117#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
118static void rtl_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
119#else
120/*<delete in kernel end>*/
121static void rtl_op_tx(struct ieee80211_hw *hw,
122 struct ieee80211_tx_control *control,
123 struct sk_buff *skb)
124/*<delete in kernel start>*/
125#endif
126/*<delete in kernel end>*/
127{
128 struct rtl_priv *rtlpriv = rtl_priv(hw);
129 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
130 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
131 struct rtl_tcb_desc tcb_desc;
132 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
133
134 if (unlikely(is_hal_stop(rtlhal) || ppsc->rfpwr_state != ERFON))
135 goto err_free;
136
137 if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
138 goto err_free;
139
140/*<delete in kernel start>*/
141#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
142 if (!rtlpriv->intf_ops->waitq_insert(hw, skb))
143 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
144#else
145/*<delete in kernel end>*/
146 if (!rtlpriv->intf_ops->waitq_insert(hw, control->sta, skb))
147 rtlpriv->intf_ops->adapter_tx(hw, control->sta, skb, &tcb_desc);
148/*<delete in kernel start>*/
149#endif
150/*<delete in kernel end>*/
151 return;
152
153err_free:
154 dev_kfree_skb_any(skb);
155 return;
156}
157/*<delete in kernel start>*/
158#endif
159/*<delete in kernel end>*/
160
161static int rtl_op_add_interface(struct ieee80211_hw *hw,
162 struct ieee80211_vif *vif)
163{
164 struct rtl_priv *rtlpriv = rtl_priv(hw);
165 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
166 int err = 0;
167
168 if (mac->vif) {
169 RT_TRACE(COMP_ERR, DBG_WARNING,
170 ("vif has been set!! mac->vif = 0x%p\n", mac->vif));
171 return -EOPNOTSUPP;
172 }
173
174/*This flag is not defined before kernel 3.4*/
175#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,0))
176 vif->driver_flags |= IEEE80211_VIF_BEACON_FILTER;
177#endif
178
179 rtl_ips_nic_on(hw);
180
181 mutex_lock(&rtlpriv->locks.conf_mutex);
182/*<delete in kernel start>*/
183#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
184 switch (ieee80211_vif_type_p2p(vif)) {
185 case NL80211_IFTYPE_P2P_CLIENT:
186 mac->p2p = P2P_ROLE_CLIENT;
187 /*fall through*/
188#else
189/*<delete in kernel end>*/
190 switch (vif->type) {
191/*<delete in kernel start>*/
192#endif
193/*<delete in kernel end>*/
194 case NL80211_IFTYPE_STATION:
195 if (mac->beacon_enabled == 1) {
196 RT_TRACE(COMP_MAC80211, DBG_LOUD,
197 ("NL80211_IFTYPE_STATION \n"));
198 mac->beacon_enabled = 0;
199 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
200 rtlpriv->cfg->maps[RTL_IBSS_INT_MASKS]);
201 }
202 break;
203 case NL80211_IFTYPE_ADHOC:
204 RT_TRACE(COMP_MAC80211, DBG_LOUD,
205 ("NL80211_IFTYPE_ADHOC \n"));
206
207 mac->link_state = MAC80211_LINKED;
208 rtlpriv->cfg->ops->set_bcn_reg(hw);
209 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
210 mac->basic_rates = 0xfff;
211 else
212 mac->basic_rates = 0xff0;
213 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
214 (u8 *) (&mac->basic_rates));
215
216 break;
217/*<delete in kernel start>*/
218#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
219 case NL80211_IFTYPE_P2P_GO:
220 mac->p2p = P2P_ROLE_GO;
221 /*fall through*/
222#endif
223/*<delete in kernel end>*/
224 case NL80211_IFTYPE_AP:
225 RT_TRACE(COMP_MAC80211, DBG_LOUD,
226 ("NL80211_IFTYPE_AP \n"));
227
228 mac->link_state = MAC80211_LINKED;
229 rtlpriv->cfg->ops->set_bcn_reg(hw);
230 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
231 mac->basic_rates = 0xfff;
232 else
233 mac->basic_rates = 0xff0;
234 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
235 (u8 *) (&mac->basic_rates));
236 break;
237 case NL80211_IFTYPE_MESH_POINT:
238 RT_TRACE(COMP_MAC80211, DBG_LOUD,
239 ("NL80211_IFTYPE_MESH_POINT \n"));
240
241 mac->link_state = MAC80211_LINKED;
242 rtlpriv->cfg->ops->set_bcn_reg(hw);
243 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
244 mac->basic_rates = 0xfff;
245 else
246 mac->basic_rates = 0xff0;
247 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
248 (u8 *) (&mac->basic_rates));
249 break;
250 default:
251 RT_TRACE(COMP_ERR, DBG_EMERG,
252 ("operation mode %d is not support!\n", vif->type));
253 err = -EOPNOTSUPP;
254 goto out;
255 }
256
257#ifdef VIF_TODO
258 if (!rtl_set_vif_info(hw, vif))
259 goto out;
260#endif
261
262 if (mac->p2p) {
263 RT_TRACE(COMP_MAC80211, DBG_LOUD,
264 ("p2p role %x \n",vif->type));
265 mac->basic_rates = 0xff0;/*disable cck rate for p2p*/
266 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
267 (u8 *) (&mac->basic_rates));
268 }
269 mac->vif = vif;
270 mac->opmode = vif->type;
271 rtlpriv->cfg->ops->set_network_type(hw, vif->type);
272 memcpy(mac->mac_addr, vif->addr, ETH_ALEN);
273 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
274
275out:
276 mutex_unlock(&rtlpriv->locks.conf_mutex);
277 return err;
278}
279
280static void rtl_op_remove_interface(struct ieee80211_hw *hw,
281 struct ieee80211_vif *vif)
282{
283 struct rtl_priv *rtlpriv = rtl_priv(hw);
284 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
285
286 mutex_lock(&rtlpriv->locks.conf_mutex);
287
288 /* Free beacon resources */
289 if ((vif->type == NL80211_IFTYPE_AP) ||
290 (vif->type == NL80211_IFTYPE_ADHOC) ||
291 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
292 if (mac->beacon_enabled == 1) {
293 mac->beacon_enabled = 0;
294 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
295 rtlpriv->cfg->maps[RTL_IBSS_INT_MASKS]);
296 }
297 }
298
299 /*
300 *Note: We assume NL80211_IFTYPE_UNSPECIFIED as
301 *NO LINK for our hardware.
302 */
303 mac->p2p = 0;
304 mac->vif = NULL;
305 mac->link_state = MAC80211_NOLINK;
306 memset(mac->bssid, 0, 6);
307 mac->vendor = PEER_UNKNOWN;
308 mac->opmode = NL80211_IFTYPE_UNSPECIFIED;
309 rtlpriv->cfg->ops->set_network_type(hw, mac->opmode);
310
311 mutex_unlock(&rtlpriv->locks.conf_mutex);
312}
313/*<delete in kernel start>*/
314#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
315/*<delete in kernel end>*/
316static int rtl_op_change_interface(struct ieee80211_hw *hw,
317 struct ieee80211_vif *vif,
318 enum nl80211_iftype new_type, bool p2p)
319{
320 struct rtl_priv *rtlpriv = rtl_priv(hw);
321 int ret;
322 rtl_op_remove_interface(hw, vif);
323
324 vif->type = new_type;
325 vif->p2p = p2p;
326 ret = rtl_op_add_interface(hw, vif);
327 RT_TRACE(COMP_MAC80211, DBG_LOUD,
328 (" p2p %x\n",p2p));
329 return ret;
330}
331/*<delete in kernel start>*/
332#endif
333/*<delete in kernel end>*/
334static int rtl_op_config(struct ieee80211_hw *hw, u32 changed)
335{
336 struct rtl_priv *rtlpriv = rtl_priv(hw);
337 struct rtl_phy *rtlphy = &(rtlpriv->phy);
338 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
339 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
340 struct ieee80211_conf *conf = &hw->conf;
341
342 if (mac->skip_scan)
343 return 1;
344
345
346 mutex_lock(&rtlpriv->locks.conf_mutex);
347 if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) { /* BIT(2) */
348 RT_TRACE(COMP_MAC80211, DBG_LOUD,
349 ("IEEE80211_CONF_CHANGE_LISTEN_INTERVAL\n"));
350 }
351
352 /*For IPS */
353 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
354 if (hw->conf.flags & IEEE80211_CONF_IDLE)
355 rtl_ips_nic_off(hw);
356 else
357 rtl_ips_nic_on(hw);
358 } else {
359 /*
360 *although rfoff may not cause by ips, but we will
361 *check the reason in set_rf_power_state function
362 */
363 if (unlikely(ppsc->rfpwr_state == ERFOFF))
364 rtl_ips_nic_on(hw);
365 }
366
367 /*For LPS */
368 if (changed & IEEE80211_CONF_CHANGE_PS) {
369 cancel_delayed_work(&rtlpriv->works.ps_work);
370 cancel_delayed_work(&rtlpriv->works.ps_rfon_wq);
371 if (conf->flags & IEEE80211_CONF_PS) {
372 rtlpriv->psc.sw_ps_enabled = true;
373 /* sleep here is must, or we may recv the beacon and
374 * cause mac80211 into wrong ps state, this will cause
375 * power save nullfunc send fail, and further cause
376 * pkt loss, So sleep must quickly but not immediatly
377 * because that will cause nullfunc send by mac80211
378 * fail, and cause pkt loss, we have tested that 5mA
379 * is worked very well */
380 if (!rtlpriv->psc.multi_buffered)
381 queue_delayed_work(rtlpriv->works.rtl_wq,
382 &rtlpriv->works.ps_work,
383 MSECS(5));
384 } else {
385 rtl_swlps_rf_awake(hw);
386 rtlpriv->psc.sw_ps_enabled = false;
387 }
388 }
389
390 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
391 RT_TRACE(COMP_MAC80211, DBG_LOUD,
392 ("IEEE80211_CONF_CHANGE_RETRY_LIMITS %x\n",
393 hw->conf.long_frame_max_tx_count));
394 mac->retry_long = hw->conf.long_frame_max_tx_count;
395 mac->retry_short = hw->conf.long_frame_max_tx_count;
396 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
397 (u8 *) (&hw->conf.long_frame_max_tx_count));
398 }
399
400 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
401#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
402 struct ieee80211_channel *channel = hw->conf.chandef.chan;
403 enum nl80211_channel_type channel_type =
404 cfg80211_get_chandef_type(&(hw->conf.chandef));
405#else
406 struct ieee80211_channel *channel = hw->conf.channel;
407 enum nl80211_channel_type channel_type = hw->conf.channel_type;
408#endif
409 u8 wide_chan = (u8) channel->hw_value;
410
411 if (mac->act_scanning)
412 mac->n_channels++;
413
414 if (rtlpriv->dm.supp_phymode_switch &&
415 mac->link_state < MAC80211_LINKED &&
416 !mac->act_scanning) {
417 if (rtlpriv->cfg->ops->check_switch_to_dmdp)
418 rtlpriv->cfg->ops->check_switch_to_dmdp(hw);
419 }
420
421 /*
422 *because we should back channel to
423 *current_network.chan in in scanning,
424 *So if set_chan == current_network.chan
425 *we should set it.
426 *because mac80211 tell us wrong bw40
427 *info for cisco1253 bw20, so we modify
428 *it here based on UPPER & LOWER
429 */
430 switch (channel_type) {
431 case NL80211_CHAN_HT20:
432 case NL80211_CHAN_NO_HT:
433 /* SC */
434 mac->cur_40_prime_sc =
435 PRIME_CHNL_OFFSET_DONT_CARE;
436 rtlphy->current_chan_bw = HT_CHANNEL_WIDTH_20;
437 mac->bw_40 = false;
438 break;
439 case NL80211_CHAN_HT40MINUS:
440 /* SC */
441 mac->cur_40_prime_sc = PRIME_CHNL_OFFSET_UPPER;
442 rtlphy->current_chan_bw =
443 HT_CHANNEL_WIDTH_20_40;
444 mac->bw_40 = true;
445
446 /*wide channel */
447 wide_chan -= 2;
448
449 break;
450 case NL80211_CHAN_HT40PLUS:
451 /* SC */
452 mac->cur_40_prime_sc = PRIME_CHNL_OFFSET_LOWER;
453 rtlphy->current_chan_bw =
454 HT_CHANNEL_WIDTH_20_40;
455 mac->bw_40 = true;
456
457 /*wide channel */
458 wide_chan += 2;
459
460 break;
461 default:
462 mac->bw_40 = false;
463 RT_TRACE(COMP_ERR, DBG_EMERG,
464 ("switch case not processed \n"));
465 break;
466 }
467
468 if (wide_chan <= 0)
469 wide_chan = 1;
470
471 /* in scanning, when before we offchannel we may send a ps=1
472 * null to AP, and then we may send a ps = 0 null to AP quickly,
473 * but first null have cause AP's put lots of packet to hw tx
474 * buffer, these packet must be tx before off channel so we must
475 * delay more time to let AP flush these packets before
476 * offchannel, or dis-association or delete BA will happen by AP
477 */
478 if (rtlpriv->mac80211.offchan_deley) {
479 rtlpriv->mac80211.offchan_deley = false;
480 mdelay(50);
481 }
482
483 rtlphy->current_channel = wide_chan;
484
485 rtlpriv->cfg->ops->switch_channel(hw);
486 rtlpriv->cfg->ops->set_channel_access(hw);
487 rtlpriv->cfg->ops->set_bw_mode(hw,
488 channel_type);
489 }
490
491 mutex_unlock(&rtlpriv->locks.conf_mutex);
492
493 return 0;
494}
495
496static void rtl_op_configure_filter(struct ieee80211_hw *hw,
497 unsigned int changed_flags,
498 unsigned int *new_flags, u64 multicast)
499{
500 struct rtl_priv *rtlpriv = rtl_priv(hw);
501 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
502
503 *new_flags &= RTL_SUPPORTED_FILTERS;
504 if (0 == changed_flags)
505 return;
506
507 /*TODO: we disable broadcase now, so enable here */
508 if (changed_flags & FIF_ALLMULTI) {
509 if (*new_flags & FIF_ALLMULTI) {
510 mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_AM] |
511 rtlpriv->cfg->maps[MAC_RCR_AB];
512 RT_TRACE(COMP_MAC80211, DBG_LOUD,
513 ("Enable receive multicast frame.\n"));
514 } else {
515 mac->rx_conf &= ~(rtlpriv->cfg->maps[MAC_RCR_AM] |
516 rtlpriv->cfg->maps[MAC_RCR_AB]);
517 RT_TRACE(COMP_MAC80211, DBG_LOUD,
518 ("Disable receive multicast frame.\n"));
519 }
520 }
521
522 if (changed_flags & FIF_FCSFAIL) {
523 if (*new_flags & FIF_FCSFAIL) {
524 mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_ACRC32];
525 RT_TRACE(COMP_MAC80211, DBG_LOUD,
526 ("Enable receive FCS error frame.\n"));
527 } else {
528 mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_ACRC32];
529 RT_TRACE(COMP_MAC80211, DBG_LOUD,
530 ("Disable receive FCS error frame.\n"));
531 }
532 }
533
534 /* if ssid not set to hw don't check bssid
535 * here just used for linked scanning, & linked
536 * and nolink check bssid is set in set network_type */
537 if ((changed_flags & FIF_BCN_PRBRESP_PROMISC) &&
538 (mac->link_state >= MAC80211_LINKED)) {
539 if (mac->opmode != NL80211_IFTYPE_AP &&
540 mac->opmode != NL80211_IFTYPE_MESH_POINT) {
541 if (*new_flags & FIF_BCN_PRBRESP_PROMISC) {
542 rtlpriv->cfg->ops->set_chk_bssid(hw, false);
543 } else {
544 rtlpriv->cfg->ops->set_chk_bssid(hw, true);
545 }
546 }
547 }
548
549 if (changed_flags & FIF_CONTROL) {
550 if (*new_flags & FIF_CONTROL) {
551 mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_ACF];
552
553 RT_TRACE(COMP_MAC80211, DBG_LOUD,
554 ("Enable receive control frame.\n"));
555 } else {
556 mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_ACF];
557 RT_TRACE(COMP_MAC80211, DBG_LOUD,
558 ("Disable receive control frame.\n"));
559 }
560 }
561
562 if (changed_flags & FIF_OTHER_BSS) {
563 if (*new_flags & FIF_OTHER_BSS) {
564 mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_AAP];
565 RT_TRACE(COMP_MAC80211, DBG_LOUD,
566 ("Enable receive other BSS's frame.\n"));
567 } else {
568 mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_AAP];
569 RT_TRACE(COMP_MAC80211, DBG_LOUD,
570 ("Disable receive other BSS's frame.\n"));
571 }
572 }
573}
574static int rtl_op_sta_add(struct ieee80211_hw *hw,
575 struct ieee80211_vif *vif,
576 struct ieee80211_sta *sta)
577{
578 struct rtl_priv *rtlpriv = rtl_priv(hw);
579 struct rtl_hal *rtlhal= rtl_hal(rtl_priv(hw));
580 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
581 struct rtl_sta_info *sta_entry;
582
583 if (sta) {
584 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
585 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
586 list_add_tail(&sta_entry->list, &rtlpriv->entry_list);
587 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
588 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
589 sta_entry->wireless_mode = WIRELESS_MODE_G;
590 if (sta->supp_rates[0] <= 0xf)
591 sta_entry->wireless_mode = WIRELESS_MODE_B;
592 if (sta->ht_cap.ht_supported == true)
593 sta_entry->wireless_mode = WIRELESS_MODE_N_24G;
594
595 if (vif->type == NL80211_IFTYPE_ADHOC)
596 sta_entry->wireless_mode = WIRELESS_MODE_G;
597 } else if (rtlhal->current_bandtype == BAND_ON_5G) {
598 sta_entry->wireless_mode = WIRELESS_MODE_A;
599 if (sta->ht_cap.ht_supported == true)
600 sta_entry->wireless_mode = WIRELESS_MODE_N_24G;
601
602 if (vif->type == NL80211_IFTYPE_ADHOC)
603 sta_entry->wireless_mode = WIRELESS_MODE_A;
604 }
605 /*disable cck rate for p2p*/
606 if (mac->p2p)
607 sta->supp_rates[0] &= 0xfffffff0;
608
609 memcpy(sta_entry->mac_addr, sta->addr, ETH_ALEN);
610 RT_TRACE(COMP_MAC80211, DBG_DMESG,
611 ("Add sta addr is %pM\n",sta->addr));
612 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 0);
613 }
614
615 return 0;
616}
617
618static int rtl_op_sta_remove(struct ieee80211_hw *hw,
619 struct ieee80211_vif *vif,
620 struct ieee80211_sta *sta)
621{
622 struct rtl_priv *rtlpriv = rtl_priv(hw);
623 struct rtl_sta_info *sta_entry;
624 if (sta) {
625 RT_TRACE(COMP_MAC80211, DBG_DMESG,
626 ("Remove sta addr is %pM\n",sta->addr));
627 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
628 sta_entry->wireless_mode = 0;
629 sta_entry->ratr_index = 0;
630 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
631 list_del(&sta_entry->list);
632 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
633 }
634 return 0;
635}
636static int _rtl_get_hal_qnum(u16 queue)
637{
638 int qnum;
639
640 switch (queue) {
641 case 0:
642 qnum = AC3_VO;
643 break;
644 case 1:
645 qnum = AC2_VI;
646 break;
647 case 2:
648 qnum = AC0_BE;
649 break;
650 case 3:
651 qnum = AC1_BK;
652 break;
653 default:
654 qnum = AC0_BE;
655 break;
656 }
657 return qnum;
658}
659
660/*
661 *for mac80211 VO=0, VI=1, BE=2, BK=3
662 *for rtl819x BE=0, BK=1, VI=2, VO=3
663 */
664#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
665static int rtl_op_conf_tx(struct ieee80211_hw *hw,
666 struct ieee80211_vif *vif, u16 queue,
667 const struct ieee80211_tx_queue_params *param)
668#else
669static int rtl_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
670 const struct ieee80211_tx_queue_params *param)
671#endif
672{
673 struct rtl_priv *rtlpriv = rtl_priv(hw);
674 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
675 int aci;
676
677 if (queue >= AC_MAX) {
678 RT_TRACE(COMP_ERR, DBG_WARNING,
679 ("queue number %d is incorrect!\n", queue));
680 return -EINVAL;
681 }
682
683 aci = _rtl_get_hal_qnum(queue);
684 mac->ac[aci].aifs = param->aifs;
685 mac->ac[aci].cw_min = param->cw_min;
686 mac->ac[aci].cw_max = param->cw_max;
687 mac->ac[aci].tx_op = param->txop;
688 memcpy(&mac->edca_param[aci], param, sizeof(*param));
689 rtlpriv->cfg->ops->set_qos(hw, aci);
690 return 0;
691}
692
693static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
694 struct ieee80211_vif *vif,
695 struct ieee80211_bss_conf *bss_conf,
696 u32 changed)
697{
698 struct rtl_priv *rtlpriv = rtl_priv(hw);
699 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
700 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
701 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
702
703 mutex_lock(&rtlpriv->locks.conf_mutex);
704 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
705 (vif->type == NL80211_IFTYPE_AP) ||
706 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
707 if ((changed & BSS_CHANGED_BEACON) ||
708 (changed & BSS_CHANGED_BEACON_ENABLED &&
709 bss_conf->enable_beacon)) {
710 if (mac->beacon_enabled == 0) {
711 RT_TRACE(COMP_MAC80211, DBG_DMESG,
712 ("BSS_CHANGED_BEACON_ENABLED \n"));
713
714 /*start hw beacon interrupt. */
715 /*rtlpriv->cfg->ops->set_bcn_reg(hw); */
716 mac->beacon_enabled = 1;
717 rtlpriv->cfg->ops->update_interrupt_mask(hw,
718 rtlpriv->cfg->maps
719 [RTL_IBSS_INT_MASKS], 0);
720
721 if (rtlpriv->cfg->ops->linked_set_reg)
722 rtlpriv->cfg->ops->linked_set_reg(hw);
723 }
724 }
725 if ((changed & BSS_CHANGED_BEACON_ENABLED &&
726 !bss_conf->enable_beacon)){
727 if (mac->beacon_enabled == 1) {
728 RT_TRACE(COMP_MAC80211, DBG_DMESG,
729 ("ADHOC DISABLE BEACON\n"));
730
731 mac->beacon_enabled = 0;
732 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
733 rtlpriv->cfg->maps
734 [RTL_IBSS_INT_MASKS]);
735 }
736 }
737 if (changed & BSS_CHANGED_BEACON_INT) {
738 RT_TRACE(COMP_BEACON, DBG_TRACE,
739 ("BSS_CHANGED_BEACON_INT\n"));
740 mac->beacon_interval = bss_conf->beacon_int;
741 rtlpriv->cfg->ops->set_bcn_intv(hw);
742 }
743 }
744
745 /*TODO: reference to enum ieee80211_bss_change */
746 if (changed & BSS_CHANGED_ASSOC) {
747 if (bss_conf->assoc) {
748 struct ieee80211_sta *sta = NULL;
749 /* we should reset all sec info & cam
750 * before set cam after linked, we should not
751 * reset in disassoc, that will cause tkip->wep
752 * fail because some flag will be wrong */
753 /* reset sec info */
754 rtl_cam_reset_sec_info(hw);
755 /* reset cam to fix wep fail issue
756 * when change from wpa to wep */
757 rtl_cam_reset_all_entry(hw);
758
759 mac->link_state = MAC80211_LINKED;
760 mac->cnt_after_linked = 0;
761 mac->assoc_id = bss_conf->aid;
762 memcpy(mac->bssid, bss_conf->bssid, 6);
763
764 if (rtlpriv->cfg->ops->linked_set_reg)
765 rtlpriv->cfg->ops->linked_set_reg(hw);
766
767 rcu_read_lock();
768 sta = ieee80211_find_sta(vif, (u8*)bss_conf->bssid);
769
770 if (vif->type == NL80211_IFTYPE_STATION && sta)
771 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 0);
772 RT_TRACE(COMP_EASY_CONCURRENT, DBG_LOUD,
773 ("send PS STATIC frame \n"));
774 if (rtlpriv->dm.supp_phymode_switch) {
775 if (sta->ht_cap.ht_supported)
776 rtl_send_smps_action(hw, sta,
777 IEEE80211_SMPS_STATIC);
778 }
779 rcu_read_unlock();
780
781 RT_TRACE(COMP_MAC80211, DBG_DMESG,
782 ("BSS_CHANGED_ASSOC\n"));
783 } else {
784 if (mac->link_state == MAC80211_LINKED)
785 rtl_lps_leave(hw);
786 if (ppsc->p2p_ps_info.p2p_ps_mode> P2P_PS_NONE)
787 rtl_p2p_ps_cmd(hw, P2P_PS_DISABLE);
788 mac->link_state = MAC80211_NOLINK;
789 memset(mac->bssid, 0, 6);
790 mac->vendor = PEER_UNKNOWN;
791
792 if (rtlpriv->dm.supp_phymode_switch) {
793 if (rtlpriv->cfg->ops->check_switch_to_dmdp)
794 rtlpriv->cfg->ops->check_switch_to_dmdp(hw);
795 }
796 RT_TRACE(COMP_MAC80211, DBG_DMESG,
797 ("BSS_CHANGED_UN_ASSOC\n"));
798 }
799 }
800
801 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
802 RT_TRACE(COMP_MAC80211, DBG_TRACE,
803 ("BSS_CHANGED_ERP_CTS_PROT\n"));
804 mac->use_cts_protect = bss_conf->use_cts_prot;
805 }
806
807 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
808 RT_TRACE(COMP_MAC80211, DBG_LOUD,
809 ("BSS_CHANGED_ERP_PREAMBLE use short preamble:%x \n",
810 bss_conf->use_short_preamble));
811
812 mac->short_preamble = bss_conf->use_short_preamble;
813 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACK_PREAMBLE,
814 (u8 *) (&mac->short_preamble));
815 }
816
817 if (changed & BSS_CHANGED_ERP_SLOT) {
818 RT_TRACE(COMP_MAC80211, DBG_TRACE,
819 ("BSS_CHANGED_ERP_SLOT\n"));
820
821 if (bss_conf->use_short_slot)
822 mac->slot_time = RTL_SLOT_TIME_9;
823 else
824 mac->slot_time = RTL_SLOT_TIME_20;
825
826 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
827 (u8 *) (&mac->slot_time));
828 }
829
830 if (changed & BSS_CHANGED_HT) {
831 struct ieee80211_sta *sta = NULL;
832
833 RT_TRACE(COMP_MAC80211, DBG_TRACE,
834 ("BSS_CHANGED_HT\n"));
835
836 rcu_read_lock();
837 sta = ieee80211_find_sta(vif, (u8*)bss_conf->bssid);
838 if (sta) {
839 if (sta->ht_cap.ampdu_density >
840 mac->current_ampdu_density)
841 mac->current_ampdu_density =
842 sta->ht_cap.ampdu_density;
843 if (sta->ht_cap.ampdu_factor <
844 mac->current_ampdu_factor)
845 mac->current_ampdu_factor =
846 sta->ht_cap.ampdu_factor;
847 }
848 rcu_read_unlock();
849
850 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SHORTGI_DENSITY,
851 (u8 *) (&mac->max_mss_density));
852 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AMPDU_FACTOR,
853 &mac->current_ampdu_factor);
854 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AMPDU_MIN_SPACE,
855 &mac->current_ampdu_density);
856 }
857
858 if (changed & BSS_CHANGED_BSSID) {
859 u32 basic_rates;
860 struct ieee80211_sta *sta = NULL;
861
862 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BSSID,
863 (u8 *) bss_conf->bssid);
864
865 RT_TRACE(COMP_MAC80211, DBG_DMESG,
866 ("bssid: %pM\n", bss_conf->bssid));
867
868 mac->vendor = PEER_UNKNOWN;
869 memcpy(mac->bssid, bss_conf->bssid, 6);
870 rtlpriv->cfg->ops->set_network_type(hw, vif->type);
871
872 rcu_read_lock();
873 sta = ieee80211_find_sta(vif, (u8*)bss_conf->bssid);
874 if (!sta) {
875 rcu_read_unlock();
876 goto out;
877 }
878
879 if (rtlhal->current_bandtype == BAND_ON_5G) {
880 mac->mode = WIRELESS_MODE_A;
881 } else {
882 if (sta->supp_rates[0] <= 0xf)
883 mac->mode = WIRELESS_MODE_B;
884 else
885 mac->mode = WIRELESS_MODE_G;
886 }
887
888 if (sta->ht_cap.ht_supported) {
889 if (rtlhal->current_bandtype == BAND_ON_2_4G)
890 mac->mode = WIRELESS_MODE_N_24G;
891 else
892 mac->mode = WIRELESS_MODE_N_5G;
893 }
894
895 /* just station need it, because ibss & ap mode will
896 * set in sta_add, and will be NULL here */
897 if (vif->type == NL80211_IFTYPE_STATION) {
898 struct rtl_sta_info *sta_entry;
899 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
900 sta_entry->wireless_mode = mac->mode;
901 }
902
903 if (sta->ht_cap.ht_supported) {
904 mac->ht_enable = true;
905
906 /*
907 * for cisco 1252 bw20 it's wrong
908 * if (ht_cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) {
909 * mac->bw_40 = true;
910 * }
911 * */
912 }
913
914 if (changed & BSS_CHANGED_BASIC_RATES) {
915 /* for 5G must << RATE_6M_INDEX=4,
916 * because 5G have no cck rate*/
917 if (rtlhal->current_bandtype == BAND_ON_5G)
918 basic_rates = sta->supp_rates[1] << 4;
919 else
920 basic_rates = sta->supp_rates[0];
921
922 mac->basic_rates = basic_rates;
923 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
924 (u8 *) (&basic_rates));
925 }
926 rcu_read_unlock();
927 }
928
929 /*
930 * For FW LPS and Keep Alive:
931 * To tell firmware we have connected
932 * to an AP. For 92SE/CE power save v2.
933 */
934 if (changed & BSS_CHANGED_ASSOC) {
935 if (bss_conf->assoc) {
936 u8 keep_alive = 10;
937 u8 mstatus = RT_MEDIA_CONNECT;
938 rtlpriv->cfg->ops->set_hw_reg(hw,
939 HW_VAR_KEEP_ALIVE,
940 (u8 *) (&keep_alive));
941
942 rtlpriv->cfg->ops->set_hw_reg(hw,
943 HW_VAR_H2C_FW_JOINBSSRPT,
944 (u8 *) (&mstatus));
945 ppsc->report_linked = true;
946
947 } else {
948
949 u8 mstatus = RT_MEDIA_DISCONNECT;
950 rtlpriv->cfg->ops->set_hw_reg(hw,
951 HW_VAR_H2C_FW_JOINBSSRPT,
952 (u8 *) (&mstatus));
953 ppsc->report_linked = false;
954
955 }
956
957 if (rtlpriv->cfg->ops->get_btc_status()){
958 rtlpriv->btcoexist.btc_ops->btc_mediastatus_notify(
959 rtlpriv, ppsc->report_linked);
960 }
961 }
962
963out:
964 mutex_unlock(&rtlpriv->locks.conf_mutex);
965}
966
967#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
968static u64 rtl_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
969#else
970static u64 rtl_op_get_tsf(struct ieee80211_hw *hw)
971#endif
972{
973 struct rtl_priv *rtlpriv = rtl_priv(hw);
974 u64 tsf;
975
976 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_CORRECT_TSF, (u8 *) (&tsf));
977 return tsf;
978}
979
980#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
981static void rtl_op_set_tsf(struct ieee80211_hw *hw,
982 struct ieee80211_vif *vif, u64 tsf)
983#else
984static void rtl_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
985#endif
986{
987 struct rtl_priv *rtlpriv = rtl_priv(hw);
988 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
989 u8 bibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ? 1 : 0;
990
991 mac->tsf = tsf;
992 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CORRECT_TSF, (u8 *) (&bibss));
993}
994
995#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
996static void rtl_op_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
997#else
998static void rtl_op_reset_tsf(struct ieee80211_hw *hw)
999#endif
1000{
1001 struct rtl_priv *rtlpriv = rtl_priv(hw);
1002 u8 tmp = 0;
1003
1004 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DUAL_TSF_RST, (u8 *) (&tmp));
1005}
1006
1007static void rtl_op_sta_notify(struct ieee80211_hw *hw,
1008 struct ieee80211_vif *vif,
1009 enum sta_notify_cmd cmd,
1010 struct ieee80211_sta *sta)
1011{
1012 switch (cmd) {
1013 case STA_NOTIFY_SLEEP:
1014 break;
1015 case STA_NOTIFY_AWAKE:
1016 break;
1017 default:
1018 break;
1019 }
1020}
1021
1022static int rtl_op_ampdu_action(struct ieee80211_hw *hw,
1023 struct ieee80211_vif *vif,
1024 enum ieee80211_ampdu_mlme_action action,
1025 struct ieee80211_sta *sta, u16 tid, u16 * ssn
1026/*<delete in kernel start>*/
1027#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39))
1028/*<delete in kernel end>*/
1029 ,u8 buf_size
1030/*<delete in kernel start>*/
1031#endif
1032/*<delete in kernel end>*/
1033 )
1034{
1035 struct rtl_priv *rtlpriv = rtl_priv(hw);
1036
1037 switch (action) {
1038 case IEEE80211_AMPDU_TX_START:
1039 RT_TRACE(COMP_MAC80211, DBG_TRACE,
1040 ("IEEE80211_AMPDU_TX_START: TID:%d\n", tid));
1041 return rtl_tx_agg_start(hw, vif, sta, tid, ssn);
1042 break;
1043#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
1044 case IEEE80211_AMPDU_TX_STOP_CONT:
1045 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1046 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1047#else
1048 case IEEE80211_AMPDU_TX_STOP:
1049#endif
1050 RT_TRACE(COMP_MAC80211, DBG_TRACE,
1051 ("IEEE80211_AMPDU_TX_STOP: TID:%d\n", tid));
1052 return rtl_tx_agg_stop(hw, vif, sta, tid);
1053 break;
1054 case IEEE80211_AMPDU_TX_OPERATIONAL:
1055 RT_TRACE(COMP_MAC80211, DBG_TRACE,
1056 ("IEEE80211_AMPDU_TX_OPERATIONAL:TID:%d\n", tid));
1057 rtl_tx_agg_oper(hw, sta, tid);
1058 break;
1059 case IEEE80211_AMPDU_RX_START:
1060 RT_TRACE(COMP_MAC80211, DBG_TRACE,
1061 ("IEEE80211_AMPDU_RX_START:TID:%d\n", tid));
1062 return rtl_rx_agg_start(hw, sta, tid);
1063 break;
1064 case IEEE80211_AMPDU_RX_STOP:
1065 RT_TRACE(COMP_MAC80211, DBG_TRACE,
1066 ("IEEE80211_AMPDU_RX_STOP:TID:%d\n", tid));
1067 return rtl_rx_agg_stop(hw, sta, tid);
1068 break;
1069 default:
1070 RT_TRACE(COMP_ERR, DBG_EMERG,
1071 ("IEEE80211_AMPDU_ERR!!!!:\n"));
1072 return -EOPNOTSUPP;
1073 }
1074 return 0;
1075}
1076
1077static void rtl_op_sw_scan_start(struct ieee80211_hw *hw)
1078{
1079 struct rtl_priv *rtlpriv = rtl_priv(hw);
1080 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1081
1082 RT_TRACE(COMP_MAC80211, DBG_LOUD, ("\n"));
1083 mac->act_scanning = true;
1084 /*rtlpriv->btcops->btc_scan_notify(rtlpriv, 0); */
1085 if (rtlpriv->link_info.b_higher_busytraffic) {
1086 mac->skip_scan = true;
1087 return;
1088 }
1089
1090 if (rtlpriv->dm.supp_phymode_switch) {
1091 if (rtlpriv->cfg->ops->check_switch_to_dmdp)
1092 rtlpriv->cfg->ops->check_switch_to_dmdp(hw);
1093 }
1094
1095 if (mac->link_state == MAC80211_LINKED) {
1096 rtl_lps_leave(hw);
1097 mac->link_state = MAC80211_LINKED_SCANNING;
1098 } else {
1099 rtl_ips_nic_on(hw);
1100 }
1101
1102 /* Dul mac */
1103 rtlpriv->rtlhal.b_load_imrandiqk_setting_for2g = false;
1104
1105 rtlpriv->cfg->ops->led_control(hw, LED_CTL_SITE_SURVEY);
1106
1107 rtlpriv->cfg->ops->scan_operation_backup(hw, SCAN_OPT_BACKUP_BAND0);
1108
1109}
1110
1111static void rtl_op_sw_scan_complete(struct ieee80211_hw *hw)
1112{
1113 struct rtl_priv *rtlpriv = rtl_priv(hw);
1114 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1115
1116 RT_TRACE(COMP_MAC80211, DBG_LOUD, ("\n"));
1117 mac->act_scanning = false;
1118 mac->skip_scan = false;
1119 if (rtlpriv->link_info.b_higher_busytraffic) {
1120 return;
1121 }
1122
1123 /* p2p will use 1/6/11 to scan */
1124 if (mac->n_channels == 3)
1125 mac->p2p_in_use = true;
1126 else
1127 mac->p2p_in_use = false;
1128 mac->n_channels = 0;
1129 /* Dul mac */
1130 rtlpriv->rtlhal.b_load_imrandiqk_setting_for2g = false;
1131
1132 if (mac->link_state == MAC80211_LINKED_SCANNING) {
1133 mac->link_state = MAC80211_LINKED;
1134 if (mac->opmode == NL80211_IFTYPE_STATION) {
1135 /* fix fwlps issue */
1136 rtlpriv->cfg->ops->set_network_type(hw, mac->opmode);
1137 }
1138 }
1139
1140 rtlpriv->cfg->ops->scan_operation_backup(hw, SCAN_OPT_RESTORE);
1141 /* rtlpriv->btcops->btc_scan_notify(rtlpriv, 1); */
1142}
1143
1144static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
1145 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
1146 struct ieee80211_key_conf *key)
1147{
1148 struct rtl_priv *rtlpriv = rtl_priv(hw);
1149 u8 key_type = NO_ENCRYPTION;
1150 u8 key_idx;
1151 bool group_key = false;
1152 bool wep_only = false;
1153 int err = 0;
1154 u8 mac_addr[ETH_ALEN];
1155 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1156 u8 zero_addr[ETH_ALEN] = { 0 };
1157
1158 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1159 RT_TRACE(COMP_ERR, DBG_WARNING,
1160 ("not open hw encryption\n"));
1161 return -ENOSPC; /*User disabled HW-crypto */
1162 }
1163 /* To support IBSS, use sw-crypto for GTK */
1164 if(((vif->type == NL80211_IFTYPE_ADHOC) ||
1165 (vif->type == NL80211_IFTYPE_MESH_POINT)) &&
1166 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
1167 return -ENOSPC;
1168 RT_TRACE(COMP_SEC, DBG_DMESG,
1169 ("%s hardware based encryption for keyidx: %d, mac: %pM\n",
1170 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
1171 sta ? sta->addr : bcast_addr));
1172 rtlpriv->sec.being_setkey = true;
1173 rtl_ips_nic_on(hw);
1174 mutex_lock(&rtlpriv->locks.conf_mutex);
1175 /* <1> get encryption alg */
1176
1177/*<delete in kernel start>*/
1178#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
1179/*<delete in kernel end>*/
1180 switch (key->cipher) {
1181 case WLAN_CIPHER_SUITE_WEP40:
1182 key_type = WEP40_ENCRYPTION;
1183 RT_TRACE(COMP_SEC, DBG_DMESG, ("alg:WEP40\n"));
1184 break;
1185 case WLAN_CIPHER_SUITE_WEP104:
1186 RT_TRACE(COMP_SEC, DBG_DMESG, ("alg:WEP104\n"));
1187 key_type = WEP104_ENCRYPTION;
1188 break;
1189 case WLAN_CIPHER_SUITE_TKIP:
1190 key_type = TKIP_ENCRYPTION;
1191 RT_TRACE(COMP_SEC, DBG_DMESG, ("alg:TKIP\n"));
1192 break;
1193 case WLAN_CIPHER_SUITE_CCMP:
1194 key_type = AESCCMP_ENCRYPTION;
1195 RT_TRACE(COMP_SEC, DBG_DMESG, ("alg:CCMP\n"));
1196 break;
1197 case WLAN_CIPHER_SUITE_AES_CMAC:
1198 /* HW don't support CMAC encryption,
1199 * use software CMAC encryption */
1200 key_type = AESCMAC_ENCRYPTION;
1201 RT_TRACE(COMP_SEC, DBG_DMESG, ("alg:CMAC\n"));
1202 RT_TRACE(COMP_SEC, DBG_DMESG,
1203 ("HW don't support CMAC encrypiton, "
1204 "use software CMAC encrypiton\n"));
1205 err = -EOPNOTSUPP;
1206 goto out_unlock;
1207 default:
1208 RT_TRACE(COMP_ERR, DBG_EMERG,
1209 ("alg_err:%x!!!!:\n", key->cipher));
1210 goto out_unlock;
1211 }
1212/*<delete in kernel start>*/
1213#else
1214 switch (key->alg) {
1215 case ALG_WEP:
1216 if (key->keylen == WLAN_KEY_LEN_WEP40) {
1217 key_type = WEP40_ENCRYPTION;
1218 RT_TRACE(COMP_SEC, DBG_DMESG, ("alg:WEP40\n"));
1219 } else {
1220 RT_TRACE(COMP_SEC, DBG_DMESG,
1221 ("alg:WEP104\n"));
1222 key_type = WEP104_ENCRYPTION;
1223 }
1224 break;
1225 case ALG_TKIP:
1226 key_type = TKIP_ENCRYPTION;
1227 RT_TRACE(COMP_SEC, DBG_DMESG, ("alg:TKIP\n"));
1228 break;
1229 case ALG_CCMP:
1230 key_type = AESCCMP_ENCRYPTION;
1231 RT_TRACE(COMP_SEC, DBG_DMESG, ("alg:CCMP\n"));
1232 break;
1233 case ALG_AES_CMAC:
1234 /*HW don't support CMAC encryption, use software CMAC encryption */
1235 key_type = AESCMAC_ENCRYPTION;
1236 RT_TRACE(COMP_SEC, DBG_DMESG, ("alg:CMAC\n"));
1237 RT_TRACE(COMP_SEC, DBG_DMESG,
1238 ("HW don't support CMAC encrypiton, "
1239 "use software CMAC encrypiton\n"));
1240 err = -EOPNOTSUPP;
1241 goto out_unlock;
1242 default:
1243 RT_TRACE(COMP_ERR, DBG_EMERG,
1244 ("alg_err:%x!!!!:\n", key->alg));
1245 goto out_unlock;
1246 }
1247#endif
1248/*<delete in kernel end>*/
1249 if(key_type == WEP40_ENCRYPTION ||
1250 key_type == WEP104_ENCRYPTION ||
1251 vif->type == NL80211_IFTYPE_ADHOC)
1252 rtlpriv->sec.use_defaultkey = true;
1253
1254 /* <2> get key_idx */
1255 key_idx = (u8) (key->keyidx);
1256 if (key_idx > 3)
1257 goto out_unlock;
1258 /* <3> if pairwise key enable_hw_sec */
1259 group_key = !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE);
1260
1261 /* wep always be group key, but there are two conditions:
1262 * 1) wep only: is just for wep enc, in this condition
1263 * rtlpriv->sec.pairwise_enc_algorithm == NO_ENCRYPTION
1264 * will be true & enable_hw_sec will be set when wep
1265 * ke setting.
1266 * 2) wep(group) + AES(pairwise): some AP like cisco
1267 * may use it, in this condition enable_hw_sec will not
1268 * be set when wep key setting */
1269 /* we must reset sec_info after lingked before set key,
1270 * or some flag will be wrong*/
1271 if (vif->type == NL80211_IFTYPE_AP ||
1272 vif->type == NL80211_IFTYPE_MESH_POINT) {
1273 if (!group_key || key_type == WEP40_ENCRYPTION ||
1274 key_type == WEP104_ENCRYPTION) {
1275 if (group_key) {
1276 wep_only = true;
1277 }
1278 rtlpriv->cfg->ops->enable_hw_sec(hw);
1279 }
1280 } else {
1281 if ((!group_key) || (vif->type == NL80211_IFTYPE_ADHOC) ||
1282 rtlpriv->sec.pairwise_enc_algorithm == NO_ENCRYPTION) {
1283 if (rtlpriv->sec.pairwise_enc_algorithm ==
1284 NO_ENCRYPTION &&
1285 (key_type == WEP40_ENCRYPTION ||
1286 key_type == WEP104_ENCRYPTION))
1287 wep_only = true;
1288 rtlpriv->sec.pairwise_enc_algorithm = key_type;
1289 RT_TRACE(COMP_SEC, DBG_DMESG,
1290 ("set enable_hw_sec, key_type:%x(OPEN:0 WEP40:"
1291 "1 TKIP:2 AES:4 WEP104:5)\n", key_type));
1292 rtlpriv->cfg->ops->enable_hw_sec(hw);
1293 }
1294 }
1295 /* <4> set key based on cmd */
1296 switch (cmd) {
1297 case SET_KEY:
1298 if (wep_only) {
1299 RT_TRACE(COMP_SEC, DBG_DMESG,
1300 ("set WEP(group/pairwise) key\n"));
1301 /* Pairwise key with an assigned MAC address. */
1302 rtlpriv->sec.pairwise_enc_algorithm = key_type;
1303 rtlpriv->sec.group_enc_algorithm = key_type;
1304 /*set local buf about wep key. */
1305 memcpy(rtlpriv->sec.key_buf[key_idx],
1306 key->key, key->keylen);
1307 rtlpriv->sec.key_len[key_idx] = key->keylen;
1308 memcpy(mac_addr, zero_addr, ETH_ALEN);
1309 } else if (group_key) { /* group key */
1310 RT_TRACE(COMP_SEC, DBG_DMESG,
1311 ("set group key\n"));
1312 /* group key */
1313 rtlpriv->sec.group_enc_algorithm = key_type;
1314 /*set local buf about group key. */
1315 memcpy(rtlpriv->sec.key_buf[key_idx],
1316 key->key, key->keylen);
1317 rtlpriv->sec.key_len[key_idx] = key->keylen;
1318 memcpy(mac_addr, bcast_addr, ETH_ALEN);
1319 } else { /* pairwise key */
1320 RT_TRACE(COMP_SEC, DBG_DMESG,
1321 ("set pairwise key\n"));
1322 if (!sta) {
1323 RT_ASSERT(false, ("pairwise key withnot"
1324 "mac_addr\n"));
1325
1326 err = -EOPNOTSUPP;
1327 goto out_unlock;
1328 }
1329 /* Pairwise key with an assigned MAC address. */
1330 rtlpriv->sec.pairwise_enc_algorithm = key_type;
1331 /*set local buf about pairwise key. */
1332 memcpy(rtlpriv->sec.key_buf[PAIRWISE_KEYIDX],
1333 key->key, key->keylen);
1334 rtlpriv->sec.key_len[PAIRWISE_KEYIDX] = key->keylen;
1335 rtlpriv->sec.pairwise_key =
1336 rtlpriv->sec.key_buf[PAIRWISE_KEYIDX];
1337 memcpy(mac_addr, sta->addr, ETH_ALEN);
1338 }
1339 rtlpriv->cfg->ops->set_key(hw, key_idx, mac_addr,
1340 group_key, key_type, wep_only,
1341 false);
1342 /* <5> tell mac80211 do something: */
1343 /*must use sw generate IV, or can not work !!!!. */
1344 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1345 key->hw_key_idx = key_idx;
1346 if (key_type == TKIP_ENCRYPTION)
1347 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1348 /*use software CCMP encryption for management frames (MFP) */
1349 if (key_type == AESCCMP_ENCRYPTION)
1350 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
1351 break;
1352 case DISABLE_KEY:
1353 RT_TRACE(COMP_SEC, DBG_DMESG,
1354 ("disable key delete one entry\n"));
1355 /*set local buf about wep key. */
1356 if (vif->type == NL80211_IFTYPE_AP ||
1357 vif->type == NL80211_IFTYPE_MESH_POINT) {
1358 if (sta)
1359 rtl_cam_del_entry(hw, sta->addr);
1360 }
1361 memset(rtlpriv->sec.key_buf[key_idx], 0, key->keylen);
1362 rtlpriv->sec.key_len[key_idx] = 0;
1363 memcpy(mac_addr, zero_addr, ETH_ALEN);
1364 /*
1365 *mac80211 will delete entrys one by one,
1366 *so don't use rtl_cam_reset_all_entry
1367 *or clear all entry here.
1368 */
1369 rtl_cam_delete_one_entry(hw, mac_addr, key_idx);
1370 break;
1371 default:
1372 RT_TRACE(COMP_ERR, DBG_EMERG,
1373 ("cmd_err:%x!!!!:\n", cmd));
1374 }
1375out_unlock:
1376 mutex_unlock(&rtlpriv->locks.conf_mutex);
1377 rtlpriv->sec.being_setkey = false;
1378 return err;
1379}
1380
1381static void rtl_op_rfkill_poll(struct ieee80211_hw *hw)
1382{
1383 struct rtl_priv *rtlpriv = rtl_priv(hw);
1384
1385 bool radio_state;
1386 bool blocked;
1387 u8 valid = 0;
1388
1389 if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
1390 return;
1391
1392 mutex_lock(&rtlpriv->locks.conf_mutex);
1393
1394 /*if Radio On return true here */
1395 radio_state = rtlpriv->cfg->ops->radio_onoff_checking(hw, &valid);
1396
1397 if (valid) {
1398 if (unlikely(radio_state != rtlpriv->rfkill.rfkill_state)) {
1399 rtlpriv->rfkill.rfkill_state = radio_state;
1400
1401 RT_TRACE(COMP_RF, DBG_DMESG,
1402 (KERN_INFO "wireless radio switch turned %s\n",
1403 radio_state ? "on" : "off"));
1404
1405 blocked = (rtlpriv->rfkill.rfkill_state == 1) ? 0 : 1;
1406 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1407 }
1408 }
1409
1410 mutex_unlock(&rtlpriv->locks.conf_mutex);
1411}
1412
1413/* this function is called by mac80211 to flush tx buffer
1414 * before switch channle or power save, or tx buffer packet
1415 * maybe send after offchannel or rf sleep, this may cause
1416 * dis-association by AP */
1417#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
1418static void rtl_op_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1419{
1420 struct rtl_priv *rtlpriv = rtl_priv(hw);
1421
1422 if (rtlpriv->intf_ops->flush)
1423 rtlpriv->intf_ops->flush(hw, queues, drop);
1424}
1425#else
1426static void rtl_op_flush(struct ieee80211_hw *hw, bool drop)
1427{
1428 struct rtl_priv *rtlpriv = rtl_priv(hw);
1429
1430 if (rtlpriv->intf_ops->flush)
1431 rtlpriv->intf_ops->flush(hw, drop);
1432}
1433#endif
1434
1435const struct ieee80211_ops rtl_ops = {
1436 .start = rtl_op_start,
1437 .stop = rtl_op_stop,
1438 .tx = rtl_op_tx,
1439 .add_interface = rtl_op_add_interface,
1440 .remove_interface = rtl_op_remove_interface,
1441/*<delete in kernel start>*/
1442#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
1443/*<delete in kernel end>*/
1444 .change_interface = rtl_op_change_interface,
1445/*<delete in kernel start>*/
1446#endif
1447/*<delete in kernel end>*/
1448 .config = rtl_op_config,
1449 .configure_filter = rtl_op_configure_filter,
1450 .set_key = rtl_op_set_key,
1451 .conf_tx = rtl_op_conf_tx,
1452 .bss_info_changed = rtl_op_bss_info_changed,
1453 .get_tsf = rtl_op_get_tsf,
1454 .set_tsf = rtl_op_set_tsf,
1455 .reset_tsf = rtl_op_reset_tsf,
1456 .sta_notify = rtl_op_sta_notify,
1457 .ampdu_action = rtl_op_ampdu_action,
1458 .sw_scan_start = rtl_op_sw_scan_start,
1459 .sw_scan_complete = rtl_op_sw_scan_complete,
1460 .rfkill_poll = rtl_op_rfkill_poll,
1461 .sta_add = rtl_op_sta_add,
1462 .sta_remove = rtl_op_sta_remove,
1463 .flush = rtl_op_flush,
1464};
diff --git a/drivers/staging/rtl8821ae/core.h b/drivers/staging/rtl8821ae/core.h
new file mode 100644
index 000000000000..4b247db2861d
--- /dev/null
+++ b/drivers/staging/rtl8821ae/core.h
@@ -0,0 +1,43 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * Tmis program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * Tmis program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * tmis program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * Tme full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_CORE_H__
31#define __RTL_CORE_H__
32
33#define RTL_SUPPORTED_FILTERS \
34 (FIF_PROMISC_IN_BSS | \
35 FIF_ALLMULTI | FIF_CONTROL | \
36 FIF_OTHER_BSS | \
37 FIF_FCSFAIL | \
38 FIF_BCN_PRBRESP_PROMISC)
39
40#define RTL_SUPPORTED_CTRL_FILTER 0xFF
41
42extern const struct ieee80211_ops rtl_ops;
43#endif
diff --git a/drivers/staging/rtl8821ae/debug.c b/drivers/staging/rtl8821ae/debug.c
new file mode 100644
index 000000000000..cb051223c684
--- /dev/null
+++ b/drivers/staging/rtl8821ae/debug.c
@@ -0,0 +1,988 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * Tmis program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * Tmis program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * tmis program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * Tme full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "cam.h"
32
33#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
34#define GET_INODE_DATA(__node) PDE_DATA(__node)
35#else
36#define GET_INODE_DATA(__node) PDE(__node)->data
37#endif
38
39
40void rtl_dbgp_flag_init(struct ieee80211_hw *hw)
41{
42 struct rtl_priv *rtlpriv = rtl_priv(hw);
43 u8 i;
44
45 rtlpriv->dbg.global_debuglevel = DBG_DMESG;
46
47 rtlpriv->dbg.global_debugcomponents =
48 COMP_ERR |
49 COMP_FW |
50 COMP_INIT |
51 COMP_RECV |
52 COMP_SEND |
53 COMP_MLME |
54 COMP_SCAN |
55 COMP_INTR |
56 COMP_LED |
57 COMP_SEC |
58 COMP_BEACON |
59 COMP_RATE |
60 COMP_RXDESC |
61 COMP_DIG |
62 COMP_TXAGC |
63 COMP_POWER |
64 COMP_POWER_TRACKING |
65 COMP_BB_POWERSAVING |
66 COMP_SWAS |
67 COMP_RF |
68 COMP_TURBO |
69 COMP_RATR |
70 COMP_CMD |
71 COMP_EASY_CONCURRENT |
72 COMP_EFUSE |
73 COMP_QOS | COMP_MAC80211 | COMP_REGD |
74 COMP_CHAN |
75 COMP_BT_COEXIST |
76 COMP_IQK |
77 0;
78
79 for (i = 0; i < DBGP_TYPE_MAX; i++)
80 rtlpriv->dbg.dbgp_type[i] = 0;
81
82 /*Init Debug flag enable condition */
83}
84
85struct proc_dir_entry *proc_topdir;
86static int rtl_proc_get_mac_0(struct seq_file *m, void *v)
87{
88 struct ieee80211_hw *hw = m->private;
89 struct rtl_priv *rtlpriv = rtl_priv(hw);
90 int i, n, page;
91 int max = 0xff;
92 page = 0x000;
93
94 for (n = 0; n <= max; ) {
95 seq_printf(m, "\n%8.8x ", n + page);
96 for (i = 0; i < 4 && n <= max; i++, n += 4)
97 seq_printf(m, "%8.8x ",
98 rtl_read_dword(rtlpriv, (page | n)));
99 }
100 seq_puts(m, "\n");
101 return 0;
102}
103
104static int dl_proc_open_mac_0(struct inode *inode, struct file *file)
105{
106 return single_open(file, rtl_proc_get_mac_0, GET_INODE_DATA(inode));
107}
108
109static const struct file_operations file_ops_mac_0 = {
110 .open = dl_proc_open_mac_0,
111 .read = seq_read,
112 .llseek = seq_lseek,
113 .release = seq_release,
114};
115
116static int rtl_proc_get_mac_1(struct seq_file *m, void *v)
117{
118 struct ieee80211_hw *hw = m->private;
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
120 int i, n, page;
121 int max = 0xff;
122 page = 0x100;
123
124 for (n = 0; n <= max; ) {
125 seq_printf(m, "\n%8.8x ", n + page);
126 for (i = 0; i < 4 && n <= max; i++, n += 4)
127 seq_printf(m, "%8.8x ",
128 rtl_read_dword(rtlpriv, (page | n)));
129 }
130 seq_puts(m, "\n");
131 return 0;
132}
133
134static int dl_proc_open_mac_1(struct inode *inode, struct file *file)
135{
136 return single_open(file, rtl_proc_get_mac_1, GET_INODE_DATA(inode));
137}
138
139static const struct file_operations file_ops_mac_1 = {
140 .open = dl_proc_open_mac_1,
141 .read = seq_read,
142 .llseek = seq_lseek,
143 .release = seq_release,
144};
145
146static int rtl_proc_get_mac_2(struct seq_file *m, void *v)
147{
148 struct ieee80211_hw *hw = m->private;
149 struct rtl_priv *rtlpriv = rtl_priv(hw);
150 int i, n, page;
151 int max = 0xff;
152 page = 0x200;
153
154 for (n = 0; n <= max; ) {
155 seq_printf(m, "\n%8.8x ", n + page);
156 for (i = 0; i < 4 && n <= max; i++, n += 4)
157 seq_printf(m, "%8.8x ",
158 rtl_read_dword(rtlpriv, (page | n)));
159 }
160 seq_puts(m, "\n");
161 return 0;
162}
163
164static int dl_proc_open_mac_2(struct inode *inode, struct file *file)
165{
166 return single_open(file, rtl_proc_get_mac_2, GET_INODE_DATA(inode));
167}
168
169static const struct file_operations file_ops_mac_2 = {
170 .open = dl_proc_open_mac_2,
171 .read = seq_read,
172 .llseek = seq_lseek,
173 .release = seq_release,
174};
175
176static int rtl_proc_get_mac_3(struct seq_file *m, void *v)
177{
178 struct ieee80211_hw *hw = m->private;
179 struct rtl_priv *rtlpriv = rtl_priv(hw);
180 int i, n, page;
181 int max = 0xff;
182 page = 0x300;
183
184 for (n = 0; n <= max; ) {
185 seq_printf(m, "\n%8.8x ", n + page);
186 for (i = 0; i < 4 && n <= max; i++, n += 4)
187 seq_printf(m, "%8.8x ",
188 rtl_read_dword(rtlpriv, (page | n)));
189 }
190 seq_puts(m, "\n");
191 return 0;
192}
193
194static int dl_proc_open_mac_3(struct inode *inode, struct file *file)
195{
196 return single_open(file, rtl_proc_get_mac_3, GET_INODE_DATA(inode));
197}
198
199static const struct file_operations file_ops_mac_3 = {
200 .open = dl_proc_open_mac_3,
201 .read = seq_read,
202 .llseek = seq_lseek,
203 .release = seq_release,
204};
205
206static int rtl_proc_get_mac_4(struct seq_file *m, void *v)
207{
208 struct ieee80211_hw *hw = m->private;
209 struct rtl_priv *rtlpriv = rtl_priv(hw);
210 int i, n, page;
211 int max = 0xff;
212 page = 0x400;
213
214 for (n = 0; n <= max; ) {
215 seq_printf(m, "\n%8.8x ", n + page);
216 for (i = 0; i < 4 && n <= max; i++, n += 4)
217 seq_printf(m, "%8.8x ",
218 rtl_read_dword(rtlpriv, (page | n)));
219 }
220 seq_puts(m, "\n");
221 return 0;
222}
223
224static int dl_proc_open_mac_4(struct inode *inode, struct file *file)
225{
226 return single_open(file, rtl_proc_get_mac_4, GET_INODE_DATA(inode));
227}
228
229static const struct file_operations file_ops_mac_4 = {
230 .open = dl_proc_open_mac_4,
231 .read = seq_read,
232 .llseek = seq_lseek,
233 .release = seq_release,
234};
235
236static int rtl_proc_get_mac_5(struct seq_file *m, void *v)
237{
238 struct ieee80211_hw *hw = m->private;
239 struct rtl_priv *rtlpriv = rtl_priv(hw);
240 int i, n, page;
241 int max = 0xff;
242 page = 0x500;
243
244 for (n = 0; n <= max; ) {
245 seq_printf(m, "\n%8.8x ", n + page);
246 for (i = 0; i < 4 && n <= max; i++, n += 4)
247 seq_printf(m, "%8.8x ",
248 rtl_read_dword(rtlpriv, (page | n)));
249 }
250 seq_puts(m, "\n");
251 return 0;
252}
253
254static int dl_proc_open_mac_5(struct inode *inode, struct file *file)
255{
256 return single_open(file, rtl_proc_get_mac_5, GET_INODE_DATA(inode));
257}
258
259static const struct file_operations file_ops_mac_5 = {
260 .open = dl_proc_open_mac_5,
261 .read = seq_read,
262 .llseek = seq_lseek,
263 .release = seq_release,
264};
265
266static int rtl_proc_get_mac_6(struct seq_file *m, void *v)
267{
268 struct ieee80211_hw *hw = m->private;
269 struct rtl_priv *rtlpriv = rtl_priv(hw);
270 int i, n, page;
271 int max = 0xff;
272 page = 0x600;
273
274 for (n = 0; n <= max; ) {
275 seq_printf(m, "\n%8.8x ", n + page);
276 for (i = 0; i < 4 && n <= max; i++, n += 4)
277 seq_printf(m, "%8.8x ",
278 rtl_read_dword(rtlpriv, (page | n)));
279 }
280 seq_puts(m, "\n");
281 return 0;
282}
283
284static int dl_proc_open_mac_6(struct inode *inode, struct file *file)
285{
286 return single_open(file, rtl_proc_get_mac_6, GET_INODE_DATA(inode));
287}
288
289static const struct file_operations file_ops_mac_6 = {
290 .open = dl_proc_open_mac_6,
291 .read = seq_read,
292 .llseek = seq_lseek,
293 .release = seq_release,
294};
295
296static int rtl_proc_get_mac_7(struct seq_file *m, void *v)
297{
298 struct ieee80211_hw *hw = m->private;
299 struct rtl_priv *rtlpriv = rtl_priv(hw);
300 int i, n, page;
301 int max = 0xff;
302 page = 0x700;
303
304 for (n = 0; n <= max; ) {
305 seq_printf(m, "\n%8.8x ", n + page);
306 for (i = 0; i < 4 && n <= max; i++, n += 4)
307 seq_printf(m, "%8.8x ",
308 rtl_read_dword(rtlpriv, (page | n)));
309 }
310 seq_puts(m, "\n");
311 return 0;
312}
313
314static int dl_proc_open_mac_7(struct inode *inode, struct file *file)
315{
316 return single_open(file, rtl_proc_get_mac_7, GET_INODE_DATA(inode));
317}
318
319static const struct file_operations file_ops_mac_7 = {
320 .open = dl_proc_open_mac_7,
321 .read = seq_read,
322 .llseek = seq_lseek,
323 .release = seq_release,
324};
325
326static int rtl_proc_get_bb_8(struct seq_file *m, void *v)
327{
328 struct ieee80211_hw *hw = m->private;
329 int i, n, page;
330 int max = 0xff;
331 page = 0x800;
332
333 for (n = 0; n <= max; ) {
334 seq_printf(m, "\n%8.8x ", n + page);
335 for (i = 0; i < 4 && n <= max; i++, n += 4)
336 seq_printf(m, "%8.8x ",
337 rtl_get_bbreg(hw, (page | n), 0xffffffff));
338 }
339 seq_puts(m, "\n");
340 return 0;
341}
342
343static int dl_proc_open_bb_8(struct inode *inode, struct file *file)
344{
345 return single_open(file, rtl_proc_get_bb_8, GET_INODE_DATA(inode));
346}
347
348static const struct file_operations file_ops_bb_8 = {
349 .open = dl_proc_open_bb_8,
350 .read = seq_read,
351 .llseek = seq_lseek,
352 .release = seq_release,
353};
354
355static int rtl_proc_get_bb_9(struct seq_file *m, void *v)
356{
357 struct ieee80211_hw *hw = m->private;
358 int i, n, page;
359 int max = 0xff;
360 page = 0x900;
361
362 for (n = 0; n <= max; ) {
363 seq_printf(m, "\n%8.8x ", n + page);
364 for (i = 0; i < 4 && n <= max; i++, n += 4)
365 seq_printf(m, "%8.8x ",
366 rtl_get_bbreg(hw, (page | n), 0xffffffff));
367 }
368 seq_puts(m, "\n");
369 return 0;
370}
371
372static int dl_proc_open_bb_9(struct inode *inode, struct file *file)
373{
374 return single_open(file, rtl_proc_get_bb_9, GET_INODE_DATA(inode));
375}
376
377static const struct file_operations file_ops_bb_9 = {
378 .open = dl_proc_open_bb_9,
379 .read = seq_read,
380 .llseek = seq_lseek,
381 .release = seq_release,
382};
383
384static int rtl_proc_get_bb_a(struct seq_file *m, void *v)
385{
386 struct ieee80211_hw *hw = m->private;
387 int i, n, page;
388 int max = 0xff;
389 page = 0xa00;
390
391 for (n = 0; n <= max; ) {
392 seq_printf(m, "\n%8.8x ", n + page);
393 for (i = 0; i < 4 && n <= max; i++, n += 4)
394 seq_printf(m, "%8.8x ",
395 rtl_get_bbreg(hw, (page | n), 0xffffffff));
396 }
397 seq_puts(m, "\n");
398 return 0;
399}
400
401static int dl_proc_open_bb_a(struct inode *inode, struct file *file)
402{
403 return single_open(file, rtl_proc_get_bb_a, GET_INODE_DATA(inode));
404}
405
406static const struct file_operations file_ops_bb_a = {
407 .open = dl_proc_open_bb_a,
408 .read = seq_read,
409 .llseek = seq_lseek,
410 .release = seq_release,
411};
412
413static int rtl_proc_get_bb_b(struct seq_file *m, void *v)
414{
415 struct ieee80211_hw *hw = m->private;
416 int i, n, page;
417 int max = 0xff;
418 page = 0xb00;
419
420 for (n = 0; n <= max; ) {
421 seq_printf(m, "\n%8.8x ", n + page);
422 for (i = 0; i < 4 && n <= max; i++, n += 4)
423 seq_printf(m, "%8.8x ",
424 rtl_get_bbreg(hw, (page | n), 0xffffffff));
425 }
426 seq_puts(m, "\n");
427 return 0;
428}
429
430static int dl_proc_open_bb_b(struct inode *inode, struct file *file)
431{
432 return single_open(file, rtl_proc_get_bb_b, GET_INODE_DATA(inode));
433}
434
435static const struct file_operations file_ops_bb_b = {
436 .open = dl_proc_open_bb_b,
437 .read = seq_read,
438 .llseek = seq_lseek,
439 .release = seq_release,
440};
441
442static int rtl_proc_get_bb_c(struct seq_file *m, void *v)
443{
444 struct ieee80211_hw *hw = m->private;
445 int i, n, page;
446 int max = 0xff;
447 page = 0xc00;
448
449 for (n = 0; n <= max; ) {
450 seq_printf(m, "\n%8.8x ", n + page);
451 for (i = 0; i < 4 && n <= max; i++, n += 4)
452 seq_printf(m, "%8.8x ",
453 rtl_get_bbreg(hw, (page | n), 0xffffffff));
454 }
455 seq_puts(m, "\n");
456 return 0;
457}
458
459static int dl_proc_open_bb_c(struct inode *inode, struct file *file)
460{
461 return single_open(file, rtl_proc_get_bb_c, GET_INODE_DATA(inode));
462}
463
464static const struct file_operations file_ops_bb_c = {
465 .open = dl_proc_open_bb_c,
466 .read = seq_read,
467 .llseek = seq_lseek,
468 .release = seq_release,
469};
470
471static int rtl_proc_get_bb_d(struct seq_file *m, void *v)
472{
473 struct ieee80211_hw *hw = m->private;
474 int i, n, page;
475 int max = 0xff;
476 page = 0xd00;
477
478 for (n = 0; n <= max; ) {
479 seq_printf(m, "\n%8.8x ", n + page);
480 for (i = 0; i < 4 && n <= max; i++, n += 4)
481 seq_printf(m, "%8.8x ",
482 rtl_get_bbreg(hw, (page | n), 0xffffffff));
483 }
484 seq_puts(m, "\n");
485 return 0;
486}
487
488static int dl_proc_open_bb_d(struct inode *inode, struct file *file)
489{
490 return single_open(file, rtl_proc_get_bb_d, GET_INODE_DATA(inode));
491}
492
493static const struct file_operations file_ops_bb_d = {
494 .open = dl_proc_open_bb_d,
495 .read = seq_read,
496 .llseek = seq_lseek,
497 .release = seq_release,
498};
499
500static int rtl_proc_get_bb_e(struct seq_file *m, void *v)
501{
502 struct ieee80211_hw *hw = m->private;
503 int i, n, page;
504 int max = 0xff;
505 page = 0xe00;
506
507 for (n = 0; n <= max; ) {
508 seq_printf(m, "\n%8.8x ", n + page);
509 for (i = 0; i < 4 && n <= max; i++, n += 4)
510 seq_printf(m, "%8.8x ",
511 rtl_get_bbreg(hw, (page | n), 0xffffffff));
512 }
513 seq_puts(m, "\n");
514 return 0;
515}
516
517static int dl_proc_open_bb_e(struct inode *inode, struct file *file)
518{
519 return single_open(file, rtl_proc_get_bb_e, GET_INODE_DATA(inode));
520}
521
522static const struct file_operations file_ops_bb_e = {
523 .open = dl_proc_open_bb_e,
524 .read = seq_read,
525 .llseek = seq_lseek,
526 .release = seq_release,
527};
528
529static int rtl_proc_get_bb_f(struct seq_file *m, void *v)
530{
531 struct ieee80211_hw *hw = m->private;
532 int i, n, page;
533 int max = 0xff;
534 page = 0xf00;
535
536 for (n = 0; n <= max; ) {
537 seq_printf(m, "\n%8.8x ", n + page);
538 for (i = 0; i < 4 && n <= max; i++, n += 4)
539 seq_printf(m, "%8.8x ",
540 rtl_get_bbreg(hw, (page | n), 0xffffffff));
541 }
542 seq_puts(m, "\n");
543 return 0;
544}
545
546static int dl_proc_open_bb_f(struct inode *inode, struct file *file)
547{
548 return single_open(file, rtl_proc_get_bb_f, GET_INODE_DATA(inode));
549}
550
551static const struct file_operations file_ops_bb_f = {
552 .open = dl_proc_open_bb_f,
553 .read = seq_read,
554 .llseek = seq_lseek,
555 .release = seq_release,
556};
557
558static int rtl_proc_get_reg_rf_a(struct seq_file *m, void *v)
559{
560 struct ieee80211_hw *hw = m->private;
561 int i, n;
562 int max = 0x40;
563
564 for (n = 0; n <= max; ) {
565 seq_printf(m, "\n%8.8x ", n);
566 for (i = 0; i < 4 && n <= max; n += 1, i++)
567 seq_printf(m, "%8.8x ",
568 rtl_get_rfreg(hw, RF90_PATH_A, n, 0xffffffff));
569 }
570 seq_puts(m, "\n");
571 return 0;
572}
573
574static int dl_proc_open_rf_a(struct inode *inode, struct file *file)
575{
576 return single_open(file, rtl_proc_get_reg_rf_a, GET_INODE_DATA(inode));
577}
578
579static const struct file_operations file_ops_rf_a = {
580 .open = dl_proc_open_rf_a,
581 .read = seq_read,
582 .llseek = seq_lseek,
583 .release = seq_release,
584};
585
586static int rtl_proc_get_reg_rf_b(struct seq_file *m, void *v)
587{
588 struct ieee80211_hw *hw = m->private;
589 int i, n;
590 int max = 0x40;
591
592 for (n = 0; n <= max; ) {
593 seq_printf(m, "\n%8.8x ", n);
594 for (i = 0; i < 4 && n <= max; n += 1, i++)
595 seq_printf(m, "%8.8x ",
596 rtl_get_rfreg(hw, RF90_PATH_B, n,
597 0xffffffff));
598 }
599 seq_puts(m, "\n");
600 return 0;
601}
602
603static int dl_proc_open_rf_b(struct inode *inode, struct file *file)
604{
605 return single_open(file, rtl_proc_get_reg_rf_b, GET_INODE_DATA(inode));
606}
607
608static const struct file_operations file_ops_rf_b = {
609 .open = dl_proc_open_rf_b,
610 .read = seq_read,
611 .llseek = seq_lseek,
612 .release = seq_release,
613};
614
615static int rtl_proc_get_cam_register_1(struct seq_file *m, void *v)
616{
617 struct ieee80211_hw *hw = m->private;
618 struct rtl_priv *rtlpriv = rtl_priv(hw);
619 u32 target_cmd = 0;
620 u32 target_val=0;
621 u8 entry_i=0;
622 u32 ulstatus;
623 int i = 100, j = 0;
624
625 /* This dump the current register page */
626 seq_puts(m,
627 "\n#################### SECURITY CAM (0-10) ##################\n ");
628
629 for (j = 0; j < 11; j++) {
630 seq_printf(m, "\nD: %2x > ", j);
631 for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
632 /* polling bit, and No Write enable, and address */
633 target_cmd = entry_i + CAM_CONTENT_COUNT * j;
634 target_cmd = target_cmd | BIT(31);
635
636 /* Check polling bit is clear */
637 while ((i--) >= 0) {
638 ulstatus = rtl_read_dword(rtlpriv,
639 rtlpriv->cfg->maps[RWCAM]);
640 if (ulstatus & BIT(31)) {
641 continue;
642 } else {
643 break;
644 }
645 }
646
647 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
648 target_cmd);
649 target_val = rtl_read_dword(rtlpriv,
650 rtlpriv->cfg->maps[RCAMO]);
651 seq_printf(m, "%8.8x ", target_val);
652 }
653 }
654 seq_puts(m, "\n");
655 return 0;
656}
657
658static int dl_proc_open_cam_1(struct inode *inode, struct file *file)
659{
660 return single_open(file, rtl_proc_get_cam_register_1,
661 GET_INODE_DATA(inode));
662}
663
664static const struct file_operations file_ops_cam_1 = {
665 .open = dl_proc_open_cam_1,
666 .read = seq_read,
667 .llseek = seq_lseek,
668 .release = seq_release,
669};
670
671static int rtl_proc_get_cam_register_2(struct seq_file *m, void *v)
672{
673 struct ieee80211_hw *hw = m->private;
674 struct rtl_priv *rtlpriv = rtl_priv(hw);
675 u32 target_cmd = 0;
676 u32 target_val = 0;
677 u8 entry_i = 0;
678 u32 ulstatus;
679 int i = 100, j = 0;
680
681 /* This dump the current register page */
682 seq_puts(m,
683 "\n################### SECURITY CAM (11-21) ##################\n ");
684
685 for (j = 11; j < 22; j++) {
686 seq_printf(m, "\nD: %2x > ", j);
687 for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
688 target_cmd = entry_i + CAM_CONTENT_COUNT * j;
689 target_cmd = target_cmd | BIT(31);
690
691 while ((i--) >= 0) {
692 ulstatus = rtl_read_dword(rtlpriv,
693 rtlpriv->cfg->maps[RWCAM]);
694 if (ulstatus & BIT(31)) {
695 continue;
696 } else {
697 break;
698 }
699 }
700
701 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
702 target_cmd);
703 target_val = rtl_read_dword(rtlpriv,
704 rtlpriv->cfg->maps[RCAMO]);
705 seq_printf(m, "%8.8x ", target_val);
706 }
707 }
708 seq_puts(m, "\n");
709 return 0;
710}
711
712static int dl_proc_open_cam_2(struct inode *inode, struct file *file)
713{
714 return single_open(file, rtl_proc_get_cam_register_2,
715 GET_INODE_DATA(inode));
716}
717
718static const struct file_operations file_ops_cam_2 = {
719 .open = dl_proc_open_cam_2,
720 .read = seq_read,
721 .llseek = seq_lseek,
722 .release = seq_release,
723};
724
725static int rtl_proc_get_cam_register_3(struct seq_file *m, void *v)
726{
727 struct ieee80211_hw *hw = m->private;
728 struct rtl_priv *rtlpriv = rtl_priv(hw);
729 u32 target_cmd = 0;
730 u32 target_val = 0;
731 u8 entry_i = 0;
732 u32 ulstatus;
733 int i = 100, j = 0;
734
735 /* This dump the current register page */
736 seq_puts(m,
737 "\n################### SECURITY CAM (22-31) ##################\n ");
738
739 for (j = 22; j < TOTAL_CAM_ENTRY; j++) {
740 seq_printf(m, "\nD: %2x > ", j);
741 for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
742 target_cmd = entry_i+CAM_CONTENT_COUNT*j;
743 target_cmd = target_cmd | BIT(31);
744
745 while ((i--) >= 0) {
746 ulstatus = rtl_read_dword(rtlpriv,
747 rtlpriv->cfg->maps[RWCAM]);
748 if (ulstatus & BIT(31)) {
749 continue;
750 } else {
751 break;
752 }
753 }
754
755 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
756 target_cmd);
757 target_val = rtl_read_dword(rtlpriv,
758 rtlpriv->cfg->maps[RCAMO]);
759 seq_printf(m, "%8.8x ", target_val);
760 }
761 }
762 seq_puts(m, "\n");
763 return 0;
764}
765
766static int dl_proc_open_cam_3(struct inode *inode, struct file *file)
767{
768 return single_open(file, rtl_proc_get_cam_register_3,
769 GET_INODE_DATA(inode));
770}
771
772static const struct file_operations file_ops_cam_3 = {
773 .open = dl_proc_open_cam_3,
774 .read = seq_read,
775 .llseek = seq_lseek,
776 .release = seq_release,
777};
778
779void rtl_proc_add_one(struct ieee80211_hw *hw)
780{
781 struct rtl_priv *rtlpriv = rtl_priv(hw);
782 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
783 struct proc_dir_entry *entry;
784
785 snprintf(rtlpriv->dbg.proc_name, 18, "%x-%x-%x-%x-%x-%x",
786 rtlefuse->dev_addr[0], rtlefuse->dev_addr[1],
787 rtlefuse->dev_addr[2], rtlefuse->dev_addr[3],
788 rtlefuse->dev_addr[4], rtlefuse->dev_addr[5]);
789
790 rtlpriv->dbg.proc_dir = proc_mkdir(rtlpriv->dbg.proc_name, proc_topdir);
791 if (!rtlpriv->dbg.proc_dir) {
792 RT_TRACE(COMP_INIT, DBG_EMERG, ("Unable to init "
793 "/proc/net/%s/%s\n", rtlpriv->cfg->name,
794 rtlpriv->dbg.proc_name));
795 return;
796 }
797
798 entry = proc_create_data("mac-0", S_IFREG | S_IRUGO,
799 rtlpriv->dbg.proc_dir, &file_ops_mac_0, hw);
800 if (!entry)
801 RT_TRACE(COMP_INIT, DBG_EMERG,
802 ("Unable to initialize /proc/net/%s/%s/mac-0\n",
803 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
804
805 entry = proc_create_data("mac-1", S_IFREG | S_IRUGO,
806 rtlpriv->dbg.proc_dir, &file_ops_mac_1, hw);
807 if (!entry)
808 RT_TRACE(COMP_INIT, COMP_ERR,
809 ("Unable to initialize /proc/net/%s/%s/mac-1\n",
810 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
811
812 entry = proc_create_data("mac-2", S_IFREG | S_IRUGO,
813 rtlpriv->dbg.proc_dir, &file_ops_mac_2, hw);
814 if (!entry)
815 RT_TRACE(COMP_INIT, COMP_ERR,
816 ("Unable to initialize /proc/net/%s/%s/mac-2\n",
817 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
818
819 entry = proc_create_data("mac-3", S_IFREG | S_IRUGO,
820 rtlpriv->dbg.proc_dir, &file_ops_mac_3, hw);
821 if (!entry)
822 RT_TRACE(COMP_INIT, COMP_ERR,
823 ("Unable to initialize /proc/net/%s/%s/mac-3\n",
824 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
825
826 entry = proc_create_data("mac-4", S_IFREG | S_IRUGO,
827 rtlpriv->dbg.proc_dir, &file_ops_mac_4, hw);
828 if (!entry)
829 RT_TRACE(COMP_INIT, COMP_ERR,
830 ("Unable to initialize /proc/net/%s/%s/mac-4\n",
831 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
832
833 entry = proc_create_data("mac-5", S_IFREG | S_IRUGO,
834 rtlpriv->dbg.proc_dir, &file_ops_mac_5, hw);
835 if (!entry)
836 RT_TRACE(COMP_INIT, COMP_ERR,
837 ("Unable to initialize /proc/net/%s/%s/mac-5\n",
838 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
839
840 entry = proc_create_data("mac-6", S_IFREG | S_IRUGO,
841 rtlpriv->dbg.proc_dir, &file_ops_mac_6, hw);
842 if (!entry)
843 RT_TRACE(COMP_INIT, COMP_ERR,
844 ("Unable to initialize /proc/net/%s/%s/mac-6\n",
845 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
846
847 entry = proc_create_data("mac-7", S_IFREG | S_IRUGO,
848 rtlpriv->dbg.proc_dir, &file_ops_mac_7, hw);
849 if (!entry)
850 RT_TRACE(COMP_INIT, COMP_ERR,
851 ("Unable to initialize /proc/net/%s/%s/mac-7\n",
852 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
853
854 entry = proc_create_data("bb-8", S_IFREG | S_IRUGO,
855 rtlpriv->dbg.proc_dir, &file_ops_bb_8, hw);
856 if (!entry)
857 RT_TRACE(COMP_INIT, COMP_ERR,
858 ("Unable to initialize /proc/net/%s/%s/bb-8\n",
859 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
860
861 entry = proc_create_data("bb-9", S_IFREG | S_IRUGO,
862 rtlpriv->dbg.proc_dir, &file_ops_bb_9, hw);
863 if (!entry)
864 RT_TRACE(COMP_INIT, COMP_ERR,
865 ("Unable to initialize /proc/net/%s/%s/bb-9\n",
866 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
867
868 entry = proc_create_data("bb-a", S_IFREG | S_IRUGO,
869 rtlpriv->dbg.proc_dir, &file_ops_bb_a, hw);
870 if (!entry)
871 RT_TRACE(COMP_INIT, COMP_ERR,
872 ("Unable to initialize /proc/net/%s/%s/bb-a\n",
873 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
874
875 entry = proc_create_data("bb-b", S_IFREG | S_IRUGO,
876 rtlpriv->dbg.proc_dir, &file_ops_bb_b, hw);
877 if (!entry)
878 RT_TRACE(COMP_INIT, COMP_ERR,
879 ("Unable to initialize /proc/net/%s/%s/bb-b\n",
880 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
881
882 entry = proc_create_data("bb-c", S_IFREG | S_IRUGO,
883 rtlpriv->dbg.proc_dir, &file_ops_bb_c, hw);
884 if (!entry)
885 RT_TRACE(COMP_INIT, COMP_ERR,
886 ("Unable to initialize /proc/net/%s/%s/bb-c\n",
887 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
888
889 entry = proc_create_data("bb-d", S_IFREG | S_IRUGO,
890 rtlpriv->dbg.proc_dir, &file_ops_bb_d, hw);
891 if (!entry)
892 RT_TRACE(COMP_INIT, COMP_ERR,
893 ("Unable to initialize /proc/net/%s/%s/bb-d\n",
894 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
895
896 entry = proc_create_data("bb-e", S_IFREG | S_IRUGO,
897 rtlpriv->dbg.proc_dir, &file_ops_bb_e, hw);
898 if (!entry)
899 RT_TRACE(COMP_INIT, COMP_ERR,
900 ("Unable to initialize /proc/net/%s/%s/bb-e\n",
901 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
902
903 entry = proc_create_data("bb-f", S_IFREG | S_IRUGO,
904 rtlpriv->dbg.proc_dir, &file_ops_bb_f, hw);
905 if (!entry)
906 RT_TRACE(COMP_INIT, COMP_ERR,
907 ("Unable to initialize /proc/net/%s/%s/bb-f\n",
908 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
909
910 entry = proc_create_data("rf-a", S_IFREG | S_IRUGO,
911 rtlpriv->dbg.proc_dir, &file_ops_rf_a, hw);
912 if (!entry)
913 RT_TRACE(COMP_INIT, COMP_ERR,
914 ("Unable to initialize /proc/net/%s/%s/rf-a\n",
915 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
916
917 entry = proc_create_data("rf-b", S_IFREG | S_IRUGO,
918 rtlpriv->dbg.proc_dir, &file_ops_rf_b, hw);
919 if (!entry)
920 RT_TRACE(COMP_INIT, COMP_ERR,
921 ("Unable to initialize /proc/net/%s/%s/rf-b\n",
922 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
923
924 entry = proc_create_data("cam-1", S_IFREG | S_IRUGO,
925 rtlpriv->dbg.proc_dir, &file_ops_cam_1, hw);
926 if (!entry)
927 RT_TRACE(COMP_INIT, COMP_ERR,
928 ("Unable to initialize /proc/net/%s/%s/cam-1\n",
929 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
930
931 entry = proc_create_data("cam-2", S_IFREG | S_IRUGO,
932 rtlpriv->dbg.proc_dir, &file_ops_cam_2, hw);
933 if (!entry)
934 RT_TRACE(COMP_INIT, COMP_ERR,
935 ("Unable to initialize /proc/net/%s/%s/cam-2\n",
936 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
937
938 entry = proc_create_data("cam-3", S_IFREG | S_IRUGO,
939 rtlpriv->dbg.proc_dir, &file_ops_cam_3, hw);
940 if (!entry)
941 RT_TRACE(COMP_INIT, COMP_ERR,
942 ("Unable to initialize /proc/net/%s/%s/cam-3\n",
943 rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
944}
945
946void rtl_proc_remove_one(struct ieee80211_hw *hw)
947{
948 struct rtl_priv *rtlpriv = rtl_priv(hw);
949
950 if (rtlpriv->dbg.proc_dir) {
951 remove_proc_entry("mac-0", rtlpriv->dbg.proc_dir);
952 remove_proc_entry("mac-1", rtlpriv->dbg.proc_dir);
953 remove_proc_entry("mac-2", rtlpriv->dbg.proc_dir);
954 remove_proc_entry("mac-3", rtlpriv->dbg.proc_dir);
955 remove_proc_entry("mac-4", rtlpriv->dbg.proc_dir);
956 remove_proc_entry("mac-5", rtlpriv->dbg.proc_dir);
957 remove_proc_entry("mac-6", rtlpriv->dbg.proc_dir);
958 remove_proc_entry("mac-7", rtlpriv->dbg.proc_dir);
959 remove_proc_entry("bb-8", rtlpriv->dbg.proc_dir);
960 remove_proc_entry("bb-9", rtlpriv->dbg.proc_dir);
961 remove_proc_entry("bb-a", rtlpriv->dbg.proc_dir);
962 remove_proc_entry("bb-b", rtlpriv->dbg.proc_dir);
963 remove_proc_entry("bb-c", rtlpriv->dbg.proc_dir);
964 remove_proc_entry("bb-d", rtlpriv->dbg.proc_dir);
965 remove_proc_entry("bb-e", rtlpriv->dbg.proc_dir);
966 remove_proc_entry("bb-f", rtlpriv->dbg.proc_dir);
967 remove_proc_entry("rf-a", rtlpriv->dbg.proc_dir);
968 remove_proc_entry("rf-b", rtlpriv->dbg.proc_dir);
969 remove_proc_entry("cam-1", rtlpriv->dbg.proc_dir);
970 remove_proc_entry("cam-2", rtlpriv->dbg.proc_dir);
971 remove_proc_entry("cam-3", rtlpriv->dbg.proc_dir);
972
973 remove_proc_entry(rtlpriv->dbg.proc_name, proc_topdir);
974
975 rtlpriv->dbg.proc_dir = NULL;
976 }
977}
978
979void rtl_proc_add_topdir(void)
980{
981 proc_topdir = proc_mkdir("rtlwifi", init_net.proc_net);
982}
983
984void rtl_proc_remove_topdir(void)
985{
986 if (proc_topdir)
987 remove_proc_entry("rtlwifi", init_net.proc_net);
988} \ No newline at end of file
diff --git a/drivers/staging/rtl8821ae/debug.h b/drivers/staging/rtl8821ae/debug.h
new file mode 100644
index 000000000000..5eb6251b89da
--- /dev/null
+++ b/drivers/staging/rtl8821ae/debug.h
@@ -0,0 +1,227 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * Tmis program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * Tmis program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * tmis program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * Tme full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_DEBUG_H__
31#define __RTL_DEBUG_H__
32
33/*--------------------------------------------------------------
34 Debug level
35--------------------------------------------------------------*/
36/*
37 *Fatal bug.
38 *For example, Tx/Rx/IO locked up,
39 *memory access violation,
40 *resource allocation failed,
41 *unexpected HW behavior, HW BUG
42 *and so on.
43 */
44#define DBG_EMERG 0
45
46/*
47 *Abnormal, rare, or unexpeted cases.
48 *For example, Packet/IO Ctl canceled,
49 *device suprisely unremoved and so on.
50 */
51#define DBG_WARNING 2
52
53/*
54 *Normal case driver developer should
55 *open, we can see link status like
56 *assoc/AddBA/DHCP/adapter start and
57 *so on basic and useful infromations.
58 */
59#define DBG_DMESG 3
60
61/*
62 *Normal case with useful information
63 *about current SW or HW state.
64 *For example, Tx/Rx descriptor to fill,
65 *Tx/Rx descriptor completed status,
66 *SW protocol state change, dynamic
67 *mechanism state change and so on.
68 */
69#define DBG_LOUD 4
70
71/*
72 *Normal case with detail execution
73 *flow or information.
74 */
75#define DBG_TRACE 5
76
77/*--------------------------------------------------------------
78 Define the rt_trace components
79--------------------------------------------------------------*/
80#define COMP_ERR BIT(0)
81#define COMP_FW BIT(1)
82#define COMP_INIT BIT(2) /*For init/deinit */
83#define COMP_RECV BIT(3) /*For Rx. */
84#define COMP_SEND BIT(4) /*For Tx. */
85#define COMP_MLME BIT(5) /*For MLME. */
86#define COMP_SCAN BIT(6) /*For Scan. */
87#define COMP_INTR BIT(7) /*For interrupt Related. */
88#define COMP_LED BIT(8) /*For LED. */
89#define COMP_SEC BIT(9) /*For sec. */
90#define COMP_BEACON BIT(10) /*For beacon. */
91#define COMP_RATE BIT(11) /*For rate. */
92#define COMP_RXDESC BIT(12) /*For rx desc. */
93#define COMP_DIG BIT(13) /*For DIG */
94#define COMP_TXAGC BIT(14) /*For Tx power */
95#define COMP_HIPWR BIT(15) /*For High Power Mechanism */
96#define COMP_POWER BIT(16) /*For lps/ips/aspm. */
97#define COMP_POWER_TRACKING BIT(17) /*For TX POWER TRACKING */
98#define COMP_BB_POWERSAVING BIT(18)
99#define COMP_SWAS BIT(19) /*For SW Antenna Switch */
100#define COMP_RF BIT(20) /*For RF. */
101#define COMP_TURBO BIT(21) /*For EDCA TURBO. */
102#define COMP_RATR BIT(22)
103#define COMP_CMD BIT(23)
104#define COMP_EFUSE BIT(24)
105#define COMP_QOS BIT(25)
106#define COMP_MAC80211 BIT(26)
107#define COMP_REGD BIT(27)
108#define COMP_CHAN BIT(28)
109#define COMP_EASY_CONCURRENT BIT(29)
110#define COMP_BT_COEXIST BIT(30)
111#define COMP_IQK BIT(31)
112
113/*--------------------------------------------------------------
114 Define the rt_print components
115--------------------------------------------------------------*/
116/* Define EEPROM and EFUSE check module bit*/
117#define EEPROM_W BIT(0)
118#define EFUSE_PG BIT(1)
119#define EFUSE_READ_ALL BIT(2)
120
121/* Define init check for module bit*/
122#define INIT_EEPROM BIT(0)
123#define INIT_TxPower BIT(1)
124#define INIT_IQK BIT(2)
125#define INIT_RF BIT(3)
126
127/* Define PHY-BB/RF/MAC check module bit */
128#define PHY_BBR BIT(0)
129#define PHY_BBW BIT(1)
130#define PHY_RFR BIT(2)
131#define PHY_RFW BIT(3)
132#define PHY_MACR BIT(4)
133#define PHY_MACW BIT(5)
134#define PHY_ALLR BIT(6)
135#define PHY_ALLW BIT(7)
136#define PHY_TXPWR BIT(8)
137#define PHY_PWRDIFF BIT(9)
138
139/* Define Dynamic Mechanism check module bit --> FDM */
140#define WA_IOT BIT(0)
141#define DM_PWDB BIT(1)
142#define DM_MONITOR BIT(2)
143#define DM_DIG BIT(3)
144#define DM_EDCA_TURBO BIT(4)
145
146enum dbgp_flag_e {
147 FQOS = 0,
148 FTX = 1,
149 FRX = 2,
150 FSEC = 3,
151 FMGNT = 4,
152 FMLME = 5,
153 FRESOURCE = 6,
154 FBEACON = 7,
155 FISR = 8,
156 FPHY = 9,
157 FMP = 10,
158 FEEPROM = 11,
159 FPWR = 12,
160 FDM = 13,
161 FDBGCtrl = 14,
162 FC2H = 15,
163 FBT = 16,
164 FINIT = 17,
165 FIOCTL = 18,
166 DBGP_TYPE_MAX
167};
168
169#define RT_ASSERT(_exp,fmt) \
170 do { \
171 if(!(_exp)) { \
172 printk(KERN_DEBUG "%s:%s(): ", KBUILD_MODNAME, \
173 __func__); \
174 printk fmt; \
175 } \
176 } while(0);
177
178#define RT_DISP(dbgtype, dbgflag, printstr)
179
180#define RT_TRACE(comp, level, fmt)\
181 do { \
182 if(unlikely(((comp) & rtlpriv->dbg.global_debugcomponents) && \
183 ((level) <= rtlpriv->dbg.global_debuglevel))) {\
184 printk(KERN_DEBUG "%s-%d:%s():<%lx-%x> ", \
185 KBUILD_MODNAME, \
186 rtlpriv->rtlhal.interfaceindex, __func__, \
187 in_interrupt(), in_atomic()); \
188 printk fmt; \
189 }\
190 } while(0);
191
192#define RTPRINT(rtlpriv, dbgtype, dbgflag, printstr) \
193 do { \
194 if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \
195 printk(KERN_DEBUG "%s: ", KBUILD_MODNAME); \
196 printk printstr; \
197 } \
198 } while(0);
199
200#define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
201 _hexdatalen) \
202 do {\
203 if(unlikely(((_comp) & rtlpriv->dbg.global_debugcomponents ) &&\
204 (_level <= rtlpriv->dbg.global_debuglevel ))) { \
205 int __i; \
206 u8* ptr = (u8*)_hexdata; \
207 printk(KERN_DEBUG "%s: ", KBUILD_MODNAME); \
208 printk(KERN_DEBUG "In process \"%s\" (pid %i):", \
209 current->comm, \
210 current->pid); \
211 printk(_titlestring); \
212 for( __i=0; __i<(int)_hexdatalen; __i++ ) { \
213 printk("%02X%s", ptr[__i], (((__i + 1) % 4) \
214 == 0)?" ":" ");\
215 if (((__i + 1) % 16) == 0) \
216 printk("\n"); \
217 } \
218 printk(KERN_DEBUG "\n"); \
219 } \
220 } while(0);
221
222void rtl_dbgp_flag_init(struct ieee80211_hw *hw);
223void rtl_proc_add_one(struct ieee80211_hw *hw);
224void rtl_proc_remove_one(struct ieee80211_hw *hw);
225void rtl_proc_add_topdir(void);
226void rtl_proc_remove_topdir(void);
227#endif
diff --git a/drivers/staging/rtl8821ae/efuse.c b/drivers/staging/rtl8821ae/efuse.c
new file mode 100644
index 000000000000..74c19ecc95a9
--- /dev/null
+++ b/drivers/staging/rtl8821ae/efuse.c
@@ -0,0 +1,1285 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * Tmis program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * Tmis program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * tmis program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * Tme full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29#include "wifi.h"
30#include "efuse.h"
31#include "btcoexist/halbt_precomp.h"
32#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
33#include <linux/export.h>
34#endif
35
36static const u8 MAX_PGPKT_SIZE = 9;
37static const u8 PGPKT_DATA_SIZE = 8;
38static const int EFUSE_MAX_SIZE = 512;
39
40static const struct efuse_map RTL8712_SDIO_EFUSE_TABLE[] = {
41 {0, 0, 0, 2},
42 {0, 1, 0, 2},
43 {0, 2, 0, 2},
44 {1, 0, 0, 1},
45 {1, 0, 1, 1},
46 {1, 1, 0, 1},
47 {1, 1, 1, 3},
48 {1, 3, 0, 17},
49 {3, 3, 1, 48},
50 {10, 0, 0, 6},
51 {10, 3, 0, 1},
52 {10, 3, 1, 1},
53 {11, 0, 0, 28}
54};
55
56static void efuse_shadow_read_1byte(struct ieee80211_hw *hw, u16 offset,
57 u8 * value);
58static void efuse_shadow_read_2byte(struct ieee80211_hw *hw, u16 offset,
59 u16 * value);
60static void efuse_shadow_read_4byte(struct ieee80211_hw *hw, u16 offset,
61 u32 * value);
62static void efuse_shadow_write_1byte(struct ieee80211_hw *hw, u16 offset,
63 u8 value);
64static void efuse_shadow_write_2byte(struct ieee80211_hw *hw, u16 offset,
65 u16 value);
66static void efuse_shadow_write_4byte(struct ieee80211_hw *hw, u16 offset,
67 u32 value);
68static int efuse_one_byte_write(struct ieee80211_hw *hw, u16 addr,
69 u8 data);
70static void efuse_read_all_map(struct ieee80211_hw *hw, u8 * efuse);
71static int efuse_pg_packet_read(struct ieee80211_hw *hw, u8 offset,
72 u8 *data);
73static int efuse_pg_packet_write(struct ieee80211_hw *hw, u8 offset,
74 u8 word_en, u8 * data);
75static void efuse_word_enable_data_read(u8 word_en, u8 * sourdata,
76 u8 * targetdata);
77static u8 efuse_word_enable_data_write(struct ieee80211_hw *hw,
78 u16 efuse_addr, u8 word_en, u8 * data);
79static void efuse_power_switch(struct ieee80211_hw *hw, u8 bwrite,
80 u8 pwrstate);
81static u16 efuse_get_current_size(struct ieee80211_hw *hw);
82static u8 efuse_calculate_word_cnts(u8 word_en);
83
84void efuse_initialize(struct ieee80211_hw *hw)
85{
86 struct rtl_priv *rtlpriv = rtl_priv(hw);
87 u8 bytetemp;
88 u8 temp;
89
90 bytetemp = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN] + 1);
91 temp = bytetemp | 0x20;
92 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN] + 1, temp);
93
94 bytetemp = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[SYS_ISO_CTRL] + 1);
95 temp = bytetemp & 0xFE;
96 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[SYS_ISO_CTRL] + 1, temp);
97
98 bytetemp = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3);
99 temp = bytetemp | 0x80;
100 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3, temp);
101
102 rtl_write_byte(rtlpriv, 0x2F8, 0x3);
103
104 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3, 0x72);
105
106}
107
108u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address)
109{
110 struct rtl_priv *rtlpriv = rtl_priv(hw);
111 u8 data;
112 u8 bytetemp;
113 u8 temp;
114 u32 k = 0;
115 const u32 efuse_real_content_len =
116 rtlpriv->cfg->maps[EFUSE_REAL_CONTENT_SIZE];
117
118 if (address < efuse_real_content_len) {
119 temp = address & 0xFF;
120 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
121 temp);
122 bytetemp = rtl_read_byte(rtlpriv,
123 rtlpriv->cfg->maps[EFUSE_CTRL] + 2);
124 temp = ((address >> 8) & 0x03) | (bytetemp & 0xFC);
125 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
126 temp);
127
128 bytetemp = rtl_read_byte(rtlpriv,
129 rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
130 temp = bytetemp & 0x7F;
131 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3,
132 temp);
133
134 bytetemp = rtl_read_byte(rtlpriv,
135 rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
136 while (!(bytetemp & 0x80)) {
137 bytetemp = rtl_read_byte(rtlpriv,
138 rtlpriv->cfg->
139 maps[EFUSE_CTRL] + 3);
140 k++;
141 if (k == 1000) {
142 k = 0;
143 break;
144 }
145 }
146 data = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
147 return data;
148 } else
149 return 0xFF;
150
151}
152//EXPORT_SYMBOL(efuse_read_1byte);
153
154void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value)
155{
156 struct rtl_priv *rtlpriv = rtl_priv(hw);
157 u8 bytetemp;
158 u8 temp;
159 u32 k = 0;
160 const u32 efuse_real_content_len =
161 rtlpriv->cfg->maps[EFUSE_REAL_CONTENT_SIZE];
162
163 RT_TRACE(COMP_EFUSE, DBG_LOUD,
164 ("Addr=%x Data =%x\n", address, value));
165
166 if (address < efuse_real_content_len) {
167 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL], value);
168
169 temp = address & 0xFF;
170 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
171 temp);
172 bytetemp = rtl_read_byte(rtlpriv,
173 rtlpriv->cfg->maps[EFUSE_CTRL] + 2);
174
175 temp = ((address >> 8) & 0x03) | (bytetemp & 0xFC);
176 rtl_write_byte(rtlpriv,
177 rtlpriv->cfg->maps[EFUSE_CTRL] + 2, temp);
178
179 bytetemp = rtl_read_byte(rtlpriv,
180 rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
181 temp = bytetemp | 0x80;
182 rtl_write_byte(rtlpriv,
183 rtlpriv->cfg->maps[EFUSE_CTRL] + 3, temp);
184
185 bytetemp = rtl_read_byte(rtlpriv,
186 rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
187
188 while (bytetemp & 0x80) {
189 bytetemp = rtl_read_byte(rtlpriv,
190 rtlpriv->cfg->
191 maps[EFUSE_CTRL] + 3);
192 k++;
193 if (k == 100) {
194 k = 0;
195 break;
196 }
197 }
198 }
199
200}
201
202void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf)
203{
204 struct rtl_priv *rtlpriv = rtl_priv(hw);
205 u32 value32;
206 u8 readbyte;
207 u16 retry;
208
209 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
210 (_offset & 0xff));
211 readbyte = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2);
212 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
213 ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
214
215 readbyte = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
216 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3,
217 (readbyte & 0x7f));
218
219 retry = 0;
220 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
221 while (!(((value32 >> 24) & 0xff) & 0x80) && (retry < 10000)) {
222 value32 = rtl_read_dword(rtlpriv,
223 rtlpriv->cfg->maps[EFUSE_CTRL]);
224 retry++;
225 }
226
227 udelay(50);
228 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
229
230 *pbuf = (u8) (value32 & 0xff);
231}
232
233void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf)
234{
235 struct rtl_priv *rtlpriv = rtl_priv(hw);
236 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
237 u8 efuse_tbl[rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]];
238 u8 rtemp8[1];
239 u16 efuse_addr = 0;
240 u8 offset, wren;
241 u8 u1temp = 0;
242 u16 i;
243 u16 j;
244 const u16 efuse_max_section =
245 rtlpriv->cfg->maps[EFUSE_MAX_SECTION_MAP];
246 const u32 efuse_real_content_len =
247 rtlpriv->cfg->maps[EFUSE_REAL_CONTENT_SIZE];
248 u16 efuse_word[efuse_max_section][EFUSE_MAX_WORD_UNIT];
249 u16 efuse_utilized = 0;
250 u8 efuse_usage;
251
252 if ((_offset + _size_byte) > rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]) {
253 RT_TRACE(COMP_EFUSE, DBG_LOUD,
254 ("read_efuse(): Invalid offset(%#x) with read "
255 "bytes(%#x)!!\n", _offset, _size_byte));
256 return;
257 }
258
259 for (i = 0; i < efuse_max_section; i++)
260 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
261 efuse_word[i][j] = 0xFFFF;
262
263 read_efuse_byte(hw, efuse_addr, rtemp8);
264 if (*rtemp8 != 0xFF) {
265 efuse_utilized++;
266 RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
267 ("Addr=%d\n", efuse_addr));
268 efuse_addr++;
269 }
270
271 while ((*rtemp8 != 0xFF) && (efuse_addr < efuse_real_content_len)) {
272 /* Check PG header for section num. */
273 if((*rtemp8 & 0x1F ) == 0x0F) {/* extended header */
274 u1temp =( (*rtemp8 & 0xE0) >> 5);
275 read_efuse_byte(hw, efuse_addr, rtemp8);
276
277 if((*rtemp8 & 0x0F) == 0x0F) {
278 efuse_addr++;
279 read_efuse_byte(hw, efuse_addr, rtemp8);
280
281 if (*rtemp8 != 0xFF &&
282 (efuse_addr < efuse_real_content_len)) {
283 efuse_addr++;
284 }
285 continue;
286 } else {
287 offset = ((*rtemp8 & 0xF0) >> 1) | u1temp;
288 wren = (*rtemp8 & 0x0F);
289 efuse_addr++;
290 }
291 } else {
292 offset = ((*rtemp8 >> 4) & 0x0f);
293 wren = (*rtemp8 & 0x0f);
294 }
295
296 if (offset < efuse_max_section) {
297 RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
298 ("offset-%d Worden=%x\n", offset, wren));
299
300 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
301 if (!(wren & 0x01)) {
302 RTPRINT(rtlpriv, FEEPROM,
303 EFUSE_READ_ALL, ("Addr=%d\n",
304 efuse_addr));
305
306 read_efuse_byte(hw, efuse_addr, rtemp8);
307 efuse_addr++;
308 efuse_utilized++;
309 efuse_word[offset][i] = (*rtemp8 &
310 0xff);
311
312 if (efuse_addr >=
313 efuse_real_content_len)
314 break;
315
316 RTPRINT(rtlpriv, FEEPROM,
317 EFUSE_READ_ALL, ("Addr=%d\n",
318 efuse_addr));
319
320 read_efuse_byte(hw, efuse_addr, rtemp8);
321 efuse_addr++;
322 efuse_utilized++;
323 efuse_word[offset][i] |=
324 (((u16) * rtemp8 << 8) & 0xff00);
325
326 if (efuse_addr >= efuse_real_content_len)
327 break;
328 }
329
330 wren >>= 1;
331 }
332 }
333
334 RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
335 ("Addr=%d\n", efuse_addr));
336 read_efuse_byte(hw, efuse_addr, rtemp8);
337 if (*rtemp8 != 0xFF && (efuse_addr < efuse_real_content_len)) {
338 efuse_utilized++;
339 efuse_addr++;
340 }
341 }
342
343 for (i = 0; i < efuse_max_section; i++) {
344 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
345 efuse_tbl[(i * 8) + (j * 2)] =
346 (efuse_word[i][j] & 0xff);
347 efuse_tbl[(i * 8) + ((j * 2) + 1)] =
348 ((efuse_word[i][j] >> 8) & 0xff);
349 }
350 }
351
352 for (i = 0; i < _size_byte; i++)
353 pbuf[i] = efuse_tbl[_offset + i];
354
355 rtlefuse->efuse_usedbytes = efuse_utilized;
356 efuse_usage = (u8) ((efuse_utilized * 100) / efuse_real_content_len);
357 rtlefuse->efuse_usedpercentage = efuse_usage;
358 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_EFUSE_BYTES,
359 (u8 *) & efuse_utilized);
360 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_EFUSE_USAGE,
361 (u8 *) & efuse_usage);
362}
363
364bool efuse_shadow_update_chk(struct ieee80211_hw *hw)
365{
366 struct rtl_priv *rtlpriv = rtl_priv(hw);
367 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
368 u8 section_idx, i, Base;
369 u16 words_need = 0, hdr_num = 0, totalbytes, efuse_used;
370 bool bwordchanged, bresult = true;
371
372 for (section_idx = 0; section_idx < 16; section_idx++) {
373 Base = section_idx * 8;
374 bwordchanged = false;
375
376 for (i = 0; i < 8; i = i + 2) {
377 if ((rtlefuse->efuse_map[EFUSE_INIT_MAP][Base + i] !=
378 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][Base + i]) ||
379 (rtlefuse->efuse_map[EFUSE_INIT_MAP][Base + i + 1] !=
380 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][Base + i +
381 1])) {
382 words_need++;
383 bwordchanged = true;
384 }
385 }
386
387 if (bwordchanged == true)
388 hdr_num++;
389 }
390
391 totalbytes = hdr_num + words_need * 2;
392 efuse_used = rtlefuse->efuse_usedbytes;
393
394 if ((totalbytes + efuse_used) >= (EFUSE_MAX_SIZE -
395 rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN]))
396 bresult = false;
397
398 RT_TRACE(COMP_EFUSE, DBG_LOUD,
399 ("efuse_shadow_update_chk(): totalbytes(%#x), "
400 "hdr_num(%#x), words_need(%#x), efuse_used(%d)\n",
401 totalbytes, hdr_num, words_need, efuse_used));
402
403 return bresult;
404}
405
406void efuse_shadow_read(struct ieee80211_hw *hw, u8 type,
407 u16 offset, u32 *value)
408{
409 if (type == 1)
410 efuse_shadow_read_1byte(hw, offset, (u8 *) value);
411 else if (type == 2)
412 efuse_shadow_read_2byte(hw, offset, (u16 *) value);
413 else if (type == 4)
414 efuse_shadow_read_4byte(hw, offset, (u32 *) value);
415
416}
417
418void efuse_shadow_write(struct ieee80211_hw *hw, u8 type, u16 offset,
419 u32 value)
420{
421 if (type == 1)
422 efuse_shadow_write_1byte(hw, offset, (u8) value);
423 else if (type == 2)
424 efuse_shadow_write_2byte(hw, offset, (u16) value);
425 else if (type == 4)
426 efuse_shadow_write_4byte(hw, offset, (u32) value);
427
428}
429
430bool efuse_shadow_update(struct ieee80211_hw *hw)
431{
432 struct rtl_priv *rtlpriv = rtl_priv(hw);
433 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
434 u16 i, offset, base;
435 u8 word_en = 0x0F;
436 u8 first_pg = false;
437
438 RT_TRACE(COMP_EFUSE, DBG_LOUD, ("\n"));
439
440 if (!efuse_shadow_update_chk(hw)) {
441 efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]);
442 memcpy(&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0],
443 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
444 rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
445
446 RT_TRACE(COMP_EFUSE, DBG_LOUD,
447 ("efuse out of capacity!!\n"));
448 return false;
449 }
450 efuse_power_switch(hw, true, true);
451
452 for (offset = 0; offset < 16; offset++) {
453
454 word_en = 0x0F;
455 base = offset * 8;
456
457 for (i = 0; i < 8; i++) {
458 if (first_pg == true) {
459
460 word_en &= ~(BIT(i / 2));
461
462 rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] =
463 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i];
464 } else {
465
466 if (rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] !=
467 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i]) {
468 word_en &= ~(BIT(i / 2));
469
470 rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] =
471 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i];
472 }
473 }
474 }
475
476 if (word_en != 0x0F) {
477 u8 tmpdata[8];
478 memcpy(tmpdata, (&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base]), 8);
479 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD,
480 ("U-efuse\n"), tmpdata, 8);
481
482 if (!efuse_pg_packet_write(hw, (u8) offset, word_en,
483 tmpdata)) {
484 RT_TRACE(COMP_ERR, DBG_WARNING,
485 ("PG section(%#x) fail!!\n", offset));
486 break;
487 }
488 }
489
490 }
491
492 efuse_power_switch(hw, true, false);
493 efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]);
494
495 memcpy(&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0],
496 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
497 rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
498
499 RT_TRACE(COMP_EFUSE, DBG_LOUD, ("\n"));
500 return true;
501}
502
503void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw)
504{
505 struct rtl_priv *rtlpriv = rtl_priv(hw);
506 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
507
508 if (rtlefuse->autoload_failflag == true) {
509 memset((&rtlefuse->efuse_map[EFUSE_INIT_MAP][0]),
510 0xFF, rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
511 } else {
512 efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]);
513 }
514
515 memcpy(&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0],
516 &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
517 rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
518
519}
520//EXPORT_SYMBOL(rtl_efuse_shadow_map_update);
521
522void efuse_force_write_vendor_Id(struct ieee80211_hw *hw)
523{
524 u8 tmpdata[8] = { 0xFF, 0xFF, 0xEC, 0x10, 0xFF, 0xFF, 0xFF, 0xFF };
525
526 efuse_power_switch(hw, true, true);
527
528 efuse_pg_packet_write(hw, 1, 0xD, tmpdata);
529
530 efuse_power_switch(hw, true, false);
531
532}
533
534void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx)
535{
536}
537
538static void efuse_shadow_read_1byte(struct ieee80211_hw *hw,
539 u16 offset, u8 *value)
540{
541 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
542 *value = rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset];
543}
544
545static void efuse_shadow_read_2byte(struct ieee80211_hw *hw,
546 u16 offset, u16 *value)
547{
548 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
549
550 *value = rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset];
551 *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] << 8;
552
553}
554
555static void efuse_shadow_read_4byte(struct ieee80211_hw *hw,
556 u16 offset, u32 *value)
557{
558 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
559
560 *value = rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset];
561 *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] << 8;
562 *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 2] << 16;
563 *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 3] << 24;
564}
565
566static void efuse_shadow_write_1byte(struct ieee80211_hw *hw,
567 u16 offset, u8 value)
568{
569 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
570
571 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset] = value;
572}
573
574static void efuse_shadow_write_2byte(struct ieee80211_hw *hw,
575 u16 offset, u16 value)
576{
577 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
578
579 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset] = value & 0x00FF;
580 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] = value >> 8;
581
582}
583
584static void efuse_shadow_write_4byte(struct ieee80211_hw *hw,
585 u16 offset, u32 value)
586{
587 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
588
589 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset] =
590 (u8) (value & 0x000000FF);
591 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] =
592 (u8) ((value >> 8) & 0x0000FF);
593 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 2] =
594 (u8) ((value >> 16) & 0x00FF);
595 rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 3] =
596 (u8) ((value >> 24) & 0xFF);
597
598}
599
600int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data)
601{
602 struct rtl_priv *rtlpriv = rtl_priv(hw);
603 u8 tmpidx = 0;
604 int bresult;
605
606 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
607 (u8) (addr & 0xff));
608 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
609 ((u8) ((addr >> 8) & 0x03)) |
610 (rtl_read_byte(rtlpriv,
611 rtlpriv->cfg->maps[EFUSE_CTRL] + 2) &
612 0xFC));
613
614 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3, 0x72);
615
616 while (!(0x80 & rtl_read_byte(rtlpriv,
617 rtlpriv->cfg->maps[EFUSE_CTRL] + 3))
618 && (tmpidx < 100)) {
619 tmpidx++;
620 }
621
622 if (tmpidx < 100) {
623 *data = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
624 bresult = true;
625 } else {
626 *data = 0xff;
627 bresult = false;
628 }
629 return bresult;
630}
631//EXPORT_SYMBOL(efuse_one_byte_read);
632
633static int efuse_one_byte_write(struct ieee80211_hw *hw, u16 addr, u8 data)
634{
635 struct rtl_priv *rtlpriv = rtl_priv(hw);
636 u8 tmpidx = 0;
637 bool bresult;
638
639 RT_TRACE(COMP_EFUSE, DBG_LOUD,
640 ("Addr = %x Data=%x\n", addr, data));
641
642 rtl_write_byte(rtlpriv,
643 rtlpriv->cfg->maps[EFUSE_CTRL] + 1, (u8) (addr & 0xff));
644 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
645 (rtl_read_byte(rtlpriv,
646 rtlpriv->cfg->maps[EFUSE_CTRL] +
647 2) & 0xFC) | (u8) ((addr >> 8) & 0x03));
648
649 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL], data);
650 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3, 0xF2);
651
652 while ((0x80 & rtl_read_byte(rtlpriv,
653 rtlpriv->cfg->maps[EFUSE_CTRL] + 3))
654 && (tmpidx < 100)) {
655 tmpidx++;
656 }
657
658 if (tmpidx < 100)
659 bresult = true;
660 else
661 bresult = false;
662
663 return bresult;
664}
665
666static void efuse_read_all_map(struct ieee80211_hw *hw, u8 * efuse)
667{
668 struct rtl_priv *rtlpriv = rtl_priv(hw);
669 efuse_power_switch(hw, false, true);
670 read_efuse(hw, 0, rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE], efuse);
671 efuse_power_switch(hw, false, false);
672}
673
674static void efuse_read_data_case1(struct ieee80211_hw *hw, u16 *efuse_addr,
675 u8 efuse_data, u8 offset, u8 *tmpdata,
676 u8 *readstate)
677{
678 bool bdataempty = true;
679 u8 hoffset;
680 u8 tmpidx;
681 u8 hworden;
682 u8 word_cnts;
683
684 hoffset = (efuse_data >> 4) & 0x0F;
685 hworden = efuse_data & 0x0F;
686 word_cnts = efuse_calculate_word_cnts(hworden);
687
688 if (hoffset == offset) {
689 for (tmpidx = 0; tmpidx < word_cnts * 2; tmpidx++) {
690 if (efuse_one_byte_read(hw, *efuse_addr + 1 + tmpidx,
691 &efuse_data)) {
692 tmpdata[tmpidx] = efuse_data;
693 if (efuse_data != 0xff)
694 bdataempty = true;
695 }
696 }
697
698 if (bdataempty == true) {
699 *readstate = PG_STATE_DATA;
700 } else {
701 *efuse_addr = *efuse_addr + (word_cnts * 2) + 1;
702 *readstate = PG_STATE_HEADER;
703 }
704
705 } else {
706 *efuse_addr = *efuse_addr + (word_cnts * 2) + 1;
707 *readstate = PG_STATE_HEADER;
708 }
709}
710
711static int efuse_pg_packet_read(struct ieee80211_hw *hw, u8 offset, u8 *data)
712{
713 u8 readstate = PG_STATE_HEADER;
714
715 bool bcontinual = true;
716
717 u8 efuse_data, word_cnts = 0;
718 u16 efuse_addr = 0;
719 u8 hworden = 0;
720 u8 tmpdata[8];
721
722 if (data == NULL)
723 return false;
724 if (offset > 15)
725 return false;
726
727 memset(data, 0xff, PGPKT_DATA_SIZE * sizeof(u8));
728 memset(tmpdata, 0xff, PGPKT_DATA_SIZE * sizeof(u8));
729
730 while (bcontinual && (efuse_addr < EFUSE_MAX_SIZE)) {
731 if (readstate & PG_STATE_HEADER) {
732 if (efuse_one_byte_read(hw, efuse_addr, &efuse_data)
733 && (efuse_data != 0xFF))
734 efuse_read_data_case1(hw, &efuse_addr, efuse_data, offset,
735 tmpdata, &readstate);
736 else
737 bcontinual = false;
738 } else if (readstate & PG_STATE_DATA) {
739 efuse_word_enable_data_read(hworden, tmpdata, data);
740 efuse_addr = efuse_addr + (word_cnts * 2) + 1;
741 readstate = PG_STATE_HEADER;
742 }
743
744 }
745
746 if ((data[0] == 0xff) && (data[1] == 0xff) &&
747 (data[2] == 0xff) && (data[3] == 0xff) &&
748 (data[4] == 0xff) && (data[5] == 0xff) &&
749 (data[6] == 0xff) && (data[7] == 0xff))
750 return false;
751 else
752 return true;
753
754}
755
756static void efuse_write_data_case1(struct ieee80211_hw *hw, u16 *efuse_addr,
757 u8 efuse_data, u8 offset, int *bcontinual,
758 u8 *write_state, struct pgpkt_struct *target_pkt,
759 int *repeat_times, int *bresult, u8 word_en)
760{
761 struct rtl_priv *rtlpriv = rtl_priv(hw);
762 struct pgpkt_struct tmp_pkt;
763 int bdataempty = true;
764 u8 originaldata[8 * sizeof(u8)];
765 u8 badworden = 0x0F;
766 u8 match_word_en, tmp_word_en;
767 u8 tmpindex;
768 u8 tmp_header = efuse_data;
769 u8 tmp_word_cnts;
770
771 tmp_pkt.offset = (tmp_header >> 4) & 0x0F;
772 tmp_pkt.word_en = tmp_header & 0x0F;
773 tmp_word_cnts = efuse_calculate_word_cnts(tmp_pkt.word_en);
774
775 if (tmp_pkt.offset != target_pkt->offset) {
776 *efuse_addr = *efuse_addr + (tmp_word_cnts * 2) + 1;
777 *write_state = PG_STATE_HEADER;
778 } else {
779 for (tmpindex = 0; tmpindex < (tmp_word_cnts * 2); tmpindex++) {
780 if (efuse_one_byte_read(hw,
781 (*efuse_addr + 1 + tmpindex),
782 &efuse_data) && (efuse_data != 0xFF))
783 bdataempty = false;
784 }
785
786 if (bdataempty == false) {
787 *efuse_addr = *efuse_addr + (tmp_word_cnts * 2) + 1;
788 *write_state = PG_STATE_HEADER;
789 } else {
790 match_word_en = 0x0F;
791 if (!((target_pkt->word_en & BIT(0)) |
792 (tmp_pkt.word_en & BIT(0))))
793 match_word_en &= (~BIT(0));
794
795 if (!((target_pkt->word_en & BIT(1)) |
796 (tmp_pkt.word_en & BIT(1))))
797 match_word_en &= (~BIT(1));
798
799 if (!((target_pkt->word_en & BIT(2)) |
800 (tmp_pkt.word_en & BIT(2))))
801 match_word_en &= (~BIT(2));
802
803 if (!((target_pkt->word_en & BIT(3)) |
804 (tmp_pkt.word_en & BIT(3))))
805 match_word_en &= (~BIT(3));
806
807 if ((match_word_en & 0x0F) != 0x0F) {
808 badworden = efuse_word_enable_data_write(hw,
809 *efuse_addr + 1,
810 tmp_pkt.word_en,
811 target_pkt->data);
812
813 if (0x0F != (badworden & 0x0F)) {
814 u8 reorg_offset = offset;
815 u8 reorg_worden = badworden;
816 efuse_pg_packet_write(hw, reorg_offset,
817 reorg_worden,
818 originaldata);
819 }
820
821 tmp_word_en = 0x0F;
822 if ((target_pkt->word_en & BIT(0)) ^
823 (match_word_en & BIT(0)))
824 tmp_word_en &= (~BIT(0));
825
826 if ((target_pkt->word_en & BIT(1)) ^
827 (match_word_en & BIT(1)))
828 tmp_word_en &= (~BIT(1));
829
830 if ((target_pkt->word_en & BIT(2)) ^
831 (match_word_en & BIT(2)))
832 tmp_word_en &= (~BIT(2));
833
834 if ((target_pkt->word_en & BIT(3)) ^
835 (match_word_en & BIT(3)))
836 tmp_word_en &= (~BIT(3));
837
838 if ((tmp_word_en & 0x0F) != 0x0F) {
839 *efuse_addr = efuse_get_current_size(hw);
840 target_pkt->offset = offset;
841 target_pkt->word_en = tmp_word_en;
842 } else {
843 *bcontinual = false;
844 }
845 *write_state = PG_STATE_HEADER;
846 *repeat_times += 1;
847 if (*repeat_times > EFUSE_REPEAT_THRESHOLD_) {
848 *bcontinual = false;
849 *bresult = false;
850 }
851 } else {
852 *efuse_addr += (2 * tmp_word_cnts) + 1;
853 target_pkt->offset = offset;
854 target_pkt->word_en = word_en;
855 *write_state = PG_STATE_HEADER;
856 }
857 }
858 }
859 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, ("efuse PG_STATE_HEADER-1\n"));
860}
861
862static void efuse_write_data_case2(struct ieee80211_hw *hw, u16 *efuse_addr,
863 int *bcontinual, u8 *write_state,
864 struct pgpkt_struct target_pkt,
865 int *repeat_times, int *bresult)
866{
867 struct rtl_priv *rtlpriv = rtl_priv(hw);
868 struct pgpkt_struct tmp_pkt;
869 u8 pg_header;
870 u8 tmp_header;
871 u8 originaldata[8 * sizeof(u8)];
872 u8 tmp_word_cnts;
873 u8 badworden = 0x0F;
874
875 pg_header = ((target_pkt.offset << 4) & 0xf0) | target_pkt.word_en;
876 efuse_one_byte_write(hw, *efuse_addr, pg_header);
877 efuse_one_byte_read(hw, *efuse_addr, &tmp_header);
878
879 if (tmp_header == pg_header) {
880 *write_state = PG_STATE_DATA;
881 } else if (tmp_header == 0xFF) {
882 *write_state = PG_STATE_HEADER;
883 *repeat_times += 1;
884 if (*repeat_times > EFUSE_REPEAT_THRESHOLD_) {
885 *bcontinual = false;
886 *bresult = false;
887 }
888 } else {
889 tmp_pkt.offset = (tmp_header >> 4) & 0x0F;
890 tmp_pkt.word_en = tmp_header & 0x0F;
891
892 tmp_word_cnts = efuse_calculate_word_cnts(tmp_pkt.word_en);
893
894 memset(originaldata, 0xff, 8 * sizeof(u8));
895
896 if (efuse_pg_packet_read(hw, tmp_pkt.offset, originaldata)) {
897 badworden = efuse_word_enable_data_write(hw,
898 *efuse_addr + 1,
899 tmp_pkt.word_en,
900 originaldata);
901
902 if (0x0F != (badworden & 0x0F)) {
903 u8 reorg_offset = tmp_pkt.offset;
904 u8 reorg_worden = badworden;
905 efuse_pg_packet_write(hw, reorg_offset,
906 reorg_worden,
907 originaldata);
908 *efuse_addr = efuse_get_current_size(hw);
909 } else {
910 *efuse_addr = *efuse_addr +
911 (tmp_word_cnts * 2) + 1;
912 }
913 } else {
914 *efuse_addr = *efuse_addr + (tmp_word_cnts * 2) + 1;
915 }
916
917 *write_state = PG_STATE_HEADER;
918 *repeat_times += 1;
919 if (*repeat_times > EFUSE_REPEAT_THRESHOLD_) {
920 *bcontinual = false;
921 *bresult = false;
922 }
923
924 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
925 ("efuse PG_STATE_HEADER-2\n"));
926 }
927}
928
929static int efuse_pg_packet_write(struct ieee80211_hw *hw,
930 u8 offset, u8 word_en, u8 *data)
931{
932 struct rtl_priv *rtlpriv = rtl_priv(hw);
933 struct pgpkt_struct target_pkt;
934 u8 write_state = PG_STATE_HEADER;
935 int bcontinual = true, bdataempty = true, bresult = true;
936 u16 efuse_addr = 0;
937 u8 efuse_data;
938 u8 target_word_cnts = 0;
939 u8 badworden = 0x0F;
940 static int repeat_times = 0;
941
942 if (efuse_get_current_size(hw) >= (EFUSE_MAX_SIZE -
943 rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN])) {
944 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
945 ("efuse_pg_packet_write error \n"));
946 return false;
947 }
948
949 target_pkt.offset = offset;
950 target_pkt.word_en = word_en;
951
952 memset(target_pkt.data, 0xFF, 8 * sizeof(u8));
953
954 efuse_word_enable_data_read(word_en, data, target_pkt.data);
955 target_word_cnts = efuse_calculate_word_cnts(target_pkt.word_en);
956
957 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, ("efuse Power ON\n"));
958
959 while (bcontinual && (efuse_addr < (EFUSE_MAX_SIZE -
960 rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN]))) {
961
962 if (write_state == PG_STATE_HEADER) {
963 bdataempty = true;
964 badworden = 0x0F;
965 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
966 ("efuse PG_STATE_HEADER\n"));
967
968 if (efuse_one_byte_read(hw, efuse_addr, &efuse_data) &&
969 (efuse_data != 0xFF))
970 efuse_write_data_case1(hw, &efuse_addr,
971 efuse_data, offset,
972 &bcontinual,
973 &write_state,
974 &target_pkt,
975 &repeat_times, &bresult,
976 word_en);
977 else
978 efuse_write_data_case2(hw, &efuse_addr,
979 &bcontinual,
980 &write_state,
981 target_pkt,
982 &repeat_times,
983 &bresult);
984
985 } else if (write_state == PG_STATE_DATA) {
986 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
987 ("efuse PG_STATE_DATA\n"));
988 badworden = 0x0f;
989 badworden =
990 efuse_word_enable_data_write(hw, efuse_addr + 1,
991 target_pkt.word_en,
992 target_pkt.data);
993
994 if ((badworden & 0x0F) == 0x0F) {
995 bcontinual = false;
996 } else {
997 efuse_addr =
998 efuse_addr + (2 * target_word_cnts) + 1;
999
1000 target_pkt.offset = offset;
1001 target_pkt.word_en = badworden;
1002 target_word_cnts =
1003 efuse_calculate_word_cnts(target_pkt.
1004 word_en);
1005 write_state = PG_STATE_HEADER;
1006 repeat_times++;
1007 if (repeat_times > EFUSE_REPEAT_THRESHOLD_) {
1008 bcontinual = false;
1009 bresult = false;
1010 }
1011 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
1012 ("efuse PG_STATE_HEADER-3\n"));
1013 }
1014 }
1015 }
1016
1017 if (efuse_addr >= (EFUSE_MAX_SIZE -
1018 rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN])) {
1019 RT_TRACE(COMP_EFUSE, DBG_LOUD,
1020 ("efuse_addr(%#x) Out of size!!\n", efuse_addr));
1021 }
1022
1023 return true;
1024}
1025
1026static void efuse_word_enable_data_read(u8 word_en, u8 * sourdata,
1027 u8 *targetdata)
1028{
1029 if (!(word_en & BIT(0))) {
1030 targetdata[0] = sourdata[0];
1031 targetdata[1] = sourdata[1];
1032 }
1033
1034 if (!(word_en & BIT(1))) {
1035 targetdata[2] = sourdata[2];
1036 targetdata[3] = sourdata[3];
1037 }
1038
1039 if (!(word_en & BIT(2))) {
1040 targetdata[4] = sourdata[4];
1041 targetdata[5] = sourdata[5];
1042 }
1043
1044 if (!(word_en & BIT(3))) {
1045 targetdata[6] = sourdata[6];
1046 targetdata[7] = sourdata[7];
1047 }
1048}
1049
1050static u8 efuse_word_enable_data_write(struct ieee80211_hw *hw,
1051 u16 efuse_addr, u8 word_en, u8 *data)
1052{
1053 struct rtl_priv *rtlpriv = rtl_priv(hw);
1054 u16 tmpaddr;
1055 u16 start_addr = efuse_addr;
1056 u8 badworden = 0x0F;
1057 u8 tmpdata[8];
1058
1059 memset(tmpdata, 0xff, PGPKT_DATA_SIZE);
1060 RT_TRACE(COMP_EFUSE, DBG_LOUD,
1061 ("word_en = %x efuse_addr=%x\n", word_en, efuse_addr));
1062
1063 if (!(word_en & BIT(0))) {
1064 tmpaddr = start_addr;
1065 efuse_one_byte_write(hw, start_addr++, data[0]);
1066 efuse_one_byte_write(hw, start_addr++, data[1]);
1067
1068 efuse_one_byte_read(hw, tmpaddr, &tmpdata[0]);
1069 efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[1]);
1070 if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
1071 badworden &= (~BIT(0));
1072 }
1073
1074 if (!(word_en & BIT(1))) {
1075 tmpaddr = start_addr;
1076 efuse_one_byte_write(hw, start_addr++, data[2]);
1077 efuse_one_byte_write(hw, start_addr++, data[3]);
1078
1079 efuse_one_byte_read(hw, tmpaddr, &tmpdata[2]);
1080 efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[3]);
1081 if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
1082 badworden &= (~BIT(1));
1083 }
1084
1085 if (!(word_en & BIT(2))) {
1086 tmpaddr = start_addr;
1087 efuse_one_byte_write(hw, start_addr++, data[4]);
1088 efuse_one_byte_write(hw, start_addr++, data[5]);
1089
1090 efuse_one_byte_read(hw, tmpaddr, &tmpdata[4]);
1091 efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[5]);
1092 if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
1093 badworden &= (~BIT(2));
1094 }
1095
1096 if (!(word_en & BIT(3))) {
1097 tmpaddr = start_addr;
1098 efuse_one_byte_write(hw, start_addr++, data[6]);
1099 efuse_one_byte_write(hw, start_addr++, data[7]);
1100
1101 efuse_one_byte_read(hw, tmpaddr, &tmpdata[6]);
1102 efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[7]);
1103 if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
1104 badworden &= (~BIT(3));
1105 }
1106
1107 return badworden;
1108}
1109
1110static void efuse_power_switch(struct ieee80211_hw *hw, u8 bwrite, u8 pwrstate)
1111{
1112 struct rtl_priv *rtlpriv = rtl_priv(hw);
1113 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1114 u8 tempval;
1115 u16 tmpV16;
1116
1117 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1118 {
1119 if (pwrstate == true)
1120 {
1121 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_ACCESS], 0x69);
1122
1123 // 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid
1124 tmpV16 = rtl_read_word(rtlpriv,
1125 rtlpriv->cfg->maps[SYS_ISO_CTRL]);
1126
1127 printk("SYS_ISO_CTRL=%04x.\n",tmpV16);
1128 if( ! (tmpV16 & PWC_EV12V ) ){
1129 tmpV16 |= PWC_EV12V ;
1130 //PlatformEFIOWrite2Byte(pAdapter,REG_SYS_ISO_CTRL,tmpV16);
1131 }
1132 // Reset: 0x0000h[28], default valid
1133 tmpV16 = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN]);
1134 printk("SYS_FUNC_EN=%04x.\n",tmpV16);
1135 if( !(tmpV16 & FEN_ELDR) ){
1136 tmpV16 |= FEN_ELDR ;
1137 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN], tmpV16);
1138 }
1139
1140 // Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid
1141 tmpV16 = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[SYS_CLK] );
1142 printk("SYS_CLK=%04x.\n",tmpV16);
1143 if( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) )
1144 {
1145 tmpV16 |= (LOADER_CLK_EN |ANA8M ) ;
1146 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[SYS_CLK], tmpV16);
1147 }
1148
1149 if(bwrite == true)
1150 {
1151 // Enable LDO 2.5V before read/write action
1152 tempval = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3);
1153 printk("EFUSE_TEST=%04x.\n",tmpV16);
1154 tempval &= ~(BIT(3) | BIT(4) |BIT(5) | BIT(6));
1155 tempval |= (VOLTAGE_V25 << 3);
1156 tempval |= BIT(7);
1157 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3, tempval);
1158 }
1159 }
1160 else
1161 {
1162 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_ACCESS], 0x00);
1163 if(bwrite == true){
1164 // Disable LDO 2.5V after read/write action
1165 tempval = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3);
1166 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3, (tempval & 0x7F));
1167 }
1168 }
1169 }
1170 else
1171 {
1172 if (pwrstate == true && (rtlhal->hw_type !=
1173 HARDWARE_TYPE_RTL8192SE)) {
1174
1175 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE)
1176 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_ACCESS],
1177 0x69);
1178
1179 tmpV16 = rtl_read_word(rtlpriv,
1180 rtlpriv->cfg->maps[SYS_ISO_CTRL]);
1181 if (!(tmpV16 & rtlpriv->cfg->maps[EFUSE_PWC_EV12V])) {
1182 tmpV16 |= rtlpriv->cfg->maps[EFUSE_PWC_EV12V];
1183 rtl_write_word(rtlpriv,
1184 rtlpriv->cfg->maps[SYS_ISO_CTRL],
1185 tmpV16);
1186 }
1187
1188 tmpV16 = rtl_read_word(rtlpriv,
1189 rtlpriv->cfg->maps[SYS_FUNC_EN]);
1190 if (!(tmpV16 & rtlpriv->cfg->maps[EFUSE_FEN_ELDR])) {
1191 tmpV16 |= rtlpriv->cfg->maps[EFUSE_FEN_ELDR];
1192 rtl_write_word(rtlpriv,
1193 rtlpriv->cfg->maps[SYS_FUNC_EN], tmpV16);
1194 }
1195
1196 tmpV16 = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[SYS_CLK]);
1197 if ((!(tmpV16 & rtlpriv->cfg->maps[EFUSE_LOADER_CLK_EN])) ||
1198 (!(tmpV16 & rtlpriv->cfg->maps[EFUSE_ANA8M]))) {
1199 tmpV16 |= (rtlpriv->cfg->maps[EFUSE_LOADER_CLK_EN] |
1200 rtlpriv->cfg->maps[EFUSE_ANA8M]);
1201 rtl_write_word(rtlpriv,
1202 rtlpriv->cfg->maps[SYS_CLK], tmpV16);
1203 }
1204 }
1205
1206 if (pwrstate == true) {
1207 if (bwrite == true) {
1208 tempval = rtl_read_byte(rtlpriv,
1209 rtlpriv->cfg->maps[EFUSE_TEST] +
1210 3);
1211
1212 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) {
1213 tempval &= 0x0F;
1214 tempval |= (VOLTAGE_V25 << 4);
1215 }
1216
1217 rtl_write_byte(rtlpriv,
1218 rtlpriv->cfg->maps[EFUSE_TEST] + 3,
1219 (tempval | 0x80));
1220 }
1221
1222 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1223 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CLK],
1224 0x03);
1225 }
1226
1227 } else {
1228 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE)
1229 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_ACCESS], 0);
1230
1231 if (bwrite == true) {
1232 tempval = rtl_read_byte(rtlpriv,
1233 rtlpriv->cfg->maps[EFUSE_TEST] +
1234 3);
1235 rtl_write_byte(rtlpriv,
1236 rtlpriv->cfg->maps[EFUSE_TEST] + 3,
1237 (tempval & 0x7F));
1238 }
1239
1240 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1241 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CLK],
1242 0x02);
1243 }
1244
1245 }
1246 }
1247
1248}
1249
1250static u16 efuse_get_current_size(struct ieee80211_hw *hw)
1251{
1252 int bcontinual = true;
1253 u16 efuse_addr = 0;
1254 u8 hoffset, hworden;
1255 u8 efuse_data, word_cnts;
1256
1257 while (bcontinual && efuse_one_byte_read(hw, efuse_addr, &efuse_data)
1258 && (efuse_addr < EFUSE_MAX_SIZE)) {
1259 if (efuse_data != 0xFF) {
1260 hoffset = (efuse_data >> 4) & 0x0F;
1261 hworden = efuse_data & 0x0F;
1262 word_cnts = efuse_calculate_word_cnts(hworden);
1263 efuse_addr = efuse_addr + (word_cnts * 2) + 1;
1264 } else {
1265 bcontinual = false;
1266 }
1267 }
1268
1269 return efuse_addr;
1270}
1271
1272static u8 efuse_calculate_word_cnts(u8 word_en)
1273{
1274 u8 word_cnts = 0;
1275 if (!(word_en & BIT(0)))
1276 word_cnts++;
1277 if (!(word_en & BIT(1)))
1278 word_cnts++;
1279 if (!(word_en & BIT(2)))
1280 word_cnts++;
1281 if (!(word_en & BIT(3)))
1282 word_cnts++;
1283 return word_cnts;
1284}
1285
diff --git a/drivers/staging/rtl8821ae/efuse.h b/drivers/staging/rtl8821ae/efuse.h
new file mode 100644
index 000000000000..a9fcbe05cf9a
--- /dev/null
+++ b/drivers/staging/rtl8821ae/efuse.h
@@ -0,0 +1,130 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_EFUSE_H_
31#define __RTL_EFUSE_H_
32
33#define EFUSE_IC_ID_OFFSET 506
34
35/*
36#define EFUSE_REAL_CONTENT_LEN 512
37#define EFUSE_MAP_LEN 128
38#define EFUSE_MAX_SECTION 16
39#define EFUSE_MAX_WORD_UNIT 4
40#define EFUSE_IC_ID_OFFSET 506
41*/
42
43#define EFUSE_MAX_WORD_UNIT 4
44
45#define EFUSE_INIT_MAP 0
46#define EFUSE_MODIFY_MAP 1
47
48#define PG_STATE_HEADER 0x01
49#define PG_STATE_WORD_0 0x02
50#define PG_STATE_WORD_1 0x04
51#define PG_STATE_WORD_2 0x08
52#define PG_STATE_WORD_3 0x10
53#define PG_STATE_DATA 0x20
54
55#define PG_SWBYTE_H 0x01
56#define PG_SWBYTE_L 0x02
57
58#define _POWERON_DELAY_
59#define _PRE_EXECUTE_READ_CMD_
60
61#define EFUSE_REPEAT_THRESHOLD_ 3
62#define EFUSE_ERROE_HANDLE 1
63
64struct efuse_map {
65 u8 offset;
66 u8 word_start;
67 u8 byte_start;
68 u8 byte_cnts;
69};
70
71struct pgpkt_struct {
72 u8 offset;
73 u8 word_en;
74 u8 data[8];
75};
76
77enum efuse_data_item {
78 EFUSE_CHIP_ID = 0,
79 EFUSE_LDO_SETTING,
80 EFUSE_CLK_SETTING,
81 EFUSE_SDIO_SETTING,
82 EFUSE_CCCR,
83 EFUSE_SDIO_MODE,
84 EFUSE_OCR,
85 EFUSE_F0CIS,
86 EFUSE_F1CIS,
87 EFUSE_MAC_ADDR,
88 EFUSE_EEPROM_VER,
89 EFUSE_CHAN_PLAN,
90 EFUSE_TXPW_TAB
91};
92
93enum {
94 VOLTAGE_V25 = 0x03,
95 LDOE25_SHIFT = 28,
96};
97
98struct efuse_priv {
99 u8 id[2];
100 u8 ldo_setting[2];
101 u8 clk_setting[2];
102 u8 cccr;
103 u8 sdio_mode;
104 u8 ocr[3];
105 u8 cis0[17];
106 u8 cis1[48];
107 u8 mac_addr[6];
108 u8 eeprom_verno;
109 u8 channel_plan;
110 u8 tx_power_b[14];
111 u8 tx_power_g[14];
112};
113
114extern void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
115extern void efuse_initialize(struct ieee80211_hw *hw);
116extern u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address);
117extern int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data);
118extern void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value);
119extern void read_efuse(struct ieee80211_hw *hw, u16 _offset,
120 u16 _size_byte, u8 * pbuf);
121extern void efuse_shadow_read(struct ieee80211_hw *hw, u8 type,
122 u16 offset, u32 * value);
123extern void efuse_shadow_write(struct ieee80211_hw *hw, u8 type,
124 u16 offset, u32 value);
125extern bool efuse_shadow_update(struct ieee80211_hw *hw);
126extern bool efuse_shadow_update_chk(struct ieee80211_hw *hw);
127extern void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw);
128extern void efuse_force_write_vendor_Id(struct ieee80211_hw *hw);
129extern void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx);
130#endif
diff --git a/drivers/staging/rtl8821ae/pci.c b/drivers/staging/rtl8821ae/pci.c
new file mode 100644
index 000000000000..cfa651edd238
--- /dev/null
+++ b/drivers/staging/rtl8821ae/pci.c
@@ -0,0 +1,2549 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "core.h"
31#include "wifi.h"
32#include "pci.h"
33#include "base.h"
34#include "ps.h"
35#include "efuse.h"
36#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
37#include <linux/export.h>
38#endif
39
40static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
41 INTEL_VENDOR_ID,
42 ATI_VENDOR_ID,
43 AMD_VENDOR_ID,
44 SIS_VENDOR_ID
45};
46
47static const u8 ac_to_hwq[] = {
48 VO_QUEUE,
49 VI_QUEUE,
50 BE_QUEUE,
51 BK_QUEUE
52};
53
54u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
55 struct sk_buff *skb)
56{
57 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
58 u16 fc = rtl_get_fc(skb);
59 u8 queue_index = skb_get_queue_mapping(skb);
60
61 if (unlikely(ieee80211_is_beacon(fc)))
62 return BEACON_QUEUE;
63 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
64 return MGNT_QUEUE;
65 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
66 if (ieee80211_is_nullfunc(fc))
67 return HIGH_QUEUE;
68
69 return ac_to_hwq[queue_index];
70}
71
72/* Update PCI dependent default settings*/
73static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
74{
75 struct rtl_priv *rtlpriv = rtl_priv(hw);
76 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
77 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
78 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
79 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
80 u8 init_aspm;
81
82 ppsc->reg_rfps_level = 0;
83 ppsc->b_support_aspm = 0;
84
85 /*Update PCI ASPM setting */
86 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
87 switch (rtlpci->const_pci_aspm) {
88 case 0:
89 /*No ASPM */
90 break;
91
92 case 1:
93 /*ASPM dynamically enabled/disable. */
94 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
95 break;
96
97 case 2:
98 /*ASPM with Clock Req dynamically enabled/disable. */
99 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
100 RT_RF_OFF_LEVL_CLK_REQ);
101 break;
102
103 case 3:
104 /*
105 * Always enable ASPM and Clock Req
106 * from initialization to halt.
107 * */
108 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
109 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
110 RT_RF_OFF_LEVL_CLK_REQ);
111 break;
112
113 case 4:
114 /*
115 * Always enable ASPM without Clock Req
116 * from initialization to halt.
117 * */
118 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
119 RT_RF_OFF_LEVL_CLK_REQ);
120 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
121 break;
122 }
123
124 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
125
126 /*Update Radio OFF setting */
127 switch (rtlpci->const_hwsw_rfoff_d3) {
128 case 1:
129 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
130 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
131 break;
132
133 case 2:
134 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
135 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
136 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
137 break;
138
139 case 3:
140 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
141 break;
142 }
143
144 /*Set HW definition to determine if it supports ASPM. */
145 switch (rtlpci->const_support_pciaspm) {
146 case 0:{
147 /*Not support ASPM. */
148 bool b_support_aspm = false;
149 ppsc->b_support_aspm = b_support_aspm;
150 break;
151 }
152 case 1:{
153 /*Support ASPM. */
154 bool b_support_aspm = true;
155 bool b_support_backdoor = true;
156 ppsc->b_support_aspm = b_support_aspm;
157
158 /*if(priv->oem_id == RT_CID_TOSHIBA &&
159 !priv->ndis_adapter.amd_l1_patch)
160 b_support_backdoor = false; */
161
162 ppsc->b_support_backdoor = b_support_backdoor;
163
164 break;
165 }
166 case 2:
167 /*ASPM value set by chipset. */
168 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
169 bool b_support_aspm = true;
170 ppsc->b_support_aspm = b_support_aspm;
171 }
172 break;
173 default:
174 RT_TRACE(COMP_ERR, DBG_EMERG,
175 ("switch case not process \n"));
176 break;
177 }
178
179 /* toshiba aspm issue, toshiba will set aspm selfly
180 * so we should not set aspm in driver */
181 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
182 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
183 init_aspm == 0x43)
184 ppsc->b_support_aspm = false;
185}
186
187static bool _rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw *hw,
188 u8 value)
189{
190 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192 bool bresult = false;
193
194 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
195 value |= 0x40;
196
197 pci_write_config_byte(rtlpci->pdev, 0x80, value);
198
199 return bresult;
200}
201
202/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
203static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
204{
205 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
206 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
207 bool bresult = false;
208
209 pci_write_config_byte(rtlpci->pdev, 0x81, value);
210 bresult = true;
211
212 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
213 udelay(100);
214
215 return bresult;
216}
217
218/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
219static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
220{
221 struct rtl_priv *rtlpriv = rtl_priv(hw);
222 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
223 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
224 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
225 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
226 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
227 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
228 /*Retrieve original configuration settings. */
229 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
230 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
231 pcibridge_linkctrlreg;
232 u16 aspmlevel = 0;
233
234 if (!ppsc->b_support_aspm)
235 return;
236
237 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
238 RT_TRACE(COMP_POWER, DBG_TRACE,
239 ("PCI(Bridge) UNKNOWN.\n"));
240
241 return;
242 }
243
244 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
245 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
246 _rtl_pci_switch_clk_req(hw, 0x0);
247 }
248
249 if (1) {
250 /*for promising device will in L0 state after an I/O. */
251 u8 tmp_u1b;
252 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
253 }
254
255 /*Set corresponding value. */
256 aspmlevel |= BIT(0) | BIT(1);
257 linkctrl_reg &= ~aspmlevel;
258 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
259
260 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
261 udelay(50);
262
263 /*4 Disable Pci Bridge ASPM */
264 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
265 pcicfg_addrport + (num4bytes << 2));
266 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
267
268 udelay(50);
269
270}
271
272/*
273 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
274 *power saving We should follow the sequence to enable
275 *RTL8192SE first then enable Pci Bridge ASPM
276 *or the system will show bluescreen.
277 */
278static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
279{
280 struct rtl_priv *rtlpriv = rtl_priv(hw);
281 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
282 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
283 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
284 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
285 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
286 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
287 u16 aspmlevel;
288 u8 u_pcibridge_aspmsetting;
289 u8 u_device_aspmsetting;
290
291 if (!ppsc->b_support_aspm)
292 return;
293
294 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
295 RT_TRACE(COMP_POWER, DBG_TRACE,
296 ("PCI(Bridge) UNKNOWN.\n"));
297 return;
298 }
299
300 /*4 Enable Pci Bridge ASPM */
301 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
302 pcicfg_addrport + (num4bytes << 2));
303
304 u_pcibridge_aspmsetting =
305 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
306 rtlpci->const_hostpci_aspm_setting;
307
308 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
309 u_pcibridge_aspmsetting &= ~BIT(0);
310
311 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
312
313 RT_TRACE(COMP_INIT, DBG_LOUD,
314 ("PlatformEnableASPM(): Write reg[%x] = %x\n",
315 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
316 u_pcibridge_aspmsetting));
317
318 udelay(50);
319
320 /*Get ASPM level (with/without Clock Req) */
321 aspmlevel = rtlpci->const_devicepci_aspm_setting;
322 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
323
324 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
325 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
326
327 u_device_aspmsetting |= aspmlevel;
328
329 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
330
331 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
332 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
333 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
334 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
335 }
336 udelay(100);
337}
338
339static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
340{
341 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
342 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
343
344 bool status = false;
345 u8 offset_e0;
346 unsigned offset_e4;
347
348 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
349 pcicfg_addrport + 0xE0);
350 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
351
352 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
353 pcicfg_addrport + 0xE0);
354 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
355
356 if (offset_e0 == 0xA0) {
357 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
358 pcicfg_addrport + 0xE4);
359 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
360 if (offset_e4 & BIT(23))
361 status = true;
362 }
363
364 return status;
365}
366
367/*<delete in kernel start>*/
368#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35))
369static u8 _rtl_pci_get_pciehdr_offset(struct ieee80211_hw *hw)
370{
371 u8 capability_offset;
372 u8 num4bytes = 0x34/4;
373 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
374 u32 pcicfg_addr_port = (pcipriv->ndis_adapter.pcibridge_busnum << 16)|
375 (pcipriv->ndis_adapter.pcibridge_devnum << 11)|
376 (pcipriv->ndis_adapter.pcibridge_funcnum << 8)|
377 (1 << 31);
378
379 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS , pcicfg_addr_port
380 + (num4bytes << 2));
381 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &capability_offset);
382 while (capability_offset != 0) {
383 struct rtl_pci_capabilities_header capability_hdr;
384
385 num4bytes = capability_offset / 4;
386 /* Read the header of the capability at this offset.
387 * If the retrieved capability is not the power management
388 * capability that we are looking for, follow the link to
389 * the next capability and continue looping.
390 */
391 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS ,
392 pcicfg_addr_port +
393 (num4bytes << 2));
394 rtl_pci_raw_read_port_ushort(PCI_CONF_DATA,
395 (u16*)&capability_hdr);
396 /* Found the PCI express capability. */
397 if (capability_hdr.capability_id ==
398 PCI_CAPABILITY_ID_PCI_EXPRESS)
399 break;
400 else
401 capability_offset = capability_hdr.next;
402 }
403 return capability_offset;
404}
405#endif
406/*<delete in kernel end>*/
407
408bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
409 struct rtl_priv **buddy_priv)
410{
411 struct rtl_priv *rtlpriv = rtl_priv(hw);
412 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
413 bool b_find_buddy_priv = false;
414 struct rtl_priv *temp_priv = NULL;
415 struct rtl_pci_priv *temp_pcipriv = NULL;
416
417 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
418 list_for_each_entry(temp_priv, &rtlpriv->glb_var->glb_priv_list,
419 list) {
420 if (temp_priv) {
421 temp_pcipriv =
422 (struct rtl_pci_priv *)temp_priv->priv;
423 RT_TRACE(COMP_INIT, DBG_LOUD,
424 (("pcipriv->ndis_adapter.funcnumber %x \n"),
425 pcipriv->ndis_adapter.funcnumber));
426 RT_TRACE(COMP_INIT, DBG_LOUD,
427 (("temp_pcipriv->ndis_adapter.funcnumber %x \n"),
428 temp_pcipriv->ndis_adapter.funcnumber));
429
430 if ((pcipriv->ndis_adapter.busnumber ==
431 temp_pcipriv->ndis_adapter.busnumber) &&
432 (pcipriv->ndis_adapter.devnumber ==
433 temp_pcipriv->ndis_adapter.devnumber) &&
434 (pcipriv->ndis_adapter.funcnumber !=
435 temp_pcipriv->ndis_adapter.funcnumber)) {
436 b_find_buddy_priv = true;
437 break;
438 }
439 }
440 }
441 }
442
443 RT_TRACE(COMP_INIT, DBG_LOUD,
444 (("b_find_buddy_priv %d \n"), b_find_buddy_priv));
445
446 if (b_find_buddy_priv)
447 *buddy_priv = temp_priv;
448
449 return b_find_buddy_priv;
450}
451
452void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
453{
454 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
455 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
456 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
457 u8 linkctrl_reg;
458 u8 num4bbytes;
459
460 num4bbytes = (capabilityoffset + 0x10) / 4;
461
462 /*Read Link Control Register */
463 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
464 pcicfg_addrport + (num4bbytes << 2));
465 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
466
467 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
468}
469
470static void rtl_pci_parse_configuration(struct pci_dev *pdev,
471 struct ieee80211_hw *hw)
472{
473 struct rtl_priv *rtlpriv = rtl_priv(hw);
474 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
475
476 u8 tmp;
477 int pos;
478 u8 linkctrl_reg;
479
480 /*Link Control Register */
481 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
482 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
483 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
484
485 RT_TRACE(COMP_INIT, DBG_TRACE,
486 ("Link Control Register =%x\n",
487 pcipriv->ndis_adapter.linkctrl_reg));
488
489 pci_read_config_byte(pdev, 0x98, &tmp);
490 tmp |= BIT(4);
491 pci_write_config_byte(pdev, 0x98, tmp);
492
493 tmp = 0x17;
494 pci_write_config_byte(pdev, 0x70f, tmp);
495}
496
497static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
498{
499 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
500
501 _rtl_pci_update_default_setting(hw);
502
503 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
504 /*Always enable ASPM & Clock Req. */
505 rtl_pci_enable_aspm(hw);
506 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
507 }
508
509}
510
511static void _rtl_pci_io_handler_init(struct device *dev,
512 struct ieee80211_hw *hw)
513{
514 struct rtl_priv *rtlpriv = rtl_priv(hw);
515
516 rtlpriv->io.dev = dev;
517
518 rtlpriv->io.write8_async = pci_write8_async;
519 rtlpriv->io.write16_async = pci_write16_async;
520 rtlpriv->io.write32_async = pci_write32_async;
521
522 rtlpriv->io.read8_sync = pci_read8_sync;
523 rtlpriv->io.read16_sync = pci_read16_sync;
524 rtlpriv->io.read32_sync = pci_read32_sync;
525
526}
527
528static bool _rtl_pci_update_earlymode_info(struct ieee80211_hw *hw,
529 struct sk_buff *skb,
530 struct rtl_tcb_desc *tcb_desc,
531 u8 tid)
532{
533 struct rtl_priv *rtlpriv = rtl_priv(hw);
534 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
535 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
536 u8 additionlen = FCS_LEN;
537 struct sk_buff *next_skb;
538
539 /* here open is 4, wep/tkip is 8, aes is 12*/
540 if (info->control.hw_key)
541 additionlen += info->control.hw_key->icv_len;
542
543 /* The most skb num is 6 */
544 tcb_desc->empkt_num = 0;
545 spin_lock_bh(&rtlpriv->locks.waitq_lock);
546 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
547 struct ieee80211_tx_info *next_info =
548 IEEE80211_SKB_CB(next_skb);
549 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
550 tcb_desc->empkt_len[tcb_desc->empkt_num] =
551 next_skb->len + additionlen;
552 tcb_desc->empkt_num++;
553 } else {
554 break;
555 }
556
557 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
558 next_skb))
559 break;
560
561 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
562 break;
563 }
564 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
565 return true;
566}
567
568/* just for early mode now */
569static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
570{
571 struct rtl_priv *rtlpriv = rtl_priv(hw);
572 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
573 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
574 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
575 struct sk_buff *skb = NULL;
576 struct ieee80211_tx_info *info = NULL;
577 int tid; /* should be int */
578
579 if (!rtlpriv->rtlhal.b_earlymode_enable)
580 return;
581 if (rtlpriv->dm.supp_phymode_switch &&
582 (rtlpriv->easy_concurrent_ctl.bswitch_in_process ||
583 (rtlpriv->buddy_priv &&
584 rtlpriv->buddy_priv->easy_concurrent_ctl.bswitch_in_process)))
585 return;
586 /* we juse use em for BE/BK/VI/VO */
587 for (tid = 7; tid >= 0; tid--) {
588 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
589 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
590 while (!mac->act_scanning &&
591 rtlpriv->psc.rfpwr_state == ERFON) {
592 struct rtl_tcb_desc tcb_desc;
593 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
594
595 spin_lock_bh(&rtlpriv->locks.waitq_lock);
596 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
597 (ring->entries - skb_queue_len(&ring->queue) >
598 rtlhal->max_earlymode_num)) {
599 skb = skb_dequeue(&mac->skb_waitq[tid]);
600 } else {
601 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
602 break;
603 }
604 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
605
606 /* Some macaddr can't do early mode. like
607 * multicast/broadcast/no_qos data */
608 info = IEEE80211_SKB_CB(skb);
609 if (info->flags & IEEE80211_TX_CTL_AMPDU)
610 _rtl_pci_update_earlymode_info(hw, skb,
611 &tcb_desc, tid);
612
613/*<delete in kernel start>*/
614#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
615 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
616#else
617/*<delete in kernel end>*/
618 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
619#endif
620/*<delete in kernel end>*/
621 }
622 }
623}
624
625static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
626{
627 struct rtl_priv *rtlpriv = rtl_priv(hw);
628 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
629 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
630
631 while (skb_queue_len(&ring->queue)) {
632 struct sk_buff *skb;
633 struct ieee80211_tx_info *info;
634 u16 fc;
635 u8 tid;
636 u8 *entry;
637
638
639 if (rtlpriv->use_new_trx_flow)
640 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
641 else
642 entry = (u8 *)(&ring->desc[ring->idx]);
643
644 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
645 return;
646
647 ring->idx = (ring->idx + 1) % ring->entries;
648
649 skb = __skb_dequeue(&ring->queue);
650
651 pci_unmap_single(rtlpci->pdev,
652 le32_to_cpu(rtlpriv->cfg->ops->
653 get_desc((u8 *) entry, true,
654 HW_DESC_TXBUFF_ADDR)),
655 skb->len, PCI_DMA_TODEVICE);
656
657 /* remove early mode header */
658 if(rtlpriv->rtlhal.b_earlymode_enable)
659 skb_pull(skb, EM_HDR_LEN);
660
661 RT_TRACE((COMP_INTR | COMP_SEND), DBG_TRACE,
662 ("new ring->idx:%d, "
663 "free: skb_queue_len:%d, free: seq:%d\n",
664 ring->idx,
665 skb_queue_len(&ring->queue),
666 *(u16 *) (skb->data + 22)));
667
668 if(prio == TXCMD_QUEUE) {
669 dev_kfree_skb(skb);
670 goto tx_status_ok;
671
672 }
673
674 /* for sw LPS, just after NULL skb send out, we can
675 * sure AP kown we are sleeped, our we should not let
676 * rf to sleep*/
677 fc = rtl_get_fc(skb);
678 if (ieee80211_is_nullfunc(fc)) {
679 if(ieee80211_has_pm(fc)) {
680 rtlpriv->mac80211.offchan_deley = true;
681 rtlpriv->psc.state_inap = 1;
682 } else {
683 rtlpriv->psc.state_inap = 0;
684 }
685 }
686 if (ieee80211_is_action(fc)) {
687 struct ieee80211_mgmt_compat *action_frame =
688 (struct ieee80211_mgmt_compat *)skb->data;
689 if (action_frame->u.action.u.ht_smps.action ==
690 WLAN_HT_ACTION_SMPS) {
691 dev_kfree_skb(skb);
692 goto tx_status_ok;
693 }
694 }
695
696 /* update tid tx pkt num */
697 tid = rtl_get_tid(skb);
698 if (tid <= 7)
699 rtlpriv->link_info.tidtx_inperiod[tid]++;
700
701 info = IEEE80211_SKB_CB(skb);
702 ieee80211_tx_info_clear_status(info);
703
704 info->flags |= IEEE80211_TX_STAT_ACK;
705 /*info->status.rates[0].count = 1; */
706
707 ieee80211_tx_status_irqsafe(hw, skb);
708
709 if ((ring->entries - skb_queue_len(&ring->queue))
710 == 2) {
711
712 RT_TRACE(COMP_ERR, DBG_LOUD,
713 ("more desc left, wake"
714 "skb_queue@%d,ring->idx = %d,"
715 "skb_queue_len = 0x%d\n",
716 prio, ring->idx,
717 skb_queue_len(&ring->queue)));
718
719 ieee80211_wake_queue(hw,
720 skb_get_queue_mapping
721 (skb));
722 }
723tx_status_ok:
724 skb = NULL;
725 }
726
727 if (((rtlpriv->link_info.num_rx_inperiod +
728 rtlpriv->link_info.num_tx_inperiod) > 8) ||
729 (rtlpriv->link_info.num_rx_inperiod > 2)) {
730 rtl_lps_leave(hw);
731 }
732}
733
734static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
735 u8 *entry, int rxring_idx, int desc_idx)
736{
737 struct rtl_priv *rtlpriv = rtl_priv(hw);
738 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
739 u32 bufferaddress;
740 u8 tmp_one = 1;
741 struct sk_buff *skb;
742
743 skb = dev_alloc_skb(rtlpci->rxbuffersize);
744 if (!skb)
745 return 0;
746 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
747
748 /* just set skb->cb to mapping addr
749 * for pci_unmap_single use */
750 *((dma_addr_t *) skb->cb) = pci_map_single(rtlpci->pdev,
751 skb_tail_pointer(skb), rtlpci->rxbuffersize,
752 PCI_DMA_FROMDEVICE);
753 bufferaddress = cpu_to_le32(*((dma_addr_t *) skb->cb));
754 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
755 return 0;
756 if (rtlpriv->use_new_trx_flow) {
757 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry, false,
758 HW_DESC_RX_PREPARE,
759 (u8 *) & bufferaddress);
760 } else {
761 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry, false,
762 HW_DESC_RXBUFF_ADDR,
763 (u8 *) & bufferaddress);
764 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry, false,
765 HW_DESC_RXPKT_LEN,
766 (u8 *) & rtlpci->rxbuffersize);
767 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry, false,
768 HW_DESC_RXOWN,
769 (u8 *) & tmp_one);
770 }
771
772 return 1;
773}
774
775/* inorder to receive 8K AMSDU we have set skb to
776 * 9100bytes in init rx ring, but if this packet is
777 * not a AMSDU, this so big packet will be sent to
778 * TCP/IP directly, this cause big packet ping fail
779 * like: "ping -s 65507", so here we will realloc skb
780 * based on the true size of packet, I think mac80211
781 * do it will be better, but now mac80211 haven't */
782
783/* but some platform will fail when alloc skb sometimes.
784 * in this condition, we will send the old skb to
785 * mac80211 directly, this will not cause any other
786 * issues, but only be losted by TCP/IP */
787static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
788 struct sk_buff *skb, struct ieee80211_rx_status rx_status)
789{
790 if (unlikely(!rtl_action_proc(hw, skb, false))) {
791 dev_kfree_skb_any(skb);
792 } else {
793 struct sk_buff *uskb = NULL;
794 u8 *pdata;
795
796 uskb = dev_alloc_skb(skb->len + 128);
797 if (likely(uskb)) {
798 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
799 sizeof(rx_status));
800 pdata = (u8 *)skb_put(uskb, skb->len);
801 memcpy(pdata, skb->data, skb->len);
802 dev_kfree_skb_any(skb);
803
804 ieee80211_rx_irqsafe(hw, uskb);
805 } else {
806 ieee80211_rx_irqsafe(hw, skb);
807 }
808 }
809}
810
811/*hsisr interrupt handler*/
812static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
813{
814 struct rtl_priv *rtlpriv = rtl_priv(hw);
815 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
816
817 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
818 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
819 rtlpci->sys_irq_mask);
820
821
822}
823static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
824{
825 struct rtl_priv *rtlpriv = rtl_priv(hw);
826 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
827 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
828
829 struct ieee80211_rx_status rx_status = { 0 };
830 unsigned int count = rtlpci->rxringcount;
831 bool unicast = false;
832 u8 hw_queue = 0;
833 unsigned int rx_remained_cnt;
834 u8 own;
835 u8 tmp_one;
836
837 struct rtl_stats status = {
838 .signal = 0,
839 .noise = -98,
840 .rate = 0,
841 };
842
843 /*RX NORMAL PKT */
844 while (count--) {
845 struct ieee80211_hdr *hdr;
846 u16 fc;
847 u16 len;
848 /*rx buffer descriptor */
849 struct rtl_rx_buffer_desc *buffer_desc = NULL;
850 /*if use new trx flow, it means wifi info */
851 struct rtl_rx_desc *pdesc = NULL;
852 /*rx pkt */
853 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
854 rtlpci->rx_ring[rxring_idx].idx];
855
856 if (rtlpriv->use_new_trx_flow) {
857 rx_remained_cnt =
858 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
859 hw_queue);
860 if (rx_remained_cnt < 1)
861 return;
862
863 } else { /* rx descriptor */
864 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
865 rtlpci->rx_ring[rxring_idx].idx];
866
867 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
868 false,
869 HW_DESC_OWN);
870 if (own) /* wait data to be filled by hardware */
871 return;
872 }
873
874 /* Get here means: data is filled already*/
875 /* AAAAAAttention !!!
876 * We can NOT access 'skb' before 'pci_unmap_single' */
877 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *) skb->cb),
878 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
879
880 if (rtlpriv->use_new_trx_flow) {
881 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
882 rtlpci->rx_ring[rxring_idx].idx];
883 /*means rx wifi info*/
884 pdesc = (struct rtl_rx_desc *)skb->data;
885 }
886
887 rtlpriv->cfg->ops->query_rx_desc(hw, &status,
888 &rx_status, (u8 *) pdesc, skb);
889
890 if (rtlpriv->use_new_trx_flow)
891 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
892 (u8 *)buffer_desc,
893 hw_queue);
894
895
896 len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false,
897 HW_DESC_RXPKT_LEN);
898
899 if (skb->end - skb->tail > len) {
900 skb_put(skb, len);
901 if (rtlpriv->use_new_trx_flow)
902 skb_reserve(skb, status.rx_drvinfo_size +
903 status.rx_bufshift + 24);
904 else
905 skb_reserve(skb, status.rx_drvinfo_size +
906 status.rx_bufshift);
907
908 } else {
909 printk("skb->end - skb->tail = %d, len is %d\n",
910 skb->end - skb->tail, len);
911 break;
912 }
913
914 rtlpriv->cfg->ops->rx_command_packet_handler(hw, status, skb);
915
916 /*
917 *NOTICE This can not be use for mac80211,
918 *this is done in mac80211 code,
919 *if you done here sec DHCP will fail
920 *skb_trim(skb, skb->len - 4);
921 */
922
923 hdr = rtl_get_hdr(skb);
924 fc = rtl_get_fc(skb);
925
926 if (!status.b_crc && !status.b_hwerror) {
927 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
928 sizeof(rx_status));
929
930 if (is_broadcast_ether_addr(hdr->addr1)) {
931 ;/*TODO*/
932 } else if (is_multicast_ether_addr(hdr->addr1)) {
933 ;/*TODO*/
934 } else {
935 unicast = true;
936 rtlpriv->stats.rxbytesunicast += skb->len;
937 }
938
939 rtl_is_special_data(hw, skb, false);
940
941 if (ieee80211_is_data(fc)) {
942 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
943
944 if (unicast)
945 rtlpriv->link_info.num_rx_inperiod++;
946 }
947
948 /* static bcn for roaming */
949 rtl_beacon_statistic(hw, skb);
950 rtl_p2p_info(hw, (void*)skb->data, skb->len);
951 /* for sw lps */
952 rtl_swlps_beacon(hw, (void*)skb->data, skb->len);
953 rtl_recognize_peer(hw, (void*)skb->data, skb->len);
954 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
955 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)&&
956 (ieee80211_is_beacon(fc) ||
957 ieee80211_is_probe_resp(fc))) {
958 dev_kfree_skb_any(skb);
959 } else {
960 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
961 }
962 } else {
963 dev_kfree_skb_any(skb);
964 }
965 if (rtlpriv->use_new_trx_flow) {
966 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
967 rtlpci->rx_ring[hw_queue].next_rx_rp %=
968 RTL_PCI_MAX_RX_COUNT;
969
970
971 rx_remained_cnt--;
972 if (1/*rx_remained_cnt == 0*/) {
973 rtl_write_word(rtlpriv, 0x3B4,
974 rtlpci->rx_ring[hw_queue].next_rx_rp);
975 }
976 }
977 if (((rtlpriv->link_info.num_rx_inperiod +
978 rtlpriv->link_info.num_tx_inperiod) > 8) ||
979 (rtlpriv->link_info.num_rx_inperiod > 2)) {
980 rtl_lps_leave(hw);
981 }
982
983 if (rtlpriv->use_new_trx_flow) {
984 _rtl_pci_init_one_rxdesc(hw, (u8 *)buffer_desc,
985 rxring_idx,
986 rtlpci->rx_ring[rxring_idx].idx);
987 } else {
988 _rtl_pci_init_one_rxdesc(hw, (u8 *)pdesc, rxring_idx,
989 rtlpci->rx_ring[rxring_idx].idx);
990
991 if (rtlpci->rx_ring[rxring_idx].idx ==
992 rtlpci->rxringcount - 1)
993 rtlpriv->cfg->ops->set_desc(hw, (u8 *) pdesc,
994 false,
995 HW_DESC_RXERO,
996 (u8 *) & tmp_one);
997 }
998 rtlpci->rx_ring[rxring_idx].idx =
999 (rtlpci->rx_ring[rxring_idx].idx + 1) %
1000 rtlpci->rxringcount;
1001 }
1002}
1003
1004static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
1005{
1006 struct ieee80211_hw *hw = dev_id;
1007 struct rtl_priv *rtlpriv = rtl_priv(hw);
1008 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1009 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1010 unsigned long flags;
1011 u32 inta = 0;
1012 u32 intb = 0;
1013
1014
1015
1016 if (rtlpci->irq_enabled == 0)
1017 return IRQ_HANDLED;
1018
1019 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock,flags);
1020
1021
1022 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMR], 0x0);
1023
1024
1025 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMRE], 0x0);
1026
1027
1028 /*read ISR: 4/8bytes */
1029 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
1030
1031
1032 /*Shared IRQ or HW disappared */
1033 if (!inta || inta == 0xffff)
1034 goto done;
1035 /*<1> beacon related */
1036 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
1037 RT_TRACE(COMP_INTR, DBG_TRACE, ("beacon ok interrupt!\n"));
1038 }
1039
1040 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
1041 RT_TRACE(COMP_INTR, DBG_TRACE, ("beacon err interrupt!\n"));
1042 }
1043
1044 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
1045 RT_TRACE(COMP_INTR, DBG_TRACE, ("beacon interrupt!\n"));
1046 }
1047
1048 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
1049 RT_TRACE(COMP_INTR, DBG_TRACE,
1050 ("prepare beacon for interrupt!\n"));
1051 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
1052 }
1053
1054
1055 /*<2> tx related */
1056 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
1057 RT_TRACE(COMP_ERR, DBG_TRACE, ("IMR_TXFOVW!\n"));
1058
1059 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
1060 RT_TRACE(COMP_INTR, DBG_TRACE, ("Manage ok interrupt!\n"));
1061 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
1062 }
1063
1064 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
1065 RT_TRACE(COMP_INTR, DBG_TRACE, ("HIGH_QUEUE ok interrupt!\n"));
1066 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
1067 }
1068
1069 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
1070 rtlpriv->link_info.num_tx_inperiod++;
1071
1072 RT_TRACE(COMP_INTR, DBG_TRACE, ("BK Tx OK interrupt!\n"));
1073 _rtl_pci_tx_isr(hw, BK_QUEUE);
1074 }
1075
1076 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
1077 rtlpriv->link_info.num_tx_inperiod++;
1078
1079 RT_TRACE(COMP_INTR, DBG_TRACE, ("BE TX OK interrupt!\n"));
1080 _rtl_pci_tx_isr(hw, BE_QUEUE);
1081 }
1082
1083 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
1084 rtlpriv->link_info.num_tx_inperiod++;
1085
1086 RT_TRACE(COMP_INTR, DBG_TRACE, ("VI TX OK interrupt!\n"));
1087 _rtl_pci_tx_isr(hw, VI_QUEUE);
1088 }
1089
1090 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1091 rtlpriv->link_info.num_tx_inperiod++;
1092
1093 RT_TRACE(COMP_INTR, DBG_TRACE, ("Vo TX OK interrupt!\n"));
1094 _rtl_pci_tx_isr(hw, VO_QUEUE);
1095 }
1096
1097 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1098 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1099 rtlpriv->link_info.num_tx_inperiod++;
1100
1101 RT_TRACE(COMP_INTR, DBG_TRACE,
1102 ("CMD TX OK interrupt!\n"));
1103 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1104 }
1105 }
1106
1107 /*<3> rx related */
1108 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1109 RT_TRACE(COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
1110
1111 _rtl_pci_rx_interrupt(hw);
1112
1113 }
1114
1115 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1116 RT_TRACE(COMP_ERR, DBG_WARNING,
1117 ("rx descriptor unavailable!\n"));
1118 rtl_write_byte(rtlpriv, 0xb4, BIT(1) );
1119 _rtl_pci_rx_interrupt(hw);
1120 }
1121
1122 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1123 RT_TRACE(COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
1124 _rtl_pci_rx_interrupt(hw);
1125 }
1126
1127 /*<4> fw related*/
1128 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1129 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1130 RT_TRACE(COMP_INTR, DBG_TRACE,
1131 ("firmware interrupt!\n"));
1132 queue_delayed_work(rtlpriv->works.rtl_wq,
1133 &rtlpriv->works.fwevt_wq, 0);
1134 }
1135 }
1136
1137 /*<5> hsisr related*/
1138 /* Only 8188EE & 8723BE Supported.
1139 * If Other ICs Come in, System will corrupt,
1140 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1141 * are not initialized*/
1142 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1143 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1144 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1145 RT_TRACE(COMP_INTR, DBG_TRACE,
1146 ("hsisr interrupt!\n"));
1147 _rtl_pci_hs_interrupt(hw);
1148 }
1149 }
1150
1151
1152 if(rtlpriv->rtlhal.b_earlymode_enable)
1153 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1154
1155 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMR],
1156 rtlpci->irq_mask[0]);
1157 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[MAC_HIMRE],
1158 rtlpci->irq_mask[1]);
1159 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1160
1161 return IRQ_HANDLED;
1162
1163done:
1164 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1165 return IRQ_HANDLED;
1166}
1167
1168static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1169{
1170 _rtl_pci_tx_chk_waitq(hw);
1171}
1172
1173static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1174{
1175 struct rtl_priv *rtlpriv = rtl_priv(hw);
1176 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1177 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1178 struct rtl8192_tx_ring *ring = NULL;
1179 struct ieee80211_hdr *hdr = NULL;
1180 struct ieee80211_tx_info *info = NULL;
1181 struct sk_buff *pskb = NULL;
1182 struct rtl_tx_desc *pdesc = NULL;
1183 struct rtl_tcb_desc tcb_desc;
1184 /*This is for new trx flow*/
1185 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1186 u8 temp_one = 1;
1187
1188 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1189 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1190 pskb = __skb_dequeue(&ring->queue);
1191 if (pskb)
1192 kfree_skb(pskb);
1193
1194 /*NB: the beacon data buffer must be 32-bit aligned. */
1195 pskb = ieee80211_beacon_get(hw, mac->vif);
1196 if (pskb == NULL)
1197 return;
1198 hdr = rtl_get_hdr(pskb);
1199 info = IEEE80211_SKB_CB(pskb);
1200 pdesc = &ring->desc[0];
1201 if (rtlpriv->use_new_trx_flow)
1202 pbuffer_desc = &ring->buffer_desc[0];
1203
1204/*<delete in kernel start>*/
1205#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1206 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1207 (u8 *)pbuffer_desc, info, pskb,
1208 BEACON_QUEUE, &tcb_desc);
1209#else
1210/*<delete in kernel end>*/
1211 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1212 (u8 *)pbuffer_desc, info, NULL, pskb,
1213 BEACON_QUEUE, &tcb_desc);
1214/*<delete in kernel start>*/
1215#endif
1216/*<delete in kernel end>*/
1217
1218 __skb_queue_tail(&ring->queue, pskb);
1219
1220 rtlpriv->cfg->ops->set_desc(hw, (u8 *) pdesc, true, HW_DESC_OWN,
1221 (u8 *) & temp_one);
1222
1223 return;
1224}
1225
1226static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1227{
1228 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1229 struct rtl_priv *rtlpriv = rtl_priv(hw);
1230 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1231 u8 i;
1232 u16 desc_num;
1233
1234 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1235 desc_num = TX_DESC_NUM_92E;
1236 else
1237 desc_num = RT_TXDESC_NUM;
1238
1239 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1240 rtlpci->txringcount[i] = desc_num;
1241 }
1242 /*
1243 *we just alloc 2 desc for beacon queue,
1244 *because we just need first desc in hw beacon.
1245 */
1246 rtlpci->txringcount[BEACON_QUEUE] = 2;
1247
1248 /*
1249 *BE queue need more descriptor for performance
1250 *consideration or, No more tx desc will happen,
1251 *and may cause mac80211 mem leakage.
1252 */
1253 if (rtl_priv(hw)->use_new_trx_flow == false)
1254 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1255
1256 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1257 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1258}
1259
1260static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1261 struct pci_dev *pdev)
1262{
1263 struct rtl_priv *rtlpriv = rtl_priv(hw);
1264 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1265 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1266 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1267
1268 rtlpriv->rtlhal.up_first_time = true;
1269 rtlpriv->rtlhal.being_init_adapter = false;
1270
1271 rtlhal->hw = hw;
1272 rtlpci->pdev = pdev;
1273
1274 /*Tx/Rx related var */
1275 _rtl_pci_init_trx_var(hw);
1276
1277 /*IBSS*/ mac->beacon_interval = 100;
1278
1279 /*AMPDU*/
1280 mac->min_space_cfg = 0;
1281 mac->max_mss_density = 0;
1282 /*set sane AMPDU defaults */
1283 mac->current_ampdu_density = 7;
1284 mac->current_ampdu_factor = 3;
1285
1286 /*QOS*/
1287 rtlpci->acm_method = eAcmWay2_SW;
1288
1289 /*task */
1290 tasklet_init(&rtlpriv->works.irq_tasklet,
1291 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1292 (unsigned long)hw);
1293 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1294 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1295 (unsigned long)hw);
1296}
1297
1298static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1299 unsigned int prio, unsigned int entries)
1300{
1301 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1302 struct rtl_priv *rtlpriv = rtl_priv(hw);
1303 struct rtl_tx_buffer_desc *buffer_desc;
1304 struct rtl_tx_desc *desc;
1305 dma_addr_t buffer_desc_dma, desc_dma;
1306 u32 nextdescaddress;
1307 int i;
1308
1309 /* alloc tx buffer desc for new trx flow*/
1310 if (rtlpriv->use_new_trx_flow) {
1311 buffer_desc = pci_alloc_consistent(rtlpci->pdev,
1312 sizeof(*buffer_desc) * entries,
1313 &buffer_desc_dma);
1314
1315 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1316 RT_TRACE(COMP_ERR, DBG_EMERG,
1317 ("Cannot allocate TX ring (prio = %d)\n",
1318 prio));
1319 return -ENOMEM;
1320 }
1321
1322 memset(buffer_desc, 0, sizeof(*buffer_desc) * entries);
1323 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1324 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1325
1326 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1327 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1328 rtlpci->tx_ring[prio].avl_desc = entries;
1329
1330 }
1331
1332 /* alloc dma for this ring */
1333 desc = pci_alloc_consistent(rtlpci->pdev,
1334 sizeof(*desc) * entries, &desc_dma);
1335
1336 if (!desc || (unsigned long)desc & 0xFF) {
1337 RT_TRACE(COMP_ERR, DBG_EMERG,
1338 ("Cannot allocate TX ring (prio = %d)\n", prio));
1339 return -ENOMEM;
1340 }
1341
1342 memset(desc, 0, sizeof(*desc) * entries);
1343 rtlpci->tx_ring[prio].desc = desc;
1344 rtlpci->tx_ring[prio].dma = desc_dma;
1345
1346 rtlpci->tx_ring[prio].idx = 0;
1347 rtlpci->tx_ring[prio].entries = entries;
1348 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1349 RT_TRACE(COMP_INIT, DBG_LOUD,
1350 ("queue:%d, ring_addr:%p\n", prio, desc));
1351
1352 /* init every desc in this ring */
1353 if (rtlpriv->use_new_trx_flow == false) {
1354 for (i = 0; i < entries; i++) {
1355 nextdescaddress = cpu_to_le32((u32) desc_dma +
1356 ((i + 1) % entries) *
1357 sizeof(*desc));
1358
1359 rtlpriv->cfg->ops->set_desc(hw, (u8 *) & (desc[i]),
1360 true,
1361 HW_DESC_TX_NEXTDESC_ADDR,
1362 (u8 *) & nextdescaddress);
1363 }
1364 }
1365 return 0;
1366}
1367
1368static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1369{
1370 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1371 struct rtl_priv *rtlpriv = rtl_priv(hw);
1372
1373 int i;
1374
1375 if (rtlpriv->use_new_trx_flow) {
1376 struct rtl_rx_buffer_desc *entry = NULL;
1377 /* alloc dma for this ring */
1378 rtlpci->rx_ring[rxring_idx].buffer_desc =
1379 pci_alloc_consistent(rtlpci->pdev,
1380 sizeof(*rtlpci->rx_ring[rxring_idx].
1381 buffer_desc) *
1382 rtlpci->rxringcount,
1383 &rtlpci->rx_ring[rxring_idx].dma);
1384 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1385 (unsigned long)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1386 RT_TRACE(COMP_ERR, DBG_EMERG, ("Cannot allocate RX ring\n"));
1387 return -ENOMEM;
1388 }
1389
1390 memset(rtlpci->rx_ring[rxring_idx].buffer_desc, 0,
1391 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1392 rtlpci->rxringcount);
1393
1394 /* init every desc in this ring */
1395 rtlpci->rx_ring[rxring_idx].idx = 0;
1396 for (i = 0; i < rtlpci->rxringcount; i++) {
1397 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1398 if (!_rtl_pci_init_one_rxdesc(hw, (u8 *)entry,
1399 rxring_idx, i))
1400 return -ENOMEM;
1401 }
1402 } else {
1403 struct rtl_rx_desc *entry = NULL;
1404 u8 tmp_one = 1;
1405 /* alloc dma for this ring */
1406 rtlpci->rx_ring[rxring_idx].desc =
1407 pci_alloc_consistent(rtlpci->pdev,
1408 sizeof(*rtlpci->rx_ring[rxring_idx].
1409 desc) * rtlpci->rxringcount,
1410 &rtlpci->rx_ring[rxring_idx].dma);
1411 if (!rtlpci->rx_ring[rxring_idx].desc ||
1412 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1413 RT_TRACE(COMP_ERR, DBG_EMERG,
1414 ("Cannot allocate RX ring\n"));
1415 return -ENOMEM;
1416 }
1417
1418 memset(rtlpci->rx_ring[rxring_idx].desc, 0,
1419 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1420 rtlpci->rxringcount);
1421
1422 /* init every desc in this ring */
1423 rtlpci->rx_ring[rxring_idx].idx = 0;
1424 for (i = 0; i < rtlpci->rxringcount; i++) {
1425 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1426 if (!_rtl_pci_init_one_rxdesc(hw, (u8 *)entry,
1427 rxring_idx, i))
1428 return -ENOMEM;
1429 }
1430 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry, false,
1431 HW_DESC_RXERO, (u8 *) & tmp_one);
1432 }
1433 return 0;
1434}
1435
1436static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1437 unsigned int prio)
1438{
1439 struct rtl_priv *rtlpriv = rtl_priv(hw);
1440 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1441 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1442
1443 /* free every desc in this ring */
1444 while (skb_queue_len(&ring->queue)) {
1445 u8 *entry;
1446 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1447 if (rtlpriv->use_new_trx_flow)
1448 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1449 else
1450 entry = (u8 *)(&ring->desc[ring->idx]);
1451
1452 pci_unmap_single(rtlpci->pdev,
1453 le32_to_cpu(rtlpriv->cfg->ops->get_desc(
1454 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR)),
1455 skb->len, PCI_DMA_TODEVICE);
1456 kfree_skb(skb);
1457 ring->idx = (ring->idx + 1) % ring->entries;
1458 }
1459
1460 /* free dma of this ring */
1461 pci_free_consistent(rtlpci->pdev,
1462 sizeof(*ring->desc) * ring->entries,
1463 ring->desc, ring->dma);
1464 ring->desc = NULL;
1465 if (rtlpriv->use_new_trx_flow) {
1466 pci_free_consistent(rtlpci->pdev,
1467 sizeof(*ring->buffer_desc) * ring->entries,
1468 ring->buffer_desc, ring->buffer_desc_dma);
1469 ring->buffer_desc = NULL;
1470 }
1471}
1472
1473static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1474{
1475 struct rtl_priv *rtlpriv = rtl_priv(hw);
1476 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1477 int i;
1478
1479 /* free every desc in this ring */
1480 for (i = 0; i < rtlpci->rxringcount; i++) {
1481 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1482 if (!skb)
1483 continue;
1484
1485 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *) skb->cb),
1486 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1487 kfree_skb(skb);
1488 }
1489
1490 /* free dma of this ring */
1491 if (rtlpriv->use_new_trx_flow) {
1492 pci_free_consistent(rtlpci->pdev,
1493 sizeof(*rtlpci->rx_ring[rxring_idx].
1494 buffer_desc) * rtlpci->rxringcount,
1495 rtlpci->rx_ring[rxring_idx].buffer_desc,
1496 rtlpci->rx_ring[rxring_idx].dma);
1497 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1498 } else {
1499 pci_free_consistent(rtlpci->pdev,
1500 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1501 rtlpci->rxringcount,
1502 rtlpci->rx_ring[rxring_idx].desc,
1503 rtlpci->rx_ring[rxring_idx].dma);
1504 rtlpci->rx_ring[rxring_idx].desc = NULL;
1505 }
1506}
1507
1508static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1509{
1510 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1511 int ret;
1512 int i, rxring_idx;
1513
1514 /* rxring_idx 0:RX_MPDU_QUEUE
1515 * rxring_idx 1:RX_CMD_QUEUE */
1516 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1517 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1518 if (ret)
1519 return ret;
1520 }
1521
1522 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1523 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1524 if (ret)
1525 goto err_free_rings;
1526 }
1527
1528 return 0;
1529
1530err_free_rings:
1531 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1532 _rtl_pci_free_rx_ring(hw, rxring_idx);
1533
1534 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1535 if (rtlpci->tx_ring[i].desc ||
1536 rtlpci->tx_ring[i].buffer_desc)
1537 _rtl_pci_free_tx_ring(hw, i);
1538
1539 return 1;
1540}
1541
1542static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1543{
1544 u32 i, rxring_idx;
1545
1546 /*free rx rings */
1547 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1548 _rtl_pci_free_rx_ring(hw, rxring_idx);
1549
1550 /*free tx rings */
1551 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1552 _rtl_pci_free_tx_ring(hw, i);
1553
1554 return 0;
1555}
1556
1557int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1558{
1559 struct rtl_priv *rtlpriv = rtl_priv(hw);
1560 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1561 int i, rxring_idx;
1562 unsigned long flags;
1563 u8 tmp_one = 1;
1564 /* rxring_idx 0:RX_MPDU_QUEUE */
1565 /* rxring_idx 1:RX_CMD_QUEUE */
1566 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1567 /* force the rx_ring[RX_MPDU_QUEUE/
1568 * RX_CMD_QUEUE].idx to the first one */
1569 /*new trx flow, do nothing*/
1570 if ((rtlpriv->use_new_trx_flow == false) &&
1571 rtlpci->rx_ring[rxring_idx].desc) {
1572 struct rtl_rx_desc *entry = NULL;
1573
1574 for (i = 0; i < rtlpci->rxringcount; i++) {
1575 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1576 rtlpriv->cfg->ops->set_desc(hw, (u8 *) entry,
1577 false,
1578 HW_DESC_RXOWN,
1579 (u8 *) & tmp_one);
1580 }
1581 }
1582 rtlpci->rx_ring[rxring_idx].idx = 0; }
1583
1584 /* after reset, release previous pending packet,
1585 * and force the tx idx to the first one */
1586 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1587 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1588 if (rtlpci->tx_ring[i].desc ||
1589 rtlpci->tx_ring[i].buffer_desc) {
1590 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1591
1592 while (skb_queue_len(&ring->queue)) {
1593 u8 *entry;
1594 struct sk_buff *skb =
1595 __skb_dequeue(&ring->queue);
1596 if (rtlpriv->use_new_trx_flow)
1597 entry = (u8 *)(&ring->buffer_desc
1598 [ring->idx]);
1599 else
1600 entry = (u8 *)(&ring->desc[ring->idx]);
1601
1602 pci_unmap_single(rtlpci->pdev,
1603 le32_to_cpu(rtlpriv->cfg->ops->get_desc(
1604 (u8 *)entry, true,
1605 HW_DESC_TXBUFF_ADDR)),
1606 skb->len, PCI_DMA_TODEVICE);
1607 kfree_skb(skb);
1608 ring->idx = (ring->idx + 1) % ring->entries;
1609 }
1610 ring->idx = 0;
1611 }
1612 }
1613
1614 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1615
1616 return 0;
1617}
1618
1619/*<delete in kernel start>*/
1620#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1621static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1622 struct sk_buff *skb)
1623#else
1624/*<delete in kernel end>*/
1625static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1626 struct ieee80211_sta *sta,
1627 struct sk_buff *skb)
1628/*<delete in kernel start>*/
1629#endif
1630/*<delete in kernel end>*/
1631{
1632 struct rtl_priv *rtlpriv = rtl_priv(hw);
1633/*<delete in kernel start>*/
1634#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1635 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1636 struct ieee80211_sta *sta = info->control.sta;
1637#endif
1638/*<delete in kernel end>*/
1639 struct rtl_sta_info *sta_entry = NULL;
1640 u8 tid = rtl_get_tid(skb);
1641 u16 fc = rtl_get_fc(skb);
1642
1643 if(!sta)
1644 return false;
1645 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1646
1647 if (!rtlpriv->rtlhal.b_earlymode_enable)
1648 return false;
1649 if (ieee80211_is_nullfunc(fc))
1650 return false;
1651 if (ieee80211_is_qos_nullfunc(fc))
1652 return false;
1653 if (ieee80211_is_pspoll(fc)) {
1654 return false;
1655 }
1656
1657 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1658 return false;
1659 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1660 return false;
1661 if (tid > 7)
1662 return false;
1663 /* maybe every tid should be checked */
1664 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1665 return false;
1666
1667 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1668 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1669 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1670
1671 return true;
1672}
1673
1674/*<delete in kernel start>*/
1675#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1676int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
1677 struct rtl_tcb_desc *ptcb_desc)
1678#else
1679/*<delete in kernel end>*/
1680static int rtl_pci_tx(struct ieee80211_hw *hw,
1681 struct ieee80211_sta *sta,
1682 struct sk_buff *skb,
1683 struct rtl_tcb_desc *ptcb_desc)
1684/*<delete in kernel start>*/
1685#endif
1686/*<delete in kernel end>*/
1687{
1688 struct rtl_priv *rtlpriv = rtl_priv(hw);
1689 struct rtl_sta_info *sta_entry = NULL;
1690 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1691/*<delete in kernel start>*/
1692#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1693 struct ieee80211_sta *sta = info->control.sta;
1694#endif
1695/*<delete in kernel end>*/
1696 struct rtl8192_tx_ring *ring;
1697 struct rtl_tx_desc *pdesc;
1698 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1699 u16 idx;
1700 u8 own;
1701 u8 temp_one = 1;
1702 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1703 unsigned long flags;
1704 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1705 u16 fc = rtl_get_fc(skb);
1706 u8 *pda_addr = hdr->addr1;
1707 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1708 /*ssn */
1709 u8 tid = 0;
1710 u16 seq_number = 0;
1711
1712
1713 if (ieee80211_is_mgmt(fc))
1714 rtl_tx_mgmt_proc(hw, skb);
1715
1716 if (rtlpriv->psc.sw_ps_enabled) {
1717 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1718 !ieee80211_has_pm(fc))
1719 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1720 }
1721
1722 rtl_action_proc(hw, skb, true);
1723
1724 if (is_multicast_ether_addr(pda_addr))
1725 rtlpriv->stats.txbytesmulticast += skb->len;
1726 else if (is_broadcast_ether_addr(pda_addr))
1727 rtlpriv->stats.txbytesbroadcast += skb->len;
1728 else
1729 rtlpriv->stats.txbytesunicast += skb->len;
1730
1731 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1732 ring = &rtlpci->tx_ring[hw_queue];
1733 if (hw_queue != BEACON_QUEUE) {
1734 if (rtlpriv->use_new_trx_flow)
1735 idx = ring->cur_tx_wp;
1736 else
1737 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1738 ring->entries;
1739 } else {
1740 idx = 0;
1741 }
1742
1743 pdesc = &ring->desc[idx];
1744
1745 if (rtlpriv->use_new_trx_flow) {
1746 ptx_bd_desc = &ring->buffer_desc[idx];
1747 } else {
1748 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1749 true, HW_DESC_OWN);
1750
1751 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1752 RT_TRACE(COMP_ERR, DBG_WARNING,
1753 ("No more TX desc@%d, ring->idx = %d,"
1754 "idx = %d, skb_queue_len = 0x%d\n",
1755 hw_queue, ring->idx, idx,
1756 skb_queue_len(&ring->queue)));
1757
1758 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1759 flags);
1760 return skb->len;
1761 }
1762 }
1763
1764 if (ieee80211_is_data_qos(fc)) {
1765 tid = rtl_get_tid(skb);
1766 if (sta) {
1767 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1768 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1769 IEEE80211_SCTL_SEQ) >> 4;
1770 seq_number += 1;
1771
1772 if (!ieee80211_has_morefrags(hdr->frame_control))
1773 sta_entry->tids[tid].seq_number = seq_number;
1774 }
1775 }
1776
1777 if (ieee80211_is_data(fc))
1778 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1779
1780/*<delete in kernel start>*/
1781#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1782 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1783 (u8 *)ptx_bd_desc, info, skb,
1784 hw_queue, ptcb_desc);
1785#else
1786/*<delete in kernel end>*/
1787 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1788 (u8 *)ptx_bd_desc, info, sta, skb,
1789 hw_queue, ptcb_desc);
1790/*<delete in kernel start>*/
1791#endif
1792/*<delete in kernel end>*/
1793
1794 __skb_queue_tail(&ring->queue, skb);
1795 if (rtlpriv->use_new_trx_flow) {
1796 rtlpriv->cfg->ops->set_desc(hw, (u8 *) pdesc, true,
1797 HW_DESC_OWN, (u8 *) & hw_queue);
1798 } else {
1799 rtlpriv->cfg->ops->set_desc(hw, (u8 *) pdesc, true,
1800 HW_DESC_OWN, (u8 *) & temp_one);
1801 }
1802
1803 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1804 hw_queue != BEACON_QUEUE) {
1805
1806 RT_TRACE(COMP_ERR, DBG_LOUD,
1807 ("less desc left, stop skb_queue@%d, "
1808 "ring->idx = %d,"
1809 "idx = %d, skb_queue_len = 0x%d\n",
1810 hw_queue, ring->idx, idx,
1811 skb_queue_len(&ring->queue)));
1812
1813 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1814 }
1815
1816 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1817
1818 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1819
1820 return 0;
1821}
1822#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
1823static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1824#else
1825static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1826#endif
1827{
1828 struct rtl_priv *rtlpriv = rtl_priv(hw);
1829 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1830 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1831 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1832 u16 i = 0;
1833 int queue_id;
1834 struct rtl8192_tx_ring *ring;
1835
1836 if (mac->skip_scan)
1837 return;
1838
1839 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1840 u32 queue_len;
1841#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
1842 if (((queues >> queue_id) & 0x1) == 0) {
1843 queue_id--;
1844 continue;
1845 }
1846#endif
1847 ring = &pcipriv->dev.tx_ring[queue_id];
1848 queue_len = skb_queue_len(&ring->queue);
1849 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1850 queue_id == TXCMD_QUEUE) {
1851 queue_id--;
1852 continue;
1853 } else {
1854 msleep(5);
1855 i++;
1856 }
1857
1858 /* we just wait 1s for all queues */
1859 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1860 is_hal_stop(rtlhal) || i >= 200)
1861 return;
1862 }
1863}
1864
1865void rtl_pci_deinit(struct ieee80211_hw *hw)
1866{
1867 struct rtl_priv *rtlpriv = rtl_priv(hw);
1868 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1869
1870 _rtl_pci_deinit_trx_ring(hw);
1871
1872 synchronize_irq(rtlpci->pdev->irq);
1873 tasklet_kill(&rtlpriv->works.irq_tasklet);
1874
1875 flush_workqueue(rtlpriv->works.rtl_wq);
1876 destroy_workqueue(rtlpriv->works.rtl_wq);
1877
1878}
1879
1880int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1881{
1882 struct rtl_priv *rtlpriv = rtl_priv(hw);
1883 int err;
1884
1885 _rtl_pci_init_struct(hw, pdev);
1886
1887 err = _rtl_pci_init_trx_ring(hw);
1888 if (err) {
1889 RT_TRACE(COMP_ERR, DBG_EMERG,
1890 ("tx ring initialization failed"));
1891 return err;
1892 }
1893
1894 return 1;
1895}
1896
1897int rtl_pci_start(struct ieee80211_hw *hw)
1898{
1899 struct rtl_priv *rtlpriv = rtl_priv(hw);
1900 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1901 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1902
1903 int err = 0;
1904 RT_TRACE(COMP_INIT, DBG_DMESG, (" rtl_pci_start \n"));
1905 rtl_pci_reset_trx_ring(hw);
1906
1907 rtlpriv->rtlhal.driver_is_goingto_unload = false;
1908 err = rtlpriv->cfg->ops->hw_init(hw);
1909 if (err) {
1910 RT_TRACE(COMP_INIT, DBG_DMESG,
1911 ("Failed to config hardware err %x!\n",err));
1912 return err;
1913 }
1914
1915 rtlpriv->cfg->ops->enable_interrupt(hw);
1916 RT_TRACE(COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1917
1918 rtl_init_rx_config(hw);
1919
1920 /*should after adapter start and interrupt enable. */
1921 set_hal_start(rtlhal);
1922
1923 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1924
1925 rtlpriv->rtlhal.up_first_time = false;
1926
1927 RT_TRACE(COMP_INIT, DBG_DMESG, ("rtl_pci_start OK\n"));
1928 return 0;
1929}
1930
1931void rtl_pci_stop(struct ieee80211_hw *hw)
1932{
1933 struct rtl_priv *rtlpriv = rtl_priv(hw);
1934 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1935 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1936 u8 RFInProgressTimeOut = 0;
1937
1938 /*
1939 *should before disable interrrupt&adapter
1940 *and will do it immediately.
1941 */
1942 set_hal_stop(rtlhal);
1943
1944 rtlpriv->cfg->ops->disable_interrupt(hw);
1945
1946 spin_lock(&rtlpriv->locks.rf_ps_lock);
1947 while (ppsc->rfchange_inprogress) {
1948 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1949 if (RFInProgressTimeOut > 100) {
1950 spin_lock(&rtlpriv->locks.rf_ps_lock);
1951 break;
1952 }
1953 mdelay(1);
1954 RFInProgressTimeOut++;
1955 spin_lock(&rtlpriv->locks.rf_ps_lock);
1956 }
1957 ppsc->rfchange_inprogress = true;
1958 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1959
1960 rtlpriv->rtlhal.driver_is_goingto_unload = true;
1961 rtlpriv->cfg->ops->hw_disable(hw);
1962 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1963
1964 spin_lock(&rtlpriv->locks.rf_ps_lock);
1965 ppsc->rfchange_inprogress = false;
1966 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1967
1968 rtl_pci_enable_aspm(hw);
1969}
1970
1971static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1972 struct ieee80211_hw *hw)
1973{
1974 struct rtl_priv *rtlpriv = rtl_priv(hw);
1975 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1976 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1977 struct pci_dev *bridge_pdev = pdev->bus->self;
1978 u16 venderid;
1979 u16 deviceid;
1980 u8 revisionid;
1981 u16 irqline;
1982 u8 tmp;
1983
1984 venderid = pdev->vendor;
1985 deviceid = pdev->device;
1986 pci_read_config_byte(pdev, 0x8, &revisionid);
1987 pci_read_config_word(pdev, 0x3C, &irqline);
1988
1989 if (deviceid == RTL_PCI_8192_DID ||
1990 deviceid == RTL_PCI_0044_DID ||
1991 deviceid == RTL_PCI_0047_DID ||
1992 deviceid == RTL_PCI_8192SE_DID ||
1993 deviceid == RTL_PCI_8174_DID ||
1994 deviceid == RTL_PCI_8173_DID ||
1995 deviceid == RTL_PCI_8172_DID ||
1996 deviceid == RTL_PCI_8171_DID) {
1997 switch (revisionid) {
1998 case RTL_PCI_REVISION_ID_8192PCIE:
1999 RT_TRACE(COMP_INIT, DBG_DMESG,
2000 ("8192E is found but not supported now-"
2001 "vid/did=%x/%x\n", venderid, deviceid));
2002 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
2003 return false;
2004 break;
2005 case RTL_PCI_REVISION_ID_8192SE:
2006 RT_TRACE(COMP_INIT, DBG_DMESG,
2007 ("8192SE is found - "
2008 "vid/did=%x/%x\n", venderid, deviceid));
2009 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
2010 break;
2011 default:
2012 RT_TRACE(COMP_ERR, DBG_WARNING,
2013 ("Err: Unknown device - "
2014 "vid/did=%x/%x\n", venderid, deviceid));
2015 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
2016 break;
2017
2018 }
2019 }else if(deviceid == RTL_PCI_8723AE_DID) {
2020 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
2021 RT_TRACE(COMP_INIT, DBG_DMESG,
2022 ("8723AE PCI-E is found - "
2023 "vid/did=%x/%x\n", venderid, deviceid));
2024 } else if (deviceid == RTL_PCI_8192CET_DID ||
2025 deviceid == RTL_PCI_8192CE_DID ||
2026 deviceid == RTL_PCI_8191CE_DID ||
2027 deviceid == RTL_PCI_8188CE_DID) {
2028 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
2029 RT_TRACE(COMP_INIT, DBG_DMESG,
2030 ("8192C PCI-E is found - "
2031 "vid/did=%x/%x\n", venderid, deviceid));
2032 } else if (deviceid == RTL_PCI_8192DE_DID ||
2033 deviceid == RTL_PCI_8192DE_DID2) {
2034 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
2035 RT_TRACE(COMP_INIT, DBG_DMESG,
2036 ("8192D PCI-E is found - "
2037 "vid/did=%x/%x\n", venderid, deviceid));
2038 }else if(deviceid == RTL_PCI_8188EE_DID){
2039 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
2040 RT_TRACE(COMP_INIT,DBG_LOUD,
2041 ("Find adapter, Hardware type is 8188EE\n"));
2042 }else if (deviceid == RTL_PCI_8723BE_DID){
2043 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
2044 RT_TRACE(COMP_INIT,DBG_LOUD,
2045 ("Find adapter, Hardware type is 8723BE\n"));
2046 }else if (deviceid == RTL_PCI_8192EE_DID){
2047 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
2048 RT_TRACE(COMP_INIT,DBG_LOUD,
2049 ("Find adapter, Hardware type is 8192EE\n"));
2050 }else if (deviceid == RTL_PCI_8821AE_DID) {
2051 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
2052 RT_TRACE(COMP_INIT,DBG_LOUD,
2053 ("Find adapter, Hardware type is 8821AE\n"));
2054 }else if (deviceid == RTL_PCI_8812AE_DID) {
2055 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
2056 RT_TRACE(COMP_INIT,DBG_LOUD,
2057 ("Find adapter, Hardware type is 8812AE\n"));
2058 }else {
2059 RT_TRACE(COMP_ERR, DBG_WARNING,
2060 ("Err: Unknown device -"
2061 " vid/did=%x/%x\n", venderid, deviceid));
2062
2063 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
2064 }
2065
2066 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
2067 if (revisionid == 0 || revisionid == 1) {
2068 if (revisionid == 0) {
2069 RT_TRACE(COMP_INIT, DBG_LOUD,
2070 ("Find 92DE MAC0.\n"));
2071 rtlhal->interfaceindex = 0;
2072 } else if (revisionid == 1) {
2073 RT_TRACE(COMP_INIT, DBG_LOUD,
2074 ("Find 92DE MAC1.\n"));
2075 rtlhal->interfaceindex = 1;
2076 }
2077 } else {
2078 RT_TRACE(COMP_INIT, DBG_LOUD, ("Unknown device - "
2079 "VendorID/DeviceID=%x/%x, Revision=%x\n",
2080 venderid, deviceid, revisionid));
2081 rtlhal->interfaceindex = 0;
2082 }
2083 }
2084
2085 /* 92ee use new trx flow */
2086 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
2087 rtlpriv->use_new_trx_flow = true;
2088 else
2089 rtlpriv->use_new_trx_flow = false;
2090
2091 /*find bus info */
2092 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2093 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2094 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2095
2096 /*find bridge info */
2097 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2098 /* some ARM have no bridge_pdev and will crash here
2099 * so we should check if bridge_pdev is NULL */
2100 if (bridge_pdev) {
2101 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2102 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2103 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2104 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2105 RT_TRACE(COMP_INIT, DBG_DMESG,
2106 ("Pci Bridge Vendor is found index: %d\n",
2107 tmp));
2108 break;
2109 }
2110 }
2111 }
2112
2113 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2114 PCI_BRIDGE_VENDOR_UNKNOWN) {
2115 pcipriv->ndis_adapter.pcibridge_busnum =
2116 bridge_pdev->bus->number;
2117 pcipriv->ndis_adapter.pcibridge_devnum =
2118 PCI_SLOT(bridge_pdev->devfn);
2119 pcipriv->ndis_adapter.pcibridge_funcnum =
2120 PCI_FUNC(bridge_pdev->devfn);
2121 pcipriv->ndis_adapter.pcicfg_addrport =
2122 (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
2123 (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
2124 (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
2125/*<delete in kernel start>*/
2126#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
2127/*<delete in kernel end>*/
2128 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2129 pci_pcie_cap(bridge_pdev);
2130/*<delete in kernel start>*/
2131#else
2132 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2133 _rtl_pci_get_pciehdr_offset(hw);
2134#endif
2135/*<delete in kernel end>*/
2136 pcipriv->ndis_adapter.num4bytes =
2137 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2138
2139 rtl_pci_get_linkcontrol_field(hw);
2140
2141 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2142 PCI_BRIDGE_VENDOR_AMD) {
2143 pcipriv->ndis_adapter.amd_l1_patch =
2144 rtl_pci_get_amd_l1_patch(hw);
2145 }
2146 }
2147
2148 RT_TRACE(COMP_INIT, DBG_DMESG,
2149 ("pcidev busnumber:devnumber:funcnumber:"
2150 "vendor:link_ctl %d:%d:%d:%x:%x\n",
2151 pcipriv->ndis_adapter.busnumber,
2152 pcipriv->ndis_adapter.devnumber,
2153 pcipriv->ndis_adapter.funcnumber,
2154 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
2155
2156 RT_TRACE(COMP_INIT, DBG_DMESG,
2157 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
2158 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2159 pcipriv->ndis_adapter.pcibridge_busnum,
2160 pcipriv->ndis_adapter.pcibridge_devnum,
2161 pcipriv->ndis_adapter.pcibridge_funcnum,
2162 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2163 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2164 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2165 pcipriv->ndis_adapter.amd_l1_patch));
2166
2167 rtl_pci_parse_configuration(pdev, hw);
2168 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2169 return true;
2170}
2171
2172static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2173{
2174 struct rtl_priv *rtlpriv = rtl_priv(hw);
2175 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2176 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2177 int ret;
2178 ret = pci_enable_msi(rtlpci->pdev);
2179 if (ret < 0)
2180 return ret;
2181
2182 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2183 IRQF_SHARED, KBUILD_MODNAME, hw);
2184 if (ret < 0) {
2185 pci_disable_msi(rtlpci->pdev);
2186 return ret;
2187 }
2188
2189 rtlpci->using_msi = true;
2190
2191 RT_TRACE(COMP_INIT|COMP_INTR, DBG_DMESG, ("MSI Interrupt Mode!\n"));
2192 return 0;
2193}
2194
2195static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2196{
2197 struct rtl_priv *rtlpriv = rtl_priv(hw);
2198 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2199 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2200 int ret;
2201
2202 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2203 IRQF_SHARED, KBUILD_MODNAME, hw);
2204 if (ret < 0) {
2205 return ret;
2206 }
2207
2208 rtlpci->using_msi = false;
2209 RT_TRACE(COMP_INIT|COMP_INTR, DBG_DMESG,
2210 ("Pin-based Interrupt Mode!\n"));
2211 return 0;
2212}
2213
2214static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2215{
2216 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2217 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2218 int ret;
2219 if (rtlpci->msi_support == true) {
2220 ret = rtl_pci_intr_mode_msi(hw);
2221 if (ret < 0)
2222 ret = rtl_pci_intr_mode_legacy(hw);
2223 } else {
2224 ret = rtl_pci_intr_mode_legacy(hw);
2225 }
2226 return ret;
2227}
2228
2229/* this is used for other modules get
2230 * hw pointer in rtl_pci_get_hw_pointer */
2231struct ieee80211_hw *hw_export = NULL;
2232
2233#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0))
2234int rtl_pci_probe(struct pci_dev *pdev,
2235 const struct pci_device_id *id)
2236
2237#else
2238int __devinit rtl_pci_probe(struct pci_dev *pdev,
2239 const struct pci_device_id *id)
2240#endif
2241{
2242 struct ieee80211_hw *hw = NULL;
2243
2244 struct rtl_priv *rtlpriv = NULL;
2245 struct rtl_pci_priv *pcipriv = NULL;
2246 struct rtl_pci *rtlpci;
2247 unsigned long pmem_start, pmem_len, pmem_flags;
2248 int err;
2249
2250
2251 err = pci_enable_device(pdev);
2252 if (err) {
2253 RT_ASSERT(false,
2254 ("%s : Cannot enable new PCI device\n",
2255 pci_name(pdev)));
2256 return err;
2257 }
2258
2259 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2260 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2261 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
2262 "for consistent allocations\n"));
2263 pci_disable_device(pdev);
2264 return -ENOMEM;
2265 }
2266 }
2267
2268 pci_set_master(pdev);
2269
2270 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2271 sizeof(struct rtl_priv), &rtl_ops);
2272 if (!hw) {
2273 RT_ASSERT(false,
2274 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
2275 err = -ENOMEM;
2276 goto fail1;
2277 }
2278 hw_export = hw;
2279
2280 SET_IEEE80211_DEV(hw, &pdev->dev);
2281 pci_set_drvdata(pdev, hw);
2282
2283 rtlpriv = hw->priv;
2284 pcipriv = (void *)rtlpriv->priv;
2285 pcipriv->dev.pdev = pdev;
2286
2287 /* init cfg & intf_ops */
2288 rtlpriv->rtlhal.interface = INTF_PCI;
2289 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2290 rtlpriv->intf_ops = &rtl_pci_ops;
2291 rtlpriv->glb_var = &global_var;
2292
2293 /*
2294 *init dbgp flags before all
2295 *other functions, because we will
2296 *use it in other funtions like
2297 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
2298 *you can not use these macro
2299 *before this
2300 */
2301 rtl_dbgp_flag_init(hw);
2302
2303 /* MEM map */
2304 err = pci_request_regions(pdev, KBUILD_MODNAME);
2305 if (err) {
2306 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
2307 return err;
2308 }
2309
2310 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2311 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2312 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2313
2314 /*shared mem start */
2315 rtlpriv->io.pci_mem_start =
2316 (unsigned long)pci_iomap(pdev,
2317 rtlpriv->cfg->bar_id, pmem_len);
2318 if (rtlpriv->io.pci_mem_start == 0) {
2319 RT_ASSERT(false, ("Can't map PCI mem\n"));
2320 goto fail2;
2321 }
2322
2323 RT_TRACE(COMP_INIT, DBG_DMESG,
2324 ("mem mapped space: start: 0x%08lx len:%08lx "
2325 "flags:%08lx, after map:0x%08lx\n",
2326 pmem_start, pmem_len, pmem_flags,
2327 rtlpriv->io.pci_mem_start));
2328
2329 /* Disable Clk Request */
2330 pci_write_config_byte(pdev, 0x81, 0);
2331 /* leave D3 mode */
2332 pci_write_config_byte(pdev, 0x44, 0);
2333 pci_write_config_byte(pdev, 0x04, 0x06);
2334 pci_write_config_byte(pdev, 0x04, 0x07);
2335
2336 /* find adapter */
2337 /* if chip not support, will return false */
2338 if(!_rtl_pci_find_adapter(pdev, hw))
2339 goto fail3;
2340
2341 /* Init IO handler */
2342 _rtl_pci_io_handler_init(&pdev->dev, hw);
2343
2344 /*like read eeprom and so on */
2345 rtlpriv->cfg->ops->read_eeprom_info(hw);
2346
2347 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2348 RT_TRACE(COMP_ERR, DBG_EMERG, ("Can't init_sw_vars.\n"));
2349 goto fail3;
2350 }
2351
2352 rtlpriv->cfg->ops->init_sw_leds(hw);
2353
2354 /*aspm */
2355 rtl_pci_init_aspm(hw);
2356
2357 /* Init mac80211 sw */
2358 err = rtl_init_core(hw);
2359 if (err) {
2360 RT_TRACE(COMP_ERR, DBG_EMERG,
2361 ("Can't allocate sw for mac80211.\n"));
2362 goto fail3;
2363 }
2364
2365 /* Init PCI sw */
2366 err = !rtl_pci_init(hw, pdev);
2367 if (err) {
2368 RT_TRACE(COMP_ERR, DBG_EMERG, ("Failed to init PCI.\n"));
2369 goto fail3;
2370 }
2371
2372 err = ieee80211_register_hw(hw);
2373 if (err) {
2374 RT_TRACE(COMP_ERR, DBG_EMERG,
2375 ("Can't register mac80211 hw.\n"));
2376 goto fail3;
2377 } else {
2378 rtlpriv->mac80211.mac80211_registered = 1;
2379 }
2380 /* the wiphy must have been registed to
2381 * cfg80211 prior to regulatory_hint */
2382 if (regulatory_hint(hw->wiphy, rtlpriv->regd.alpha2)) {
2383 RT_TRACE(COMP_ERR, DBG_WARNING, ("regulatory_hint fail\n"));
2384 }
2385
2386 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
2387 if (err) {
2388 RT_TRACE(COMP_ERR, DBG_EMERG,
2389 ("failed to create sysfs device attributes\n"));
2390 goto fail3;
2391 }
2392 /* add for prov */
2393 rtl_proc_add_one(hw);
2394
2395 /*init rfkill */
2396 rtl_init_rfkill(hw);
2397
2398 rtlpci = rtl_pcidev(pcipriv);
2399
2400 err = rtl_pci_intr_mode_decide(hw);
2401 if (err) {
2402 RT_TRACE(COMP_INIT, DBG_DMESG,
2403 ("%s: failed to register IRQ handler\n",
2404 wiphy_name(hw->wiphy)));
2405 goto fail3;
2406 } else {
2407 rtlpci->irq_alloc = 1;
2408 }
2409
2410 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2411 return 0;
2412
2413fail3:
2414 pci_set_drvdata(pdev, NULL);
2415 rtl_deinit_core(hw);
2416 ieee80211_free_hw(hw);
2417
2418 if (rtlpriv->io.pci_mem_start != 0)
2419 pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start);
2420
2421fail2:
2422 pci_release_regions(pdev);
2423
2424fail1:
2425
2426 pci_disable_device(pdev);
2427
2428 return -ENODEV;
2429
2430}
2431//EXPORT_SYMBOL(rtl_pci_probe);
2432
2433struct ieee80211_hw *rtl_pci_get_hw_pointer(void)
2434{
2435 return hw_export;
2436}
2437//EXPORT_SYMBOL(rtl_pci_get_hw_pointer);
2438
2439void rtl_pci_disconnect(struct pci_dev *pdev)
2440{
2441 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2442 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2443 struct rtl_priv *rtlpriv = rtl_priv(hw);
2444 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2445 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2446
2447 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2448
2449 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
2450
2451 /* add for prov */
2452 rtl_proc_remove_one(hw);
2453
2454
2455 /*ieee80211_unregister_hw will call ops_stop */
2456 if (rtlmac->mac80211_registered == 1) {
2457 ieee80211_unregister_hw(hw);
2458 rtlmac->mac80211_registered = 0;
2459 } else {
2460 rtl_deinit_deferred_work(hw);
2461 rtlpriv->intf_ops->adapter_stop(hw);
2462 }
2463
2464 /*deinit rfkill */
2465 rtl_deinit_rfkill(hw);
2466
2467 rtl_pci_deinit(hw);
2468 rtl_deinit_core(hw);
2469 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2470
2471 if (rtlpci->irq_alloc) {
2472 synchronize_irq(rtlpci->pdev->irq);
2473 free_irq(rtlpci->pdev->irq, hw);
2474 rtlpci->irq_alloc = 0;
2475 }
2476
2477 if (rtlpci->using_msi == true)
2478 pci_disable_msi(rtlpci->pdev);
2479
2480 list_del(&rtlpriv->list);
2481 if (rtlpriv->io.pci_mem_start != 0) {
2482 pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start);
2483 pci_release_regions(pdev);
2484 }
2485
2486 pci_disable_device(pdev);
2487
2488 rtl_pci_disable_aspm(hw);
2489
2490 pci_set_drvdata(pdev, NULL);
2491
2492 ieee80211_free_hw(hw);
2493}
2494//EXPORT_SYMBOL(rtl_pci_disconnect);
2495
2496/***************************************
2497kernel pci power state define:
2498PCI_D0 ((pci_power_t __force) 0)
2499PCI_D1 ((pci_power_t __force) 1)
2500PCI_D2 ((pci_power_t __force) 2)
2501PCI_D3hot ((pci_power_t __force) 3)
2502PCI_D3cold ((pci_power_t __force) 4)
2503PCI_UNKNOWN ((pci_power_t __force) 5)
2504
2505This function is called when system
2506goes into suspend state mac80211 will
2507call rtl_mac_stop() from the mac80211
2508suspend function first, So there is
2509no need to call hw_disable here.
2510****************************************/
2511int rtl_pci_suspend(struct device *dev)
2512{
2513 struct pci_dev *pdev = to_pci_dev(dev);
2514 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2515 struct rtl_priv *rtlpriv = rtl_priv(hw);
2516
2517 rtlpriv->cfg->ops->hw_suspend(hw);
2518 rtl_deinit_rfkill(hw);
2519
2520 return 0;
2521}
2522//EXPORT_SYMBOL(rtl_pci_suspend);
2523
2524int rtl_pci_resume(struct device *dev)
2525{
2526 struct pci_dev *pdev = to_pci_dev(dev);
2527 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2528 struct rtl_priv *rtlpriv = rtl_priv(hw);
2529
2530 rtlpriv->cfg->ops->hw_resume(hw);
2531 rtl_init_rfkill(hw);
2532
2533 return 0;
2534}
2535//EXPORT_SYMBOL(rtl_pci_resume);
2536
2537struct rtl_intf_ops rtl_pci_ops = {
2538 .read_efuse_byte = read_efuse_byte,
2539 .adapter_start = rtl_pci_start,
2540 .adapter_stop = rtl_pci_stop,
2541 .check_buddy_priv = rtl_pci_check_buddy_priv,
2542 .adapter_tx = rtl_pci_tx,
2543 .flush = rtl_pci_flush,
2544 .reset_trx_ring = rtl_pci_reset_trx_ring,
2545 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2546
2547 .disable_aspm = rtl_pci_disable_aspm,
2548 .enable_aspm = rtl_pci_enable_aspm,
2549};
diff --git a/drivers/staging/rtl8821ae/pci.h b/drivers/staging/rtl8821ae/pci.h
new file mode 100644
index 000000000000..9f206550a657
--- /dev/null
+++ b/drivers/staging/rtl8821ae/pci.h
@@ -0,0 +1,353 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_PCI_H__
31#define __RTL_PCI_H__
32
33#include <linux/pci.h>
34/*
351: MSDU packet queue,
362: Rx Command Queue
37*/
38#define RTL_PCI_RX_MPDU_QUEUE 0
39#define RTL_PCI_RX_CMD_QUEUE 1
40#define RTL_PCI_MAX_RX_QUEUE 2
41
42#define RTL_PCI_MAX_RX_COUNT 512//64
43#define RTL_PCI_MAX_TX_QUEUE_COUNT 9
44
45#define RT_TXDESC_NUM 128
46#define TX_DESC_NUM_92E 512
47#define RT_TXDESC_NUM_BE_QUEUE 256
48
49#define BK_QUEUE 0
50#define BE_QUEUE 1
51#define VI_QUEUE 2
52#define VO_QUEUE 3
53#define BEACON_QUEUE 4
54#define TXCMD_QUEUE 5
55#define MGNT_QUEUE 6
56#define HIGH_QUEUE 7
57#define HCCA_QUEUE 8
58
59#define RTL_PCI_DEVICE(vend, dev, cfg) \
60 .vendor = (vend), \
61 .device = (dev), \
62 .subvendor = PCI_ANY_ID, \
63 .subdevice = PCI_ANY_ID,\
64 .driver_data = (kernel_ulong_t)&(cfg)
65
66#define INTEL_VENDOR_ID 0x8086
67#define SIS_VENDOR_ID 0x1039
68#define ATI_VENDOR_ID 0x1002
69#define ATI_DEVICE_ID 0x7914
70#define AMD_VENDOR_ID 0x1022
71
72#define PCI_MAX_BRIDGE_NUMBER 255
73#define PCI_MAX_DEVICES 32
74#define PCI_MAX_FUNCTION 8
75
76#define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
77#define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
78
79#define PCI_CLASS_BRIDGE_DEV 0x06
80#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
81#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
82#define PCI_CAP_ID_EXP 0x10
83
84#define U1DONTCARE 0xFF
85#define U2DONTCARE 0xFFFF
86#define U4DONTCARE 0xFFFFFFFF
87
88#define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
89#define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
90#define RTL_PCI_8174_DID 0x8174 /*8192 SE */
91#define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
92#define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
93#define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
94#define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
95#define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
96#define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
97#define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
98#define RTL_PCI_700F_DID 0x700F
99#define RTL_PCI_701F_DID 0x701F
100#define RTL_PCI_DLINK_DID 0x3304
101#define RTL_PCI_8723AE_DID 0x8723 /*8723e */
102#define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
103#define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
104#define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
105#define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
106#define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
107#define RTL_PCI_8192DE_DID 0x8193 /*8192de */
108#define RTL_PCI_8192DE_DID2 0x002B /*92DE*/
109#define RTL_PCI_8188EE_DID 0x8179 /*8188ee*/
110#define RTL_PCI_8723BE_DID 0xB723 /*8723be*/
111#define RTL_PCI_8192EE_DID 0x818B /*8192ee*/
112#define RTL_PCI_8821AE_DID 0x8821 /*8821ae*/
113#define RTL_PCI_8812AE_DID 0x8812 /*8812ae*/
114
115/*8192 support 16 pages of IO registers*/
116#define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
117#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
118#define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
119#define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
120#define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
121
122#define RTL_PCI_REVISION_ID_8190PCI 0x00
123#define RTL_PCI_REVISION_ID_8192PCIE 0x01
124#define RTL_PCI_REVISION_ID_8192SE 0x10
125#define RTL_PCI_REVISION_ID_8192CE 0x1
126#define RTL_PCI_REVISION_ID_8192DE 0x0
127
128#define PCI_VENDOR_ID_REALTEK 0x10ec
129
130#define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
131
132enum pci_bridge_vendor {
133 PCI_BRIDGE_VENDOR_INTEL = 0x0, /*0b'0000,0001 */
134 PCI_BRIDGE_VENDOR_ATI, /*0b'0000,0010*/
135 PCI_BRIDGE_VENDOR_AMD, /*0b'0000,0100*/
136 PCI_BRIDGE_VENDOR_SIS, /*0b'0000,1000*/
137 PCI_BRIDGE_VENDOR_UNKNOWN, /*0b'0100,0000*/
138 PCI_BRIDGE_VENDOR_MAX,
139};
140
141struct rtl_pci_capabilities_header {
142 u8 capability_id;
143 u8 next;
144};
145
146/* In new TRX flow, Buffer_desc is new concept
147 * But TX wifi info == TX descriptor in old flow
148 * RX wifi info == RX descriptor in old flow */
149struct rtl_tx_buffer_desc {
150#if (RTL8192EE_SEG_NUM == 2)
151 u32 dword[2*(DMA_IS_64BIT + 1)*8]; //seg = 8
152#elif (RTL8192EE_SEG_NUM == 1)
153 u32 dword[2*(DMA_IS_64BIT + 1)*4]; //seg = 4
154#elif (RTL8192EE_SEG_NUM == 0)
155 u32 dword[2*(DMA_IS_64BIT + 1)*2]; //seg = 2
156#endif
157} __packed;
158
159struct rtl_tx_desc {/*old: tx desc*//*new: tx wifi info*/
160 u32 dword[16];
161} __packed;
162
163struct rtl_rx_buffer_desc { /*rx buffer desc*/
164 u32 dword[2];
165} __packed;
166
167struct rtl_rx_desc { /*old: rx desc*//*new: rx wifi info*/
168 u32 dword[8];
169} __packed;
170
171struct rtl_tx_cmd_desc {
172 u32 dword[16];
173} __packed;
174
175struct rtl8192_tx_ring {
176 struct rtl_tx_desc *desc; /*tx desc / tx wifi info*/
177 dma_addr_t dma; /*tx desc dma memory / tx wifi info dma memory*/
178 unsigned int idx;
179 unsigned int entries;
180 struct sk_buff_head queue;
181 /*add for new trx flow*/
182 struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
183 dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
184 u16 avl_desc; /* available_desc_to_write */
185 u16 cur_tx_wp; /* current_tx_write_point */
186 u16 cur_tx_rp; /* current_tx_read_point */
187};
188
189struct rtl8192_rx_ring {
190 struct rtl_rx_desc *desc;/*for old trx flow, not uesd in new trx*/
191 /*dma matches either 'desc' or 'buffer_desc'*/
192 dma_addr_t dma;
193 unsigned int idx;
194 struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
195 /*add for new trx flow*/
196 struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
197 u16 next_rx_rp; /* next_rx_read_point */
198};
199
200struct rtl_pci {
201 struct pci_dev *pdev;
202 bool irq_enabled;
203
204 /*Tx */
205 struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
206 int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
207 u32 transmit_config;
208
209 /*Rx */
210 struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
211 int rxringcount;
212 u16 rxbuffersize;
213 u32 receive_config;
214
215 /*irq */
216 u8 irq_alloc;
217 u32 irq_mask[2];
218 u32 sys_irq_mask;
219
220 /*Bcn control register setting */
221 u32 reg_bcn_ctrl_val;
222
223 /*ASPM*/ u8 const_pci_aspm;
224 u8 const_amdpci_aspm;
225 u8 const_hwsw_rfoff_d3;
226 u8 const_support_pciaspm;
227 /*pci-e bridge */
228 u8 const_hostpci_aspm_setting;
229 /*pci-e device */
230 u8 const_devicepci_aspm_setting;
231 /*If it supports ASPM, Offset[560h] = 0x40,
232 otherwise Offset[560h] = 0x00. */
233 bool b_support_aspm;
234 bool b_support_backdoor;
235
236 /*QOS & EDCA */
237 enum acm_method acm_method;
238
239 u16 shortretry_limit;
240 u16 longretry_limit;
241
242 /* MSI support */
243 bool msi_support;
244 bool using_msi;
245};
246
247struct mp_adapter {
248 u8 linkctrl_reg;
249
250 u8 busnumber;
251 u8 devnumber;
252 u8 funcnumber;
253
254 u8 pcibridge_busnum;
255 u8 pcibridge_devnum;
256 u8 pcibridge_funcnum;
257
258 u8 pcibridge_vendor;
259 u16 pcibridge_vendorid;
260 u16 pcibridge_deviceid;
261
262 u32 pcicfg_addrport;
263 u8 num4bytes;
264
265 u8 pcibridge_pciehdr_offset;
266 u8 pcibridge_linkctrlreg;
267
268 bool amd_l1_patch;
269};
270
271struct rtl_pci_priv {
272 struct rtl_pci dev;
273 struct mp_adapter ndis_adapter;
274 struct rtl_led_ctl ledctl;
275 struct bt_coexist_info btcoexist;
276};
277
278#define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
279#define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
280
281int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
282
283extern struct rtl_intf_ops rtl_pci_ops;
284
285#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0))
286int rtl_pci_probe(struct pci_dev *pdev,
287 const struct pci_device_id *id);
288#else
289int __devinit rtl_pci_probe(struct pci_dev *pdev,
290 const struct pci_device_id *id);
291#endif
292void rtl_pci_disconnect(struct pci_dev *pdev);
293int rtl_pci_suspend(struct device *dev);
294int rtl_pci_resume(struct device *dev);
295
296static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
297{
298 return 0xff & readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
299}
300
301static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
302{
303 return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
304}
305
306static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
307{
308 return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
309}
310
311static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
312{
313 writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
314}
315
316static inline void pci_write16_async(struct rtl_priv *rtlpriv,
317 u32 addr, u16 val)
318{
319 writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
320}
321
322static inline void pci_write32_async(struct rtl_priv *rtlpriv,
323 u32 addr, u32 val)
324{
325 writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
326}
327
328static inline void rtl_pci_raw_write_port_ulong(u32 port, u32 val)
329{
330 outl(val, port);
331}
332
333static inline void rtl_pci_raw_write_port_uchar(u32 port, u8 val)
334{
335 outb(val, port);
336}
337
338static inline void rtl_pci_raw_read_port_uchar(u32 port, u8 * pval)
339{
340 *pval = inb(port);
341}
342
343static inline void rtl_pci_raw_read_port_ushort(u32 port, u16 * pval)
344{
345 *pval = inw(port);
346}
347
348static inline void rtl_pci_raw_read_port_ulong(u32 port, u32 * pval)
349{
350 *pval = inl(port);
351}
352
353#endif
diff --git a/drivers/staging/rtl8821ae/ps.c b/drivers/staging/rtl8821ae/ps.c
new file mode 100644
index 000000000000..f12ffa83c58d
--- /dev/null
+++ b/drivers/staging/rtl8821ae/ps.c
@@ -0,0 +1,1025 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "base.h"
32#include "ps.h"
33#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
34#include <linux/export.h>
35#endif
36#include "btcoexist/rtl_btc.h"
37
38bool rtl_ps_enable_nic(struct ieee80211_hw *hw)
39{
40 struct rtl_priv *rtlpriv = rtl_priv(hw);
41 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
42 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
43 bool init_status = true;
44
45 /*<1> reset trx ring */
46 if (rtlhal->interface == INTF_PCI)
47 rtlpriv->intf_ops->reset_trx_ring(hw);
48
49 if (is_hal_stop(rtlhal))
50 RT_TRACE(COMP_ERR, DBG_WARNING, ("Driver is already down!\n"));
51
52 /*<2> Enable Adapter */
53 rtlpriv->cfg->ops->hw_init(hw);
54 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
55 /*init_status = false; */
56
57 /*<3> Enable Interrupt */
58 rtlpriv->cfg->ops->enable_interrupt(hw);
59
60 /*<enable timer> */
61 rtl_watch_dog_timer_callback((unsigned long)hw);
62
63 return init_status;
64}
65//EXPORT_SYMBOL(rtl_ps_enable_nic);
66
67bool rtl_ps_disable_nic(struct ieee80211_hw *hw)
68{
69 bool status = true;
70 struct rtl_priv *rtlpriv = rtl_priv(hw);
71
72 /*<1> Stop all timer */
73 rtl_deinit_deferred_work(hw);
74
75 /*<2> Disable Interrupt */
76 rtlpriv->cfg->ops->disable_interrupt(hw);
77
78 /*<3> Disable Adapter */
79 rtlpriv->cfg->ops->hw_disable(hw);
80
81 return status;
82}
83//EXPORT_SYMBOL(rtl_ps_disable_nic);
84
85bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
86 enum rf_pwrstate state_toset,
87 u32 changesource, bool protect_or_not)
88{
89 struct rtl_priv *rtlpriv = rtl_priv(hw);
90 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
91 enum rf_pwrstate rtstate;
92 bool b_actionallowed = false;
93 u16 rfwait_cnt = 0;
94
95 /*protect_or_not = true; */
96
97 if (protect_or_not)
98 goto no_protect;
99
100 /*
101 *Only one thread can change
102 *the RF state at one time, and others
103 *should wait to be executed.
104 */
105 while (true) {
106 spin_lock(&rtlpriv->locks.rf_ps_lock);
107 if (ppsc->rfchange_inprogress) {
108 spin_unlock(&rtlpriv->locks.rf_ps_lock);
109
110 RT_TRACE(COMP_ERR, DBG_WARNING,
111 ("RF Change in progress!"
112 "Wait to set..state_toset(%d).\n",
113 state_toset));
114
115 /* Set RF after the previous action is done. */
116 while (ppsc->rfchange_inprogress) {
117 rfwait_cnt++;
118 mdelay(1);
119 /*
120 *Wait too long, return false to avoid
121 *to be stuck here.
122 */
123 if (rfwait_cnt > 100)
124 return false;
125 }
126 } else {
127 ppsc->rfchange_inprogress = true;
128 spin_unlock(&rtlpriv->locks.rf_ps_lock);
129 break;
130 }
131 }
132
133no_protect:
134 rtstate = ppsc->rfpwr_state;
135
136 switch (state_toset) {
137 case ERFON:
138 ppsc->rfoff_reason &= (~changesource);
139
140 if ((changesource == RF_CHANGE_BY_HW) &&
141 (ppsc->b_hwradiooff == true)) {
142 ppsc->b_hwradiooff = false;
143 }
144
145 if (!ppsc->rfoff_reason) {
146 ppsc->rfoff_reason = 0;
147 b_actionallowed = true;
148 }
149
150 break;
151
152 case ERFOFF:
153
154 if ((changesource == RF_CHANGE_BY_HW) &&
155 (ppsc->b_hwradiooff == false)) {
156 ppsc->b_hwradiooff = true;
157 }
158
159 ppsc->rfoff_reason |= changesource;
160 b_actionallowed = true;
161 break;
162
163 case ERFSLEEP:
164 ppsc->rfoff_reason |= changesource;
165 b_actionallowed = true;
166 break;
167
168 default:
169 RT_TRACE(COMP_ERR, DBG_EMERG, ("switch case not process \n"));
170 break;
171 }
172
173 if (b_actionallowed)
174 rtlpriv->cfg->ops->set_rf_power_state(hw, state_toset);
175
176 if (!protect_or_not) {
177 spin_lock(&rtlpriv->locks.rf_ps_lock);
178 ppsc->rfchange_inprogress = false;
179 spin_unlock(&rtlpriv->locks.rf_ps_lock);
180 }
181
182 return b_actionallowed;
183}
184//EXPORT_SYMBOL(rtl_ps_set_rf_state);
185
186static void _rtl_ps_inactive_ps(struct ieee80211_hw *hw)
187{
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
190 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
191
192 ppsc->b_swrf_processing = true;
193
194 if (ppsc->inactive_pwrstate == ERFON && rtlhal->interface == INTF_PCI) {
195 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
196 RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM) &&
197 rtlhal->interface == INTF_PCI) {
198 rtlpriv->intf_ops->disable_aspm(hw);
199 RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
200 }
201 }
202
203 if (rtlpriv->cfg->ops->get_btc_status()){
204 rtlpriv->btcoexist.btc_ops->btc_ips_notify(rtlpriv,
205 ppsc->inactive_pwrstate);
206 }
207 rtl_ps_set_rf_state(hw, ppsc->inactive_pwrstate,
208 RF_CHANGE_BY_IPS, false);
209
210 if (ppsc->inactive_pwrstate == ERFOFF &&
211 rtlhal->interface == INTF_PCI) {
212 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM &&
213 !RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
214 rtlpriv->intf_ops->enable_aspm(hw);
215 RT_SET_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
216 }
217 }
218
219 ppsc->b_swrf_processing = false;
220}
221
222void rtl_ips_nic_off_wq_callback(void *data)
223{
224 struct rtl_works *rtlworks =
225 container_of_dwork_rtl(data, struct rtl_works, ips_nic_off_wq);
226 struct ieee80211_hw *hw = rtlworks->hw;
227 struct rtl_priv *rtlpriv = rtl_priv(hw);
228 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
229 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
230 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
231 enum rf_pwrstate rtstate;
232
233 if (mac->opmode != NL80211_IFTYPE_STATION) {
234 RT_TRACE(COMP_ERR, DBG_WARNING, ("not station return\n"));
235 return;
236 }
237
238 if (mac->p2p_in_use)
239 return;
240
241 if (mac->link_state > MAC80211_NOLINK)
242 return;
243
244 if (is_hal_stop(rtlhal))
245 return;
246
247 if (rtlpriv->sec.being_setkey)
248 return;
249
250 if(rtlpriv->cfg->ops->bt_turn_off_bt_coexist_before_enter_lps)
251 rtlpriv->cfg->ops->bt_turn_off_bt_coexist_before_enter_lps(hw);
252
253 if (ppsc->b_inactiveps) {
254 rtstate = ppsc->rfpwr_state;
255
256 /*
257 *Do not enter IPS in the following conditions:
258 *(1) RF is already OFF or Sleep
259 *(2) b_swrf_processing (indicates the IPS is still under going)
260 *(3) Connectted (only disconnected can trigger IPS)
261 *(4) IBSS (send Beacon)
262 *(5) AP mode (send Beacon)
263 *(6) monitor mode (rcv packet)
264 */
265
266 if (rtstate == ERFON &&
267 !ppsc->b_swrf_processing &&
268 (mac->link_state == MAC80211_NOLINK) &&
269 !mac->act_scanning) {
270 RT_TRACE(COMP_RF, DBG_LOUD,
271 ("IPSEnter(): Turn off RF.\n"));
272
273 ppsc->inactive_pwrstate = ERFOFF;
274 ppsc->b_in_powersavemode = true;
275
276 /*rtl_pci_reset_trx_ring(hw); */
277 _rtl_ps_inactive_ps(hw);
278 }
279 }
280}
281
282void rtl_ips_nic_off(struct ieee80211_hw *hw)
283{
284 struct rtl_priv *rtlpriv = rtl_priv(hw);
285
286 /*
287 *because when link with ap, mac80211 will ask us
288 *to disable nic quickly after scan before linking,
289 *this will cause link failed, so we delay 100ms here
290 */
291 queue_delayed_work(rtlpriv->works.rtl_wq,
292 &rtlpriv->works.ips_nic_off_wq, MSECS(100));
293}
294
295/* NOTICE: any opmode should exc nic_on, or disable without
296 * nic_on may something wrong, like adhoc TP*/
297void rtl_ips_nic_on(struct ieee80211_hw *hw)
298{
299 struct rtl_priv *rtlpriv = rtl_priv(hw);
300 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
301 enum rf_pwrstate rtstate;
302
303 cancel_delayed_work(&rtlpriv->works.ips_nic_off_wq);
304
305 spin_lock(&rtlpriv->locks.ips_lock);
306 if (ppsc->b_inactiveps) {
307 rtstate = ppsc->rfpwr_state;
308
309 if (rtstate != ERFON &&
310 !ppsc->b_swrf_processing &&
311 ppsc->rfoff_reason <= RF_CHANGE_BY_IPS) {
312
313 ppsc->inactive_pwrstate = ERFON;
314 ppsc->b_in_powersavemode = false;
315 _rtl_ps_inactive_ps(hw);
316 }
317 }
318 spin_unlock(&rtlpriv->locks.ips_lock);
319}
320
321/*for FW LPS*/
322
323/*
324 *Determine if we can set Fw into PS mode
325 *in current condition.Return true if it
326 *can enter PS mode.
327 */
328static bool rtl_get_fwlps_doze(struct ieee80211_hw *hw)
329{
330 struct rtl_priv *rtlpriv = rtl_priv(hw);
331 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
332 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
333 u32 ps_timediff;
334
335 ps_timediff = jiffies_to_msecs(jiffies -
336 ppsc->last_delaylps_stamp_jiffies);
337
338 if (ps_timediff < 2000) {
339 RT_TRACE(COMP_POWER, DBG_LOUD,
340 ("Delay enter Fw LPS for DHCP, ARP,"
341 " or EAPOL exchanging state.\n"));
342 return false;
343 }
344
345 if (mac->link_state != MAC80211_LINKED)
346 return false;
347
348 if (mac->opmode == NL80211_IFTYPE_ADHOC)
349 return false;
350
351 return true;
352}
353
354/* Change current and default preamble mode.*/
355void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode)
356{
357 struct rtl_priv *rtlpriv = rtl_priv(hw);
358 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
359 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
360 bool enter_fwlps;
361
362 if (mac->opmode == NL80211_IFTYPE_ADHOC)
363 return;
364
365 if (mac->link_state != MAC80211_LINKED)
366 return;
367
368 if (ppsc->dot11_psmode == rt_psmode)
369 return;
370
371 /* Update power save mode configured. */
372 ppsc->dot11_psmode = rt_psmode;
373
374 /*
375 *<FW control LPS>
376 *1. Enter PS mode
377 * Set RPWM to Fw to turn RF off and send H2C fw_pwrmode
378 * cmd to set Fw into PS mode.
379 *2. Leave PS mode
380 * Send H2C fw_pwrmode cmd to Fw to set Fw into Active
381 * mode and set RPWM to turn RF on.
382 */
383
384 if ((ppsc->b_fwctrl_lps) && ppsc->report_linked) {
385 if (ppsc->dot11_psmode == EACTIVE) {
386 RT_TRACE(COMP_RF, DBG_DMESG,
387 ("FW LPS leave ps_mode:%x\n",
388 FW_PS_ACTIVE_MODE));
389 enter_fwlps = false;
390 ppsc->pwr_mode = FW_PS_ACTIVE_MODE;
391 ppsc->smart_ps = 0;
392 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_LPS_ACTION,
393 (u8 *)(&enter_fwlps));
394 if (ppsc->p2p_ps_info.opp_ps)
395 rtl_p2p_ps_cmd(hw,P2P_PS_ENABLE);
396
397 } else {
398 if (rtl_get_fwlps_doze(hw)) {
399 RT_TRACE(COMP_RF, DBG_DMESG,
400 ("FW LPS enter ps_mode:%x\n",
401 ppsc->fwctrl_psmode));
402 enter_fwlps = true;
403 ppsc->pwr_mode = ppsc->fwctrl_psmode;
404 ppsc->smart_ps = 2;
405 rtlpriv->cfg->ops->set_hw_reg(hw,
406 HW_VAR_FW_LPS_ACTION,
407 (u8 *)(&enter_fwlps));
408
409 } else {
410 /* Reset the power save related parameters. */
411 ppsc->dot11_psmode = EACTIVE;
412 }
413 }
414 }
415}
416
417/*Enter the leisure power save mode.*/
418void rtl_lps_enter(struct ieee80211_hw *hw)
419{
420 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
421 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
422 struct rtl_priv *rtlpriv = rtl_priv(hw);
423 unsigned long flag;
424
425 if (!ppsc->b_fwctrl_lps)
426 return;
427
428 if (rtlpriv->sec.being_setkey)
429 return;
430
431 if (rtlpriv->link_info.b_busytraffic)
432 return;
433
434 /*sleep after linked 10s, to let DHCP and 4-way handshake ok enough!! */
435 if (mac->cnt_after_linked < 5)
436 return;
437
438 if (mac->opmode == NL80211_IFTYPE_ADHOC)
439 return;
440
441 if (mac->link_state != MAC80211_LINKED)
442 return;
443
444 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
445
446 /* Idle for a while if we connect to AP a while ago. */
447 if (mac->cnt_after_linked >= 2) {
448 if (ppsc->dot11_psmode == EACTIVE) {
449 RT_TRACE(COMP_POWER, DBG_LOUD,
450 ("Enter 802.11 power save mode...\n"));
451
452 rtl_lps_set_psmode(hw, EAUTOPS);
453 }
454 }
455
456 spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
457}
458
459/*Leave the leisure power save mode.*/
460void rtl_lps_leave(struct ieee80211_hw *hw)
461{
462 struct rtl_priv *rtlpriv = rtl_priv(hw);
463 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
464 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
465 unsigned long flag;
466
467 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
468
469 if (ppsc->b_fwctrl_lps) {
470 if (ppsc->dot11_psmode != EACTIVE) {
471
472 /*FIX ME */
473 rtlpriv->cfg->ops->enable_interrupt(hw);
474
475 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM &&
476 RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM) &&
477 rtlhal->interface == INTF_PCI) {
478 rtlpriv->intf_ops->disable_aspm(hw);
479 RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
480 }
481
482 RT_TRACE(COMP_POWER, DBG_LOUD,
483 ("Busy Traffic,Leave 802.11 power save..\n"));
484
485 rtl_lps_set_psmode(hw, EACTIVE);
486 }
487 }
488 spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
489}
490
491/* For sw LPS*/
492void rtl_swlps_beacon(struct ieee80211_hw *hw, void *data, unsigned int len)
493{
494 struct rtl_priv *rtlpriv = rtl_priv(hw);
495 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
496 struct ieee80211_hdr *hdr = (void *) data;
497 struct ieee80211_tim_ie *tim_ie;
498 u8 *tim;
499 u8 tim_len;
500 bool u_buffed;
501 bool m_buffed;
502
503 if (mac->opmode != NL80211_IFTYPE_STATION)
504 return;
505
506 if (!rtlpriv->psc.b_swctrl_lps)
507 return;
508
509 if (rtlpriv->mac80211.link_state != MAC80211_LINKED)
510 return;
511
512 if (!rtlpriv->psc.sw_ps_enabled)
513 return;
514
515 if (rtlpriv->psc.b_fwctrl_lps)
516 return;
517
518 if (likely(!(hw->conf.flags & IEEE80211_CONF_PS)))
519 return;
520
521 /* check if this really is a beacon */
522 if (!ieee80211_is_beacon(hdr->frame_control))
523 return;
524
525 /* min. beacon length + FCS_LEN */
526 if (len <= 40 + FCS_LEN)
527 return;
528
529 /* and only beacons from the associated BSSID, please */
530 if (ether_addr_equal(hdr->addr3, rtlpriv->mac80211.bssid))
531 return;
532
533 rtlpriv->psc.last_beacon = jiffies;
534
535 tim = rtl_find_ie(data, len - FCS_LEN, WLAN_EID_TIM);
536 if (!tim)
537 return;
538
539 if (tim[1] < sizeof(*tim_ie))
540 return;
541
542 tim_len = tim[1];
543 tim_ie = (struct ieee80211_tim_ie *) &tim[2];
544
545/*<delete in kernel start>*/
546#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
547/*<delete in kernel end>*/
548 if (!WARN_ON_ONCE(!hw->conf.ps_dtim_period))
549 rtlpriv->psc.dtim_counter = tim_ie->dtim_count;
550/*<delete in kernel start>*/
551#else
552 if (!WARN_ON_ONCE(!mac->vif->bss_conf.dtim_period))
553 rtlpriv->psc.dtim_counter = tim_ie->dtim_count;
554#endif
555/*<delete in kernel end>*/
556
557 /* Check whenever the PHY can be turned off again. */
558
559 /* 1. What about buffered unicast traffic for our AID? */
560 u_buffed = ieee80211_check_tim(tim_ie, tim_len,
561 rtlpriv->mac80211.assoc_id);
562
563 /* 2. Maybe the AP wants to send multicast/broadcast data? */
564 m_buffed = tim_ie->bitmap_ctrl & 0x01;
565 rtlpriv->psc.multi_buffered = m_buffed;
566
567 /* unicast will process by mac80211 through
568 * set ~IEEE80211_CONF_PS, So we just check
569 * multicast frames here */
570 if (!m_buffed ) {//&&) {// !rtlpriv->psc.tx_doing) {
571 /* back to low-power land. and delay is
572 * prevent null power save frame tx fail */
573 queue_delayed_work(rtlpriv->works.rtl_wq,
574 &rtlpriv->works.ps_work, MSECS(5));
575 } else {
576 RT_TRACE(COMP_POWER, DBG_DMESG,
577 ("u_bufferd: %x, m_buffered: %x\n",
578 u_buffed, m_buffed));
579 }
580}
581
582void rtl_swlps_rf_awake(struct ieee80211_hw *hw)
583{
584 struct rtl_priv *rtlpriv = rtl_priv(hw);
585 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
586 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
587 unsigned long flag;
588
589 if (!rtlpriv->psc.b_swctrl_lps)
590 return;
591 if (mac->link_state != MAC80211_LINKED)
592 return;
593
594 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM &&
595 RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
596 rtlpriv->intf_ops->disable_aspm(hw);
597 RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
598 }
599
600 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
601 rtl_ps_set_rf_state(hw, ERFON, RF_CHANGE_BY_PS, false);
602 spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
603}
604
605void rtl_swlps_rfon_wq_callback(void *data)
606{
607 struct rtl_works *rtlworks =
608 container_of_dwork_rtl(data, struct rtl_works, ps_rfon_wq);
609 struct ieee80211_hw *hw = rtlworks->hw;
610
611 rtl_swlps_rf_awake(hw);
612}
613
614void rtl_swlps_rf_sleep(struct ieee80211_hw *hw)
615{
616 struct rtl_priv *rtlpriv = rtl_priv(hw);
617 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
618 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
619 unsigned long flag;
620 u8 sleep_intv;
621
622 if (!rtlpriv->psc.sw_ps_enabled)
623 return;
624
625 if ((rtlpriv->sec.being_setkey) ||
626 (mac->opmode == NL80211_IFTYPE_ADHOC))
627 return;
628
629 /*sleep after linked 10s, to let DHCP and 4-way handshake ok enough!! */
630 if ((mac->link_state != MAC80211_LINKED) || (mac->cnt_after_linked < 5))
631 return;
632
633 if (rtlpriv->link_info.b_busytraffic)
634 return;
635
636 spin_lock(&rtlpriv->locks.rf_ps_lock);
637 if (rtlpriv->psc.rfchange_inprogress) {
638 spin_unlock(&rtlpriv->locks.rf_ps_lock);
639 return;
640 }
641 spin_unlock(&rtlpriv->locks.rf_ps_lock);
642
643 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
644 rtl_ps_set_rf_state(hw, ERFSLEEP, RF_CHANGE_BY_PS,false);
645 spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
646
647 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM &&
648 !RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
649 rtlpriv->intf_ops->enable_aspm(hw);
650 RT_SET_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
651 }
652
653 /* here is power save alg, when this beacon is DTIM
654 * we will set sleep time to dtim_period * n;
655 * when this beacon is not DTIM, we will set sleep
656 * time to sleep_intv = rtlpriv->psc.dtim_counter or
657 * MAX_SW_LPS_SLEEP_INTV(default set to 5) */
658
659/*<delete in kernel start>*/
660#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35))
661/*<delete in kernel end>*/
662 if (rtlpriv->psc.dtim_counter == 0) {
663 if (hw->conf.ps_dtim_period == 1)
664 sleep_intv = hw->conf.ps_dtim_period * 2;
665 else
666 sleep_intv = hw->conf.ps_dtim_period;
667 } else {
668 sleep_intv = rtlpriv->psc.dtim_counter;
669 }
670/*<delete in kernel start>*/
671#else
672 if (rtlpriv->psc.dtim_counter == 0) {
673 if (mac->vif->bss_conf.dtim_period == 1)
674 sleep_intv = mac->vif->bss_conf.dtim_period * 2;
675 else
676 sleep_intv = mac->vif->bss_conf.dtim_period;
677 } else {
678 sleep_intv = rtlpriv->psc.dtim_counter;
679 }
680#endif
681/*<delete in kernel end>*/
682
683 if (sleep_intv > MAX_SW_LPS_SLEEP_INTV)
684 sleep_intv = MAX_SW_LPS_SLEEP_INTV;
685
686 /* this print should always be dtim_conter = 0 &
687 * sleep = dtim_period, that meaons, we should
688 * awake before every dtim */
689 RT_TRACE(COMP_POWER, DBG_DMESG,
690 ("dtim_counter:%x will sleep :%d beacon_intv\n",
691 rtlpriv->psc.dtim_counter, sleep_intv));
692
693 /* we tested that 40ms is enough for sw & hw sw delay */
694 queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.ps_rfon_wq,
695 MSECS(sleep_intv * mac->vif->bss_conf.beacon_int - 40));
696}
697
698
699void rtl_swlps_wq_callback(void *data)
700{
701 struct rtl_works *rtlworks =
702 container_of_dwork_rtl(data, struct rtl_works, ps_work);
703 struct ieee80211_hw *hw = rtlworks->hw;
704 struct rtl_priv *rtlpriv = rtl_priv(hw);
705 bool ps = false;
706
707 ps = (hw->conf.flags & IEEE80211_CONF_PS);
708
709 /* we can sleep after ps null send ok */
710 if (rtlpriv->psc.state_inap) {
711 rtl_swlps_rf_sleep(hw);
712
713 if (rtlpriv->psc.state && !ps) {
714 rtlpriv->psc.sleep_ms =
715 jiffies_to_msecs(jiffies -
716 rtlpriv->psc.last_action);
717 }
718
719 if (ps)
720 rtlpriv->psc.last_slept = jiffies;
721
722 rtlpriv->psc.last_action = jiffies;
723 rtlpriv->psc.state = ps;
724 }
725}
726
727
728void rtl_p2p_noa_ie(struct ieee80211_hw *hw, void *data, unsigned int len)
729{
730 struct rtl_priv *rtlpriv = rtl_priv(hw);
731 struct ieee80211_mgmt *mgmt = (void *)data;
732 struct rtl_p2p_ps_info *p2pinfo = &(rtlpriv->psc.p2p_ps_info);
733 u8 *pos, *end, *ie;
734 u16 noa_len;
735 static u8 p2p_oui_ie_type[4] = {0x50, 0x6f, 0x9a, 0x09};
736 u8 noa_num, index,i, noa_index = 0;
737 bool find_p2p_ie = false , find_p2p_ps_ie = false;
738 pos = (u8 *)mgmt->u.beacon.variable;
739 end = data + len;
740 ie = NULL;
741
742 while (pos + 1 < end) {
743
744 if (pos + 2 + pos[1] > end)
745 return;
746
747 if (pos[0] == 221 && pos[1] > 4) {
748 if (memcmp(&pos[2], p2p_oui_ie_type, 4) == 0) {
749 ie = pos + 2+4;
750 break;
751 }
752 }
753 pos += 2 + pos[1];
754 }
755
756 if (ie == NULL)
757 return;
758 find_p2p_ie = true;
759 /*to find noa ie*/
760 while (ie + 1 < end) {
761 noa_len = READEF2BYTE(&ie[1]);
762 if (ie + 3 + ie[1] > end)
763 return;
764
765 if (ie[0] == 12) {
766 find_p2p_ps_ie = true;
767 if ( (noa_len - 2) % 13 != 0){
768 RT_TRACE(COMP_INIT, DBG_LOUD,
769 ("P2P notice of absence: "
770 "invalid length.%d\n",noa_len));
771 return;
772 } else {
773 noa_num = (noa_len - 2) / 13;
774 }
775 noa_index = ie[3];
776 if (rtlpriv->psc.p2p_ps_info.p2p_ps_mode == P2P_PS_NONE
777 || noa_index != p2pinfo->noa_index) {
778 RT_TRACE(COMP_FW, DBG_LOUD,
779 ("update NOA ie.\n"));
780 p2pinfo->noa_index = noa_index;
781 p2pinfo->opp_ps= (ie[4] >> 7);
782 p2pinfo->ctwindow = ie[4] & 0x7F;
783 p2pinfo->noa_num = noa_num;
784 index = 5;
785 for (i = 0; i< noa_num; i++){
786 p2pinfo->noa_count_type[i] =
787 READEF1BYTE(ie+index);
788 index += 1;
789 p2pinfo->noa_duration[i] =
790 READEF4BYTE(ie+index);
791 index += 4;
792 p2pinfo->noa_interval[i] =
793 READEF4BYTE(ie+index);
794 index += 4;
795 p2pinfo->noa_start_time[i] =
796 READEF4BYTE(ie+index);
797 index += 4;
798 }
799
800 if (p2pinfo->opp_ps == 1) {
801 p2pinfo->p2p_ps_mode = P2P_PS_CTWINDOW;
802 /* Driver should wait LPS
803 * entering CTWindow*/
804 if (rtlpriv->psc.b_fw_current_inpsmode){
805 rtl_p2p_ps_cmd(hw,
806 P2P_PS_ENABLE);
807 }
808 } else if (p2pinfo->noa_num > 0) {
809 p2pinfo->p2p_ps_mode = P2P_PS_NOA;
810 rtl_p2p_ps_cmd(hw, P2P_PS_ENABLE);
811 } else if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
812 rtl_p2p_ps_cmd(hw, P2P_PS_DISABLE);
813 }
814 }
815
816 break;
817 }
818 ie += 3 + noa_len;
819 }
820
821 if (find_p2p_ie == true) {
822 if ((p2pinfo->p2p_ps_mode > P2P_PS_NONE) &&
823 (find_p2p_ps_ie == false))
824 rtl_p2p_ps_cmd(hw, P2P_PS_DISABLE);
825 }
826}
827
828void rtl_p2p_action_ie(struct ieee80211_hw *hw, void *data, unsigned int len)
829{
830 struct rtl_priv *rtlpriv = rtl_priv(hw);
831 struct ieee80211_mgmt *mgmt = (void *)data;
832 struct rtl_p2p_ps_info *p2pinfo = &(rtlpriv->psc.p2p_ps_info);
833 bool find_p2p_ie = false , find_p2p_ps_ie = false;
834 u8 noa_num, index,i, noa_index = 0;
835 u8 *pos, *end, *ie;
836 u16 noa_len;
837 static u8 p2p_oui_ie_type[4] = {0x50, 0x6f, 0x9a, 0x09};
838
839 pos = (u8 *) &mgmt->u.action.category;
840 end = data + len;
841 ie = NULL;
842
843 if (pos[0] == 0x7f ) {
844 if (memcmp(&pos[1], p2p_oui_ie_type, 4) == 0) {
845 ie = pos + 3+4;
846 }
847 }
848
849 if (ie == NULL)
850 return;
851 find_p2p_ie = true;
852
853 RT_TRACE(COMP_FW, DBG_LOUD, ("action frame find P2P IE.\n"));
854 /*to find noa ie*/
855 while (ie + 1 < end) {
856 noa_len = READEF2BYTE(&ie[1]);
857 if (ie + 3 + ie[1] > end)
858 return;
859
860 if (ie[0] == 12) {
861 RT_TRACE(COMP_FW, DBG_LOUD, ("find NOA IE.\n"));
862 RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_LOUD, ("noa ie "),
863 ie, noa_len);
864 find_p2p_ps_ie = true;
865 if ( (noa_len - 2) % 13 != 0){
866 RT_TRACE(COMP_FW, DBG_LOUD,
867 ("P2P notice of absence: "
868 "invalid length.%d\n",noa_len));
869 return;
870 } else {
871 noa_num = (noa_len - 2) / 13;
872 }
873 noa_index = ie[3];
874 if (rtlpriv->psc.p2p_ps_info.p2p_ps_mode == P2P_PS_NONE
875 || noa_index != p2pinfo->noa_index) {
876 p2pinfo->noa_index = noa_index;
877 p2pinfo->opp_ps= (ie[4] >> 7);
878 p2pinfo->ctwindow = ie[4] & 0x7F;
879 p2pinfo->noa_num = noa_num;
880 index = 5;
881 for (i = 0; i< noa_num; i++){
882 p2pinfo->noa_count_type[i] =
883 READEF1BYTE(ie+index);
884 index += 1;
885 p2pinfo->noa_duration[i] =
886 READEF4BYTE(ie+index);
887 index += 4;
888 p2pinfo->noa_interval[i] =
889 READEF4BYTE(ie+index);
890 index += 4;
891 p2pinfo->noa_start_time[i] =
892 READEF4BYTE(ie+index);
893 index += 4;
894 }
895
896 if (p2pinfo->opp_ps == 1) {
897 p2pinfo->p2p_ps_mode = P2P_PS_CTWINDOW;
898 /* Driver should wait LPS
899 * entering CTWindow */
900 if (rtlpriv->psc.b_fw_current_inpsmode){
901 rtl_p2p_ps_cmd(hw,
902 P2P_PS_ENABLE);
903 }
904 } else if (p2pinfo->noa_num > 0) {
905 p2pinfo->p2p_ps_mode = P2P_PS_NOA;
906 rtl_p2p_ps_cmd(hw, P2P_PS_ENABLE);
907 } else if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
908 rtl_p2p_ps_cmd(hw, P2P_PS_DISABLE);
909 }
910 }
911
912 break;
913 }
914 ie += 3 + noa_len;
915 }
916
917
918}
919
920
921void rtl_p2p_ps_cmd(struct ieee80211_hw *hw,u8 p2p_ps_state)
922{
923 struct rtl_priv *rtlpriv = rtl_priv(hw);
924 struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
925 struct rtl_p2p_ps_info *p2pinfo = &(rtlpriv->psc.p2p_ps_info);
926
927 RT_TRACE(COMP_FW, DBG_LOUD, (" p2p state %x\n",p2p_ps_state));
928 switch (p2p_ps_state) {
929 case P2P_PS_DISABLE:
930 p2pinfo->p2p_ps_state = p2p_ps_state;
931 rtlpriv->cfg->ops->set_hw_reg(hw,
932 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
933 (u8 *)(&p2p_ps_state));
934
935 p2pinfo->noa_index = 0;
936 p2pinfo->ctwindow = 0;
937 p2pinfo->opp_ps = 0;
938 p2pinfo->noa_num = 0;
939 p2pinfo->p2p_ps_mode = P2P_PS_NONE;
940 if (rtlps->b_fw_current_inpsmode == true) {
941 if (rtlps->smart_ps == 0) {
942 rtlps->smart_ps = 2;
943 rtlpriv->cfg->ops->set_hw_reg(hw,
944 HW_VAR_H2C_FW_PWRMODE,
945 (u8 *)(&rtlps->pwr_mode));
946 }
947
948 }
949 break;
950 case P2P_PS_ENABLE:
951 if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
952 p2pinfo->p2p_ps_state = p2p_ps_state;
953
954 if (p2pinfo->ctwindow > 0) {
955 if (rtlps->smart_ps != 0){
956 rtlps->smart_ps = 0;
957 rtlpriv->cfg->ops->set_hw_reg(
958 hw, HW_VAR_H2C_FW_PWRMODE,
959 (u8 *)(&rtlps->pwr_mode));
960 }
961 }
962 rtlpriv->cfg->ops->set_hw_reg(hw,
963 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
964 (u8 *)(&p2p_ps_state));
965
966 }
967 break;
968 case P2P_PS_SCAN:
969 case P2P_PS_SCAN_DONE:
970 case P2P_PS_ALLSTASLEEP:
971 if (p2pinfo->p2p_ps_mode > P2P_PS_NONE) {
972 p2pinfo->p2p_ps_state = p2p_ps_state;
973 rtlpriv->cfg->ops->set_hw_reg(hw,
974 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
975 (u8 *)(&p2p_ps_state));
976 }
977 break;
978 default:
979 break;
980
981 }
982 RT_TRACE(COMP_FW, DBG_LOUD, (" ctwindow %x oppps %x \n",
983 p2pinfo->ctwindow,p2pinfo->opp_ps));
984 RT_TRACE(COMP_FW, DBG_LOUD, ("count %x duration %x index %x interval %x"
985 " start time %x noa num %x\n",
986 p2pinfo->noa_count_type[0],
987 p2pinfo->noa_duration[0],
988 p2pinfo->noa_index,
989 p2pinfo->noa_interval[0],
990 p2pinfo->noa_start_time[0],
991 p2pinfo->noa_num));
992 RT_TRACE(COMP_FW, DBG_LOUD, ("end\n"));
993}
994
995void rtl_p2p_info(struct ieee80211_hw *hw, void *data, unsigned int len)
996{
997 struct rtl_priv *rtlpriv = rtl_priv(hw);
998 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
999 struct ieee80211_hdr *hdr = (void *) data;
1000
1001 if (!mac->p2p)
1002 return;
1003 if (mac->link_state != MAC80211_LINKED)
1004 return;
1005 /* min. beacon length + FCS_LEN */
1006 if (len <= 40 + FCS_LEN)
1007 return;
1008
1009 /* and only beacons from the associated BSSID, please */
1010 if (ether_addr_equal(hdr->addr3, rtlpriv->mac80211.bssid))
1011 return;
1012
1013 /* check if this really is a beacon */
1014 if (!(ieee80211_is_beacon(hdr->frame_control) ||
1015 ieee80211_is_probe_resp(hdr->frame_control) ||
1016 ieee80211_is_action(hdr->frame_control)))
1017 return;
1018
1019 if (ieee80211_is_action(hdr->frame_control)) {
1020 rtl_p2p_action_ie(hw,data,len - FCS_LEN);
1021 } else {
1022 rtl_p2p_noa_ie(hw,data,len - FCS_LEN);
1023 }
1024
1025}
diff --git a/drivers/staging/rtl8821ae/ps.h b/drivers/staging/rtl8821ae/ps.h
new file mode 100644
index 000000000000..374ed77c4126
--- /dev/null
+++ b/drivers/staging/rtl8821ae/ps.h
@@ -0,0 +1,55 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __REALTEK_RTL_PCI_PS_H__
31#define __REALTEK_RTL_PCI_PS_H__
32
33#define MAX_SW_LPS_SLEEP_INTV 5
34
35bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
36 enum rf_pwrstate state_toset, u32 changesource,
37 bool protect_or_not);
38bool rtl_ps_enable_nic(struct ieee80211_hw *hw);
39bool rtl_ps_disable_nic(struct ieee80211_hw *hw);
40void rtl_ips_nic_off(struct ieee80211_hw *hw);
41void rtl_ips_nic_on(struct ieee80211_hw *hw);
42void rtl_ips_nic_off_wq_callback(void *data);
43void rtl_lps_enter(struct ieee80211_hw *hw);
44void rtl_lps_leave(struct ieee80211_hw *hw);
45
46void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode);
47
48void rtl_swlps_beacon(struct ieee80211_hw *hw, void *data, unsigned int len);
49void rtl_swlps_wq_callback(void *data);
50void rtl_swlps_rfon_wq_callback(void *data);
51void rtl_swlps_rf_awake(struct ieee80211_hw *hw);
52void rtl_swlps_rf_sleep(struct ieee80211_hw *hw);
53void rtl_p2p_ps_cmd(struct ieee80211_hw *hw,u8 p2p_ps_state);
54void rtl_p2p_info(struct ieee80211_hw *hw, void *data, unsigned int len);
55#endif
diff --git a/drivers/staging/rtl8821ae/rc.c b/drivers/staging/rtl8821ae/rc.c
new file mode 100644
index 000000000000..d387f13ea7dc
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rc.c
@@ -0,0 +1,309 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "base.h"
32#include "rc.h"
33
34/*
35 *Finds the highest rate index we can use
36 *if skb is special data like DHCP/EAPOL, we set should
37 *it to lowest rate CCK_1M, otherwise we set rate to
38 *highest rate based on wireless mode used for iwconfig
39 *show Tx rate.
40 */
41static u8 _rtl_rc_get_highest_rix(struct rtl_priv *rtlpriv,
42 struct ieee80211_sta *sta,
43 struct sk_buff *skb, bool not_data)
44{
45 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
46 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
47 struct rtl_phy *rtlphy = &(rtlpriv->phy);
48 struct rtl_sta_info *sta_entry = NULL;
49 u8 wireless_mode = 0;
50
51 /*
52 *this rate is no use for true rate, firmware
53 *will control rate at all it just used for
54 *1.show in iwconfig in B/G mode
55 *2.in rtl_get_tcb_desc when we check rate is
56 * 1M we will not use FW rate but user rate.
57 */
58 if (rtlmac->opmode == NL80211_IFTYPE_AP ||
59 rtlmac->opmode == NL80211_IFTYPE_ADHOC ||
60 rtlmac->opmode == NL80211_IFTYPE_MESH_POINT) {
61 if (sta) {
62 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
63 wireless_mode = sta_entry->wireless_mode;
64 } else {
65 return 0;
66 }
67 } else {
68 wireless_mode = rtlmac->mode;
69 }
70
71 if (rtl_is_special_data(rtlpriv->mac80211.hw, skb, true) || not_data) {
72 return 0;
73 } else {
74 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
75 if (wireless_mode == WIRELESS_MODE_B) {
76 return B_MODE_MAX_RIX;
77 } else if (wireless_mode == WIRELESS_MODE_G) {
78 return G_MODE_MAX_RIX;
79 } else {
80 if (get_rf_type(rtlphy) != RF_2T2R)
81 return N_MODE_MCS7_RIX;
82 else
83 return N_MODE_MCS15_RIX;
84 }
85 } else {
86 if (wireless_mode == WIRELESS_MODE_A) {
87 return A_MODE_MAX_RIX;
88 } else {
89 if (get_rf_type(rtlphy) != RF_2T2R)
90 return N_MODE_MCS7_RIX;
91 else
92 return N_MODE_MCS15_RIX;
93 }
94 }
95 }
96}
97
98static void _rtl_rc_rate_set_series(struct rtl_priv *rtlpriv,
99 struct ieee80211_sta *sta,
100 struct ieee80211_tx_rate *rate,
101 struct ieee80211_tx_rate_control *txrc,
102 u8 tries, char rix, int rtsctsenable,
103 bool not_data)
104{
105 struct rtl_mac *mac = rtl_mac(rtlpriv);
106 u8 sgi_20 = 0, sgi_40 = 0;
107
108 if (sta) {
109 sgi_20 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20;
110 sgi_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40;
111 }
112 rate->count = tries;
113 rate->idx = rix >= 0x00 ? rix : 0x00;
114
115 if (!not_data) {
116 if (txrc->short_preamble)
117 rate->flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
118 if (mac->opmode == NL80211_IFTYPE_AP ||
119 mac->opmode == NL80211_IFTYPE_ADHOC) {
120 if (sta && (sta->ht_cap.cap &
121 IEEE80211_HT_CAP_SUP_WIDTH_20_40))
122 rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
123 } else {
124 if (mac->bw_40)
125 rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
126 }
127 if (sgi_20 || sgi_40)
128 rate->flags |= IEEE80211_TX_RC_SHORT_GI;
129 if (sta && sta->ht_cap.ht_supported)
130 rate->flags |= IEEE80211_TX_RC_MCS;
131 }
132}
133
134static void rtl_get_rate(void *ppriv, struct ieee80211_sta *sta,
135 void *priv_sta,
136 struct ieee80211_tx_rate_control *txrc)
137{
138 struct rtl_priv *rtlpriv = ppriv;
139 struct sk_buff *skb = txrc->skb;
140 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
141 struct ieee80211_tx_rate *rates = tx_info->control.rates;
142 __le16 fc = rtl_get_fc(skb);
143 u8 try_per_rate, i, rix;
144 bool not_data = !ieee80211_is_data(fc);
145
146 if (rate_control_send_low(sta, priv_sta, txrc))
147 return;
148
149 rix = _rtl_rc_get_highest_rix(rtlpriv, sta, skb, not_data);
150 try_per_rate = 1;
151 _rtl_rc_rate_set_series(rtlpriv, sta, &rates[0], txrc,
152 try_per_rate, rix, 1, not_data);
153
154 if (!not_data) {
155 for (i = 1; i < 4; i++)
156 _rtl_rc_rate_set_series(rtlpriv, sta, &rates[i],
157 txrc, i, (rix - i), 1,
158 not_data);
159 }
160}
161
162static bool _rtl_tx_aggr_check(struct rtl_priv *rtlpriv,
163 struct rtl_sta_info *sta_entry, u16 tid)
164{
165 struct rtl_mac *mac = rtl_mac(rtlpriv);
166
167 if (mac->act_scanning)
168 return false;
169
170 if (mac->opmode == NL80211_IFTYPE_STATION &&
171 mac->cnt_after_linked < 3)
172 return false;
173
174 if (sta_entry->tids[tid].agg.agg_state == RTL_AGG_STOP)
175 return true;
176
177 return false;
178}
179
180/*mac80211 Rate Control callbacks*/
181static void rtl_tx_status(void *ppriv,
182 struct ieee80211_supported_band *sband,
183 struct ieee80211_sta *sta, void *priv_sta,
184 struct sk_buff *skb)
185{
186 struct rtl_priv *rtlpriv = ppriv;
187 struct rtl_mac *mac = rtl_mac(rtlpriv);
188 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
189 __le16 fc = rtl_get_fc(skb);
190 struct rtl_sta_info *sta_entry;
191
192 if (!priv_sta || !ieee80211_is_data(fc))
193 return;
194
195 if (rtl_is_special_data(mac->hw, skb, true))
196 return;
197
198 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
199 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
200 return;
201
202 if (sta) {
203 /* Check if aggregation has to be enabled for this tid */
204 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
205 if ((sta->ht_cap.ht_supported == true) &&
206 !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
207 if (ieee80211_is_data_qos(fc)) {
208 u8 tid = rtl_get_tid(skb);
209 if (_rtl_tx_aggr_check(rtlpriv, sta_entry,
210 tid)) {
211 sta_entry->tids[tid].agg.agg_state =
212 RTL_AGG_PROGRESS;
213 /*<delete in kernel start>*/
214#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38))
215 /*<delete in kernel end>*/
216 ieee80211_start_tx_ba_session(sta, tid,
217 5000);
218 /*<delete in kernel start>*/
219#else
220 ieee80211_start_tx_ba_session(sta, tid);
221#endif
222 /*<delete in kernel end>*/
223 }
224 }
225 }
226 }
227}
228
229static void rtl_rate_init(void *ppriv,
230 struct ieee80211_supported_band *sband,
231 struct cfg80211_chan_def *chandef,
232 struct ieee80211_sta *sta, void *priv_sta)
233{
234}
235#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0))
236static void rtl_rate_update(void *ppriv,
237 struct ieee80211_supported_band *sband,
238 struct ieee80211_sta *sta, void *priv_sta,
239 u32 changed,
240 enum nl80211_channel_type oper_chan_type)
241{
242}
243#else
244static void rtl_rate_update(void *ppriv,
245 struct ieee80211_supported_band *sband,
246 struct cfg80211_chan_def *chandef,
247 struct ieee80211_sta *sta, void *priv_sta,
248 u32 changed)
249{
250}
251#endif
252static void *rtl_rate_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)
253{
254 struct rtl_priv *rtlpriv = rtl_priv(hw);
255 return rtlpriv;
256}
257
258static void rtl_rate_free(void *rtlpriv)
259{
260 return;
261}
262
263static void *rtl_rate_alloc_sta(void *ppriv,
264 struct ieee80211_sta *sta, gfp_t gfp)
265{
266 struct rtl_priv *rtlpriv = ppriv;
267 struct rtl_rate_priv *rate_priv;
268
269 rate_priv = kzalloc(sizeof(struct rtl_rate_priv), gfp);
270 if (!rate_priv) {
271 RT_TRACE(COMP_ERR, DBG_EMERG,
272 ("Unable to allocate private rc structure\n"));
273 return NULL;
274 }
275
276 rtlpriv->rate_priv = rate_priv;
277
278 return rate_priv;
279}
280
281static void rtl_rate_free_sta(void *rtlpriv,
282 struct ieee80211_sta *sta, void *priv_sta)
283{
284 struct rtl_rate_priv *rate_priv = priv_sta;
285 kfree(rate_priv);
286}
287
288static struct rate_control_ops rtl_rate_ops = {
289 .module = NULL,
290 .name = "rtl_rc",
291 .alloc = rtl_rate_alloc,
292 .free = rtl_rate_free,
293 .alloc_sta = rtl_rate_alloc_sta,
294 .free_sta = rtl_rate_free_sta,
295 .rate_init = rtl_rate_init,
296 .rate_update = rtl_rate_update,
297 .tx_status = rtl_tx_status,
298 .get_rate = rtl_get_rate,
299};
300
301int rtl_rate_control_register(void)
302{
303 return ieee80211_rate_control_register(&rtl_rate_ops);
304}
305
306void rtl_rate_control_unregister(void)
307{
308 ieee80211_rate_control_unregister(&rtl_rate_ops);
309}
diff --git a/drivers/staging/rtl8821ae/rc.h b/drivers/staging/rtl8821ae/rc.h
new file mode 100644
index 000000000000..4afa2c20adcf
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rc.h
@@ -0,0 +1,47 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_RC_H__
31#define __RTL_RC_H__
32
33#define B_MODE_MAX_RIX 3
34#define G_MODE_MAX_RIX 11
35#define A_MODE_MAX_RIX 7
36
37/* in mac80211 mcs0-mcs15 is idx0-idx15*/
38#define N_MODE_MCS7_RIX 7
39#define N_MODE_MCS15_RIX 15
40
41struct rtl_rate_priv {
42 u8 ht_cap;
43};
44
45int rtl_rate_control_register(void);
46void rtl_rate_control_unregister(void);
47#endif
diff --git a/drivers/staging/rtl8821ae/regd.c b/drivers/staging/rtl8821ae/regd.c
new file mode 100644
index 000000000000..d89f15cb8089
--- /dev/null
+++ b/drivers/staging/rtl8821ae/regd.c
@@ -0,0 +1,503 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "wifi.h"
31#include "regd.h"
32
33static struct country_code_to_enum_rd allCountries[] = {
34 {COUNTRY_CODE_FCC, "US"},
35 {COUNTRY_CODE_IC, "US"},
36 {COUNTRY_CODE_ETSI, "EC"},
37 {COUNTRY_CODE_SPAIN, "EC"},
38 {COUNTRY_CODE_FRANCE, "EC"},
39 {COUNTRY_CODE_MKK, "JP"},
40 {COUNTRY_CODE_MKK1, "JP"},
41 {COUNTRY_CODE_ISRAEL, "EC"},
42 {COUNTRY_CODE_TELEC, "JP"},
43 {COUNTRY_CODE_MIC, "JP"},
44 {COUNTRY_CODE_GLOBAL_DOMAIN, "JP"},
45 {COUNTRY_CODE_WORLD_WIDE_13, "EC"},
46 {COUNTRY_CODE_TELEC_NETGEAR, "EC"},
47};
48
49/*
50 *Only these channels all allow active
51 *scan on all world regulatory domains
52 */
53#define RTL819x_2GHZ_CH01_11 \
54 REG_RULE(2412-10, 2462+10, 40, 0, 20, 0)
55
56/*
57 *We enable active scan on these a case
58 *by case basis by regulatory domain
59 */
60#define RTL819x_2GHZ_CH12_13 \
61 REG_RULE(2467-10, 2472+10, 40, 0, 20,\
62 NL80211_RRF_PASSIVE_SCAN)
63
64#define RTL819x_2GHZ_CH14 \
65 REG_RULE(2484-10, 2484+10, 40, 0, 20, \
66 NL80211_RRF_PASSIVE_SCAN | \
67 NL80211_RRF_NO_OFDM)
68
69/* 5G chan 36 - chan 64*/
70#define RTL819x_5GHZ_5150_5350 \
71 REG_RULE(5150-10, 5350+10, 40, 0, 30, \
72 NL80211_RRF_PASSIVE_SCAN | \
73 NL80211_RRF_NO_IBSS)
74
75/* 5G chan 100 - chan 165*/
76#define RTL819x_5GHZ_5470_5850 \
77 REG_RULE(5470-10, 5850+10, 40, 0, 30, \
78 NL80211_RRF_PASSIVE_SCAN | \
79 NL80211_RRF_NO_IBSS)
80
81/* 5G chan 149 - chan 165*/
82#define RTL819x_5GHZ_5725_5850 \
83 REG_RULE(5725-10, 5850+10, 40, 0, 30, \
84 NL80211_RRF_PASSIVE_SCAN | \
85 NL80211_RRF_NO_IBSS)
86
87#define RTL819x_5GHZ_ALL \
88 RTL819x_5GHZ_5150_5350, RTL819x_5GHZ_5470_5850
89
90static const struct ieee80211_regdomain rtl_regdom_11 = {
91 .n_reg_rules = 1,
92 .alpha2 = "99",
93 .reg_rules = {
94 RTL819x_2GHZ_CH01_11,
95 }
96};
97
98static const struct ieee80211_regdomain rtl_regdom_12_13 = {
99 .n_reg_rules = 2,
100 .alpha2 = "99",
101 .reg_rules = {
102 RTL819x_2GHZ_CH01_11,
103 RTL819x_2GHZ_CH12_13,
104 }
105};
106
107static const struct ieee80211_regdomain rtl_regdom_no_midband = {
108 .n_reg_rules = 3,
109 .alpha2 = "99",
110 .reg_rules = {
111 RTL819x_2GHZ_CH01_11,
112 RTL819x_5GHZ_5150_5350,
113 RTL819x_5GHZ_5725_5850,
114 }
115};
116
117static const struct ieee80211_regdomain rtl_regdom_60_64 = {
118 .n_reg_rules = 3,
119 .alpha2 = "99",
120 .reg_rules = {
121 RTL819x_2GHZ_CH01_11,
122 RTL819x_2GHZ_CH12_13,
123 RTL819x_5GHZ_5725_5850,
124 }
125};
126
127static const struct ieee80211_regdomain rtl_regdom_14_60_64 = {
128 .n_reg_rules = 4,
129 .alpha2 = "99",
130 .reg_rules = {
131 RTL819x_2GHZ_CH01_11,
132 RTL819x_2GHZ_CH12_13,
133 RTL819x_2GHZ_CH14,
134 RTL819x_5GHZ_5725_5850,
135 }
136};
137
138static const struct ieee80211_regdomain rtl_regdom_14 = {
139 .n_reg_rules = 3,
140 .alpha2 = "99",
141 .reg_rules = {
142 RTL819x_2GHZ_CH01_11,
143 RTL819x_2GHZ_CH12_13,
144 RTL819x_2GHZ_CH14,
145 }
146};
147
148static bool _rtl_is_radar_freq(u16 center_freq)
149{
150 return (center_freq >= 5260 && center_freq <= 5700);
151}
152
153static void _rtl_reg_apply_beaconing_flags(struct wiphy *wiphy,
154 enum nl80211_reg_initiator initiator)
155{
156 enum ieee80211_band band;
157 struct ieee80211_supported_band *sband;
158 const struct ieee80211_reg_rule *reg_rule;
159 struct ieee80211_channel *ch;
160 unsigned int i;
161#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0))
162 u32 bandwidth = 0;
163 int r;
164#endif
165
166 for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
167
168 if (!wiphy->bands[band])
169 continue;
170
171 sband = wiphy->bands[band];
172
173 for (i = 0; i < sband->n_channels; i++) {
174 ch = &sband->channels[i];
175 if (_rtl_is_radar_freq(ch->center_freq) ||
176 (ch->flags & IEEE80211_CHAN_RADAR))
177 continue;
178 if (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) {
179#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
180 reg_rule = freq_reg_info(wiphy, ch->center_freq);
181 if (IS_ERR(reg_rule))
182 continue;
183#else
184 r = freq_reg_info(wiphy, ch->center_freq,
185 bandwidth, &reg_rule);
186 if (r)
187 continue;
188#endif
189
190 /*
191 *If 11d had a rule for this channel ensure
192 *we enable adhoc/beaconing if it allows us to
193 *use it. Note that we would have disabled it
194 *by applying our static world regdomain by
195 *default during init, prior to calling our
196 *regulatory_hint().
197 */
198
199 if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
200 ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
201 if (!(reg_rule->flags &
202 NL80211_RRF_PASSIVE_SCAN))
203 ch->flags &=
204 ~IEEE80211_CHAN_PASSIVE_SCAN;
205 } else {
206 if (ch->beacon_found)
207 ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
208 IEEE80211_CHAN_PASSIVE_SCAN);
209 }
210 }
211 }
212}
213
214/* Allows active scan scan on Ch 12 and 13 */
215static void _rtl_reg_apply_active_scan_flags(struct wiphy *wiphy,
216 enum nl80211_reg_initiator
217 initiator)
218{
219 struct ieee80211_supported_band *sband;
220 struct ieee80211_channel *ch;
221 const struct ieee80211_reg_rule *reg_rule;
222#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0))
223 u32 bandwidth = 0;
224 int r;
225#endif
226
227 if (!wiphy->bands[IEEE80211_BAND_2GHZ])
228 return;
229 sband = wiphy->bands[IEEE80211_BAND_2GHZ];
230
231 /*
232 *If no country IE has been received always enable active scan
233 *on these channels. This is only done for specific regulatory SKUs
234 */
235 if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
236 ch = &sband->channels[11]; /* CH 12 */
237 if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
238 ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
239 ch = &sband->channels[12]; /* CH 13 */
240 if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
241 ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
242 return;
243 }
244
245 /*
246 *If a country IE has been recieved check its rule for this
247 *channel first before enabling active scan. The passive scan
248 *would have been enforced by the initial processing of our
249 *custom regulatory domain.
250 */
251
252 ch = &sband->channels[11]; /* CH 12 */
253#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
254 reg_rule = freq_reg_info(wiphy, ch->center_freq);
255 if (!IS_ERR(reg_rule)) {
256#else
257 r = freq_reg_info(wiphy, ch->center_freq, bandwidth, &reg_rule);
258 if (!r) {
259#endif
260 if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
261 if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
262 ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
263 }
264
265 ch = &sband->channels[12]; /* CH 13 */
266#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
267 reg_rule = freq_reg_info(wiphy, ch->center_freq);
268 if (!IS_ERR(reg_rule)) {
269#else
270 r = freq_reg_info(wiphy, ch->center_freq, bandwidth, &reg_rule);
271 if (!r) {
272#endif
273 if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
274 if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
275 ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
276 }
277}
278
279/*
280 *Always apply Radar/DFS rules on
281 *freq range 5260 MHz - 5700 MHz
282 */
283static void _rtl_reg_apply_radar_flags(struct wiphy *wiphy)
284{
285 struct ieee80211_supported_band *sband;
286 struct ieee80211_channel *ch;
287 unsigned int i;
288
289 if (!wiphy->bands[IEEE80211_BAND_5GHZ])
290 return;
291
292 sband = wiphy->bands[IEEE80211_BAND_5GHZ];
293
294 for (i = 0; i < sband->n_channels; i++) {
295 ch = &sband->channels[i];
296 if (!_rtl_is_radar_freq(ch->center_freq))
297 continue;
298
299 /*
300 *We always enable radar detection/DFS on this
301 *frequency range. Additionally we also apply on
302 *this frequency range:
303 *- If STA mode does not yet have DFS supports disable
304 * active scanning
305 *- If adhoc mode does not support DFS yet then disable
306 * adhoc in the frequency.
307 *- If AP mode does not yet support radar detection/DFS
308 *do not allow AP mode
309 */
310 if (!(ch->flags & IEEE80211_CHAN_DISABLED))
311 ch->flags |= IEEE80211_CHAN_RADAR |
312 IEEE80211_CHAN_NO_IBSS |
313 IEEE80211_CHAN_PASSIVE_SCAN;
314 }
315}
316
317static void _rtl_reg_apply_world_flags(struct wiphy *wiphy,
318 enum nl80211_reg_initiator initiator,
319 struct rtl_regulatory *reg)
320{
321 _rtl_reg_apply_beaconing_flags(wiphy, initiator);
322 _rtl_reg_apply_active_scan_flags(wiphy, initiator);
323 return;
324}
325
326static void _rtl_dump_channel_map(struct wiphy *wiphy)
327{
328 enum ieee80211_band band;
329 struct ieee80211_supported_band *sband;
330 struct ieee80211_channel *ch;
331 unsigned int i;
332
333 for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
334 if (!wiphy->bands[band])
335 continue;
336 sband = wiphy->bands[band];
337 for (i = 0; i < sband->n_channels; i++)
338 ch = &sband->channels[i];
339 }
340}
341
342static int _rtl_reg_notifier_apply(struct wiphy *wiphy,
343 struct regulatory_request *request,
344 struct rtl_regulatory *reg)
345{
346 /* We always apply this */
347 _rtl_reg_apply_radar_flags(wiphy);
348
349 switch (request->initiator) {
350 case NL80211_REGDOM_SET_BY_DRIVER:
351 case NL80211_REGDOM_SET_BY_CORE:
352 case NL80211_REGDOM_SET_BY_USER:
353 break;
354 case NL80211_REGDOM_SET_BY_COUNTRY_IE:
355 _rtl_reg_apply_world_flags(wiphy, request->initiator, reg);
356 break;
357 }
358
359 _rtl_dump_channel_map(wiphy);
360
361 return 0;
362}
363
364static const struct ieee80211_regdomain *_rtl_regdomain_select(
365 struct rtl_regulatory *reg)
366{
367 switch (reg->country_code) {
368 case COUNTRY_CODE_FCC:
369 return &rtl_regdom_no_midband;
370 case COUNTRY_CODE_IC:
371 return &rtl_regdom_11;
372 case COUNTRY_CODE_ETSI:
373 case COUNTRY_CODE_TELEC_NETGEAR:
374 return &rtl_regdom_60_64;
375 case COUNTRY_CODE_SPAIN:
376 case COUNTRY_CODE_FRANCE:
377 case COUNTRY_CODE_ISRAEL:
378 case COUNTRY_CODE_WORLD_WIDE_13:
379 return &rtl_regdom_12_13;
380 case COUNTRY_CODE_MKK:
381 case COUNTRY_CODE_MKK1:
382 case COUNTRY_CODE_TELEC:
383 case COUNTRY_CODE_MIC:
384 return &rtl_regdom_14_60_64;
385 case COUNTRY_CODE_GLOBAL_DOMAIN:
386 return &rtl_regdom_14;
387 default:
388 return &rtl_regdom_no_midband;
389 }
390}
391
392#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
393static int _rtl_regd_init_wiphy(struct rtl_regulatory *reg,
394 struct wiphy *wiphy,
395 void (*reg_notifier) (struct wiphy * wiphy,
396 struct regulatory_request *
397 request))
398#else
399static int _rtl_regd_init_wiphy(struct rtl_regulatory *reg,
400 struct wiphy *wiphy,
401 int (*reg_notifier) (struct wiphy * wiphy,
402 struct regulatory_request *
403 request))
404#endif
405{
406 const struct ieee80211_regdomain *regd;
407
408 wiphy->reg_notifier = reg_notifier;
409
410 wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY;
411 wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY;
412 wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS;
413
414 regd = _rtl_regdomain_select(reg);
415 wiphy_apply_custom_regulatory(wiphy, regd);
416 _rtl_reg_apply_radar_flags(wiphy);
417 _rtl_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg);
418 return 0;
419}
420
421static struct country_code_to_enum_rd *_rtl_regd_find_country(u16 countrycode)
422{
423 int i;
424
425 for (i = 0; i < ARRAY_SIZE(allCountries); i++) {
426 if (allCountries[i].countrycode == countrycode)
427 return &allCountries[i];
428 }
429 return NULL;
430}
431
432#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
433int rtl_regd_init(struct ieee80211_hw *hw,
434 void (*reg_notifier) (struct wiphy *wiphy,
435 struct regulatory_request *request))
436#else
437int rtl_regd_init(struct ieee80211_hw *hw,
438 int (*reg_notifier) (struct wiphy *wiphy,
439 struct regulatory_request *request))
440#endif
441{
442 struct rtl_priv *rtlpriv = rtl_priv(hw);
443 struct wiphy *wiphy = hw->wiphy;
444 struct country_code_to_enum_rd *country = NULL;
445
446 if (wiphy == NULL || &rtlpriv->regd == NULL)
447 return -EINVAL;
448
449 /* init country_code from efuse channel plan */
450 rtlpriv->regd.country_code = rtlpriv->efuse.channel_plan;
451
452 RT_TRACE(COMP_REGD, DBG_TRACE,
453 (KERN_DEBUG "rtl: EEPROM regdomain: 0x%0x\n",
454 rtlpriv->regd.country_code));
455
456 if (rtlpriv->regd.country_code >= COUNTRY_CODE_MAX) {
457 RT_TRACE(COMP_REGD, DBG_DMESG,
458 (KERN_DEBUG "rtl: EEPROM indicates invalid contry code"
459 "world wide 13 should be used\n"));
460
461 rtlpriv->regd.country_code = COUNTRY_CODE_WORLD_WIDE_13;
462 }
463
464 country = _rtl_regd_find_country(rtlpriv->regd.country_code);
465
466 if (country) {
467 rtlpriv->regd.alpha2[0] = country->iso_name[0];
468 rtlpriv->regd.alpha2[1] = country->iso_name[1];
469 } else {
470 rtlpriv->regd.alpha2[0] = '0';
471 rtlpriv->regd.alpha2[1] = '0';
472 }
473
474 RT_TRACE(COMP_REGD, DBG_TRACE,
475 (KERN_DEBUG "rtl: Country alpha2 being used: %c%c\n",
476 rtlpriv->regd.alpha2[0], rtlpriv->regd.alpha2[1]));
477
478 _rtl_regd_init_wiphy(&rtlpriv->regd, wiphy, reg_notifier);
479
480 return 0;
481}
482
483#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
484void rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
485{
486 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
487 struct rtl_priv *rtlpriv = rtl_priv(hw);
488
489 RT_TRACE(COMP_REGD, DBG_LOUD, ("\n"));
490
491 _rtl_reg_notifier_apply(wiphy, request, &rtlpriv->regd);
492}
493#else
494int rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
495{
496 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
497 struct rtl_priv *rtlpriv = rtl_priv(hw);
498
499 RT_TRACE(COMP_REGD, DBG_LOUD, ("\n"));
500
501 return _rtl_reg_notifier_apply(wiphy, request, &rtlpriv->regd);
502}
503#endif
diff --git a/drivers/staging/rtl8821ae/regd.h b/drivers/staging/rtl8821ae/regd.h
new file mode 100644
index 000000000000..abc60ab8165c
--- /dev/null
+++ b/drivers/staging/rtl8821ae/regd.h
@@ -0,0 +1,75 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_REGD_H__
31#define __RTL_REGD_H__
32
33#define IEEE80211_CHAN_NO_IBSS 1<<2
34#define IEEE80211_CHAN_PASSIVE_SCAN 1<<1
35#define WIPHY_FLAG_CUSTOM_REGULATORY BIT(0)
36#define WIPHY_FLAG_STRICT_REGULATORY BIT(1)
37#define WIPHY_FLAG_DISABLE_BEACON_HINTS BIT(2)
38
39struct country_code_to_enum_rd {
40 u16 countrycode;
41 const char *iso_name;
42};
43
44enum country_code_type_t {
45 COUNTRY_CODE_FCC = 0,
46 COUNTRY_CODE_IC = 1,
47 COUNTRY_CODE_ETSI = 2,
48 COUNTRY_CODE_SPAIN = 3,
49 COUNTRY_CODE_FRANCE = 4,
50 COUNTRY_CODE_MKK = 5,
51 COUNTRY_CODE_MKK1 = 6,
52 COUNTRY_CODE_ISRAEL = 7,
53 COUNTRY_CODE_TELEC = 8,
54 COUNTRY_CODE_MIC = 9,
55 COUNTRY_CODE_GLOBAL_DOMAIN = 10,
56 COUNTRY_CODE_WORLD_WIDE_13 = 11,
57 COUNTRY_CODE_TELEC_NETGEAR = 12,
58
59 /*add new channel plan above this line */
60 COUNTRY_CODE_MAX
61};
62
63#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
64int rtl_regd_init(struct ieee80211_hw *hw,
65 void (*reg_notifier) (struct wiphy *wiphy,
66 struct regulatory_request *request));
67void rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
68#else
69int rtl_regd_init(struct ieee80211_hw *hw,
70 int (*reg_notifier) (struct wiphy *wiphy,
71 struct regulatory_request *request));
72int rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
73#endif
74
75#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/btc.h b/drivers/staging/rtl8821ae/rtl8821ae/btc.h
new file mode 100644
index 000000000000..74ac189e3a88
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/btc.h
@@ -0,0 +1,87 @@
1
2/******************************************************************************
3 **
4 ** Copyright(c) 2009-2010 Realtek Corporation.
5 **
6 ** This program is free software; you can redistribute it and/or modify it
7 ** under the terms of version 2 of the GNU General Public License as
8 ** published by the Free Software Foundation.
9 **
10 ** This program is distributed in the hope that it will be useful, but WITHOUT
11 ** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 ** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 ** more details.
14 **
15 ** You should have received a copy of the GNU General Public License along with
16 ** this program; if not, write to the Free Software Foundation, Inc.,
17 ** 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 **
19 ** The full GNU General Public License is included in this distribution in the
20 ** file called LICENSE.
21 **
22 ** Contact Information:
23 ** wlanfae <wlanfae@realtek.com>
24 ** Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
25 ** Hsinchu 300, Taiwan.
26 ** Larry Finger <Larry.Finger@lwfinger.net>
27 **
28 ******************************************************************************/
29
30#ifndef __RTL8821AE_BTC_H__
31#define __RTL8821AE_BTC_H__
32
33#include "../wifi.h"
34#include "hal_bt_coexist.h"
35
36struct bt_coexist_c2h_info {
37 u8 no_parse_c2h;
38 u8 has_c2h;
39};
40
41struct btdm_8821ae {
42 bool b_all_off;
43 bool b_agc_table_en;
44 bool b_adc_back_off_on;
45 bool b2_ant_hid_en;
46 bool b_low_penalty_rate_adaptive;
47 bool b_rf_rx_lpf_shrink;
48 bool b_reject_aggre_pkt;
49 bool b_tra_tdma_on;
50 u8 tra_tdma_nav;
51 u8 tra_tdma_ant;
52 bool b_tdma_on;
53 u8 tdma_ant;
54 u8 tdma_nav;
55 u8 tdma_dac_swing;
56 u8 fw_dac_swing_lvl;
57 bool b_ps_tdma_on;
58 u8 ps_tdma_byte[5];
59 bool b_pta_on;
60 u32 val_0x6c0;
61 u32 val_0x6c8;
62 u32 val_0x6cc;
63 bool b_sw_dac_swing_on;
64 u32 sw_dac_swing_lvl;
65 u32 wlan_act_hi;
66 u32 wlan_act_lo;
67 u32 bt_retry_index;
68 bool b_dec_bt_pwr;
69 bool b_ignore_wlan_act;
70};
71
72struct bt_coexist_8821ae {
73 u32 high_priority_tx;
74 u32 high_priority_rx;
75 u32 low_priority_tx;
76 u32 low_priority_rx;
77 u8 c2h_bt_info;
78 bool b_c2h_bt_info_req_sent;
79 bool b_c2h_bt_inquiry_page;
80 u32 bt_inq_page_start_time;
81 u8 bt_retry_cnt;
82 u8 c2h_bt_info_original;
83 u8 bt_inquiry_page_cnt;
84 struct btdm_8821ae btdm;
85};
86
87#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/def.h b/drivers/staging/rtl8821ae/rtl8821ae/def.h
new file mode 100644
index 000000000000..72ebdeaa6e7d
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/def.h
@@ -0,0 +1,442 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8821AE_DEF_H__
31#define __RTL8821AE_DEF_H__
32
33/*--------------------------Define -------------------------------------------*/
34/* BIT 7 HT Rate*/
35/*TxHT = 0*/
36#define MGN_1M 0x02
37#define MGN_2M 0x04
38#define MGN_5_5M 0x0b
39#define MGN_11M 0x16
40
41#define MGN_6M 0x0c
42#define MGN_9M 0x12
43#define MGN_12M 0x18
44#define MGN_18M 0x24
45#define MGN_24M 0x30
46#define MGN_36M 0x48
47#define MGN_48M 0x60
48#define MGN_54M 0x6c
49
50// TxHT = 1
51#define MGN_MCS0 0x80
52#define MGN_MCS1 0x81
53#define MGN_MCS2 0x82
54#define MGN_MCS3 0x83
55#define MGN_MCS4 0x84
56#define MGN_MCS5 0x85
57#define MGN_MCS6 0x86
58#define MGN_MCS7 0x87
59#define MGN_MCS8 0x88
60#define MGN_MCS9 0x89
61#define MGN_MCS10 0x8a
62#define MGN_MCS11 0x8b
63#define MGN_MCS12 0x8c
64#define MGN_MCS13 0x8d
65#define MGN_MCS14 0x8e
66#define MGN_MCS15 0x8f
67//VHT rate
68#define MGN_VHT1SS_MCS0 0x90
69#define MGN_VHT1SS_MCS1 0x91
70#define MGN_VHT1SS_MCS2 0x92
71#define MGN_VHT1SS_MCS3 0x93
72#define MGN_VHT1SS_MCS4 0x94
73#define MGN_VHT1SS_MCS5 0x95
74#define MGN_VHT1SS_MCS6 0x96
75#define MGN_VHT1SS_MCS7 0x97
76#define MGN_VHT1SS_MCS8 0x98
77#define MGN_VHT1SS_MCS9 0x99
78#define MGN_VHT2SS_MCS0 0x9a
79#define MGN_VHT2SS_MCS1 0x9b
80#define MGN_VHT2SS_MCS2 0x9c
81#define MGN_VHT2SS_MCS3 0x9d
82#define MGN_VHT2SS_MCS4 0x9e
83#define MGN_VHT2SS_MCS5 0x9f
84#define MGN_VHT2SS_MCS6 0xa0
85#define MGN_VHT2SS_MCS7 0xa1
86#define MGN_VHT2SS_MCS8 0xa2
87#define MGN_VHT2SS_MCS9 0xa3
88
89#define MGN_VHT3SS_MCS0 0xa4
90#define MGN_VHT3SS_MCS1 0xa5
91#define MGN_VHT3SS_MCS2 0xa6
92#define MGN_VHT3SS_MCS3 0xa7
93#define MGN_VHT3SS_MCS4 0xa8
94#define MGN_VHT3SS_MCS5 0xa9
95#define MGN_VHT3SS_MCS6 0xaa
96#define MGN_VHT3SS_MCS7 0xab
97#define MGN_VHT3SS_MCS8 0xac
98#define MGN_VHT3SS_MCS9 0xad
99
100#define MGN_MCS0_SG 0xc0
101#define MGN_MCS1_SG 0xc1
102#define MGN_MCS2_SG 0xc2
103#define MGN_MCS3_SG 0xc3
104#define MGN_MCS4_SG 0xc4
105#define MGN_MCS5_SG 0xc5
106#define MGN_MCS6_SG 0xc6
107#define MGN_MCS7_SG 0xc7
108#define MGN_MCS8_SG 0xc8
109#define MGN_MCS9_SG 0xc9
110#define MGN_MCS10_SG 0xca
111#define MGN_MCS11_SG 0xcb
112#define MGN_MCS12_SG 0xcc
113#define MGN_MCS13_SG 0xcd
114#define MGN_MCS14_SG 0xce
115#define MGN_MCS15_SG 0xcf
116
117#define MGN_UNKNOWN 0xff
118
119
120/* 30 ms */
121#define WIFI_NAV_UPPER_US 30000
122#define HAL_92C_NAV_UPPER_UNIT 128
123
124#define HAL_RETRY_LIMIT_INFRA 48
125#define HAL_RETRY_LIMIT_AP_ADHOC 7
126
127#define RESET_DELAY_8185 20
128
129#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
130#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
131
132#define NUM_OF_FIRMWARE_QUEUE 10
133#define NUM_OF_PAGES_IN_FW 0x100
134#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
135#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
136#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
137#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
138#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
139#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
140#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
141#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
142#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
143#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
144
145#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
146#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
147#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
148#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
149#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
150
151#define MAX_RX_DMA_BUFFER_SIZE 0x3E80
152
153
154#define MAX_LINES_HWCONFIG_TXT 1000
155#define MAX_BYTES_LINE_HWCONFIG_TXT 256
156
157#define SW_THREE_WIRE 0
158#define HW_THREE_WIRE 2
159
160#define BT_DEMO_BOARD 0
161#define BT_QA_BOARD 1
162#define BT_FPGA 2
163
164#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
165#define HAL_PRIME_CHNL_OFFSET_LOWER 1
166#define HAL_PRIME_CHNL_OFFSET_UPPER 2
167
168#define MAX_H2C_QUEUE_NUM 10
169
170#define RX_MPDU_QUEUE 0
171#define RX_CMD_QUEUE 1
172#define RX_MAX_QUEUE 2
173#define AC2QUEUEID(_AC) (_AC)
174
175#define C2H_RX_CMD_HDR_LEN 8
176#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
177 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
178#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
179 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
180#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
181 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
182#define GET_C2H_CMD_CONTINUE(__prxhdr) \
183 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
184#define GET_C2H_CMD_CONTENT(__prxhdr) \
185 ((u8*)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
186
187#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
188 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
189#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
190 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
191#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
192 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
193#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
194 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
195#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
196 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
197#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
198 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
199#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
200 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
201#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
202 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
203#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
204 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
205
206#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
207
208#define CHIP_8812 BIT(2)
209#define CHIP_8821 (BIT(0)|BIT(2))
210
211#define CHIP_8821A (BIT(0)|BIT(2))
212#define NORMAL_CHIP BIT(3)
213#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
214#define RF_TYPE_1T2R BIT(4)
215#define RF_TYPE_2T2R BIT(5)
216#define CHIP_VENDOR_UMC BIT(7)
217#define B_CUT_VERSION BIT(12)
218#define C_CUT_VERSION BIT(13)
219#define D_CUT_VERSION ((BIT(12)|BIT(13)))
220#define E_CUT_VERSION BIT(14)
221#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
222
223
224
225enum version_8821ae {
226 VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
227 VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
228 VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
229 VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
230 VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
231 VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
232 VERSION_TEST_CHIP_8821 = 0x0005,
233 VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
234 VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
235 VERSION_UNKNOWN = 0xFF,
236};
237
238enum vht_data_sc{
239 VHT_DATA_SC_DONOT_CARE = 0,
240 VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
241 VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
242 VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
243 VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
244 VHT_DATA_SC_20_RECV1 = 5,
245 VHT_DATA_SC_20_RECV2 = 6,
246 VHT_DATA_SC_20_RECV3 = 7,
247 VHT_DATA_SC_20_RECV4 = 8,
248 VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
249 VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
250};
251
252
253/* MASK */
254#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
255#define CHIP_TYPE_MASK BIT(3)
256#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
257#define MANUFACTUER_MASK BIT(7)
258#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
259#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
260
261/* Get element */
262#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
263#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
264#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
265#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
266#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
267#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
268
269#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version))? false : true)
270#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
271 ? true : false)
272#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
273 ? true : false)
274
275#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812)? \
276 true : false)
277#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821)? \
278 true : false)
279
280#define IS_VENDOR_8812A_TEST_CHIP(version) ((IS_8812_SERIES(version)) ? \
281 ((IS_NORMAL_CHIP(version)) ? \
282 false : true) : false)
283#define IS_VENDOR_8812A_MP_CHIP(version) ((IS_8812_SERIES(version)) ? \
284 ((IS_NORMAL_CHIP(version)) ? \
285 true : false) : false)
286#define IS_VENDOR_8812A_C_CUT(version) ((IS_8812_SERIES(version)) ? \
287 ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? \
288 true : false) : false)
289
290#define IS_VENDOR_8821A_TEST_CHIP(version) ((IS_8821_SERIES(version)) ? \
291 ((IS_NORMAL_CHIP(version)) ? \
292 false : true) : false)
293#define IS_VENDOR_8821A_MP_CHIP(version) ((IS_8821_SERIES(version)) ? \
294 ((IS_NORMAL_CHIP(version)) ? \
295 true : false) : false)
296#define IS_VENDOR_8821A_B_CUT(version) ((IS_8821_SERIES(version)) ? \
297 ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? \
298 true : false) : false)
299
300
301enum rf_optype {
302 RF_OP_BY_SW_3WIRE = 0,
303 RF_OP_BY_FW,
304 RF_OP_MAX
305};
306
307enum rf_power_state {
308 RF_ON,
309 RF_OFF,
310 RF_SLEEP,
311 RF_SHUT_DOWN,
312};
313
314enum power_save_mode {
315 POWER_SAVE_MODE_ACTIVE,
316 POWER_SAVE_MODE_SAVE,
317};
318
319enum power_polocy_config {
320 POWERCFG_MAX_POWER_SAVINGS,
321 POWERCFG_GLOBAL_POWER_SAVINGS,
322 POWERCFG_LOCAL_POWER_SAVINGS,
323 POWERCFG_LENOVO,
324};
325
326enum interface_select_pci {
327 INTF_SEL1_MINICARD = 0,
328 INTF_SEL0_PCIE = 1,
329 INTF_SEL2_RSV = 2,
330 INTF_SEL3_RSV = 3,
331};
332
333enum hal_fw_c2h_cmd_id {
334 HAL_FW_C2H_CMD_Read_MACREG = 0,
335 HAL_FW_C2H_CMD_Read_BBREG = 1,
336 HAL_FW_C2H_CMD_Read_RFREG = 2,
337 HAL_FW_C2H_CMD_Read_EEPROM = 3,
338 HAL_FW_C2H_CMD_Read_EFUSE = 4,
339 HAL_FW_C2H_CMD_Read_CAM = 5,
340 HAL_FW_C2H_CMD_Get_BasicRate = 6,
341 HAL_FW_C2H_CMD_Get_DataRate = 7,
342 HAL_FW_C2H_CMD_Survey = 8,
343 HAL_FW_C2H_CMD_SurveyDone = 9,
344 HAL_FW_C2H_CMD_JoinBss = 10,
345 HAL_FW_C2H_CMD_AddSTA = 11,
346 HAL_FW_C2H_CMD_DelSTA = 12,
347 HAL_FW_C2H_CMD_AtimDone = 13,
348 HAL_FW_C2H_CMD_TX_Report = 14,
349 HAL_FW_C2H_CMD_CCX_Report = 15,
350 HAL_FW_C2H_CMD_DTM_Report = 16,
351 HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
352 HAL_FW_C2H_CMD_C2HLBK = 18,
353 HAL_FW_C2H_CMD_C2HDBG = 19,
354 HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
355 HAL_FW_C2H_CMD_MAX
356};
357
358enum rtl_desc_qsel {
359 QSLT_BK = 0x2,
360 QSLT_BE = 0x0,
361 QSLT_VI = 0x5,
362 QSLT_VO = 0x7,
363 QSLT_BEACON = 0x10,
364 QSLT_HIGH = 0x11,
365 QSLT_MGNT = 0x12,
366 QSLT_CMD = 0x13,
367};
368
369enum rtl_desc8821ae_rate {
370 DESC_RATE1M = 0x00,
371 DESC_RATE2M = 0x01,
372 DESC_RATE5_5M = 0x02,
373 DESC_RATE11M = 0x03,
374
375 DESC_RATE6M = 0x04,
376 DESC_RATE9M = 0x05,
377 DESC_RATE12M = 0x06,
378 DESC_RATE18M = 0x07,
379 DESC_RATE24M = 0x08,
380 DESC_RATE36M = 0x09,
381 DESC_RATE48M = 0x0a,
382 DESC_RATE54M = 0x0b,
383
384 DESC_RATEMCS0 = 0x0c,
385 DESC_RATEMCS1 = 0x0d,
386 DESC_RATEMCS2 = 0x0e,
387 DESC_RATEMCS3 = 0x0f,
388 DESC_RATEMCS4 = 0x10,
389 DESC_RATEMCS5 = 0x11,
390 DESC_RATEMCS6 = 0x12,
391 DESC_RATEMCS7 = 0x13,
392 DESC_RATEMCS8 = 0x14,
393 DESC_RATEMCS9 = 0x15,
394 DESC_RATEMCS10 = 0x16,
395 DESC_RATEMCS11 = 0x17,
396 DESC_RATEMCS12 = 0x18,
397 DESC_RATEMCS13 = 0x19,
398 DESC_RATEMCS14 = 0x1a,
399 DESC_RATEMCS15 = 0x1b,
400 DESC_RATEVHT1SS_MCS0 = 0x1c,
401 DESC_RATEVHT1SS_MCS1 = 0x1d,
402 DESC_RATEVHT1SS_MCS2 = 0x1e,
403 DESC_RATEVHT1SS_MCS3 = 0x1f,
404 DESC_RATEVHT1SS_MCS4 = 0x20,
405 DESC_RATEVHT1SS_MCS5 = 0x21,
406 DESC_RATEVHT1SS_MCS6 = 0x22,
407 DESC_RATEVHT1SS_MCS7 = 0x23,
408 DESC_RATEVHT1SS_MCS8 = 0x24,
409 DESC_RATEVHT1SS_MCS9 = 0x25,
410 DESC_RATEVHT2SS_MCS0 = 0x26,
411 DESC_RATEVHT2SS_MCS1 = 0x27,
412 DESC_RATEVHT2SS_MCS2 = 0x28,
413 DESC_RATEVHT2SS_MCS3 = 0x29,
414 DESC_RATEVHT2SS_MCS4 = 0x2a,
415 DESC_RATEVHT2SS_MCS5 = 0x2b,
416 DESC_RATEVHT2SS_MCS6 = 0x2c,
417 DESC_RATEVHT2SS_MCS7 = 0x2d,
418 DESC_RATEVHT2SS_MCS8 = 0x2e,
419 DESC_RATEVHT2SS_MCS9 = 0x2f,
420};
421
422enum rx_packet_type{
423 NORMAL_RX,
424 TX_REPORT1,
425 TX_REPORT2,
426 HIS_REPORT,
427 C2H_PACKET,
428};
429
430struct phy_sts_cck_8821ae_t {
431 u8 adc_pwdb_X[4];
432 u8 sq_rpt;
433 u8 cck_agc_rpt;
434};
435
436struct h2c_cmd_8821ae {
437 u8 element_id;
438 u32 cmd_len;
439 u8 *p_cmdbuffer;
440};
441
442#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/dm.c b/drivers/staging/rtl8821ae/rtl8821ae/dm.c
new file mode 100644
index 000000000000..8634206b8929
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/dm.c
@@ -0,0 +1,3045 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../base.h"
32#include "../pci.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "dm.h"
37#include "fw.h"
38#include "trx.h"
39#include "../btcoexist/rtl_btc.h"
40
41struct dig_t dm_digtable;
42static struct ps_t dm_pstable;
43
44static const u32 rtl8812ae_txscaling_table[TXSCALE_TABLE_SIZE] =
45{
46 0x081, // 0, -12.0dB
47 0x088, // 1, -11.5dB
48 0x090, // 2, -11.0dB
49 0x099, // 3, -10.5dB
50 0x0A2, // 4, -10.0dB
51 0x0AC, // 5, -9.5dB
52 0x0B6, // 6, -9.0dB
53 0x0C0, // 7, -8.5dB
54 0x0CC, // 8, -8.0dB
55 0x0D8, // 9, -7.5dB
56 0x0E5, // 10, -7.0dB
57 0x0F2, // 11, -6.5dB
58 0x101, // 12, -6.0dB
59 0x110, // 13, -5.5dB
60 0x120, // 14, -5.0dB
61 0x131, // 15, -4.5dB
62 0x143, // 16, -4.0dB
63 0x156, // 17, -3.5dB
64 0x16A, // 18, -3.0dB
65 0x180, // 19, -2.5dB
66 0x197, // 20, -2.0dB
67 0x1AF, // 21, -1.5dB
68 0x1C8, // 22, -1.0dB
69 0x1E3, // 23, -0.5dB
70 0x200, // 24, +0 dB
71 0x21E, // 25, +0.5dB
72 0x23E, // 26, +1.0dB
73 0x261, // 27, +1.5dB
74 0x285, // 28, +2.0dB
75 0x2AB, // 29, +2.5dB
76 0x2D3, // 30, +3.0dB
77 0x2FE, // 31, +3.5dB
78 0x32B, // 32, +4.0dB
79 0x35C, // 33, +4.5dB
80 0x38E, // 34, +5.0dB
81 0x3C4, // 35, +5.5dB
82 0x3FE // 36, +6.0dB
83};
84
85static const u32 rtl8821ae_txscaling_table[TXSCALE_TABLE_SIZE] = {
86 0x081, // 0, -12.0dB
87 0x088, // 1, -11.5dB
88 0x090, // 2, -11.0dB
89 0x099, // 3, -10.5dB
90 0x0A2, // 4, -10.0dB
91 0x0AC, // 5, -9.5dB
92 0x0B6, // 6, -9.0dB
93 0x0C0, // 7, -8.5dB
94 0x0CC, // 8, -8.0dB
95 0x0D8, // 9, -7.5dB
96 0x0E5, // 10, -7.0dB
97 0x0F2, // 11, -6.5dB
98 0x101, // 12, -6.0dB
99 0x110, // 13, -5.5dB
100 0x120, // 14, -5.0dB
101 0x131, // 15, -4.5dB
102 0x143, // 16, -4.0dB
103 0x156, // 17, -3.5dB
104 0x16A, // 18, -3.0dB
105 0x180, // 19, -2.5dB
106 0x197, // 20, -2.0dB
107 0x1AF, // 21, -1.5dB
108 0x1C8, // 22, -1.0dB
109 0x1E3, // 23, -0.5dB
110 0x200, // 24, +0 dB
111 0x21E, // 25, +0.5dB
112 0x23E, // 26, +1.0dB
113 0x261, // 27, +1.5dB
114 0x285, // 28, +2.0dB
115 0x2AB, // 29, +2.5dB
116 0x2D3, // 30, +3.0dB
117 0x2FE, // 31, +3.5dB
118 0x32B, // 32, +4.0dB
119 0x35C, // 33, +4.5dB
120 0x38E, // 34, +5.0dB
121 0x3C4, // 35, +5.5dB
122 0x3FE // 36, +6.0dB
123};
124
125static const u32 ofdmswing_table[] = {
126 0x0b40002d, // 0, -15.0dB
127 0x0c000030, // 1, -14.5dB
128 0x0cc00033, // 2, -14.0dB
129 0x0d800036, // 3, -13.5dB
130 0x0e400039, // 4, -13.0dB
131 0x0f00003c, // 5, -12.5dB
132 0x10000040, // 6, -12.0dB
133 0x11000044, // 7, -11.5dB
134 0x12000048, // 8, -11.0dB
135 0x1300004c, // 9, -10.5dB
136 0x14400051, // 10, -10.0dB
137 0x15800056, // 11, -9.5dB
138 0x16c0005b, // 12, -9.0dB
139 0x18000060, // 13, -8.5dB
140 0x19800066, // 14, -8.0dB
141 0x1b00006c, // 15, -7.5dB
142 0x1c800072, // 16, -7.0dB
143 0x1e400079, // 17, -6.5dB
144 0x20000080, // 18, -6.0dB
145 0x22000088, // 19, -5.5dB
146 0x24000090, // 20, -5.0dB
147 0x26000098, // 21, -4.5dB
148 0x288000a2, // 22, -4.0dB
149 0x2ac000ab, // 23, -3.5dB
150 0x2d4000b5, // 24, -3.0dB
151 0x300000c0, // 25, -2.5dB
152 0x32c000cb, // 26, -2.0dB
153 0x35c000d7, // 27, -1.5dB
154 0x390000e4, // 28, -1.0dB
155 0x3c8000f2, // 29, -0.5dB
156 0x40000100, // 30, +0dB
157 0x43c0010f, // 31, +0.5dB
158 0x47c0011f, // 32, +1.0dB
159 0x4c000130, // 33, +1.5dB
160 0x50800142, // 34, +2.0dB
161 0x55400155, // 35, +2.5dB
162 0x5a400169, // 36, +3.0dB
163 0x5fc0017f, // 37, +3.5dB
164 0x65400195, // 38, +4.0dB
165 0x6b8001ae, // 39, +4.5dB
166 0x71c001c7, // 40, +5.0dB
167 0x788001e2, // 41, +5.5dB
168 0x7f8001fe // 42, +6.0dB
169};
170
171static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
172 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB
173 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB
174 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB
175 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB
176 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB
177 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB
178 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB
179 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB
180 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB
181 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB
182 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB
183 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB
184 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB
185 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB
186 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB
187 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB
188 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB
189 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB
190 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB
191 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB
192 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 20, -6.0dB
193 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB
194 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB
195 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB
196 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB
197 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB
198 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB
199 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB
200 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB
201 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB
202 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB
203 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB
204 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB
205};
206
207static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8]= {
208 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB
209 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB
210 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB
211 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB
212 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB
213 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB
214 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB
215 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB
216 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB
217 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB
218 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB
219 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB
220 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB
221 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB
222 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB
223 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB
224 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB
225 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB
226 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB
227 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB
228 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB
229 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB
230 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB
231 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB
232 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB
233 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB
234 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB
235 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB
236 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB
237 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB
238 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB
239 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB
240 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB
241};
242
243static const u32 edca_setting_dl[PEER_MAX] = {
244 0xa44f, /* 0 UNKNOWN */
245 0x5ea44f, /* 1 REALTEK_90 */
246 0x5e4322, /* 2 REALTEK_92SE */
247 0x5ea42b, /* 3 BROAD */
248 0xa44f, /* 4 RAL */
249 0xa630, /* 5 ATH */
250 0x5ea630, /* 6 CISCO */
251 0x5ea42b, /* 7 MARVELL */
252};
253
254static const u32 edca_setting_ul[PEER_MAX] = {
255 0x5e4322, /* 0 UNKNOWN */
256 0xa44f, /* 1 REALTEK_90 */
257 0x5ea44f, /* 2 REALTEK_92SE */
258 0x5ea32b, /* 3 BROAD */
259 0x5ea422, /* 4 RAL */
260 0x5ea322, /* 5 ATH */
261 0x3ea430, /* 6 CISCO */
262 0x5ea44f, /* 7 MARV */
263};
264
265static u8 rtl8818e_delta_swing_table_idx_24gb_p_txpwrtrack[] =
266 {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
267static u8 rtl8818e_delta_swing_table_idx_24gb_n_txpwrtrack[] =
268 {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
269
270
271u8 rtl8812ae_delta_swing_table_idx_24gb_n_txpwrtrack[] =
272 {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11};
273u8 rtl8812ae_delta_swing_table_idx_24gb_p_txpwrtrack[] =
274 {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9};
275u8 rtl8812ae_delta_swing_table_idx_24ga_n_txpwrtrack[] =
276 {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11};
277u8 rtl8812ae_delta_swing_table_idx_24ga_p_txpwrtrack[] =
278 {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9};
279u8 rtl8812ae_delta_swing_table_idx_24gcckb_n_txpwrtrack[] =
280 {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11};
281u8 rtl8812ae_delta_swing_table_idx_24gcckb_p_txpwrtrack[] =
282 {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9};
283u8 rtl8812ae_delta_swing_table_idx_24gccka_n_txpwrtrack[] =
284 {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11};
285u8 rtl8812ae_delta_swing_table_idx_24gccka_p_txpwrtrack[] =
286 {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9};
287
288u8 rtl8812ae_delta_swing_table_idx_5gb_n_txpwrtrack[][DELTA_SWINGIDX_SIZE] = {
289 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 13},
290 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13},
291 {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 8, 9, 10, 11, 12, 12, 13, 14, 14, 14, 15, 16, 17, 17, 17, 18, 18, 18},
292};
293u8 rtl8812ae_delta_swing_table_idx_5gb_p_txpwrtrack[][DELTA_SWINGIDX_SIZE] = {
294 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11},
295 {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11},
296 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
297};
298u8 rtl8812ae_delta_swing_table_idx_5ga_n_txpwrtrack[][DELTA_SWINGIDX_SIZE] = {
299 {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 13, 13, 13},
300 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 8, 9, 9, 10, 10, 11, 11, 11, 12, 12, 12, 12, 12, 13, 13},
301 {0, 1, 1, 2, 2, 3, 3, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 14, 14, 15, 15, 15, 16, 16, 16, 17, 17, 18, 18},
302};
303u8 rtl8812ae_delta_swing_table_idx_5ga_p_txpwrtrack[][DELTA_SWINGIDX_SIZE] = {
304 {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11},
305 {0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
306 {0, 1, 1, 2, 3, 3, 4, 4, 5, 6, 6, 7, 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11},
307};
308
309u8 rtl8821ae_delta_swing_table_idx_24gb_n_txpwrtrack[] =
310 {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10};
311u8 rtl8821ae_delta_swing_table_idx_24gb_p_txpwrtrack[] =
312 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12};
313u8 rtl8821ae_delta_swing_table_idx_24ga_n_txpwrtrack[] =
314 {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10};
315u8 rtl8821ae_delta_swing_table_idx_24ga_p_txpwrtrack[] =
316 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12};
317u8 rtl8821ae_delta_swing_table_idx_24gcckb_n_txpwrtrack[] =
318 {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10};
319u8 rtl8821ae_delta_swing_table_idx_24gcckb_p_txpwrtrack[] =
320 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12};
321u8 rtl8821ae_delta_swing_table_idx_24gccka_n_txpwrtrack[] =
322 {0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10};
323u8 rtl8821ae_delta_swing_table_idx_24gccka_p_txpwrtrack[] =
324 {0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12};
325
326u8 rtl8821ae_delta_swing_table_idx_5gb_n_txpwrtrack[][DELTA_SWINGIDX_SIZE] = {
327 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
328 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
329 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
330};
331
332u8 rtl8821ae_delta_swing_table_idx_5gb_p_txpwrtrack[][DELTA_SWINGIDX_SIZE] = {
333 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
334 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
335 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
336};
337
338u8 rtl8821ae_delta_swing_table_idx_5ga_n_txpwrtrack[][DELTA_SWINGIDX_SIZE] = {
339 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
340 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
341 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
342};
343
344u8 rtl8821ae_delta_swing_table_idx_5ga_p_txpwrtrack[][DELTA_SWINGIDX_SIZE] = {
345 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
346 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
347 {0, 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16},
348};
349
350void rtl8812ae_dm_read_and_config_txpower_track(
351 struct ieee80211_hw *hw)
352{
353 struct rtl_priv *rtlpriv = rtl_priv(hw);
354 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
355 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
356 ("===> rtl8821ae_dm_read_and_config_txpower_track\n"));
357
358
359 memcpy(rtldm->delta_swing_table_idx_24ga_p,
360 rtl8812ae_delta_swing_table_idx_24ga_p_txpwrtrack, DELTA_SWINGIDX_SIZE);
361 memcpy(rtldm->delta_swing_table_idx_24ga_n,
362 rtl8812ae_delta_swing_table_idx_24ga_n_txpwrtrack, DELTA_SWINGIDX_SIZE);
363 memcpy(rtldm->delta_swing_table_idx_24gb_p,
364 rtl8812ae_delta_swing_table_idx_24gb_p_txpwrtrack, DELTA_SWINGIDX_SIZE);
365 memcpy(rtldm->delta_swing_table_idx_24gb_n,
366 rtl8812ae_delta_swing_table_idx_24gb_n_txpwrtrack, DELTA_SWINGIDX_SIZE);
367
368 memcpy(rtldm->delta_swing_table_idx_24gccka_p,
369 rtl8812ae_delta_swing_table_idx_24gccka_p_txpwrtrack, DELTA_SWINGIDX_SIZE);
370 memcpy(rtldm->delta_swing_table_idx_24gccka_n,
371 rtl8812ae_delta_swing_table_idx_24gccka_n_txpwrtrack, DELTA_SWINGIDX_SIZE);
372 memcpy(rtldm->delta_swing_table_idx_24gcckb_p,
373 rtl8812ae_delta_swing_table_idx_24gcckb_p_txpwrtrack, DELTA_SWINGIDX_SIZE);
374 memcpy(rtldm->delta_swing_table_idx_24gcckb_n,
375 rtl8812ae_delta_swing_table_idx_24gcckb_n_txpwrtrack, DELTA_SWINGIDX_SIZE);
376
377 memcpy(rtldm->delta_swing_table_idx_5ga_p,
378 rtl8812ae_delta_swing_table_idx_5ga_p_txpwrtrack, DELTA_SWINGIDX_SIZE*3);
379 memcpy(rtldm->delta_swing_table_idx_5ga_n,
380 rtl8812ae_delta_swing_table_idx_5ga_n_txpwrtrack, DELTA_SWINGIDX_SIZE*3);
381 memcpy(rtldm->delta_swing_table_idx_5gb_p,
382 rtl8812ae_delta_swing_table_idx_5gb_p_txpwrtrack, DELTA_SWINGIDX_SIZE*3);
383 memcpy(rtldm->delta_swing_table_idx_5gb_n,
384 rtl8812ae_delta_swing_table_idx_5gb_n_txpwrtrack, DELTA_SWINGIDX_SIZE*3);
385}
386
387void rtl8821ae_dm_read_and_config_txpower_track(
388 struct ieee80211_hw *hw)
389{
390 struct rtl_priv *rtlpriv = rtl_priv(hw);
391 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
392 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
393 ("===> rtl8821ae_dm_read_and_config_txpower_track\n"));
394
395
396 memcpy(rtldm->delta_swing_table_idx_24ga_p,
397 rtl8821ae_delta_swing_table_idx_24ga_p_txpwrtrack, DELTA_SWINGIDX_SIZE);
398 memcpy(rtldm->delta_swing_table_idx_24ga_n,
399 rtl8821ae_delta_swing_table_idx_24ga_n_txpwrtrack, DELTA_SWINGIDX_SIZE);
400 memcpy(rtldm->delta_swing_table_idx_24gb_p,
401 rtl8821ae_delta_swing_table_idx_24gb_p_txpwrtrack, DELTA_SWINGIDX_SIZE);
402 memcpy(rtldm->delta_swing_table_idx_24gb_n,
403 rtl8821ae_delta_swing_table_idx_24gb_n_txpwrtrack, DELTA_SWINGIDX_SIZE);
404
405 memcpy(rtldm->delta_swing_table_idx_24gccka_p,
406 rtl8821ae_delta_swing_table_idx_24gccka_p_txpwrtrack, DELTA_SWINGIDX_SIZE);
407 memcpy(rtldm->delta_swing_table_idx_24gccka_n,
408 rtl8821ae_delta_swing_table_idx_24gccka_n_txpwrtrack, DELTA_SWINGIDX_SIZE);
409 memcpy(rtldm->delta_swing_table_idx_24gcckb_p,
410 rtl8821ae_delta_swing_table_idx_24gcckb_p_txpwrtrack, DELTA_SWINGIDX_SIZE);
411 memcpy(rtldm->delta_swing_table_idx_24gcckb_n,
412 rtl8821ae_delta_swing_table_idx_24gcckb_n_txpwrtrack, DELTA_SWINGIDX_SIZE);
413
414 memcpy(rtldm->delta_swing_table_idx_5ga_p,
415 rtl8821ae_delta_swing_table_idx_5ga_p_txpwrtrack, DELTA_SWINGIDX_SIZE*3);
416 memcpy(rtldm->delta_swing_table_idx_5ga_n,
417 rtl8821ae_delta_swing_table_idx_5ga_n_txpwrtrack, DELTA_SWINGIDX_SIZE*3);
418 memcpy(rtldm->delta_swing_table_idx_5gb_p,
419 rtl8821ae_delta_swing_table_idx_5gb_p_txpwrtrack, DELTA_SWINGIDX_SIZE*3);
420 memcpy(rtldm->delta_swing_table_idx_5gb_n,
421 rtl8821ae_delta_swing_table_idx_5gb_n_txpwrtrack, DELTA_SWINGIDX_SIZE*3);
422}
423
424
425
426#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \
427 do {\
428 for(_offset = 0; _offset < _size; _offset++)\
429 {\
430 if(_deltaThermal < thermal_threshold[_direction][_offset])\
431 {\
432 if(_offset != 0)\
433 _offset--;\
434 break;\
435 }\
436 } \
437 if(_offset >= _size)\
438 _offset = _size-1;\
439 } while(0)
440
441
442void rtl8821ae_dm_txpower_track_adjust(struct ieee80211_hw *hw,
443 u8 type,u8 *pdirection,
444 u32 *poutwrite_val)
445{
446 struct rtl_priv *rtlpriv = rtl_priv(hw);
447 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
448 u8 pwr_val = 0;
449
450 if (type == 0){
451 if (rtlpriv->dm.bb_swing_idx_ofdm[RF90_PATH_A] <=
452 rtlpriv->dm.bb_swing_idx_ofdm_base[RF90_PATH_A]) {
453 *pdirection = 1;
454 pwr_val = rtldm->bb_swing_idx_ofdm_base[RF90_PATH_A] - rtldm->bb_swing_idx_ofdm[RF90_PATH_A];
455 } else {
456 *pdirection = 2;
457 pwr_val = rtldm->bb_swing_idx_ofdm[RF90_PATH_A] - rtldm->bb_swing_idx_ofdm_base[RF90_PATH_A];
458 }
459 } else if (type ==1) {
460 if (rtldm->bb_swing_idx_cck <= rtldm->bb_swing_idx_cck_base) {
461 *pdirection = 1;
462 pwr_val = rtldm->bb_swing_idx_cck_base - rtldm->bb_swing_idx_cck;
463 } else {
464 *pdirection = 2;
465 pwr_val = rtldm->bb_swing_idx_cck - rtldm->bb_swing_idx_cck_base;
466 }
467 }
468
469 if (pwr_val >= TXPWRTRACK_MAX_IDX && (*pdirection == 1))
470 pwr_val = TXPWRTRACK_MAX_IDX;
471
472 *poutwrite_val = pwr_val |(pwr_val << 8)|(pwr_val << 16) | (pwr_val << 24);
473}
474
475void rtl8821ae_dm_clear_txpower_tracking_state(struct ieee80211_hw *hw)
476{
477 struct rtl_priv *rtlpriv = rtl_priv(hw);
478 struct rtl_dm *rtldm = rtl_dm(rtlpriv);
479 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
480 u8 p = 0;
481 rtldm->bb_swing_idx_cck_base = rtldm->default_cck_index;
482 rtldm->bb_swing_idx_cck = rtldm->default_cck_index;
483 rtldm->cck_index = 0;
484
485 for (p = RF90_PATH_A; p < MAX_RF_PATH; ++p) {
486 rtldm->bb_swing_idx_ofdm_base[p] = rtldm->default_ofdm_index;
487 rtldm->bb_swing_idx_ofdm[p] = rtldm->default_ofdm_index;
488 rtldm->ofdm_index[p] = rtldm->default_ofdm_index;
489
490 rtldm->power_index_offset[p] = 0;
491 rtldm->delta_power_index[p] = 0;
492 rtldm->delta_power_index_last[p] = 0;
493
494 rtldm->aboslute_ofdm_swing_idx[p] = 0; /*Initial Mix mode power tracking*/
495 rtldm->remnant_ofdm_swing_idx[p] = 0;
496 }
497
498 rtldm->modify_txagc_flag_path_a = false; /*Initial at Modify Tx Scaling Mode*/
499 rtldm->modify_txagc_flag_path_b = false; /*Initial at Modify Tx Scaling Mode*/
500 rtldm->remnant_cck_idx = 0;
501 rtldm->thermalvalue = rtlefuse->eeprom_thermalmeter;
502 rtldm->thermalvalue_iqk = rtlefuse->eeprom_thermalmeter;
503 rtldm->thermalvalue_lck = rtlefuse->eeprom_thermalmeter;
504}
505
506u8 rtl8821ae_dm_get_swing_index(struct ieee80211_hw *hw)
507{
508 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
509 u8 i = 0;
510 u32 bb_swing;
511
512 bb_swing =rtl8821ae_phy_query_bb_reg(hw, rtlhal->current_bandtype, RF90_PATH_A);
513
514 for (i = 0; i < TXSCALE_TABLE_SIZE; ++i)
515 if ( bb_swing == rtl8821ae_txscaling_table[i])
516 break;
517
518 return i;
519}
520
521void rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(
522 struct ieee80211_hw *hw)
523{
524 struct rtl_priv *rtlpriv = rtl_priv(hw);
525 struct rtl_dm *rtldm = rtl_dm(rtlpriv);
526 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
527 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
528 u8 default_swing_index = 0;
529 u8 p = 0;
530
531 rtlpriv->dm.txpower_track_control = true;
532 rtldm->thermalvalue = rtlefuse->eeprom_thermalmeter;
533 rtldm->thermalvalue_iqk = rtlefuse->eeprom_thermalmeter;
534 rtldm->thermalvalue_lck = rtlefuse->eeprom_thermalmeter;
535
536 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
537 rtl8812ae_dm_read_and_config_txpower_track(hw);
538 else
539 rtl8821ae_dm_read_and_config_txpower_track(hw);
540
541 default_swing_index = rtl8821ae_dm_get_swing_index(hw);
542
543 rtldm->default_ofdm_index = (default_swing_index == TXSCALE_TABLE_SIZE) ? 24 : default_swing_index;
544 rtldm->default_cck_index = 24;
545
546 rtldm->bb_swing_idx_cck_base = rtldm->default_cck_index;
547 rtldm->cck_index = rtldm->default_cck_index;
548
549 for (p = RF90_PATH_A; p < MAX_RF_PATH; ++p)
550 {
551 rtldm->bb_swing_idx_ofdm_base[p] = rtldm->default_ofdm_index;
552 rtldm->ofdm_index[p] = rtldm->default_ofdm_index;
553 rtldm->delta_power_index[p] = 0;
554 rtldm->power_index_offset[p] = 0;
555 rtldm->delta_power_index_last[p] = 0;
556 }
557}
558
559static void rtl8821ae_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
560{
561 dm_pstable.pre_ccastate = CCA_MAX;
562 dm_pstable.cur_ccasate = CCA_MAX;
563 dm_pstable.pre_rfstate = RF_MAX;
564 dm_pstable.cur_rfstate = RF_MAX;
565 dm_pstable.rssi_val_min = 0;
566 dm_pstable.initialize = 0;
567}
568
569
570static void rtl8821ae_dm_diginit(struct ieee80211_hw *hw)
571{
572 struct rtl_priv *rtlpriv = rtl_priv(hw);
573 //dm_digtable.dig_enable_flag = true;
574 dm_digtable.cur_igvalue = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f);
575 /*dm_digtable.pre_igvalue = 0;
576 dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
577 dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
578 dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;*/
579 dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
580 dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
581 dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
582 dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
583 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
584 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
585 dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
586 dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
587 dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
588 dm_digtable.pre_cck_cca_thres = 0xff;
589 dm_digtable.cur_cck_cca_thres = 0x83;
590 dm_digtable.forbidden_igi = DM_DIG_MIN;
591 dm_digtable.large_fa_hit = 0;
592 dm_digtable.recover_cnt = 0;
593 dm_digtable.dig_dynamic_min_0 = DM_DIG_MIN;
594 dm_digtable.dig_dynamic_min_1 = DM_DIG_MIN;
595 dm_digtable.b_media_connect_0 = false;
596 dm_digtable.b_media_connect_1 = false;
597 rtlpriv->dm.b_dm_initialgain_enable = true;
598 dm_digtable.bt30_cur_igi = 0x32;
599}
600
601static void rtl8821ae_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
602{
603 struct rtl_priv *rtlpriv = rtl_priv(hw);
604
605 rtlpriv->dm.bdynamic_txpower_enable = false;
606
607 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
608 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
609}
610
611
612void rtl8821ae_dm_init_edca_turbo(struct ieee80211_hw *hw)
613{
614 struct rtl_priv *rtlpriv = rtl_priv(hw);
615 rtlpriv->dm.bcurrent_turbo_edca = false;
616 rtlpriv->dm.bis_any_nonbepkts = false;
617 rtlpriv->dm.bis_cur_rdlstate = false;
618}
619
620
621void rtl8821ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
622{
623 struct rtl_priv *rtlpriv = rtl_priv(hw);
624 struct rate_adaptive *p_ra = &(rtlpriv->ra);
625
626 p_ra->ratr_state = DM_RATR_STA_INIT;
627 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
628
629 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
630 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
631 rtlpriv->dm.b_useramask = true;
632 else
633 rtlpriv->dm.b_useramask = false;
634
635 p_ra->high_rssi_thresh_for_ra = 50;
636 p_ra->low_rssi_thresh_for_ra = 20;
637}
638
639
640static void rtl8821ae_dm_init_txpower_tracking(struct ieee80211_hw *hw)
641{
642 struct rtl_priv *rtlpriv = rtl_priv(hw);
643
644 rtlpriv->dm.btxpower_tracking = true;
645 rtlpriv->dm.btxpower_trackinginit = false;
646 rtlpriv->dm.txpowercount = 0;
647 rtlpriv->dm.txpower_track_control = true;
648 rtlpriv->dm.thermalvalue = 0;
649
650 rtlpriv->dm.ofdm_index[0] = 30;
651 rtlpriv->dm.cck_index = 20;
652
653 rtlpriv->dm.bb_swing_idx_cck_base = rtlpriv->dm.cck_index;
654
655
656 rtlpriv->dm.bb_swing_idx_ofdm[RF90_PATH_A] = rtlpriv->dm.ofdm_index[0];
657 rtlpriv->dm.bb_swing_idx_ofdm[RF90_PATH_B] = rtlpriv->dm.ofdm_index[0];
658 rtlpriv->dm.delta_power_index[0] = 0;
659 rtlpriv->dm.delta_power_index_last[0] = 0;
660 rtlpriv->dm.power_index_offset[0] = 0;
661
662 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
663 (" rtlpriv->dm.btxpower_tracking = %d\n",
664 rtlpriv->dm.btxpower_tracking));
665}
666
667
668void rtl8821ae_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw)
669{
670 struct rtl_priv *rtlpriv = rtl_priv(hw);
671
672 rtlpriv->dm.crystal_cap = rtlpriv->efuse.crystalcap;
673
674 rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11));
675 rtlpriv->dm.cfo_threshold = CFO_THRESHOLD_XTAL;
676}
677
678
679void rtl8821ae_dm_init(struct ieee80211_hw *hw)
680{
681 struct rtl_priv *rtlpriv = rtl_priv(hw);
682 struct rtl_phy *rtlphy = &(rtlpriv->phy);
683
684 spin_lock(&rtlpriv->locks.iqk_lock);
685 rtlphy->b_iqk_in_progress = false;
686 spin_unlock(&rtlpriv->locks.iqk_lock);
687
688 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
689 rtl8821ae_dm_diginit(hw);
690 rtl8821ae_dm_init_rate_adaptive_mask(hw);
691 rtl8812ae_dm_path_diversity_init(hw);
692 rtl8821ae_dm_init_edca_turbo(hw);
693 rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(hw);
694#if 1
695 rtl8821ae_dm_init_dynamic_bb_powersaving(hw);
696 rtl8821ae_dm_init_dynamic_txpower(hw);
697 rtl8821ae_dm_init_txpower_tracking(hw);
698#endif
699 rtl8821ae_dm_init_dynamic_atc_switch(hw);
700}
701
702void rtl8821ae_dm_find_minimum_rssi(struct ieee80211_hw *hw)
703{
704 struct rtl_priv *rtlpriv = rtl_priv(hw);
705 struct rtl_dig *rtl_dm_dig = &(rtlpriv->dm.dm_digtable);
706 struct rtl_mac *mac = rtl_mac(rtlpriv);
707
708 /* Determine the minimum RSSI */
709 if ((mac->link_state < MAC80211_LINKED) &&
710 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
711 rtl_dm_dig->min_undecorated_pwdb_for_dm = 0;
712 RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD,
713 ("Not connected to any \n"));
714 }
715 if (mac->link_state >= MAC80211_LINKED) {
716 if (mac->opmode == NL80211_IFTYPE_AP ||
717 mac->opmode == NL80211_IFTYPE_ADHOC) {
718 rtl_dm_dig->min_undecorated_pwdb_for_dm =
719 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
720 RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD,
721 ("AP Client PWDB = 0x%lx \n",
722 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb));
723 } else {
724 rtl_dm_dig->min_undecorated_pwdb_for_dm =
725 rtlpriv->dm.undecorated_smoothed_pwdb;
726 RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD,
727 ("STA Default Port PWDB = 0x%x \n",
728 rtl_dm_dig->min_undecorated_pwdb_for_dm));
729 }
730 } else {
731 rtl_dm_dig->min_undecorated_pwdb_for_dm =
732 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
733 RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD,
734 ("AP Ext Port or disconnet PWDB = 0x%x \n",
735 rtl_dm_dig->min_undecorated_pwdb_for_dm));
736 }
737 RT_TRACE(COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",
738 rtl_dm_dig->min_undecorated_pwdb_for_dm));
739}
740
741#if 0
742void rtl8812ae_dm_rssi_dump_to_register(
743 struct ieee80211_hw *hw
744 )
745{
746 struct rtl_priv *rtlpriv = rtl_priv(hw);
747
748 rtl_write_byte(rtlpriv, RA_RSSI_DUMP, Adapter->RxStats.RxRSSIPercentage[0]);
749 rtl_write_byte(rtlpriv, RB_RSSI_DUMP, Adapter->RxStats.RxRSSIPercentage[1]);
750
751 /* Rx EVM*/
752 rtl_write_byte(rtlpriv, RS1_RX_EVM_DUMP, Adapter->RxStats.RxEVMdbm[0]);
753 rtl_write_byte(rtlpriv, RS2_RX_EVM_DUMP, Adapter->RxStats.RxEVMdbm[1]);
754
755 /*Rx SNR*/
756 rtl_write_byte(rtlpriv, RA_RX_SNR_DUMP, (u1Byte)(Adapter->RxStats.RxSNRdB[0]));
757 rtl_write_byte(rtlpriv, RB_RX_SNR_DUMP, (u1Byte)(Adapter->RxStats.RxSNRdB[1]));
758
759 /*Rx Cfo_Short*/
760 rtl_write_word(rtlpriv, RA_CFO_SHORT_DUMP, Adapter->RxStats.RxCfoShort[0]);
761 rtl_write_word(rtlpriv, RB_CFO_SHORT_DUMP, Adapter->RxStats.RxCfoShort[1]);
762
763 /*Rx Cfo_Tail*/
764 rtl_write_word(rtlpriv, RA_CFO_LONG_DUMP, Adapter->RxStats.RxCfoTail[0]);
765 rtl_write_word(rtlpriv, RB_CFO_LONG_DUMP, Adapter->RxStats.RxCfoTail[1]);
766
767}
768#endif
769
770static void rtl8821ae_dm_check_rssi_monitor(struct ieee80211_hw *hw)
771{
772 struct rtl_priv *rtlpriv = rtl_priv(hw);
773 struct rtl_sta_info *drv_priv;
774 u8 h2c_parameter[3] = { 0 };
775 long tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff;
776
777
778 /* AP & ADHOC & MESH */
779 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
780 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
781 if(drv_priv->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb)
782 tmp_entry_min_pwdb = drv_priv->rssi_stat.undecorated_smoothed_pwdb;
783 if(drv_priv->rssi_stat.undecorated_smoothed_pwdb > tmp_entry_max_pwdb)
784 tmp_entry_max_pwdb = drv_priv->rssi_stat.undecorated_smoothed_pwdb;
785
786 /*h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
787 h2c_parameter[1] = 0x20;
788 h2c_parameter[0] = drv_priv->rssi_stat;
789 rtl8821ae_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);*/
790 }
791 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
792
793 /* If associated entry is found */
794 if (tmp_entry_max_pwdb != 0) {
795 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = tmp_entry_max_pwdb;
796 RTPRINT(rtlpriv, FDM, DM_PWDB, ("EntryMaxPWDB = 0x%lx(%ld)\n",
797 tmp_entry_max_pwdb, tmp_entry_max_pwdb));
798 } else {
799 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
800 }
801 /* If associated entry is found */
802 if (tmp_entry_min_pwdb != 0xff) {
803 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = tmp_entry_min_pwdb;
804 RTPRINT(rtlpriv, FDM, DM_PWDB, ("EntryMinPWDB = 0x%lx(%ld)\n",
805 tmp_entry_min_pwdb, tmp_entry_min_pwdb));
806 } else {
807 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
808 }
809 /* Indicate Rx signal strength to FW. */
810 if (rtlpriv->dm.b_useramask) {
811 h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
812 h2c_parameter[1] = 0x20;
813 h2c_parameter[0] = 0;
814 rtl8821ae_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
815 } else {
816 rtl_write_byte(rtlpriv, 0x4fe, rtlpriv->dm.undecorated_smoothed_pwdb);
817 }
818 rtl8821ae_dm_find_minimum_rssi(hw);
819 dm_digtable.rssi_val_min = rtlpriv->dm.dm_digtable.min_undecorated_pwdb_for_dm;
820}
821
822void rtl8821ae_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 current_cca)
823{
824 struct rtl_priv *rtlpriv = rtl_priv(hw);
825
826 if (dm_digtable.cur_cck_cca_thres != current_cca)
827 rtl_write_byte(rtlpriv, DM_REG_CCK_CCA_11AC, current_cca);
828
829 dm_digtable.pre_cck_cca_thres = dm_digtable.cur_cck_cca_thres;
830 dm_digtable.cur_cck_cca_thres = current_cca;
831}
832
833void rtl8821ae_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi)
834{
835 struct rtl_priv *rtlpriv = rtl_priv(hw);
836 if(dm_digtable.stop_dig)
837 return;
838
839 if (dm_digtable.cur_igvalue != current_igi){
840 rtl_set_bbreg(hw, DM_REG_IGI_A_11AC, DM_BIT_IGI_11AC, current_igi);
841 if (rtlpriv->phy.rf_type != RF_1T1R)
842 rtl_set_bbreg(hw, DM_REG_IGI_B_11AC, DM_BIT_IGI_11AC, current_igi);
843 }
844 //dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
845 dm_digtable.cur_igvalue = current_igi;
846}
847
848static void rtl8821ae_dm_dig(struct ieee80211_hw *hw)
849{
850 struct rtl_priv *rtlpriv = rtl_priv(hw);
851 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
852 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
853 u8 dig_dynamic_min;
854 u8 dig_max_of_min;
855 bool first_connect, first_disconnect;
856 u8 dm_dig_max, dm_dig_min, offset;
857 u8 current_igi =dm_digtable.cur_igvalue;
858
859
860 RT_TRACE(COMP_DIG, DBG_LOUD,("rtl8821ae_dm_dig()==>\n"));
861
862
863 if (mac->act_scanning == true) {
864 RT_TRACE(COMP_DIG, DBG_LOUD,("rtl8821ae_dm_dig() Return: In Scan Progress \n"));
865 return;
866 }
867
868 /*add by Neil Chen to avoid PSD is processing*/
869 dig_dynamic_min = dm_digtable.dig_dynamic_min_0;
870 first_connect = (mac->link_state >= MAC80211_LINKED) &&
871 (dm_digtable.b_media_connect_0 == false);
872 first_disconnect = (mac->link_state < MAC80211_LINKED) &&
873 (dm_digtable.b_media_connect_0 == true);
874
875 /*1 Boundary Decision*/
876
877
878 dm_dig_max = 0x5A;
879
880 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8821AE)
881 dm_dig_min = DM_DIG_MIN;
882 else
883 dm_dig_min = 0x1C;
884
885 dig_max_of_min = DM_DIG_MAX_AP;
886
887 if (mac->link_state >= MAC80211_LINKED) {
888 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8821AE)
889 offset = 20;
890 else
891 offset = 10;
892
893 if ((dm_digtable.rssi_val_min + offset) > dm_dig_max)
894 dm_digtable.rx_gain_range_max = dm_dig_max;
895 else if ((dm_digtable.rssi_val_min + offset) < dm_dig_min)
896 dm_digtable.rx_gain_range_max = dm_dig_min;
897 else
898 dm_digtable.rx_gain_range_max = dm_digtable.rssi_val_min + offset;
899
900 if(rtlpriv->dm.b_one_entry_only){
901 offset = 0;
902
903 if (dm_digtable.rssi_val_min - offset < dm_dig_min)
904 dig_dynamic_min = dm_dig_min;
905 else if (dm_digtable.rssi_val_min - offset > dig_max_of_min)
906 dig_dynamic_min = dig_max_of_min;
907 else
908 dig_dynamic_min = dm_digtable.rssi_val_min - offset;
909
910 RT_TRACE(COMP_DIG, DBG_LOUD,
911 ("rtl8821ae_dm_dig() : bOneEntryOnly=TRUE, dig_dynamic_min=0x%x\n",
912 dig_dynamic_min));
913 RT_TRACE(COMP_DIG, DBG_LOUD,
914 ("rtl8821ae_dm_dig() : dm_digtable.rssi_val_min=%d",dm_digtable.
915 rssi_val_min));
916 } else {
917 dig_dynamic_min = dm_dig_min;
918 }
919 } else {
920 dm_digtable.rx_gain_range_max = dm_dig_max;
921 dig_dynamic_min = dm_dig_min;
922 RT_TRACE(COMP_DIG, DBG_LOUD,
923 ("rtl8821ae_dm_dig() : No Link\n"));
924 }
925
926 if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
927 RT_TRACE(COMP_DIG, DBG_LOUD,
928 ("rtl8821ae_dm_dig(): Abnornally false alarm case. \n"));
929
930 if (dm_digtable.large_fa_hit != 3)
931 dm_digtable.large_fa_hit++;
932 if (dm_digtable.forbidden_igi < current_igi) {
933 dm_digtable.forbidden_igi = current_igi;
934 dm_digtable.large_fa_hit = 1;
935 }
936
937 if (dm_digtable.large_fa_hit >= 3) {
938 if((dm_digtable.forbidden_igi + 1) > dm_digtable.rx_gain_range_max)
939 dm_digtable.rx_gain_range_min = dm_digtable.rx_gain_range_max;
940 else
941 dm_digtable.rx_gain_range_min = (dm_digtable.forbidden_igi + 1);
942 dm_digtable.recover_cnt = 3600;
943 }
944
945 } else {
946 /*Recovery mechanism for IGI lower bound*/
947 if (dm_digtable.recover_cnt != 0)
948 dm_digtable.recover_cnt --;
949 else {
950 if (dm_digtable.large_fa_hit < 3) {
951 if ((dm_digtable.forbidden_igi -1) < dig_dynamic_min) {
952 dm_digtable.forbidden_igi = dig_dynamic_min;
953 dm_digtable.rx_gain_range_min = dig_dynamic_min;
954 RT_TRACE(COMP_DIG, DBG_LOUD,
955 ("rtl8821ae_dm_dig(): Normal Case: At Lower Bound\n"));
956 } else {
957 dm_digtable.forbidden_igi --;
958 dm_digtable.rx_gain_range_min = (dm_digtable.forbidden_igi + 1);
959 RT_TRACE(COMP_DIG, DBG_LOUD,
960 ("rtl8821ae_dm_dig(): Normal Case: Approach Lower Bound\n"));
961 }
962 } else {
963 dm_digtable.large_fa_hit = 0;
964 }
965 }
966 }
967 RT_TRACE(COMP_DIG, DBG_LOUD,
968 ("rtl8821ae_dm_dig(): pDM_DigTable->LargeFAHit=%d\n",
969 dm_digtable.large_fa_hit));
970
971 if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 10)
972 dm_digtable.rx_gain_range_min = dm_dig_min;
973
974 if (dm_digtable.rx_gain_range_min > dm_digtable.rx_gain_range_max)
975 dm_digtable.rx_gain_range_min = dm_digtable.rx_gain_range_max;
976
977 /*Adjust initial gain by false alarm*/
978 if (mac->link_state >= MAC80211_LINKED) {
979 RT_TRACE(COMP_DIG, DBG_LOUD,
980 ("rtl8821ae_dm_dig(): DIG AfterLink\n"));
981 if (first_connect) {
982 if (dm_digtable.rssi_val_min <= dig_max_of_min)
983 current_igi = dm_digtable.rssi_val_min;
984 else
985 current_igi = dig_max_of_min;
986 RT_TRACE(COMP_DIG, DBG_LOUD,
987 ("rtl8821ae_dm_dig: First Connect\n"));
988 } else {
989 if(rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
990 current_igi = current_igi + 4;
991 else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
992 current_igi = current_igi + 2;
993 else if(rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
994 current_igi = current_igi - 2;
995
996 if((rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 10)
997 &&(rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)) {
998 current_igi = dm_digtable.rx_gain_range_min;
999 RT_TRACE(COMP_DIG, DBG_LOUD,
1000 ("rtl8821ae_dm_dig(): Beacon is less than 10 and FA is less than 768, IGI GOES TO 0x1E!!!!!!!!!!!!\n"));
1001 }
1002 }
1003 } else{
1004 RT_TRACE(COMP_DIG, DBG_LOUD,
1005 ("rtl8821ae_dm_dig(): DIG BeforeLink\n"));
1006 if (first_disconnect){
1007 current_igi = dm_digtable.rx_gain_range_min;
1008 RT_TRACE(COMP_DIG, DBG_LOUD,
1009 ("rtl8821ae_dm_dig(): First DisConnect \n"));
1010 } else {
1011 /*2012.03.30 LukeLee: enable DIG before link but with very high thresholds*/
1012 if (rtlpriv->falsealm_cnt.cnt_all > 2000)
1013 current_igi = current_igi + 4;
1014 else if (rtlpriv->falsealm_cnt.cnt_all > 600)
1015 current_igi = current_igi + 2;
1016 else if(rtlpriv->falsealm_cnt.cnt_all < 300)
1017 current_igi = current_igi - 2;
1018 if (current_igi >= 0x3e)
1019 current_igi = 0x3e;
1020 RT_TRACE(COMP_DIG, DBG_LOUD,("rtl8821ae_dm_dig(): England DIG \n"));
1021 }
1022 }
1023 RT_TRACE(COMP_DIG, DBG_LOUD,
1024 ("rtl8821ae_dm_dig(): DIG End Adjust IGI\n"));
1025 /* Check initial gain by upper/lower bound*/
1026
1027 if (current_igi > dm_digtable.rx_gain_range_max)
1028 current_igi = dm_digtable.rx_gain_range_max;
1029 if (current_igi < dm_digtable.rx_gain_range_min)
1030 current_igi = dm_digtable.rx_gain_range_min;
1031
1032 RT_TRACE(COMP_DIG, DBG_LOUD,
1033 ("rtl8821ae_dm_dig(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
1034 dm_digtable.rx_gain_range_max, dm_digtable.rx_gain_range_min));
1035 RT_TRACE(COMP_DIG, DBG_LOUD,
1036 ("rtl8821ae_dm_dig(): TotalFA=%d\n", rtlpriv->falsealm_cnt.cnt_all));
1037 RT_TRACE(COMP_DIG, DBG_LOUD,
1038 ("rtl8821ae_dm_dig(): CurIGValue=0x%x\n", current_igi));
1039
1040 rtl8821ae_dm_write_dig(hw, current_igi);
1041 dm_digtable.b_media_connect_0= ((mac->link_state >= MAC80211_LINKED) ? true :false);
1042 dm_digtable.dig_dynamic_min_0 = dig_dynamic_min;
1043}
1044
1045static void rtl8821ae_dm_common_info_self_update(struct ieee80211_hw *hw)
1046{
1047 struct rtl_priv *rtlpriv = rtl_priv(hw);
1048 u8 cnt = 0;
1049 struct rtl_sta_info *drv_priv;
1050
1051 rtlpriv->dm.b_one_entry_only = false;
1052
1053 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION &&
1054 rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
1055 rtlpriv->dm.b_one_entry_only = true;
1056 return;
1057 }
1058
1059 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
1060 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC ||
1061 rtlpriv->mac80211.opmode == NL80211_IFTYPE_MESH_POINT) {
1062 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1063 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
1064 cnt ++;
1065 }
1066 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1067
1068 if (cnt == 1)
1069 rtlpriv->dm.b_one_entry_only = true;
1070 }
1071}
1072
1073
1074static void rtl8821ae_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
1075{
1076 struct rtl_priv *rtlpriv = rtl_priv(hw);
1077 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
1078 u32 cck_enable =0;
1079
1080 /*read OFDM FA counter*/
1081 falsealm_cnt->cnt_ofdm_fail = rtl_get_bbreg(hw, ODM_REG_OFDM_FA_11AC, BMASKLWORD);
1082 falsealm_cnt->cnt_cck_fail = rtl_get_bbreg(hw, ODM_REG_CCK_FA_11AC, BMASKLWORD);
1083
1084 cck_enable = rtl_get_bbreg(hw, ODM_REG_BB_RX_PATH_11AC, BIT(28));
1085 if (cck_enable) /*if(pDM_Odm->pBandType == ODM_BAND_2_4G)*/
1086 falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail + falsealm_cnt->cnt_cck_fail;
1087 else
1088 falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail;
1089
1090 /*reset OFDM FA coutner*/
1091 rtl_set_bbreg(hw, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1);
1092 rtl_set_bbreg(hw, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0);
1093 /* reset CCK FA counter*/
1094 rtl_set_bbreg(hw, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0);
1095 rtl_set_bbreg(hw, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1);
1096
1097 RT_TRACE(COMP_DIG, DBG_LOUD, ("Cnt_Cck_fail=%d\n",
1098 falsealm_cnt->cnt_cck_fail));
1099 RT_TRACE(COMP_DIG, DBG_LOUD, ("cnt_ofdm_fail=%d\n",
1100 falsealm_cnt->cnt_ofdm_fail));
1101 RT_TRACE(COMP_DIG, DBG_LOUD, ("Total False Alarm=%d\n",
1102 falsealm_cnt->cnt_all));
1103}
1104
1105void rtl8812ae_dm_check_txpower_tracking_thermalmeter(
1106 struct ieee80211_hw *hw)
1107{
1108 struct rtl_priv *rtlpriv = rtl_priv(hw);
1109 static u8 tm_trigger = 0;
1110
1111 if (!rtlpriv->dm.btxpower_tracking)
1112 return;
1113
1114 if (!tm_trigger) {
1115 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER_88E, BIT(17)|BIT(16), 0x03);
1116 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1117 ("Trigger 8812 Thermal Meter!!\n"));
1118 tm_trigger = 1;
1119 return;
1120 } else {
1121 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1122 ("Schedule TxPowerTracking direct call!!\n"));
1123 rtl8812ae_dm_txpower_tracking_callback_thermalmeter(hw);
1124 tm_trigger = 0;
1125 }
1126}
1127
1128static void rtl8821ae_dm_iq_calibrate(struct ieee80211_hw *hw)
1129{
1130 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1131 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1132 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1133
1134 if (mac->link_state >= MAC80211_LINKED) {
1135 /*if ((*rtldm->p_channel != rtldm->pre_channel )
1136 && (!mac->act_scanning)) {
1137 rtldm->pre_channel = *rtldm->p_channel;
1138 rtldm->linked_interval = 0;
1139 }*/
1140
1141 if(rtldm->linked_interval < 3)
1142 rtldm->linked_interval ++;
1143
1144 if(rtldm->linked_interval == 2)
1145 {
1146 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1147 rtl8812ae_phy_iq_calibrate(hw, false);
1148 else
1149 rtl8821ae_phy_iq_calibrate(hw, false);
1150 }
1151 } else {
1152 rtldm->linked_interval = 0;
1153 }
1154}
1155
1156
1157void rtl8812ae_get_delta_swing_table(
1158 struct ieee80211_hw *hw,
1159 u8 **temperature_up_a,
1160 u8 **temperature_down_a,
1161 u8 **temperature_up_b,
1162 u8 **temperature_down_b
1163 )
1164{
1165 struct rtl_priv *rtlpriv = rtl_priv(hw);
1166 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1167 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1168 u8 channel = rtlphy->current_channel;
1169 u8 rate = rtldm->tx_rate;
1170
1171
1172 if ( 1 <= channel && channel <= 14) {
1173 if (RX_HAL_IS_CCK_RATE(rate)) {
1174 *temperature_up_a = rtldm->delta_swing_table_idx_24gccka_p;
1175 *temperature_down_a = rtldm->delta_swing_table_idx_24gccka_n;
1176 *temperature_up_b = rtldm->delta_swing_table_idx_24gcckb_p;
1177 *temperature_down_b = rtldm->delta_swing_table_idx_24gcckb_n;
1178 } else {
1179 *temperature_up_a = rtldm->delta_swing_table_idx_24ga_p;
1180 *temperature_down_a = rtldm->delta_swing_table_idx_24ga_n;
1181 *temperature_up_b = rtldm->delta_swing_table_idx_24gb_p;
1182 *temperature_down_b = rtldm->delta_swing_table_idx_24gb_n;
1183 }
1184 } else if ( 36 <= channel && channel <= 64) {
1185 *temperature_up_a = rtldm->delta_swing_table_idx_5ga_p[0];
1186 *temperature_down_a = rtldm->delta_swing_table_idx_5ga_n[0];
1187 *temperature_up_b = rtldm->delta_swing_table_idx_5gb_p[0];
1188 *temperature_down_b = rtldm->delta_swing_table_idx_5gb_n[0];
1189 } else if ( 100 <= channel && channel <= 140) {
1190 *temperature_up_a = rtldm->delta_swing_table_idx_5ga_p[1];
1191 *temperature_down_a = rtldm->delta_swing_table_idx_5ga_n[1];
1192 *temperature_up_b = rtldm->delta_swing_table_idx_5gb_p[1];
1193 *temperature_down_b = rtldm->delta_swing_table_idx_5gb_n[1];
1194 } else if ( 149 <= channel && channel <= 173) {
1195 *temperature_up_a = rtldm->delta_swing_table_idx_5ga_p[2];
1196 *temperature_down_a = rtldm->delta_swing_table_idx_5ga_n[2];
1197 *temperature_up_b = rtldm->delta_swing_table_idx_5gb_p[2];
1198 *temperature_down_b = rtldm->delta_swing_table_idx_5gb_n[2];
1199 } else {
1200 *temperature_up_a = (u8*)rtl8818e_delta_swing_table_idx_24gb_p_txpwrtrack;
1201 *temperature_down_a =(u8*)rtl8818e_delta_swing_table_idx_24gb_n_txpwrtrack;
1202 *temperature_up_b = (u8*)rtl8818e_delta_swing_table_idx_24gb_p_txpwrtrack;
1203 *temperature_down_b = (u8*)rtl8818e_delta_swing_table_idx_24gb_n_txpwrtrack;
1204 }
1205
1206 return;
1207}
1208
1209void rtl8812ae_phy_lccalibrate(
1210 struct ieee80211_hw *hw)
1211{
1212 struct rtl_priv *rtlpriv = rtl_priv(hw);
1213
1214 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===> rtl8812ae_phy_lccalibrate\n"));
1215
1216 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("<=== rtl8812ae_phy_lccalibrate\n"));
1217
1218}
1219
1220void rtl8812ae_dm_update_init_rate(
1221 struct ieee80211_hw *hw,
1222 u8 rate
1223 )
1224{
1225 struct rtl_priv *rtlpriv = rtl_priv(hw);
1226 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1227 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1228 u8 p = 0;
1229
1230 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1231 ("Get C2H Command! Rate=0x%x\n", rate));
1232
1233 rtldm->tx_rate = rate;
1234
1235 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE){
1236 rtl8821ae_dm_txpwr_track_set_pwr(hw, MIX_MODE, RF90_PATH_A, 0);
1237 }
1238 else
1239 {
1240 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1241 {
1242 rtl8812ae_dm_txpwr_track_set_pwr(hw, BBSWING, p, 0);
1243 }
1244 }
1245
1246}
1247
1248u8 rtl8812ae_hw_rate_to_mrate(
1249 struct ieee80211_hw *hw,
1250 u8 rate
1251 )
1252{
1253 struct rtl_priv *rtlpriv = rtl_priv(hw);
1254 u8 ret_rate = MGN_1M;
1255
1256
1257 switch(rate)
1258 {
1259 case DESC_RATE1M: ret_rate = MGN_1M; break;
1260 case DESC_RATE2M: ret_rate = MGN_2M; break;
1261 case DESC_RATE5_5M: ret_rate = MGN_5_5M; break;
1262 case DESC_RATE11M: ret_rate = MGN_11M; break;
1263 case DESC_RATE6M: ret_rate = MGN_6M; break;
1264 case DESC_RATE9M: ret_rate = MGN_9M; break;
1265 case DESC_RATE12M: ret_rate = MGN_12M; break;
1266 case DESC_RATE18M: ret_rate = MGN_18M; break;
1267 case DESC_RATE24M: ret_rate = MGN_24M; break;
1268 case DESC_RATE36M: ret_rate = MGN_36M; break;
1269 case DESC_RATE48M: ret_rate = MGN_48M; break;
1270 case DESC_RATE54M: ret_rate = MGN_54M; break;
1271 case DESC_RATEMCS0: ret_rate = MGN_MCS0; break;
1272 case DESC_RATEMCS1: ret_rate = MGN_MCS1; break;
1273 case DESC_RATEMCS2: ret_rate = MGN_MCS2; break;
1274 case DESC_RATEMCS3: ret_rate = MGN_MCS3; break;
1275 case DESC_RATEMCS4: ret_rate = MGN_MCS4; break;
1276 case DESC_RATEMCS5: ret_rate = MGN_MCS5; break;
1277 case DESC_RATEMCS6: ret_rate = MGN_MCS6; break;
1278 case DESC_RATEMCS7: ret_rate = MGN_MCS7; break;
1279 case DESC_RATEMCS8: ret_rate = MGN_MCS8; break;
1280 case DESC_RATEMCS9: ret_rate = MGN_MCS9; break;
1281 case DESC_RATEMCS10: ret_rate = MGN_MCS10; break;
1282 case DESC_RATEMCS11: ret_rate = MGN_MCS11; break;
1283 case DESC_RATEMCS12: ret_rate = MGN_MCS12; break;
1284 case DESC_RATEMCS13: ret_rate = MGN_MCS13; break;
1285 case DESC_RATEMCS14: ret_rate = MGN_MCS14; break;
1286 case DESC_RATEMCS15: ret_rate = MGN_MCS15; break;
1287 case DESC_RATEVHT1SS_MCS0: ret_rate = MGN_VHT1SS_MCS0; break;
1288 case DESC_RATEVHT1SS_MCS1: ret_rate = MGN_VHT1SS_MCS1; break;
1289 case DESC_RATEVHT1SS_MCS2: ret_rate = MGN_VHT1SS_MCS2; break;
1290 case DESC_RATEVHT1SS_MCS3: ret_rate = MGN_VHT1SS_MCS3; break;
1291 case DESC_RATEVHT1SS_MCS4: ret_rate = MGN_VHT1SS_MCS4; break;
1292 case DESC_RATEVHT1SS_MCS5: ret_rate = MGN_VHT1SS_MCS5; break;
1293 case DESC_RATEVHT1SS_MCS6: ret_rate = MGN_VHT1SS_MCS6; break;
1294 case DESC_RATEVHT1SS_MCS7: ret_rate = MGN_VHT1SS_MCS7; break;
1295 case DESC_RATEVHT1SS_MCS8: ret_rate = MGN_VHT1SS_MCS8; break;
1296 case DESC_RATEVHT1SS_MCS9: ret_rate = MGN_VHT1SS_MCS9; break;
1297 case DESC_RATEVHT2SS_MCS0: ret_rate = MGN_VHT2SS_MCS0; break;
1298 case DESC_RATEVHT2SS_MCS1: ret_rate = MGN_VHT2SS_MCS1; break;
1299 case DESC_RATEVHT2SS_MCS2: ret_rate = MGN_VHT2SS_MCS2; break;
1300 case DESC_RATEVHT2SS_MCS3: ret_rate = MGN_VHT2SS_MCS3; break;
1301 case DESC_RATEVHT2SS_MCS4: ret_rate = MGN_VHT2SS_MCS4; break;
1302 case DESC_RATEVHT2SS_MCS5: ret_rate = MGN_VHT2SS_MCS5; break;
1303 case DESC_RATEVHT2SS_MCS6: ret_rate = MGN_VHT2SS_MCS6; break;
1304 case DESC_RATEVHT2SS_MCS7: ret_rate = MGN_VHT2SS_MCS7; break;
1305 case DESC_RATEVHT2SS_MCS8: ret_rate = MGN_VHT2SS_MCS8; break;
1306 case DESC_RATEVHT2SS_MCS9: ret_rate = MGN_VHT2SS_MCS9; break;
1307
1308 default:
1309 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1310 ("HwRateToMRate8812(): Non supported Rate [%x]!!!\n",rate ));
1311 break;
1312 }
1313 return ret_rate;
1314}
1315
1316/*-----------------------------------------------------------------------------
1317 * Function: odm_TxPwrTrackSetPwr88E()
1318 *
1319 * Overview: 88E change all channel tx power accordign to flag.
1320 * OFDM & CCK are all different.
1321 *
1322 * Input: NONE
1323 *
1324 * Output: NONE
1325 *
1326 * Return: NONE
1327 *
1328 * Revised History:
1329 * When Who Remark
1330 * 04/23/2012 MHC Create Version 0.
1331 *
1332 *---------------------------------------------------------------------------*/
1333void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
1334 enum pwr_track_control_method method, u8 rf_path, u8 channel_mapped_index)
1335{
1336 struct rtl_priv *rtlpriv = rtl_priv(hw);
1337 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1338 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1339 u32 final_bb_swing_idx[2];
1340 u8 pwr_tracking_limit = 26; /*+1.0dB*/
1341 u8 tx_rate = 0xFF;
1342 s8 final_ofdm_swing_index = 0;
1343
1344 if(rtldm->tx_rate != 0xFF)
1345 tx_rate = rtl8812ae_hw_rate_to_mrate(hw, rtldm->tx_rate);
1346
1347
1348 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1349 ("===>rtl8812ae_dm_txpwr_track_set_pwr\n"));
1350
1351 if(tx_rate != 0xFF) { /*20130429 Mimic Modify High Rate BBSwing Limit.*/
1352 /*CCK*/
1353 if((tx_rate >= MGN_1M) && (tx_rate <= MGN_11M))
1354 pwr_tracking_limit = 32; /*+4dB*/
1355 /*OFDM*/
1356 else if((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
1357 pwr_tracking_limit = 30; /*+3dB*/
1358 else if(tx_rate == MGN_54M)
1359 pwr_tracking_limit = 28; /*+2dB*/
1360 /*HT*/
1361 else if((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2)) /*QPSK/BPSK*/
1362 pwr_tracking_limit = 34; /*+5dB*/
1363 else if((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4)) /*16QAM*/
1364 pwr_tracking_limit = 30; /*+3dB*/
1365 else if((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7)) /*64QAM*/
1366 pwr_tracking_limit = 28; /*+2dB*/
1367
1368 else if((tx_rate >= MGN_MCS8) && (tx_rate <= MGN_MCS10)) /*QPSK/BPSK*/
1369 pwr_tracking_limit = 34; /*+5dB*/
1370 else if((tx_rate >= MGN_MCS11) && (tx_rate <= MGN_MCS12)) /*16QAM*/
1371 pwr_tracking_limit = 30; /*+3dB*/
1372 else if((tx_rate >= MGN_MCS13) && (tx_rate <= MGN_MCS15)) /*64QAM*/
1373 pwr_tracking_limit = 28; /*+2dB*/
1374
1375 /*2 VHT*/
1376 else if((tx_rate >= MGN_VHT1SS_MCS0) && (tx_rate <= MGN_VHT1SS_MCS2)) /*QPSK/BPSK*/
1377 pwr_tracking_limit = 34; /*+5dB*/
1378 else if((tx_rate >= MGN_VHT1SS_MCS3) && (tx_rate <= MGN_VHT1SS_MCS4)) /*16QAM*/
1379 pwr_tracking_limit = 30; /*+3dB*/
1380 else if((tx_rate >= MGN_VHT1SS_MCS5)&&(tx_rate <= MGN_VHT1SS_MCS6)) /*64QAM*/
1381 pwr_tracking_limit = 28; /*+2dB*/
1382 else if(tx_rate == MGN_VHT1SS_MCS7) /*64QAM*/
1383 pwr_tracking_limit = 26; /*+1dB*/
1384 else if(tx_rate == MGN_VHT1SS_MCS8) /*256QAM*/
1385 pwr_tracking_limit = 24; /*+0dB*/
1386 else if(tx_rate == MGN_VHT1SS_MCS9) /*256QAM*/
1387 pwr_tracking_limit = 22; /*-1dB*/
1388
1389 else if((tx_rate >= MGN_VHT2SS_MCS0)&&(tx_rate <= MGN_VHT2SS_MCS2)) /*QPSK/BPSK*/
1390 pwr_tracking_limit = 34; /*+5dB*/
1391 else if((tx_rate >= MGN_VHT2SS_MCS3)&&(tx_rate <= MGN_VHT2SS_MCS4)) /*16QAM*/
1392 pwr_tracking_limit = 30; /*+3dB*/
1393 else if((tx_rate >= MGN_VHT2SS_MCS5)&&(tx_rate <= MGN_VHT2SS_MCS6)) /*64QAM*/
1394 pwr_tracking_limit = 28; /*+2dB*/
1395 else if(tx_rate == MGN_VHT2SS_MCS7) /*64QAM*/
1396 pwr_tracking_limit = 26; /*+1dB*/
1397 else if(tx_rate == MGN_VHT2SS_MCS8) /*256QAM*/
1398 pwr_tracking_limit = 24; /*+0dB*/
1399 else if(tx_rate == MGN_VHT2SS_MCS9) /*256QAM*/
1400 pwr_tracking_limit = 22; /*-1dB*/
1401 else
1402 pwr_tracking_limit = 24;
1403 }
1404 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1405 ("TxRate=0x%x, PwrTrackingLimit=%d\n", tx_rate, pwr_tracking_limit));
1406
1407
1408 if (method == BBSWING) {
1409 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1410 ("===>rtl8812ae_dm_txpwr_track_set_pwr\n"));
1411
1412 if (rf_path == RF90_PATH_A) {
1413 final_bb_swing_idx[RF90_PATH_A] =
1414 (rtldm->ofdm_index[RF90_PATH_A] > pwr_tracking_limit) ?
1415 pwr_tracking_limit : rtldm->ofdm_index[RF90_PATH_A];
1416 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1417 ("pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]=%d, \
1418 pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n",
1419 rtldm->ofdm_index[RF90_PATH_A], final_bb_swing_idx[RF90_PATH_A]));
1420
1421 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[final_bb_swing_idx[RF90_PATH_A]]);
1422 } else {
1423 final_bb_swing_idx[RF90_PATH_B] =
1424 rtldm->ofdm_index[RF90_PATH_B] > pwr_tracking_limit ? \
1425 pwr_tracking_limit : rtldm->ofdm_index[RF90_PATH_B];
1426 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1427 ("pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_B]=%d, \
1428 pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_B]=%d\n",
1429 rtldm->ofdm_index[RF90_PATH_B], final_bb_swing_idx[RF90_PATH_B]));
1430
1431 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[final_bb_swing_idx[RF90_PATH_B]]);
1432 }
1433 } else if (method == MIX_MODE) {
1434 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1435 ("pDM_Odm->DefaultOfdmIndex=%d, \
1436 pDM_Odm->Aboslute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
1437 rtldm->default_ofdm_index, rtldm->aboslute_ofdm_swing_idx[rf_path],
1438 rf_path ));
1439
1440
1441 final_ofdm_swing_index = rtldm->default_ofdm_index + rtldm->aboslute_ofdm_swing_idx[rf_path];
1442
1443 if (rf_path == RF90_PATH_A) {
1444 if(final_ofdm_swing_index > pwr_tracking_limit) { /*BBSwing higher then Limit*/
1445
1446 rtldm->remnant_cck_idx = final_ofdm_swing_index - pwr_tracking_limit;
1447 /* CCK Follow the same compensate value as Path A*/
1448 rtldm->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit;
1449
1450 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[pwr_tracking_limit]);
1451
1452 rtldm->modify_txagc_flag_path_a = true;
1453
1454 /*Set TxAGC Page C{};*/
1455 rtl8821ae_phy_set_txpower_level_by_path(hw, rtlphy->current_channel, RF90_PATH_A);
1456
1457 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1458 ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n",
1459 pwr_tracking_limit, rtldm->remnant_ofdm_swing_idx[rf_path]));
1460 } else if (final_ofdm_swing_index < 0) {
1461 rtldm->remnant_cck_idx = final_ofdm_swing_index;
1462 /* CCK Follow the same compensate value as Path A*/
1463 rtldm->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index;
1464
1465 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[0]);
1466
1467 rtldm->modify_txagc_flag_path_a = true;
1468
1469 /*Set TxAGC Page C{};*/
1470 rtl8821ae_phy_set_txpower_level_by_path(hw, rtlphy->current_channel, RF90_PATH_A);
1471
1472 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1473 ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n",
1474 rtldm->remnant_ofdm_swing_idx[rf_path]));
1475 } else {
1476 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[final_ofdm_swing_index]);
1477
1478 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1479 ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n",
1480 final_ofdm_swing_index));
1481
1482 if(rtldm->modify_txagc_flag_path_a) { /*If TxAGC has changed, reset TxAGC again*/
1483 rtldm->remnant_cck_idx = 0;
1484 rtldm->remnant_ofdm_swing_idx[rf_path] = 0;
1485
1486 /*Set TxAGC Page C{};*/
1487 rtl8821ae_phy_set_txpower_level_by_path(hw, rtlphy->current_channel, RF90_PATH_A);
1488
1489 rtldm->modify_txagc_flag_path_a = false;
1490
1491 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1492 ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n"));
1493 }
1494 }
1495 }
1496
1497 if (rf_path == RF90_PATH_B) {
1498 if(final_ofdm_swing_index > pwr_tracking_limit) { /*BBSwing higher then Limit*/
1499 rtldm->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit;
1500
1501 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[pwr_tracking_limit]);
1502
1503 rtldm->modify_txagc_flag_path_b = true;
1504
1505 /*Set TxAGC Page E{};*/
1506 rtl8821ae_phy_set_txpower_level_by_path(hw, rtlphy->current_channel, RF90_PATH_B);
1507
1508 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1509 ("******Path_B Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n",
1510 pwr_tracking_limit, rtldm->remnant_ofdm_swing_idx[rf_path]));
1511 } else if (final_ofdm_swing_index < 0) {
1512 rtldm->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index;
1513
1514 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[0]);
1515
1516 rtldm->modify_txagc_flag_path_b = true;
1517
1518 /*Set TxAGC Page E{};*/
1519 rtl8821ae_phy_set_txpower_level_by_path(hw, rtlphy->current_channel, RF90_PATH_B);
1520
1521 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1522 ("******Path_B Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n",
1523 rtldm->remnant_ofdm_swing_idx[rf_path] ));
1524 } else {
1525 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[final_ofdm_swing_index]);
1526
1527 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1528 ("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n",
1529 final_ofdm_swing_index));
1530
1531 if(rtldm->modify_txagc_flag_path_b) { /*If TxAGC has changed, reset TxAGC again*/
1532 rtldm->remnant_ofdm_swing_idx[rf_path] = 0;
1533
1534 /*Set TxAGC Page E{};*/
1535 rtl8821ae_phy_set_txpower_level_by_path(hw, rtlphy->current_channel, RF90_PATH_B);
1536
1537 rtldm->modify_txagc_flag_path_b = false;
1538
1539 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1540 ("******Path_B pDM_Odm->Modify_TxAGC_Flag = FALSE \n"));
1541 }
1542 }
1543 }
1544
1545 } else {
1546 return;
1547 }
1548}
1549
1550void rtl8812ae_dm_txpower_tracking_callback_thermalmeter
1551 (struct ieee80211_hw *hw)
1552{
1553 struct rtl_priv *rtlpriv = rtl_priv(hw);
1554 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1555 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1556 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1557 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1558
1559 u8 thermal_value = 0, delta, delta_lck, delta_iqk, p = 0, i = 0;
1560 u8 thermal_value_avg_count = 0;
1561 u32 thermal_value_avg = 0;
1562
1563 u8 ofdm_min_index = 6; /*OFDM BB Swing should be less than +3.0dB, which is required by Arthur*/
1564 u8 index_for_channel = 0; /* GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/
1565
1566 /* 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/
1567 u8 *delta_swing_table_idx_tup_a;
1568 u8 *delta_swing_table_idx_tdown_a;
1569 u8 *delta_swing_table_idx_tup_b;
1570 u8 *delta_swing_table_idx_tdown_b;
1571
1572 /*2. Initilization ( 7 steps in total )*/
1573 rtl8812ae_get_delta_swing_table(hw, (u8**)&delta_swing_table_idx_tup_a,
1574 (u8**)&delta_swing_table_idx_tdown_a,
1575 (u8**)&delta_swing_table_idx_tup_b,
1576 (u8**)&delta_swing_table_idx_tdown_b);
1577
1578 rtldm->btxpower_trackinginit = true;
1579
1580 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1581 ("===>rtl8812ae_dm_txpower_tracking_callback_thermalmeter, \
1582 \n pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase[A]:\
1583 %d, pDM_Odm->DefaultOfdmIndex: %d\n",
1584 rtldm->bb_swing_idx_cck_base,
1585 rtldm->bb_swing_idx_ofdm_base[RF90_PATH_A],
1586 rtldm->default_ofdm_index));
1587
1588 thermal_value = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER_8812A, 0xfc00); /*0x42: RF Reg[15:10] 88E*/
1589 if( ! rtldm->txpower_track_control || rtlefuse->eeprom_thermalmeter == 0 ||
1590 rtlefuse->eeprom_thermalmeter == 0xFF)
1591 return;
1592
1593
1594 /* 3. Initialize ThermalValues of RFCalibrateInfo*/
1595
1596 if(rtlhal->reloadtxpowerindex)
1597 {
1598 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1599 ("reload ofdm index for band switch\n"));
1600 }
1601
1602 /*4. Calculate average thermal meter*/
1603 rtldm->thermalvalue_avg[rtldm->thermalvalue_avg_index] = thermal_value;
1604 rtldm->thermalvalue_avg_index++;
1605 if(rtldm->thermalvalue_avg_index == AVG_THERMAL_NUM_8812A)
1606 /*Average times = c.AverageThermalNum*/
1607 rtldm->thermalvalue_avg_index = 0;
1608
1609 for(i = 0; i < AVG_THERMAL_NUM_8812A; i++)
1610 {
1611 if(rtldm->thermalvalue_avg[i])
1612 {
1613 thermal_value_avg += rtldm->thermalvalue_avg[i];
1614 thermal_value_avg_count++;
1615 }
1616 }
1617
1618 if(thermal_value_avg_count) /*Calculate Average ThermalValue after average enough times*/
1619 {
1620 thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
1621 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1622 ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n",
1623 thermal_value, rtlefuse->eeprom_thermalmeter));
1624 }
1625
1626 /*5. Calculate delta, delta_LCK, delta_IQK.*/
1627 /*"delta" here is used to determine whether thermal value changes or not.*/
1628 delta = (thermal_value > rtldm->thermalvalue) ? \
1629 (thermal_value - rtldm->thermalvalue): \
1630 (rtldm->thermalvalue - thermal_value);
1631 delta_lck = (thermal_value > rtldm->thermalvalue_lck) ? \
1632 (thermal_value - rtldm->thermalvalue_lck) : \
1633 (rtldm->thermalvalue_lck - thermal_value);
1634 delta_iqk = (thermal_value > rtldm->thermalvalue_iqk) ? \
1635 (thermal_value - rtldm->thermalvalue_iqk) : \
1636 (rtldm->thermalvalue_iqk - thermal_value);
1637
1638 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1639 ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n",
1640 delta, delta_lck, delta_iqk));
1641
1642 /* 6. If necessary, do LCK. */
1643
1644 if (delta_lck >= IQK_THRESHOLD) /*Delta temperature is equal to or larger than 20 centigrade.*/
1645 {
1646 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1647 ("delta_LCK(%d) >= Threshold_IQK(%d)\n",
1648 delta_lck, IQK_THRESHOLD));
1649 rtldm->thermalvalue_lck = thermal_value;
1650 rtl8812ae_phy_lccalibrate(hw);
1651 }
1652
1653 /*7. If necessary, move the index of swing table to adjust Tx power.*/
1654
1655 if (delta > 0 && rtldm->txpower_track_control)
1656 {
1657 /*"delta" here is used to record the absolute value of differrence.*/
1658 delta = thermal_value > rtlefuse->eeprom_thermalmeter ? \
1659 (thermal_value - rtlefuse->eeprom_thermalmeter) : \
1660 (rtlefuse->eeprom_thermalmeter - thermal_value);
1661
1662 if (delta >= TXPWR_TRACK_TABLE_SIZE)
1663 delta = TXPWR_TRACK_TABLE_SIZE - 1;
1664
1665 /*7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/
1666
1667 if(thermal_value > rtlefuse->eeprom_thermalmeter) {
1668
1669 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1670 ("delta_swing_table_idx_tup_a[%d] = %d\n",
1671 delta, delta_swing_table_idx_tup_a[delta]));
1672 rtldm->delta_power_index_last[RF90_PATH_A] = rtldm->delta_power_index[RF90_PATH_A];
1673 rtldm->delta_power_index[RF90_PATH_A] = delta_swing_table_idx_tup_a[delta];
1674
1675 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_A] = delta_swing_table_idx_tup_a[delta];
1676 /*Record delta swing for mix mode power tracking*/
1677
1678 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1679 ("******Temp is higher and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n",
1680 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_A]));
1681
1682
1683 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1684 ("delta_swing_table_idx_tup_b[%d] = %d\n",
1685 delta, delta_swing_table_idx_tup_b[delta]));
1686 rtldm->delta_power_index_last[RF90_PATH_B] = rtldm->delta_power_index[RF90_PATH_B];
1687 rtldm->delta_power_index[RF90_PATH_B] = delta_swing_table_idx_tup_b[delta];
1688
1689 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_B] = delta_swing_table_idx_tup_b[delta];
1690 /*Record delta swing for mix mode power tracking*/
1691
1692 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1693 ("******Temp is higher and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n",
1694 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_B]));
1695
1696 } else {
1697 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1698 ("delta_swing_table_idx_tdown_a[%d] = %d\n",
1699 delta, delta_swing_table_idx_tdown_a[delta]));
1700
1701 rtldm->delta_power_index_last[RF90_PATH_A] = rtldm->delta_power_index[RF90_PATH_A];
1702 rtldm->delta_power_index[RF90_PATH_A] = -1 * delta_swing_table_idx_tdown_a[delta];
1703
1704 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_A] = -1 * delta_swing_table_idx_tdown_a[delta];
1705 /* Record delta swing for mix mode power tracking*/
1706 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1707 ("******Temp is lower and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n",
1708 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_A]));
1709
1710
1711 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1712 ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n",
1713 delta, delta_swing_table_idx_tdown_b[delta]));
1714
1715 rtldm->delta_power_index_last[RF90_PATH_B] = rtldm->delta_power_index[RF90_PATH_B];
1716 rtldm->delta_power_index[RF90_PATH_B] = -1 * delta_swing_table_idx_tdown_b[delta];
1717
1718 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_B] = -1 * delta_swing_table_idx_tdown_b[delta];
1719 /*Record delta swing for mix mode power tracking*/
1720
1721 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1722 ("******Temp is lower and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n",
1723 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_B]));
1724 }
1725
1726 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1727 {
1728 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1729 ("\n\n================================ [Path-%c] \
1730 Calculating PowerIndexOffset ================================\n",
1731 (p == RF90_PATH_A ? 'A' : 'B')));
1732
1733 if (rtldm->delta_power_index[p] == rtldm->delta_power_index_last[p])
1734 /*If Thermal value changes but lookup table value still the same*/
1735 rtldm->power_index_offset[p] = 0;
1736 else
1737 rtldm->power_index_offset[p] =
1738 rtldm->delta_power_index[p] - rtldm->delta_power_index_last[p];
1739 /*Power Index Diff between 2 times Power Tracking*/
1740
1741 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1742 ("[Path-%c] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n",
1743 (p == RF90_PATH_A ? 'A' : 'B'),
1744 rtldm->power_index_offset[p],
1745 rtldm->delta_power_index[p] ,
1746 rtldm->delta_power_index_last[p]));
1747
1748 rtldm->ofdm_index[p] =
1749 rtldm->bb_swing_idx_ofdm_base[p] + rtldm->power_index_offset[p];
1750 rtldm->cck_index =
1751 rtldm->bb_swing_idx_cck_base + rtldm->power_index_offset[p];
1752
1753 rtldm->bb_swing_idx_cck = rtldm->cck_index;
1754 rtldm->bb_swing_idx_ofdm[p] = rtldm->ofdm_index[p];
1755
1756 /*************Print BB Swing Base and Index Offset*************/
1757
1758 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1759 ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n",
1760 rtldm->bb_swing_idx_cck,
1761 rtldm->bb_swing_idx_cck_base,
1762 rtldm->power_index_offset[p]));
1763 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1764 ("The 'OFDM' final index(%d) = BaseIndex[%c](%d) + PowerIndexOffset(%d)\n",
1765 rtldm->bb_swing_idx_ofdm[p],
1766 (p == RF90_PATH_A ? 'A' : 'B'),
1767 rtldm->bb_swing_idx_ofdm_base[p],
1768 rtldm->power_index_offset[p]));
1769
1770 /*7.1 Handle boundary conditions of index.*/
1771
1772
1773 if(rtldm->ofdm_index[p] > TXSCALE_TABLE_SIZE -1)
1774 {
1775 rtldm->ofdm_index[p] = TXSCALE_TABLE_SIZE -1;
1776 }
1777 else if (rtldm->ofdm_index[p] < ofdm_min_index)
1778 {
1779 rtldm->ofdm_index[p] = ofdm_min_index;
1780 }
1781 }
1782 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1783 ("\n\n======================================================\
1784 ==================================================\n"));
1785 if(rtldm->cck_index > TXSCALE_TABLE_SIZE -1)
1786 rtldm->cck_index = TXSCALE_TABLE_SIZE -1;
1787 else if (rtldm->cck_index < 0)
1788 rtldm->cck_index = 0;
1789 } else {
1790 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1791 ("The thermal meter is unchanged or TxPowerTracking OFF(%d): \
1792 ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d\n",
1793 rtldm->txpower_track_control,
1794 thermal_value,
1795 rtldm->thermalvalue));
1796
1797 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1798 rtldm->power_index_offset[p] = 0;
1799 }
1800 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1801 ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
1802 rtldm->cck_index, rtldm->bb_swing_idx_cck_base)); /*Print Swing base & current*/
1803 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1804 {
1805 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1806 ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%c]: %d\n",
1807 rtldm->ofdm_index[p],
1808 (p == RF90_PATH_A ? 'A' : 'B'),
1809 rtldm->bb_swing_idx_ofdm_base[p]));
1810 }
1811
1812 if ((rtldm->power_index_offset[RF90_PATH_A] != 0 ||
1813 rtldm->power_index_offset[RF90_PATH_B] != 0 ) &&
1814 rtldm->txpower_track_control)
1815 {
1816 /*7.2 Configure the Swing Table to adjust Tx Power.*/
1817 /*Always TRUE after Tx Power is adjusted by power tracking.*/
1818 /*
1819 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
1820 to increase TX power. Otherwise, EVM will be bad.
1821
1822 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
1823 */
1824 if (thermal_value > rtldm->thermalvalue)
1825 {
1826 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1827 ("Temperature Increasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
1828 rtldm->power_index_offset[RF90_PATH_A],
1829 delta, thermal_value,
1830 rtlefuse->eeprom_thermalmeter,
1831 rtldm->thermalvalue));
1832
1833 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1834 ("Temperature Increasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
1835 rtldm->power_index_offset[RF90_PATH_B],
1836 delta, thermal_value,
1837 rtlefuse->eeprom_thermalmeter,
1838 rtldm->thermalvalue));
1839
1840 } else if (thermal_value < rtldm->thermalvalue) { /*Low temperature*/
1841 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1842 ("Temperature Decreasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
1843 rtldm->power_index_offset[RF90_PATH_A],
1844 delta, thermal_value,
1845 rtlefuse->eeprom_thermalmeter,
1846 rtldm->thermalvalue));
1847
1848 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1849 ("Temperature Decreasing(B): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
1850 rtldm->power_index_offset[RF90_PATH_B],
1851 delta, thermal_value,
1852 rtlefuse->eeprom_thermalmeter,
1853 rtldm->thermalvalue));
1854 }
1855
1856 if (thermal_value > rtlefuse->eeprom_thermalmeter) {
1857 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1858 ("Temperature(%d) higher than PG value(%d)\n",
1859 thermal_value, rtlefuse->eeprom_thermalmeter));
1860
1861
1862 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1863 ("**********Enter POWER Tracking MIX_MODE**********\n"));
1864 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1865 rtl8812ae_dm_txpwr_track_set_pwr(hw, MIX_MODE, p, 0);
1866
1867 } else {
1868 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1869 ("Temperature(%d) lower than PG value(%d)\n",
1870 thermal_value, rtlefuse->eeprom_thermalmeter));
1871
1872
1873 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1874 ("**********Enter POWER Tracking MIX_MODE**********\n"));
1875 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1876 rtl8812ae_dm_txpwr_track_set_pwr(hw, MIX_MODE, p, index_for_channel);
1877
1878 }
1879
1880 rtldm->bb_swing_idx_cck_base = rtldm->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
1881 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8812A; p++)
1882 rtldm->bb_swing_idx_ofdm_base[p] = rtldm->bb_swing_idx_ofdm[p];
1883
1884 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1885 ("pDM_Odm->RFCalibrateInfo.ThermalValue = %d ThermalValue= %d\n",
1886 rtldm->thermalvalue, thermal_value));
1887
1888 rtldm->thermalvalue = thermal_value; /*Record last Power Tracking Thermal Value*/
1889
1890 }
1891 /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
1892 if ((delta_iqk >= IQK_THRESHOLD)) {
1893
1894 if ( !rtlphy->b_iqk_in_progress) {
1895
1896 spin_lock(&rtlpriv->locks.iqk_lock);
1897 rtlphy->b_iqk_in_progress = true;
1898 spin_unlock(&rtlpriv->locks.iqk_lock);
1899
1900 rtl8812ae_do_iqk(hw, delta_iqk, thermal_value, 8);
1901
1902 spin_lock(&rtlpriv->locks.iqk_lock);
1903 rtlphy->b_iqk_in_progress = false;
1904 spin_unlock(&rtlpriv->locks.iqk_lock);
1905 }
1906 }
1907
1908 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
1909 ("<===rtl8812ae_dm_txpower_tracking_callback_thermalmeter\n"));
1910}
1911
1912
1913void rtl8821ae_get_delta_swing_table(
1914 struct ieee80211_hw *hw,
1915 u8 **temperature_up_a,
1916 u8 **temperature_down_a,
1917 u8 **temperature_up_b,
1918 u8 **temperature_down_b
1919 )
1920{
1921 struct rtl_priv *rtlpriv = rtl_priv(hw);
1922 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1923 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1924 u8 channel = rtlphy->current_channel;
1925 u8 rate = rtldm->tx_rate;
1926
1927
1928 if ( 1 <= channel && channel <= 14) {
1929 if (RX_HAL_IS_CCK_RATE(rate)) {
1930 *temperature_up_a = rtldm->delta_swing_table_idx_24gccka_p;
1931 *temperature_down_a = rtldm->delta_swing_table_idx_24gccka_n;
1932 *temperature_up_b = rtldm->delta_swing_table_idx_24gcckb_p;
1933 *temperature_down_b = rtldm->delta_swing_table_idx_24gcckb_n;
1934 } else {
1935 *temperature_up_a = rtldm->delta_swing_table_idx_24ga_p;
1936 *temperature_down_a = rtldm->delta_swing_table_idx_24ga_n;
1937 *temperature_up_b = rtldm->delta_swing_table_idx_24gb_p;
1938 *temperature_down_b = rtldm->delta_swing_table_idx_24gb_n;
1939 }
1940 } else if ( 36 <= channel && channel <= 64) {
1941 *temperature_up_a = rtldm->delta_swing_table_idx_5ga_p[0];
1942 *temperature_down_a = rtldm->delta_swing_table_idx_5ga_n[0];
1943 *temperature_up_b = rtldm->delta_swing_table_idx_5gb_p[0];
1944 *temperature_down_b = rtldm->delta_swing_table_idx_5gb_n[0];
1945 } else if ( 100 <= channel && channel <= 140) {
1946 *temperature_up_a = rtldm->delta_swing_table_idx_5ga_p[1];
1947 *temperature_down_a = rtldm->delta_swing_table_idx_5ga_n[1];
1948 *temperature_up_b = rtldm->delta_swing_table_idx_5gb_p[1];
1949 *temperature_down_b = rtldm->delta_swing_table_idx_5gb_n[1];
1950 } else if ( 149 <= channel && channel <= 173) {
1951 *temperature_up_a = rtldm->delta_swing_table_idx_5ga_p[2];
1952 *temperature_down_a = rtldm->delta_swing_table_idx_5ga_n[2];
1953 *temperature_up_b = rtldm->delta_swing_table_idx_5gb_p[2];
1954 *temperature_down_b = rtldm->delta_swing_table_idx_5gb_n[2];
1955 } else {
1956 *temperature_up_a = (u8*)rtl8818e_delta_swing_table_idx_24gb_p_txpwrtrack;
1957 *temperature_down_a =(u8*)rtl8818e_delta_swing_table_idx_24gb_n_txpwrtrack;
1958 *temperature_up_b = (u8*)rtl8818e_delta_swing_table_idx_24gb_p_txpwrtrack;
1959 *temperature_down_b = (u8*)rtl8818e_delta_swing_table_idx_24gb_n_txpwrtrack;
1960 }
1961
1962 return;
1963}
1964
1965void rtl8821ae_phy_lccalibrate(
1966 struct ieee80211_hw *hw)
1967{
1968 struct rtl_priv *rtlpriv = rtl_priv(hw);
1969
1970 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===> rtl8812ae_phy_lccalibrate\n"));
1971
1972 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("<=== rtl8812ae_phy_lccalibrate\n"));
1973
1974}
1975
1976/*-----------------------------------------------------------------------------
1977 * Function: odm_TxPwrTrackSetPwr88E()
1978 *
1979 * Overview: 88E change all channel tx power accordign to flag.
1980 * OFDM & CCK are all different.
1981 *
1982 * Input: NONE
1983 *
1984 * Output: NONE
1985 *
1986 * Return: NONE
1987 *
1988 * Revised History:
1989 * When Who Remark
1990 * 04/23/2012 MHC Create Version 0.
1991 *
1992 *---------------------------------------------------------------------------*/
1993void rtl8821ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
1994 enum pwr_track_control_method method, u8 rf_path, u8 channel_mapped_index)
1995{
1996 struct rtl_priv *rtlpriv = rtl_priv(hw);
1997 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
1998 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1999 u32 final_bb_swing_idx[1];
2000 u8 pwr_tracking_limit = 26; /*+1.0dB*/
2001 u8 tx_rate = 0xFF;
2002 s8 final_ofdm_swing_index = 0;
2003
2004 if(rtldm->tx_rate != 0xFF)
2005 tx_rate = rtl8812ae_hw_rate_to_mrate(hw, rtldm->tx_rate);
2006
2007
2008 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2009 ("===>rtl8812ae_dm_txpwr_track_set_pwr\n"));
2010
2011 if(tx_rate != 0xFF) { /*20130429 Mimic Modify High Rate BBSwing Limit.*/
2012 /*CCK*/
2013 if((tx_rate >= MGN_1M) && (tx_rate <= MGN_11M))
2014 pwr_tracking_limit = 32; /*+4dB*/
2015 /*OFDM*/
2016 else if((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
2017 pwr_tracking_limit = 30; /*+3dB*/
2018 else if(tx_rate == MGN_54M)
2019 pwr_tracking_limit = 28; /*+2dB*/
2020 /*HT*/
2021 else if((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2)) /*QPSK/BPSK*/
2022 pwr_tracking_limit = 34; /*+5dB*/
2023 else if((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4)) /*16QAM*/
2024 pwr_tracking_limit = 30; /*+3dB*/
2025 else if((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7)) /*64QAM*/
2026 pwr_tracking_limit = 28; /*+2dB*/
2027#if 0
2028 else if((tx_rate >= MGN_MCS8) && (tx_rate <= MGN_MCS10)) /*QPSK/BPSK*/
2029 pwr_tracking_limit = 34; /*+5dB*/
2030 else if((tx_rate >= MGN_MCS11) && (tx_rate <= MGN_MCS12)) /*16QAM*/
2031 pwr_tracking_limit = 30; /*+3dB*/
2032 else if((tx_rate >= MGN_MCS13) && (tx_rate <= MGN_MCS15)) /*64QAM*/
2033 pwr_tracking_limit = 28; /*+2dB*/
2034#endif
2035 /*2 VHT*/
2036 else if((tx_rate >= MGN_VHT1SS_MCS0) && (tx_rate <= MGN_VHT1SS_MCS2)) /*QPSK/BPSK*/
2037 pwr_tracking_limit = 34; /*+5dB*/
2038 else if((tx_rate >= MGN_VHT1SS_MCS3) && (tx_rate <= MGN_VHT1SS_MCS4)) /*16QAM*/
2039 pwr_tracking_limit = 30; /*+3dB*/
2040 else if((tx_rate >= MGN_VHT1SS_MCS5)&&(tx_rate <= MGN_VHT1SS_MCS6)) /*64QAM*/
2041 pwr_tracking_limit = 28; /*+2dB*/
2042 else if(tx_rate == MGN_VHT1SS_MCS7) /*64QAM*/
2043 pwr_tracking_limit = 26; /*+1dB*/
2044 else if(tx_rate == MGN_VHT1SS_MCS8) /*256QAM*/
2045 pwr_tracking_limit = 24; /*+0dB*/
2046 else if(tx_rate == MGN_VHT1SS_MCS9) /*256QAM*/
2047 pwr_tracking_limit = 22; /*-1dB*/
2048 else
2049 pwr_tracking_limit = 24;
2050 }
2051 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2052 ("TxRate=0x%x, PwrTrackingLimit=%d\n", tx_rate, pwr_tracking_limit));
2053
2054
2055 if (method == BBSWING) {
2056 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2057 ("===>rtl8812ae_dm_txpwr_track_set_pwr\n"));
2058
2059 if (rf_path == RF90_PATH_A) {
2060 final_bb_swing_idx[RF90_PATH_A] =
2061 (rtldm->ofdm_index[RF90_PATH_A] > pwr_tracking_limit) ?
2062 pwr_tracking_limit : rtldm->ofdm_index[RF90_PATH_A];
2063 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2064 ("pDM_Odm->RFCalibrateInfo.OFDM_index[ODM_RF_PATH_A]=%d, \
2065 pDM_Odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n",
2066 rtldm->ofdm_index[RF90_PATH_A], final_bb_swing_idx[RF90_PATH_A]));
2067
2068 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[final_bb_swing_idx[RF90_PATH_A]]);
2069 }
2070 } else if (method == MIX_MODE) {
2071 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2072 ("pDM_Odm->DefaultOfdmIndex=%d, \
2073 pDM_Odm->Aboslute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
2074 rtldm->default_ofdm_index, rtldm->aboslute_ofdm_swing_idx[rf_path],
2075 rf_path ));
2076
2077
2078 final_ofdm_swing_index = rtldm->default_ofdm_index + rtldm->aboslute_ofdm_swing_idx[rf_path];
2079
2080 if (rf_path == RF90_PATH_A) {
2081 if(final_ofdm_swing_index > pwr_tracking_limit) { /*BBSwing higher then Limit*/
2082
2083 rtldm->remnant_cck_idx = final_ofdm_swing_index - pwr_tracking_limit;
2084 /* CCK Follow the same compensate value as Path A*/
2085 rtldm->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit;
2086
2087 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[pwr_tracking_limit]);
2088
2089 rtldm->modify_txagc_flag_path_a = true;
2090
2091 /*Set TxAGC Page C{};*/
2092 rtl8821ae_phy_set_txpower_level_by_path(hw, rtlphy->current_channel, RF90_PATH_A);
2093
2094 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2095 ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n",
2096 pwr_tracking_limit, rtldm->remnant_ofdm_swing_idx[rf_path]));
2097 } else if (final_ofdm_swing_index < 0) {
2098 rtldm->remnant_cck_idx = final_ofdm_swing_index;
2099 /* CCK Follow the same compensate value as Path A*/
2100 rtldm->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index;
2101
2102 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[0]);
2103
2104 rtldm->modify_txagc_flag_path_a = true;
2105
2106 /*Set TxAGC Page C{};*/
2107 rtl8821ae_phy_set_txpower_level_by_path(hw, rtlphy->current_channel, RF90_PATH_A);
2108
2109 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2110 ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d \n",
2111 rtldm->remnant_ofdm_swing_idx[rf_path]));
2112 } else {
2113 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000, rtl8812ae_txscaling_table[final_ofdm_swing_index]);
2114
2115 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2116 ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n",
2117 final_ofdm_swing_index));
2118
2119 if(rtldm->modify_txagc_flag_path_a) { /*If TxAGC has changed, reset TxAGC again*/
2120 rtldm->remnant_cck_idx = 0;
2121 rtldm->remnant_ofdm_swing_idx[rf_path] = 0;
2122
2123 /*Set TxAGC Page C{};*/
2124 rtl8821ae_phy_set_txpower_level_by_path(hw, rtlphy->current_channel, RF90_PATH_A);
2125
2126 rtldm->modify_txagc_flag_path_a = false;
2127
2128 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2129 ("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n"));
2130 }
2131 }
2132 }
2133
2134 } else {
2135 return;
2136 }
2137}
2138
2139
2140void rtl8821ae_dm_txpower_tracking_callback_thermalmeter
2141 (struct ieee80211_hw *hw)
2142{
2143 struct rtl_priv *rtlpriv = rtl_priv(hw);
2144 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2145 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2146 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2147 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2148
2149 u8 thermal_value = 0, delta, delta_lck, delta_iqk, p = 0, i = 0;
2150 u8 thermal_value_avg_count = 0;
2151 u32 thermal_value_avg = 0;
2152
2153 u8 ofdm_min_index = 6; /*OFDM BB Swing should be less than +3.0dB, which is required by Arthur*/
2154 u8 index_for_channel = 0; /* GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/
2155
2156 /* 1. The following TWO tables decide the final index of OFDM/CCK swing table.*/
2157 u8 *delta_swing_table_idx_tup_a;
2158 u8 *delta_swing_table_idx_tdown_a;
2159 u8 *delta_swing_table_idx_tup_b;
2160 u8 *delta_swing_table_idx_tdown_b;
2161
2162 /*2. Initilization ( 7 steps in total )*/
2163 rtl8821ae_get_delta_swing_table(hw, (u8**)&delta_swing_table_idx_tup_a,
2164 (u8**)&delta_swing_table_idx_tdown_a,
2165 (u8**)&delta_swing_table_idx_tup_b,
2166 (u8**)&delta_swing_table_idx_tdown_b);
2167
2168 rtldm->btxpower_trackinginit = true;
2169
2170 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2171 ("===>rtl8812ae_dm_txpower_tracking_callback_thermalmeter, \
2172 \n pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase[A]:\
2173 %d, pDM_Odm->DefaultOfdmIndex: %d\n",
2174 rtldm->bb_swing_idx_cck_base,
2175 rtldm->bb_swing_idx_ofdm_base[RF90_PATH_A],
2176 rtldm->default_ofdm_index));
2177
2178 thermal_value = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER_8812A, 0xfc00); /*0x42: RF Reg[15:10] 88E*/
2179 if( ! rtldm->txpower_track_control || rtlefuse->eeprom_thermalmeter == 0 ||
2180 rtlefuse->eeprom_thermalmeter == 0xFF)
2181 return;
2182
2183
2184 /* 3. Initialize ThermalValues of RFCalibrateInfo*/
2185
2186 if(rtlhal->reloadtxpowerindex)
2187 {
2188 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2189 ("reload ofdm index for band switch\n"));
2190 }
2191
2192 /*4. Calculate average thermal meter*/
2193 rtldm->thermalvalue_avg[rtldm->thermalvalue_avg_index] = thermal_value;
2194 rtldm->thermalvalue_avg_index++;
2195 if(rtldm->thermalvalue_avg_index == AVG_THERMAL_NUM_8812A)
2196 /*Average times = c.AverageThermalNum*/
2197 rtldm->thermalvalue_avg_index = 0;
2198
2199 for(i = 0; i < AVG_THERMAL_NUM_8812A; i++)
2200 {
2201 if(rtldm->thermalvalue_avg[i])
2202 {
2203 thermal_value_avg += rtldm->thermalvalue_avg[i];
2204 thermal_value_avg_count++;
2205 }
2206 }
2207
2208 if(thermal_value_avg_count) /*Calculate Average ThermalValue after average enough times*/
2209 {
2210 thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
2211 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2212 ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n",
2213 thermal_value, rtlefuse->eeprom_thermalmeter));
2214 }
2215
2216 /*5. Calculate delta, delta_LCK, delta_IQK.*/
2217 /*"delta" here is used to determine whether thermal value changes or not.*/
2218 delta = (thermal_value > rtldm->thermalvalue) ? \
2219 (thermal_value - rtldm->thermalvalue): \
2220 (rtldm->thermalvalue - thermal_value);
2221 delta_lck = (thermal_value > rtldm->thermalvalue_lck) ? \
2222 (thermal_value - rtldm->thermalvalue_lck) : \
2223 (rtldm->thermalvalue_lck - thermal_value);
2224 delta_iqk = (thermal_value > rtldm->thermalvalue_iqk) ? \
2225 (thermal_value - rtldm->thermalvalue_iqk) : \
2226 (rtldm->thermalvalue_iqk - thermal_value);
2227
2228 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2229 ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n",
2230 delta, delta_lck, delta_iqk));
2231
2232 /* 6. If necessary, do LCK. */
2233
2234 if (delta_lck >= IQK_THRESHOLD) /*Delta temperature is equal to or larger than 20 centigrade.*/
2235 {
2236 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2237 ("delta_LCK(%d) >= Threshold_IQK(%d)\n",
2238 delta_lck, IQK_THRESHOLD));
2239 rtldm->thermalvalue_lck = thermal_value;
2240 rtl8821ae_phy_lccalibrate(hw);
2241 }
2242
2243 /*7. If necessary, move the index of swing table to adjust Tx power.*/
2244
2245 if (delta > 0 && rtldm->txpower_track_control)
2246 {
2247 /*"delta" here is used to record the absolute value of differrence.*/
2248 delta = thermal_value > rtlefuse->eeprom_thermalmeter ? \
2249 (thermal_value - rtlefuse->eeprom_thermalmeter) : \
2250 (rtlefuse->eeprom_thermalmeter - thermal_value);
2251
2252 if (delta >= TXSCALE_TABLE_SIZE)
2253 delta = TXSCALE_TABLE_SIZE - 1;
2254
2255 /*7.1 The Final Power Index = BaseIndex + PowerIndexOffset*/
2256
2257 if(thermal_value > rtlefuse->eeprom_thermalmeter) {
2258
2259 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2260 ("delta_swing_table_idx_tup_a[%d] = %d\n",
2261 delta, delta_swing_table_idx_tup_a[delta]));
2262 rtldm->delta_power_index_last[RF90_PATH_A] = rtldm->delta_power_index[RF90_PATH_A];
2263 rtldm->delta_power_index[RF90_PATH_A] = delta_swing_table_idx_tup_a[delta];
2264
2265 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_A] = delta_swing_table_idx_tup_a[delta];
2266 /*Record delta swing for mix mode power tracking*/
2267
2268 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2269 ("******Temp is higher and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n",
2270 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_A]));
2271
2272 } else {
2273 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2274 ("delta_swing_table_idx_tdown_a[%d] = %d\n",
2275 delta, delta_swing_table_idx_tdown_a[delta]));
2276
2277 rtldm->delta_power_index_last[RF90_PATH_A] = rtldm->delta_power_index[RF90_PATH_A];
2278 rtldm->delta_power_index[RF90_PATH_A] = -1 * delta_swing_table_idx_tdown_a[delta];
2279
2280 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_A] = -1 * delta_swing_table_idx_tdown_a[delta];
2281 /* Record delta swing for mix mode power tracking*/
2282 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2283 ("******Temp is lower and pDM_Odm->Aboslute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n",
2284 rtldm->aboslute_ofdm_swing_idx[RF90_PATH_A]));
2285 }
2286
2287 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++)
2288 {
2289 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2290 ("\n\n================================ [Path-%c] \
2291 Calculating PowerIndexOffset ================================\n",
2292 (p == RF90_PATH_A ? 'A' : 'B')));
2293
2294 if (rtldm->delta_power_index[p] == rtldm->delta_power_index_last[p])
2295 /*If Thermal value changes but lookup table value still the same*/
2296 rtldm->power_index_offset[p] = 0;
2297 else
2298 rtldm->power_index_offset[p] =
2299 rtldm->delta_power_index[p] - rtldm->delta_power_index_last[p];
2300 /*Power Index Diff between 2 times Power Tracking*/
2301
2302 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2303 ("[Path-%c] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n",
2304 (p == RF90_PATH_A ? 'A' : 'B'),
2305 rtldm->power_index_offset[p],
2306 rtldm->delta_power_index[p] ,
2307 rtldm->delta_power_index_last[p]));
2308
2309 rtldm->ofdm_index[p] =
2310 rtldm->bb_swing_idx_ofdm_base[p] + rtldm->power_index_offset[p];
2311 rtldm->cck_index =
2312 rtldm->bb_swing_idx_cck_base + rtldm->power_index_offset[p];
2313
2314 rtldm->bb_swing_idx_cck = rtldm->cck_index;
2315 rtldm->bb_swing_idx_ofdm[p] = rtldm->ofdm_index[p];
2316
2317 /*************Print BB Swing Base and Index Offset*************/
2318
2319 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2320 ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n",
2321 rtldm->bb_swing_idx_cck,
2322 rtldm->bb_swing_idx_cck_base,
2323 rtldm->power_index_offset[p]));
2324 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2325 ("The 'OFDM' final index(%d) = BaseIndex[%c](%d) + PowerIndexOffset(%d)\n",
2326 rtldm->bb_swing_idx_ofdm[p],
2327 (p == RF90_PATH_A ? 'A' : 'B'),
2328 rtldm->bb_swing_idx_ofdm_base[p],
2329 rtldm->power_index_offset[p]));
2330
2331 /*7.1 Handle boundary conditions of index.*/
2332
2333
2334 if(rtldm->ofdm_index[p] > TXSCALE_TABLE_SIZE -1)
2335 {
2336 rtldm->ofdm_index[p] = TXSCALE_TABLE_SIZE -1;
2337 }
2338 else if (rtldm->ofdm_index[p] < ofdm_min_index)
2339 {
2340 rtldm->ofdm_index[p] = ofdm_min_index;
2341 }
2342 }
2343 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2344 ("\n\n======================================================\
2345 ==================================================\n"));
2346 if(rtldm->cck_index > TXSCALE_TABLE_SIZE -1)
2347 rtldm->cck_index = TXSCALE_TABLE_SIZE -1;
2348 else if (rtldm->cck_index < 0)
2349 rtldm->cck_index = 0;
2350 } else {
2351 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2352 ("The thermal meter is unchanged or TxPowerTracking OFF(%d): \
2353 ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d\n",
2354 rtldm->txpower_track_control,
2355 thermal_value,
2356 rtldm->thermalvalue));
2357
2358 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++)
2359 rtldm->power_index_offset[p] = 0;
2360 }
2361 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2362 ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n",
2363 rtldm->cck_index, rtldm->bb_swing_idx_cck_base)); /*Print Swing base & current*/
2364 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++)
2365 {
2366 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2367 ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%c]: %d\n",
2368 rtldm->ofdm_index[p],
2369 (p == RF90_PATH_A ? 'A' : 'B'),
2370 rtldm->bb_swing_idx_ofdm_base[p]));
2371 }
2372
2373 if ((rtldm->power_index_offset[RF90_PATH_A] != 0 ||
2374 rtldm->power_index_offset[RF90_PATH_B] != 0 ) &&
2375 rtldm->txpower_track_control)
2376 {
2377 /*7.2 Configure the Swing Table to adjust Tx Power.*/
2378 /*Always TRUE after Tx Power is adjusted by power tracking.*/
2379 /*
2380 2012/04/23 MH According to Luke's suggestion, we can not write BB digital
2381 to increase TX power. Otherwise, EVM will be bad.
2382
2383 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E.
2384 */
2385 if (thermal_value > rtldm->thermalvalue)
2386 {
2387 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2388 ("Temperature Increasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
2389 rtldm->power_index_offset[RF90_PATH_A],
2390 delta, thermal_value,
2391 rtlefuse->eeprom_thermalmeter,
2392 rtldm->thermalvalue));
2393 } else if (thermal_value < rtldm->thermalvalue) { /*Low temperature*/
2394 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2395 ("Temperature Decreasing(A): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n",
2396 rtldm->power_index_offset[RF90_PATH_A],
2397 delta, thermal_value,
2398 rtlefuse->eeprom_thermalmeter,
2399 rtldm->thermalvalue));
2400 }
2401
2402 if (thermal_value > rtlefuse->eeprom_thermalmeter) {
2403 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2404 ("Temperature(%d) higher than PG value(%d)\n",
2405 thermal_value, rtlefuse->eeprom_thermalmeter));
2406
2407
2408 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2409 ("**********Enter POWER Tracking MIX_MODE**********\n"));
2410 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++)
2411 rtl8821ae_dm_txpwr_track_set_pwr(hw, MIX_MODE, p, index_for_channel);
2412
2413 } else {
2414 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2415 ("Temperature(%d) lower than PG value(%d)\n",
2416 thermal_value, rtlefuse->eeprom_thermalmeter));
2417
2418
2419 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2420 ("**********Enter POWER Tracking MIX_MODE**********\n"));
2421 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++)
2422 rtl8812ae_dm_txpwr_track_set_pwr(hw, MIX_MODE, p, index_for_channel);
2423
2424 }
2425
2426 rtldm->bb_swing_idx_cck_base = rtldm->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/
2427 for (p = RF90_PATH_A; p < MAX_PATH_NUM_8821A; p++)
2428 rtldm->bb_swing_idx_ofdm_base[p] = rtldm->bb_swing_idx_ofdm[p];
2429
2430 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2431 ("pDM_Odm->RFCalibrateInfo.ThermalValue = %d ThermalValue= %d\n",
2432 rtldm->thermalvalue, thermal_value));
2433
2434 rtldm->thermalvalue = thermal_value; /*Record last Power Tracking Thermal Value*/
2435
2436 }
2437 /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/
2438 if ((delta_iqk >= IQK_THRESHOLD)) {
2439
2440 if ( !rtlphy->b_iqk_in_progress) {
2441
2442 spin_lock(&rtlpriv->locks.iqk_lock);
2443 rtlphy->b_iqk_in_progress = true;
2444 spin_unlock(&rtlpriv->locks.iqk_lock);
2445
2446 rtl8821ae_do_iqk(hw, delta_iqk, thermal_value, 8);
2447
2448 spin_lock(&rtlpriv->locks.iqk_lock);
2449 rtlphy->b_iqk_in_progress = false;
2450 spin_unlock(&rtlpriv->locks.iqk_lock);
2451 }
2452 }
2453
2454 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2455 ("<===rtl8812ae_dm_txpower_tracking_callback_thermalmeter\n"));
2456}
2457
2458
2459void rtl8821ae_dm_check_txpower_tracking_thermalmeter(struct ieee80211_hw *hw)
2460{
2461 struct rtl_priv *rtlpriv = rtl_priv(hw);
2462 static u8 tm_trigger = 0;
2463
2464 //if (!rtlpriv->dm.btxpower_tracking)
2465 // return;
2466
2467 if (!tm_trigger) {
2468 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER_88E, BIT(17)|BIT(16),
2469 0x03);
2470 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2471 ("Trigger 8821ae Thermal Meter!!\n"));
2472 tm_trigger = 1;
2473 return;
2474 } else {
2475 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
2476 ("Schedule TxPowerTracking !!\n"));
2477
2478 rtl8821ae_dm_txpower_tracking_callback_thermalmeter(hw);
2479 tm_trigger = 0;
2480 }
2481}
2482
2483
2484void rtl8821ae_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
2485{
2486 struct rtl_priv *rtlpriv = rtl_priv(hw);
2487 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2488 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2489 struct rate_adaptive *p_ra = &(rtlpriv->ra);
2490 u32 low_rssithresh_for_ra = p_ra->low2high_rssi_thresh_for_ra;
2491 u32 high_rssithresh_for_ra = p_ra->high_rssi_thresh_for_ra;
2492 u8 go_up_gap = 5;
2493 struct ieee80211_sta *sta = NULL;
2494
2495 if (is_hal_stop(rtlhal)) {
2496 RT_TRACE(COMP_RATE, DBG_LOUD,
2497 ("driver is going to unload\n"));
2498 return;
2499 }
2500
2501 if (!rtlpriv->dm.b_useramask) {
2502 RT_TRACE(COMP_RATE, DBG_LOUD,
2503 ("driver does not control rate adaptive mask\n"));
2504 return;
2505 }
2506
2507 if (mac->link_state == MAC80211_LINKED &&
2508 mac->opmode == NL80211_IFTYPE_STATION) {
2509
2510 switch (p_ra->pre_ratr_state) {
2511 case DM_RATR_STA_MIDDLE:
2512 high_rssithresh_for_ra += go_up_gap;
2513 break;
2514 case DM_RATR_STA_LOW:
2515 high_rssithresh_for_ra += go_up_gap;
2516 low_rssithresh_for_ra += go_up_gap;
2517 break;
2518 default:
2519 break;
2520 }
2521
2522 if (rtlpriv->dm.undecorated_smoothed_pwdb >
2523 (long)high_rssithresh_for_ra)
2524 p_ra->ratr_state = DM_RATR_STA_HIGH;
2525 else if (rtlpriv->dm.undecorated_smoothed_pwdb >
2526 (long)low_rssithresh_for_ra)
2527 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
2528 else
2529 p_ra->ratr_state = DM_RATR_STA_LOW;
2530
2531 if (p_ra->pre_ratr_state != p_ra->ratr_state ) {
2532 RT_TRACE(COMP_RATE, DBG_LOUD,
2533 ("RSSI = %ld\n",
2534 rtlpriv->dm.undecorated_smoothed_pwdb));
2535 RT_TRACE(COMP_RATE, DBG_LOUD,
2536 ("RSSI_LEVEL = %d\n", p_ra->ratr_state));
2537 RT_TRACE(COMP_RATE, DBG_LOUD,
2538 ("PreState = %d, CurState = %d\n",
2539 p_ra->pre_ratr_state, p_ra->ratr_state));
2540
2541 rcu_read_lock();
2542 sta = rtl_find_sta(hw, mac->bssid);
2543 if (sta)
2544 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, p_ra->ratr_state);
2545 rcu_read_unlock();
2546
2547 p_ra->pre_ratr_state = p_ra->ratr_state;
2548 }
2549 }
2550}
2551
2552bool rtl8821ae_dm_is_edca_turbo_disable(struct ieee80211_hw *hw)
2553{
2554 struct rtl_priv *rtlpriv = rtl_priv(hw);
2555
2556 if (rtlpriv->btcoexist.btc_ops->btc_is_disable_edca_turbo(rtlpriv))
2557 return true;
2558 if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
2559 return true;
2560
2561 return false;
2562}
2563
2564void rtl8821ae_dm_edca_choose_traffic_idx(
2565 struct ieee80211_hw *hw, u64 cur_tx_bytes, u64 cur_rx_bytes, bool b_bias_on_rx,
2566 bool *pb_is_cur_rdl_state)
2567{
2568 struct rtl_priv *rtlpriv = rtl_priv(hw);
2569
2570 if(b_bias_on_rx)
2571 {
2572 if (cur_tx_bytes > (cur_rx_bytes*4)) {
2573 *pb_is_cur_rdl_state = false;
2574 RT_TRACE(COMP_TURBO, DBG_LOUD,
2575 ("Uplink Traffic\n "));
2576 } else {
2577 *pb_is_cur_rdl_state = true;
2578 RT_TRACE(COMP_TURBO, DBG_LOUD,
2579 ("Balance Traffic\n"));
2580 }
2581 } else {
2582 if (cur_rx_bytes > (cur_tx_bytes*4)) {
2583 *pb_is_cur_rdl_state = true;
2584 RT_TRACE(COMP_TURBO, DBG_LOUD,
2585 ("Downlink Traffic\n"));
2586 } else {
2587 *pb_is_cur_rdl_state = false;
2588 RT_TRACE(COMP_TURBO, DBG_LOUD,
2589 ("Balance Traffic\n"));
2590 }
2591 }
2592 return ;
2593}
2594
2595static void rtl8821ae_dm_check_edca_turbo(struct ieee80211_hw *hw)
2596{
2597 struct rtl_priv *rtlpriv = rtl_priv(hw);
2598 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2599 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2600
2601 /*Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.*/
2602 unsigned long cur_tx_ok_cnt = 0;
2603 unsigned long cur_rx_ok_cnt = 0;
2604 u32 edca_be_ul = 0x5ea42b;
2605 u32 edca_be_dl = 0x5ea42b;
2606 u32 edca_be = 0x5ea42b;
2607 u8 iot_peer = 0;
2608 bool *pb_is_cur_rdl_state = NULL;
2609 bool b_last_is_cur_rdl_state = false;
2610 bool b_bias_on_rx = false;
2611 bool b_edca_turbo_on = false;
2612
2613 RT_TRACE(COMP_TURBO, DBG_LOUD,
2614 ("rtl8821ae_dm_check_edca_turbo=====>"));
2615 RT_TRACE(COMP_TURBO, DBG_LOUD,
2616 ("Orginial BE PARAM: 0x%x\n",
2617 rtl_read_dword(rtlpriv, DM_REG_EDCA_BE_11N)));
2618
2619 /*===============================
2620 list paramter for different platform
2621 ===============================*/
2622 b_last_is_cur_rdl_state = rtlpriv->dm.bis_cur_rdlstate;
2623 pb_is_cur_rdl_state = &( rtlpriv->dm.bis_cur_rdlstate);
2624
2625 cur_tx_ok_cnt = rtlpriv->stats.txbytesunicast - rtldm->last_tx_ok_cnt;
2626 cur_rx_ok_cnt = rtlpriv->stats.rxbytesunicast - rtldm->last_rx_ok_cnt;
2627
2628 rtldm->last_tx_ok_cnt = rtlpriv->stats.txbytesunicast;
2629 rtldm->last_rx_ok_cnt = rtlpriv->stats.rxbytesunicast;
2630
2631 iot_peer = rtlpriv->mac80211.vendor;
2632 b_bias_on_rx = (iot_peer == PEER_RAL || iot_peer == PEER_ATH) ?
2633 true : false;
2634 b_edca_turbo_on = ((!rtlpriv->dm.bis_any_nonbepkts) &&
2635 (!rtlpriv->dm.b_disable_framebursting)) ?
2636 true : false;
2637
2638 /*if (rtl8821ae_dm_is_edca_turbo_disable(hw))
2639 goto dm_CheckEdcaTurbo_EXIT;*/
2640
2641 if ((iot_peer == PEER_CISCO) && (mac->mode == WIRELESS_MODE_N_24G))
2642 {
2643 edca_be_dl = edca_setting_dl[iot_peer];
2644 edca_be_ul = edca_setting_ul[iot_peer];
2645 }
2646
2647 RT_TRACE(COMP_TURBO, DBG_LOUD,
2648 ("bIsAnyNonBEPkts : 0x%x bDisableFrameBursting : 0x%x \n",
2649 rtlpriv->dm.bis_any_nonbepkts, rtlpriv->dm.b_disable_framebursting));
2650
2651 RT_TRACE(COMP_TURBO, DBG_LOUD,
2652 ("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",
2653 b_edca_turbo_on, b_bias_on_rx));
2654
2655 if (b_edca_turbo_on) {
2656 RT_TRACE(COMP_TURBO, DBG_LOUD,
2657 ("curTxOkCnt : 0x%lx \n",cur_tx_ok_cnt));
2658 RT_TRACE(COMP_TURBO, DBG_LOUD,
2659 ("curRxOkCnt : 0x%lx \n",cur_rx_ok_cnt));
2660 if(b_bias_on_rx)
2661 rtl8821ae_dm_edca_choose_traffic_idx(hw, cur_tx_ok_cnt,
2662 cur_rx_ok_cnt, true, pb_is_cur_rdl_state);
2663 else
2664 rtl8821ae_dm_edca_choose_traffic_idx(hw, cur_tx_ok_cnt,
2665 cur_rx_ok_cnt, false, pb_is_cur_rdl_state);
2666
2667 edca_be = ((*pb_is_cur_rdl_state) == true) ? edca_be_dl : edca_be_ul;
2668
2669 rtl_write_dword(rtlpriv, DM_REG_EDCA_BE_11N, edca_be);
2670
2671 RT_TRACE(COMP_TURBO, DBG_LOUD,
2672 ("EDCA Turbo on: EDCA_BE:0x%x\n", edca_be));
2673
2674 rtlpriv->dm.bcurrent_turbo_edca = true;
2675
2676 RT_TRACE(COMP_TURBO, DBG_LOUD,
2677 ("EDCA_BE_DL : 0x%x EDCA_BE_UL : 0x%x EDCA_BE : 0x%x \n",
2678 edca_be_dl, edca_be_ul, edca_be));
2679 } else {
2680 if (rtlpriv->dm.bcurrent_turbo_edca) {
2681 u8 tmp = AC0_BE;
2682 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
2683 (u8 *) (&tmp));
2684 }
2685 rtlpriv->dm.bcurrent_turbo_edca = false;
2686 }
2687
2688/* dm_CheckEdcaTurbo_EXIT: */
2689 rtlpriv->dm.bis_any_nonbepkts = false;
2690 rtldm->last_tx_ok_cnt = rtlpriv->stats.txbytesunicast;
2691 rtldm->last_rx_ok_cnt = rtlpriv->stats.rxbytesunicast;
2692}
2693
2694static void rtl8821ae_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
2695{
2696 struct rtl_priv *rtlpriv = rtl_priv(hw);
2697 u8 cur_cck_cca_thresh;
2698
2699 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
2700 /*dm_digtable.rssi_val_min = rtl8821ae_dm_initial_gain_min_pwdb(hw);*/
2701 if (dm_digtable.rssi_val_min > 25)
2702 cur_cck_cca_thresh = 0xcd;
2703 else if ((dm_digtable.rssi_val_min <= 25) && (dm_digtable.rssi_val_min > 10))
2704 cur_cck_cca_thresh = 0x83;
2705 else {
2706 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
2707 cur_cck_cca_thresh = 0x83;
2708 else
2709 cur_cck_cca_thresh = 0x40;
2710 }
2711
2712 } else {
2713 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
2714 cur_cck_cca_thresh = 0x83;
2715 else
2716 cur_cck_cca_thresh = 0x40;
2717 }
2718
2719 if (dm_digtable.cur_cck_cca_thres != cur_cck_cca_thresh) {
2720 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, cur_cck_cca_thresh);
2721 }
2722
2723 dm_digtable.pre_cck_cca_thres = dm_digtable.cur_cck_cca_thres;
2724 dm_digtable.cur_cck_cca_thres = cur_cck_cca_thresh;
2725 RT_TRACE(COMP_DIG, DBG_TRACE,
2726 ("CCK cca thresh hold =%x\n", dm_digtable.cur_cck_cca_thres));
2727
2728}
2729
2730void rtl8821ae_dm_dynamic_edcca(struct ieee80211_hw *hw)
2731{
2732 struct rtl_priv *rtlpriv = rtl_priv(hw);
2733 bool b_fw_current_in_ps_mode = false;
2734
2735 rtlpriv->cfg->ops->get_hw_reg(hw,HW_VAR_FW_PSMODE_STATUS, \
2736 (u8*)(&b_fw_current_in_ps_mode));
2737 if (b_fw_current_in_ps_mode)
2738 return;
2739}
2740
2741void rtl8812ae_dm_update_txpath(struct ieee80211_hw *hw, u8 path)
2742{
2743 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2744 struct rtl_priv *rtlpriv = rtl_priv(hw);
2745
2746 if (rtldm->resp_tx_path != path) {
2747 RT_TRACE(COMP_DIG, DBG_LOUD, \
2748 ("Need to Update Tx Path\n"));
2749 if (path == RF90_PATH_A) {
2750 /*Tx by Reg*/
2751 rtl_set_bbreg(hw, 0x80c, 0xFFF0, 0x111);
2752 /*Resp Tx by Txinfo*/
2753 rtl_set_bbreg(hw, 0x6d8, BIT(7) | BIT(6), 1);
2754 } else {
2755 /*Tx by Reg*/
2756 rtl_set_bbreg(hw, 0x80c, 0xFFF0, 0x222);
2757 /*Resp Tx by Txinfo*/
2758 rtl_set_bbreg(hw, 0x6d8, BIT(7) |BIT(6), 2);
2759 }
2760 }
2761 rtldm->resp_tx_path = path;
2762 RT_TRACE(COMP_DIG, DBG_LOUD, \
2763 ("Path=%s\n",(path == RF90_PATH_A) ? \
2764 "RF90_PATH_A":"RF90_PATH_A"));
2765}
2766
2767void rtl8812ae_dm_path_diversity_init(struct ieee80211_hw *hw)
2768{
2769 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2770
2771 //rtl_set_bbreg(hw, 0x80c , BIT(29), 1); /*Tx path from Reg*/
2772 rtl_set_bbreg(hw, 0x80c , 0xFFF0, 0x111); /*Tx by Reg*/
2773 rtl_set_bbreg(hw, 0x6d8 , BIT(7) | BIT(6), 1); /*Resp Tx by Txinfo*/
2774 rtl8812ae_dm_update_txpath(hw, RF90_PATH_A);
2775
2776 rtldm->path_sel = 1; /* TxInfo default at path-A*/
2777}
2778
2779void rtl812ae_dm_set_txpath_by_txinfo(struct ieee80211_hw *hw,
2780 u8 *pdesc)
2781{
2782 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2783
2784 SET_TX_DESC_TX_ANT(pdesc, rtldm->path_sel);
2785}
2786
2787void rtl8812ae_dm_path_statistics(struct ieee80211_hw *hw,
2788 u32 rssi_a, u32 rssi_b)
2789{
2790 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2791
2792 rtldm->patha_sum += rssi_a;
2793 rtldm->patha_cnt ++;
2794
2795 rtldm->pathb_sum += rssi_b;
2796 rtldm->pathb_cnt ++;
2797}
2798
2799void rtl8812ae_dm_path_diversity(struct ieee80211_hw *hw)
2800{
2801 struct rtl_priv *rtlpriv = rtl_priv(hw);
2802 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2803 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2804 u32 rssi_avg_a = 0;
2805 u32 rssi_avg_b = 0;
2806 u32 local_min_rssi = 0;
2807 u32 min_rssi = 0xFF;
2808 u8 tx_resp_path=0, target_path;
2809 struct ieee80211_sta *sta = NULL;
2810
2811 sta = rtl_find_sta(hw, mac->bssid);
2812 if (sta) {
2813 /*Caculate RSSI per Path*/
2814 rssi_avg_a = (rtldm->patha_cnt != 0) ? \
2815 (rtldm->patha_sum / rtldm->patha_cnt) : 0;
2816 rssi_avg_b = (rtldm->pathb_cnt != 0) ? \
2817 (rtldm->pathb_sum / rtldm->pathb_cnt) : 0;
2818
2819 target_path = (rssi_avg_a == rssi_avg_b) ? rtldm->resp_tx_path : \
2820 ((rssi_avg_a>=rssi_avg_b) ? RF90_PATH_A : RF90_PATH_B);
2821
2822 RT_TRACE(COMP_DIG, DBG_TRACE, \
2823 ("assoc_id=%d, PathA_Sum=%d, PathA_Cnt=%d\n", \
2824 mac->assoc_id, rtldm->patha_sum, rtldm->patha_cnt));
2825 RT_TRACE(COMP_DIG, DBG_TRACE, \
2826 ("assoc_id=%d, PathB_Sum=%d, PathB_Cnt=%d\n", \
2827 mac->assoc_id, rtldm->pathb_sum, rtldm->pathb_cnt));
2828 RT_TRACE(COMP_DIG, DBG_TRACE, \
2829 ("assoc_id=%d, RssiAvgA= %d, RssiAvgB= %d\n", \
2830 mac->assoc_id, rssi_avg_a, rssi_avg_b));
2831
2832 /*Select Resp Tx Path*/
2833 local_min_rssi = (rssi_avg_a > rssi_avg_b) ? rssi_avg_b : rssi_avg_a;
2834 if(local_min_rssi < min_rssi)
2835 {
2836 min_rssi = local_min_rssi;
2837 tx_resp_path = target_path;
2838 }
2839
2840 /*Select Tx DESC*/
2841 if(target_path == RF90_PATH_A)
2842 rtldm->path_sel = 1;
2843 else
2844 rtldm->path_sel = 2;
2845
2846 RT_TRACE(COMP_DIG, DBG_TRACE, \
2847 ("Tx from TxInfo, TargetPath=%s\n", \
2848 (target_path==RF90_PATH_A) ? \
2849 "ODM_RF_PATH_A":"ODM_RF_PATH_B"));
2850 RT_TRACE(COMP_DIG, DBG_TRACE, \
2851 ("pDM_PathDiv->PathSel= %d\n", \
2852 rtldm->path_sel));
2853 }
2854 rtldm->patha_cnt = 0;
2855 rtldm->patha_sum = 0;
2856 rtldm->pathb_cnt = 0;
2857 rtldm->pathb_sum = 0;
2858}
2859
2860void rtl8821ae_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
2861{
2862 struct rtl_priv *rtlpriv = rtl_priv(hw);
2863 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
2864 u8 crystal_cap;
2865 u32 packet_count;
2866 int cfo_khz_a,cfo_khz_b,cfo_ave = 0, adjust_xtal = 0;
2867 int cfo_ave_diff;
2868
2869 if (rtlpriv->mac80211.link_state < MAC80211_LINKED){
2870 /*1.Enable ATC*/
2871 if (rtldm->atc_status == ATC_STATUS_OFF)
2872 {
2873 rtl_set_bbreg(hw, RFC_AREA, BIT(14), ATC_STATUS_ON);
2874 rtldm->atc_status = ATC_STATUS_ON;
2875 }
2876
2877 RT_TRACE(COMP_DIG, DBG_LOUD, \
2878 ("rtl8821ae_dm_dynamic_atc_switch(): No link!!\n"));
2879 RT_TRACE(COMP_DIG, DBG_LOUD, \
2880 ("rtl8821ae_dm_dynamic_atc_switch(): atc_status = %d\n", \
2881 rtldm->atc_status));
2882
2883 if (rtldm->crystal_cap != rtlpriv->efuse.crystalcap)
2884 {
2885 rtldm->crystal_cap = rtlpriv->efuse.crystalcap;
2886 crystal_cap = rtldm->crystal_cap & 0x3f;
2887 crystal_cap = crystal_cap & 0x3f;
2888 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, \
2889 0x7ff80000, (crystal_cap | (crystal_cap << 6)));
2890 }
2891 RT_TRACE(COMP_DIG, DBG_LOUD, \
2892 ("rtl8821ae_dm_dynamic_atc_switch(): crystal_cap = 0x%x\n", \
2893 rtldm->crystal_cap));
2894 }else{
2895 /*1. Calculate CFO for path-A & path-B*/
2896 cfo_khz_a = (int)(rtldm->cfo_tail[0] * 3125) / 1280;
2897 cfo_khz_b = (int)(rtldm->cfo_tail[1] * 3125) / 1280;
2898 packet_count = rtldm->packet_count;
2899
2900 /*2.No new packet*/
2901 if (packet_count == rtldm->packet_count_pre) {
2902 RT_TRACE(COMP_DIG, DBG_LOUD, \
2903 ("rtl8821ae_dm_dynamic_atc_switch(): packet counter doesn't change\n"));
2904 return;
2905 }
2906
2907 rtldm->packet_count_pre = packet_count;
2908 RT_TRACE(COMP_DIG, DBG_LOUD, \
2909 ("rtl8821ae_dm_dynamic_atc_switch(): packet counter = %d\n", \
2910 rtldm->packet_count));
2911
2912 /*3.Average CFO*/
2913 if (rtlpriv->phy.rf_type == RF_1T1R)
2914 cfo_ave = cfo_khz_a;
2915 else
2916 cfo_ave = (cfo_khz_a + cfo_khz_b) >> 1;
2917
2918 RT_TRACE(COMP_DIG, DBG_LOUD, \
2919 ("rtl8821ae_dm_dynamic_atc_switch():"
2920 "cfo_khz_a = %dkHz, cfo_khz_b = %dkHz, cfo_ave = %dkHz\n",
2921 cfo_khz_a, cfo_khz_b, cfo_ave));
2922
2923 /*4.Avoid abnormal large CFO*/
2924 cfo_ave_diff = (rtldm->cfo_ave_pre >= cfo_ave)?
2925 (rtldm->cfo_ave_pre - cfo_ave):
2926 (cfo_ave - rtldm->cfo_ave_pre);
2927
2928 if (cfo_ave_diff > 20 && rtldm->large_cfo_hit == 0){
2929 RT_TRACE(COMP_DIG, DBG_LOUD, \
2930 ("rtl8821ae_dm_dynamic_atc_switch(): first large CFO hit\n"));
2931 rtldm->large_cfo_hit = 1;
2932 return;
2933 }
2934 else
2935 rtldm->large_cfo_hit = 0;
2936
2937 rtldm->cfo_ave_pre = cfo_ave;
2938
2939 /*CFO tracking by adjusting Xtal cap.*/
2940
2941 /*1.Dynamic Xtal threshold*/
2942 if (cfo_ave >= -rtldm->cfo_threshold &&
2943 cfo_ave <= rtldm->cfo_threshold &&
2944 rtldm->is_freeze == 0){
2945 if (rtldm->cfo_threshold == CFO_THRESHOLD_XTAL){
2946 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL + 10;
2947 rtldm->is_freeze = 1;
2948 }
2949 else
2950 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL;
2951 }
2952 RT_TRACE(COMP_DIG, DBG_LOUD, \
2953 ("rtl8821ae_dm_dynamic_atc_switch(): Dynamic threshold = %d\n", \
2954 rtldm->cfo_threshold));
2955
2956 /* 2.Calculate Xtal offset*/
2957 if (cfo_ave > rtldm->cfo_threshold && rtldm->crystal_cap < 0x3f)
2958 adjust_xtal = ((cfo_ave - CFO_THRESHOLD_XTAL) >> 2) + 1;
2959 else if ((cfo_ave < -rtlpriv->dm.cfo_threshold) && rtlpriv->dm.crystal_cap > 0)
2960 adjust_xtal = ((cfo_ave + CFO_THRESHOLD_XTAL) >> 2) - 1;
2961 RT_TRACE(COMP_DIG, DBG_LOUD, \
2962 ("rtl8821ae_dm_dynamic_atc_switch(): "
2963 "Crystal cap = 0x%x, Crystal cap offset = %d\n",
2964 rtldm->crystal_cap, adjust_xtal));
2965
2966 /*3.Adjudt Crystal Cap.*/
2967 if (adjust_xtal != 0){
2968 rtldm->is_freeze = 0;
2969 rtldm->crystal_cap += adjust_xtal;
2970
2971 if (rtldm->crystal_cap > 0x3f)
2972 rtldm->crystal_cap = 0x3f;
2973 else if (rtldm->crystal_cap < 0)
2974 rtldm->crystal_cap = 0;
2975
2976 crystal_cap = rtldm->crystal_cap & 0x3f;
2977 crystal_cap = crystal_cap & 0x3f;
2978 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, \
2979 0x7ff80000, (crystal_cap | (crystal_cap << 6)));
2980 RT_TRACE(COMP_DIG, DBG_LOUD, \
2981 ("rtl8821ae_dm_dynamic_atc_switch(): New crystal cap = 0x%x \n", \
2982 rtldm->crystal_cap));
2983 }
2984 }
2985
2986}
2987
2988void rtl8821ae_dm_watchdog(struct ieee80211_hw *hw)
2989{
2990 struct rtl_priv *rtlpriv = rtl_priv(hw);
2991 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2992 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2993 bool b_fw_current_inpsmode = false;
2994 bool b_fw_ps_awake = true;
2995
2996 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
2997 (u8 *) (&b_fw_current_inpsmode));
2998
2999 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
3000 (u8 *) (&b_fw_ps_awake));
3001
3002 if(ppsc->p2p_ps_info.p2p_ps_mode)
3003 b_fw_ps_awake = false;
3004
3005 if((ppsc->rfpwr_state == ERFON) &&
3006 ((!b_fw_current_inpsmode) && b_fw_ps_awake) &&
3007 (!ppsc->rfchange_inprogress)) {
3008 rtl8821ae_dm_common_info_self_update(hw);
3009 rtl8821ae_dm_false_alarm_counter_statistics(hw);
3010 rtl8821ae_dm_check_rssi_monitor(hw);
3011 rtl8821ae_dm_dig(hw);
3012 rtl8821ae_dm_dynamic_edcca(hw);
3013 rtl8821ae_dm_cck_packet_detection_thresh(hw);
3014 rtl8821ae_dm_refresh_rate_adaptive_mask(hw);
3015 rtl8821ae_dm_check_edca_turbo(hw);
3016 rtl8821ae_dm_dynamic_atc_switch(hw);
3017 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3018 rtl8812ae_dm_check_txpower_tracking_thermalmeter(hw);
3019 else
3020 rtl8821ae_dm_check_txpower_tracking_thermalmeter(hw);
3021 rtl8821ae_dm_iq_calibrate(hw);
3022 if (rtlpriv->cfg->ops->get_btc_status()){
3023 rtlpriv->btcoexist.btc_ops->btc_periodical(rtlpriv);
3024 }
3025 }
3026
3027 rtlpriv->dm.dbginfo.num_qry_beacon_pkt = 0;
3028}
3029
3030void rtl8821ae_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
3031 u8 *pdesc, u32 mac_id)
3032{
3033 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3034 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3035 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
3036 struct fast_ant_trainning *pfat_table= &(rtldm->fat_table);
3037
3038 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8812AE)
3039 return;
3040
3041 if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
3042 (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV)){
3043 SET_TX_DESC_TX_ANT(pdesc, pfat_table->antsel_a[mac_id]);
3044 }
3045}
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/dm.h b/drivers/staging/rtl8821ae/rtl8821ae/dm.h
new file mode 100644
index 000000000000..ebbff9b6cacf
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/dm.h
@@ -0,0 +1,426 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8821AE_DM_H__
31#define __RTL8821AE_DM_H__
32
33#define MAIN_ANT 0
34#define AUX_ANT 1
35#define MAIN_ANT_CG_TRX 1
36#define AUX_ANT_CG_TRX 0
37#define MAIN_ANT_CGCS_RX 0
38#define AUX_ANT_CGCS_RX 1
39
40#define TXSCALE_TABLE_SIZE 37
41
42/*RF REG LIST*/
43#define DM_REG_RF_MODE_11N 0x00
44#define DM_REG_RF_0B_11N 0x0B
45#define DM_REG_CHNBW_11N 0x18
46#define DM_REG_T_METER_11N 0x24
47#define DM_REG_RF_25_11N 0x25
48#define DM_REG_RF_26_11N 0x26
49#define DM_REG_RF_27_11N 0x27
50#define DM_REG_RF_2B_11N 0x2B
51#define DM_REG_RF_2C_11N 0x2C
52#define DM_REG_RXRF_A3_11N 0x3C
53#define DM_REG_T_METER_92D_11N 0x42
54#define DM_REG_T_METER_88E_11N 0x42
55
56
57
58/*BB REG LIST*/
59/*PAGE 8 */
60#define DM_REG_BB_CTRL_11N 0x800
61#define DM_REG_RF_PIN_11N 0x804
62#define DM_REG_PSD_CTRL_11N 0x808
63#define DM_REG_TX_ANT_CTRL_11N 0x80C
64#define DM_REG_BB_PWR_SAV5_11N 0x818
65#define DM_REG_CCK_RPT_FORMAT_11N 0x824
66#define DM_REG_RX_DEFUALT_A_11N 0x858
67#define DM_REG_RX_DEFUALT_B_11N 0x85A
68#define DM_REG_BB_PWR_SAV3_11N 0x85C
69#define DM_REG_ANTSEL_CTRL_11N 0x860
70#define DM_REG_RX_ANT_CTRL_11N 0x864
71#define DM_REG_PIN_CTRL_11N 0x870
72#define DM_REG_BB_PWR_SAV1_11N 0x874
73#define DM_REG_ANTSEL_PATH_11N 0x878
74#define DM_REG_BB_3WIRE_11N 0x88C
75#define DM_REG_SC_CNT_11N 0x8C4
76#define DM_REG_PSD_DATA_11N 0x8B4
77/*PAGE 9*/
78#define DM_REG_ANT_MAPPING1_11N 0x914
79#define DM_REG_ANT_MAPPING2_11N 0x918
80/*PAGE A*/
81#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
82#define DM_REG_CCK_CCA_11N 0xA0A
83#define DM_REG_CCK_CCA_11AC 0xA0A
84#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
85#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
86#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
87#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
88#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
89#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
90#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
91#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
92#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
93#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
94#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
95#define DM_REG_CCK_FA_RST_11N 0xA2C
96#define DM_REG_CCK_FA_MSB_11N 0xA58
97#define DM_REG_CCK_FA_LSB_11N 0xA5C
98#define DM_REG_CCK_CCA_CNT_11N 0xA60
99#define DM_REG_BB_PWR_SAV4_11N 0xA74
100/*PAGE B */
101#define DM_REG_LNA_SWITCH_11N 0xB2C
102#define DM_REG_PATH_SWITCH_11N 0xB30
103#define DM_REG_RSSI_CTRL_11N 0xB38
104#define DM_REG_CONFIG_ANTA_11N 0xB68
105#define DM_REG_RSSI_BT_11N 0xB9C
106/*PAGE C */
107#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
108#define DM_REG_RX_PATH_11N 0xC04
109#define DM_REG_TRMUX_11N 0xC08
110#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
111#define DM_REG_RXIQI_MATRIX_11N 0xC14
112#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
113#define DM_REG_IGI_A_11N 0xC50
114#define DM_REG_IGI_A_11AC 0xC50
115#define DM_REG_ANTDIV_PARA2_11N 0xC54
116#define DM_REG_IGI_B_11N 0xC58
117#define DM_REG_IGI_B_11AC 0xE50
118#define DM_REG_ANTDIV_PARA3_11N 0xC5C
119#define DM_REG_BB_PWR_SAV2_11N 0xC70
120#define DM_REG_RX_OFF_11N 0xC7C
121#define DM_REG_TXIQK_MATRIXA_11N 0xC80
122#define DM_REG_TXIQK_MATRIXB_11N 0xC88
123#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
124#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
125#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
126#define DM_REG_ANTDIV_PARA1_11N 0xCA4
127#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
128/*PAGE D */
129#define DM_REG_OFDM_FA_RSTD_11N 0xD00
130#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
131#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
132#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
133/*PAGE E */
134#define DM_REG_TXAGC_A_6_18_11N 0xE00
135#define DM_REG_TXAGC_A_24_54_11N 0xE04
136#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
137#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
138#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
139#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
140#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
141#define DM_REG_FPGA0_IQK_11N 0xE28
142#define DM_REG_TXIQK_TONE_A_11N 0xE30
143#define DM_REG_RXIQK_TONE_A_11N 0xE34
144#define DM_REG_TXIQK_PI_A_11N 0xE38
145#define DM_REG_RXIQK_PI_A_11N 0xE3C
146#define DM_REG_TXIQK_11N 0xE40
147#define DM_REG_RXIQK_11N 0xE44
148#define DM_REG_IQK_AGC_PTS_11N 0xE48
149#define DM_REG_IQK_AGC_RSP_11N 0xE4C
150#define DM_REG_BLUETOOTH_11N 0xE6C
151#define DM_REG_RX_WAIT_CCA_11N 0xE70
152#define DM_REG_TX_CCK_RFON_11N 0xE74
153#define DM_REG_TX_CCK_BBON_11N 0xE78
154#define DM_REG_OFDM_RFON_11N 0xE7C
155#define DM_REG_OFDM_BBON_11N 0xE80
156#define DM_REG_TX2RX_11N 0xE84
157#define DM_REG_TX2TX_11N 0xE88
158#define DM_REG_RX_CCK_11N 0xE8C
159#define DM_REG_RX_OFDM_11N 0xED0
160#define DM_REG_RX_WAIT_RIFS_11N 0xED4
161#define DM_REG_RX2RX_11N 0xED8
162#define DM_REG_STANDBY_11N 0xEDC
163#define DM_REG_SLEEP_11N 0xEE0
164#define DM_REG_PMPD_ANAEN_11N 0xEEC
165
166
167/*MAC REG LIST*/
168#define DM_REG_BB_RST_11N 0x02
169#define DM_REG_ANTSEL_PIN_11N 0x4C
170#define DM_REG_EARLY_MODE_11N 0x4D0
171#define DM_REG_RSSI_MONITOR_11N 0x4FE
172#define DM_REG_EDCA_VO_11N 0x500
173#define DM_REG_EDCA_VI_11N 0x504
174#define DM_REG_EDCA_BE_11N 0x508
175#define DM_REG_EDCA_BK_11N 0x50C
176#define DM_REG_TXPAUSE_11N 0x522
177#define DM_REG_RESP_TX_11N 0x6D8
178#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
179#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
180
181
182/*DIG Related*/
183#define DM_BIT_IGI_11N 0x0000007F
184#define DM_BIT_IGI_11AC 0xFFFFFFFF
185
186
187
188#define HAL_DM_DIG_DISABLE BIT(0)
189#define HAL_DM_HIPWR_DISABLE BIT(1)
190
191#define OFDM_TABLE_LENGTH 43
192#define CCK_TABLE_LENGTH 33
193
194#define OFDM_TABLE_SIZE 37
195#define CCK_TABLE_SIZE 33
196
197#define BW_AUTO_SWITCH_HIGH_LOW 25
198#define BW_AUTO_SWITCH_LOW_HIGH 30
199
200#define DM_DIG_THRESH_HIGH 40
201#define DM_DIG_THRESH_LOW 35
202
203#define DM_FALSEALARM_THRESH_LOW 400
204#define DM_FALSEALARM_THRESH_HIGH 1000
205
206#define DM_DIG_MAX 0x3e
207#define DM_DIG_MIN 0x1e
208
209#define DM_DIG_MAX_AP 0x32
210#define DM_DIG_MIN_AP 0x20
211
212#define DM_DIG_FA_UPPER 0x3e
213#define DM_DIG_FA_LOWER 0x1e
214#define DM_DIG_FA_TH0 0x200
215#define DM_DIG_FA_TH1 0x300
216#define DM_DIG_FA_TH2 0x400
217
218#define DM_DIG_BACKOFF_MAX 12
219#define DM_DIG_BACKOFF_MIN -4
220#define DM_DIG_BACKOFF_DEFAULT 10
221
222#define RXPATHSELECTION_SS_TH_lOW 30
223#define RXPATHSELECTION_DIFF_TH 18
224
225#define DM_RATR_STA_INIT 0
226#define DM_RATR_STA_HIGH 1
227#define DM_RATR_STA_MIDDLE 2
228#define DM_RATR_STA_LOW 3
229
230#define CTS2SELF_THVAL 30
231#define REGC38_TH 20
232
233#define WAIOTTHVal 25
234
235#define TXHIGHPWRLEVEL_NORMAL 0
236#define TXHIGHPWRLEVEL_LEVEL1 1
237#define TXHIGHPWRLEVEL_LEVEL2 2
238#define TXHIGHPWRLEVEL_BT1 3
239#define TXHIGHPWRLEVEL_BT2 4
240
241#define DM_TYPE_BYFW 0
242#define DM_TYPE_BYDRIVER 1
243
244#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
245#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
246#define TXPWRTRACK_MAX_IDX 6
247
248/* Dynamic ATC switch */
249#define ATC_STATUS_OFF 0x0 /* enable */
250#define ATC_STATUS_ON 0x1 /* disable */
251#define CFO_THRESHOLD_XTAL 10 /* kHz */
252#define CFO_THRESHOLD_ATC 80 /* kHz */
253
254#define AVG_THERMAL_NUM_8812A 4
255#define TXPWR_TRACK_TABLE_SIZE 30
256#define MAX_PATH_NUM_8812A 2
257#define MAX_PATH_NUM_8821A 1
258
259
260struct ps_t {
261 u8 pre_ccastate;
262 u8 cur_ccasate;
263 u8 pre_rfstate;
264 u8 cur_rfstate;
265 u8 initialize;
266 long rssi_val_min;
267
268};
269
270struct dig_t {
271 u8 dig_enable_flag;
272 u8 dig_ext_port_stage;
273 u32 rssi_lowthresh;
274 u32 rssi_highthresh;
275
276 u32 fa_lowthresh;
277 u32 fa_highthresh;
278
279 u8 cursta_connectctate;
280 u8 presta_connectstate;
281 u8 curmultista_connectstate;
282
283 u8 pre_igvalue;
284 u8 cur_igvalue;
285 u8 bt30_cur_igi;
286 u8 backup_igvalue;
287 u8 stop_dig;
288
289 char backoff_val;
290 char backoff_val_range_max;
291 char backoff_val_range_min;
292 u8 rx_gain_range_max;
293 u8 rx_gain_range_min;
294 u8 rssi_val_min;
295
296 u8 pre_cck_cca_thres;
297 u8 cur_cck_cca_thres;
298 u8 pre_cck_pd_state;
299 u8 cur_cck_pd_state;
300
301 u8 large_fa_hit;
302 u8 forbidden_igi;
303 u32 recover_cnt;
304
305 u8 dig_dynamic_min_0;
306 u8 dig_dynamic_min_1;
307 bool b_media_connect_0;
308 bool b_media_connect_1;
309
310 u32 antdiv_rssi_max;
311 u32 rssi_max;
312};
313
314
315enum FAT_STATE {
316 FAT_NORMAL_STATE = 0,
317 FAT_TRAINING_STATE = 1,
318};
319
320enum tag_dynamic_init_gain_operation_type_definition {
321 DIG_TYPE_THRESH_HIGH = 0,
322 DIG_TYPE_THRESH_LOW = 1,
323 DIG_TYPE_BACKOFF = 2,
324 DIG_TYPE_RX_GAIN_MIN = 3,
325 DIG_TYPE_RX_GAIN_MAX = 4,
326 DIG_TYPE_ENABLE = 5,
327 DIG_TYPE_DISABLE = 6,
328 DIG_OP_TYPE_MAX
329};
330
331enum tag_cck_packet_detection_threshold_type_definition {
332 CCK_PD_STAGE_LowRssi = 0,
333 CCK_PD_STAGE_HighRssi = 1,
334 CCK_FA_STAGE_Low = 2,
335 CCK_FA_STAGE_High = 3,
336 CCK_PD_STAGE_MAX = 4,
337};
338
339enum dm_1r_cca_e {
340 CCA_1R = 0,
341 CCA_2R = 1,
342 CCA_MAX = 2,
343};
344
345enum dm_rf_e {
346 RF_SAVE = 0,
347 RF_NORMAL = 1,
348 RF_MAX = 2,
349};
350
351enum dm_sw_ant_switch_e {
352 ANS_ANTENNA_B = 1,
353 ANS_ANTENNA_A = 2,
354 ANS_ANTENNA_MAX = 3,
355};
356
357enum dm_dig_ext_port_alg_e {
358 DIG_EXT_PORT_STAGE_0 = 0,
359 DIG_EXT_PORT_STAGE_1 = 1,
360 DIG_EXT_PORT_STAGE_2 = 2,
361 DIG_EXT_PORT_STAGE_3 = 3,
362 DIG_EXT_PORT_STAGE_MAX = 4,
363};
364
365enum dm_dig_connect_e {
366 DIG_STA_DISCONNECT = 0,
367 DIG_STA_CONNECT = 1,
368 DIG_STA_BEFORE_CONNECT = 2,
369 DIG_MULTISTA_DISCONNECT = 3,
370 DIG_MULTISTA_CONNECT = 4,
371 DIG_CONNECT_MAX
372};
373
374enum pwr_track_control_method {
375 BBSWING,
376 TXAGC,
377 MIX_MODE
378};
379
380#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
381#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
382#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
383#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
384#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
385#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
386 (((struct rtl_priv *)(_priv))->mac80211.opmode == NL80211_IFTYPE_ADHOC)? \
387 (((struct rtl_priv *)(_priv))->dm.entry_min_undecoratedsmoothed_pwdb): \
388 (((struct rtl_priv *)(_priv))->dm.undecorated_smoothed_pwdb)
389
390extern struct dig_t dm_digtable;
391void rtl8821ae_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
392 u8 *pdesc, u32 mac_id);
393void rtl8821ae_dm_ant_sel_statistics(struct ieee80211_hw *hw,
394 u8 antsel_tr_mux, u32 mac_id,
395 u32 rx_pwdb_all);
396void rtl8821ae_dm_fast_antenna_trainning_callback(unsigned long data);
397void rtl8821ae_dm_init(struct ieee80211_hw *hw);
398void rtl8821ae_dm_watchdog(struct ieee80211_hw *hw);
399void rtl8821ae_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
400void rtl8821ae_dm_init_edca_turbo(struct ieee80211_hw *hw);
401void rtl8821ae_dm_check_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
402void rtl8821ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
403void rtl8821ae_dm_txpower_track_adjust(struct ieee80211_hw *hw,
404 u8 type,u8 *pdirection,
405 u32 *poutwrite_val);
406void rtl8821ae_dm_clear_txpower_tracking_state(struct ieee80211_hw *hw);
407void rtl8821ae_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 current_cca);
408void rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
409void rtl8812ae_dm_path_diversity(struct ieee80211_hw *hw);
410void rtl8812ae_dm_path_diversity_init(struct ieee80211_hw *hw);
411void rtl8812ae_dm_path_statistics(struct ieee80211_hw *hw,
412 u32 rssi_a, u32 rssi_b);
413void rtl812ae_dm_set_txpath_by_txinfo(struct ieee80211_hw *hw,
414 u8 *pdesc);
415void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
416 enum pwr_track_control_method method,
417 u8 rf_path,
418 u8 channel_mapped_index);
419void rtl8821ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
420 enum pwr_track_control_method method, u8 rf_path, u8 channel_mapped_index);
421
422void rtl8812ae_dm_update_init_rate(struct ieee80211_hw *hw, u8 rate);
423u8 rtl8812ae_hw_rate_to_mrate(struct ieee80211_hw *hw, u8 rate);
424void rtl8812ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
425void rtl8821ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
426#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/fw.c b/drivers/staging/rtl8821ae/rtl8821ae/fw.c
new file mode 100644
index 000000000000..4083cab926a3
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/fw.c
@@ -0,0 +1,1349 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../base.h"
33#include "reg.h"
34#include "def.h"
35#include "fw.h"
36#include "dm.h"
37
38static void _rtl8821ae_enable_fw_download(struct ieee80211_hw *hw, bool enable)
39{
40 struct rtl_priv *rtlpriv = rtl_priv(hw);
41 u8 tmp;
42
43 if (enable) {
44 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x05);
45
46 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
47 rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
48
49 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
50 //printk("0x80=%02x.\n",tmp);
51 } else {
52 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
53 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
54 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
55 //printk("0x80=%02x.\n",tmp);
56 }
57
58}
59
60static void _rtl8821ae_fw_block_write(struct ieee80211_hw *hw,
61 const u8 *buffer, u32 size)
62{
63 struct rtl_priv *rtlpriv = rtl_priv(hw);
64 u32 blockSize = sizeof(u32);
65 u8 *bufferPtr = (u8 *) buffer;
66 u32 *pu4BytePtr = (u32 *) buffer;
67 u32 i, offset, blockCount, remainSize;
68
69 blockCount = size / blockSize;
70 remainSize = size % blockSize;
71
72 for (i = 0; i < blockCount; i++) {
73 offset = i * blockSize;
74 rtl_write_dword(rtlpriv, (FW_8821AE_START_ADDRESS + offset),
75 *(pu4BytePtr + i));
76 }
77
78 if (remainSize) {
79 offset = blockCount * blockSize;
80 bufferPtr += offset;
81 for (i = 0; i < remainSize; i++) {
82 rtl_write_byte(rtlpriv, (FW_8821AE_START_ADDRESS +
83 offset + i), *(bufferPtr + i));
84 }
85 }
86}
87
88static void _rtl8821ae_fw_page_write(struct ieee80211_hw *hw,
89 u32 page, const u8 *buffer, u32 size)
90{
91 struct rtl_priv *rtlpriv = rtl_priv(hw);
92 u8 value8;
93 u8 u8page = (u8) (page & 0x07);
94
95 value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
96
97 rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
98 _rtl8821ae_fw_block_write(hw, buffer, size);
99}
100
101static void _rtl8821ae_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
102{
103 u32 fwlen = *pfwlen;
104 u8 remain = (u8) (fwlen % 4);
105
106 remain = (remain == 0) ? 0 : (4 - remain);
107
108 while (remain > 0) {
109 pfwbuf[fwlen] = 0;
110 fwlen++;
111 remain--;
112 }
113
114 *pfwlen = fwlen;
115}
116
117static void _rtl8821ae_write_fw(struct ieee80211_hw *hw,
118 enum version_8821ae version,
119 u8 *buffer, u32 size)
120{
121 struct rtl_priv *rtlpriv = rtl_priv(hw);
122 u8 *bufferPtr = (u8 *) buffer;
123 u32 pageNums, remainSize;
124 u32 page, offset;
125
126 RT_TRACE(COMP_FW, DBG_LOUD, ("FW size is %d bytes,\n", size));
127
128 _rtl8821ae_fill_dummy(bufferPtr, &size);
129
130 pageNums = size / FW_8821AE_PAGE_SIZE;
131 remainSize = size % FW_8821AE_PAGE_SIZE;
132
133 if (pageNums > 8) {
134 RT_TRACE(COMP_ERR, DBG_EMERG,
135 ("Page numbers should not greater then 8\n"));
136 }
137
138 for (page = 0; page < pageNums; page++) {
139 offset = page * FW_8821AE_PAGE_SIZE;
140 _rtl8821ae_fw_page_write(hw, page, (bufferPtr + offset),
141 FW_8821AE_PAGE_SIZE);
142 }
143
144 if (remainSize) {
145 offset = pageNums * FW_8821AE_PAGE_SIZE;
146 page = pageNums;
147 _rtl8821ae_fw_page_write(hw, page, (bufferPtr + offset),
148 remainSize);
149 }
150
151}
152
153static int _rtl8821ae_fw_free_to_go(struct ieee80211_hw *hw)
154{
155 struct rtl_priv *rtlpriv = rtl_priv(hw);
156 int err = -EIO;
157 u32 counter = 0;
158 u32 value32;
159
160 do {
161 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
162 } while ((counter++ < FW_8821AE_POLLING_TIMEOUT_COUNT) &&
163 (!(value32 & FWDL_CHKSUM_RPT)));
164
165 if (counter >= FW_8821AE_POLLING_TIMEOUT_COUNT) {
166 RT_TRACE(COMP_ERR, DBG_LOUD,
167 ("chksum report faill ! REG_MCUFWDL:0x%08x .\n",
168 value32));
169 goto exit;
170 }
171
172 RT_TRACE(COMP_FW, DBG_EMERG,
173 ("Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32));
174
175 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
176 value32 |= MCUFWDL_RDY;
177 value32 &= ~WINTINI_RDY;
178 rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
179
180 rtl8821ae_firmware_selfreset(hw);
181
182 counter = 0;
183 do {
184 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
185 if (value32 & WINTINI_RDY) {
186 RT_TRACE(COMP_FW, DBG_LOUD,
187 ("Polling FW ready success!! REG_MCUFWDL:0x%08x .\n",
188 value32));
189 err = 0;
190 goto exit;
191 }
192
193 udelay(FW_8821AE_POLLING_DELAY);
194
195 } while (counter++ < FW_8821AE_POLLING_TIMEOUT_COUNT);
196
197 RT_TRACE(COMP_ERR, DBG_EMERG,
198 ("Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", value32));
199
200exit:
201 return err;
202}
203
204int rtl8821ae_download_fw(struct ieee80211_hw *hw,
205 bool buse_wake_on_wlan_fw
206 )
207{
208 struct rtl_priv *rtlpriv = rtl_priv(hw);
209 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
210 struct rtl8821a_firmware_header *pfwheader;
211 u8 *pfwdata;
212 u32 fwsize;
213 int err;
214 enum version_8821ae version = rtlhal->version;
215
216 if(!rtlhal->pfirmware)
217 return 1;
218
219 pfwheader = (struct rtl8821a_firmware_header *)rtlhal->pfirmware;
220 pfwdata = (u8 *) rtlhal->pfirmware;
221 fwsize = rtlhal->fwsize;
222 RT_TRACE(COMP_FW, DBG_DMESG,
223 ("normal Firmware SIZE %d \n",fwsize));
224
225 if (IS_FW_HEADER_EXIST_8812(pfwheader) || IS_FW_HEADER_EXIST_8821(pfwheader)) {
226 RT_TRACE(COMP_FW, DBG_DMESG,
227 ("Firmware Version(%d), Signature(%#x),Size(%d)\n",
228 pfwheader->version, pfwheader->signature,
229 (int)sizeof(struct rtl8821a_firmware_header)));
230
231 pfwdata = pfwdata + sizeof(struct rtl8821a_firmware_header);
232 fwsize = fwsize - sizeof(struct rtl8821a_firmware_header);
233 }
234
235 if(rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)){
236 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
237 rtl8821ae_firmware_selfreset(hw);
238 }
239 _rtl8821ae_enable_fw_download(hw, true);
240 _rtl8821ae_write_fw(hw, version, pfwdata, fwsize);
241 _rtl8821ae_enable_fw_download(hw, false);
242
243 err = _rtl8821ae_fw_free_to_go(hw);
244 if (err) {
245 RT_TRACE(COMP_ERR, DBG_EMERG,
246 ("Firmware is not ready to run!\n"));
247 } else {
248 RT_TRACE(COMP_FW, DBG_LOUD,
249 ("Firmware is ready to run!\n"));
250 }
251
252 return 0;
253}
254
255static bool _rtl8821ae_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
256{
257 struct rtl_priv *rtlpriv = rtl_priv(hw);
258 u8 val_hmetfr;
259 bool result = false;
260
261 val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
262 if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
263 result = true;
264 return result;
265}
266
267static void _rtl8821ae_fill_h2c_command(struct ieee80211_hw *hw,
268 u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
269{
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
272 u8 boxnum =0;
273 u16 box_reg = 0, box_extreg = 0;
274 u8 u1b_tmp = 0;
275 bool isfw_read = false;
276 u8 buf_index = 0;
277 bool bwrite_sucess = false;
278 u8 wait_h2c_limmit = 100;
279 /*u8 wait_writeh2c_limmit = 100;*/
280 u8 boxcontent[4], boxextcontent[4];
281 u32 h2c_waitcounter = 0;
282 unsigned long flag =0;
283 u8 idx =0;
284
285 RT_TRACE(COMP_CMD, DBG_LOUD, ("come in\n"));
286
287 while (true) {
288 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
289 if (rtlhal->b_h2c_setinprogress) {
290 RT_TRACE(COMP_CMD, DBG_LOUD,
291 ("H2C set in progress! Wait to set.."
292 "element_id(%d).\n", element_id));
293
294 while (rtlhal->b_h2c_setinprogress) {
295 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
296 flag);
297 h2c_waitcounter++;
298 RT_TRACE(COMP_CMD, DBG_LOUD,
299 ("Wait 100 us (%d times)...\n",
300 h2c_waitcounter));
301 udelay(100);
302
303 if (h2c_waitcounter > 1000)
304 return;
305 spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
306 flag);
307 }
308 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
309 } else {
310 rtlhal->b_h2c_setinprogress = true;
311 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
312 break;
313 }
314 }
315
316 while (!bwrite_sucess) {
317 /*cosa remove this because never reach this.*/
318#if 0
319 wait_writeh2c_limmit--;
320 if (wait_writeh2c_limmit == 0) {
321 RT_TRACE(COMP_ERR, DBG_EMERG,
322 ("Write H2C fail because no trigger "
323 "for FW INT!\n"));
324 break;
325 }
326#endif
327
328 boxnum = rtlhal->last_hmeboxnum;
329 switch (boxnum) {
330 case 0:
331 box_reg = REG_HMEBOX_0;
332 box_extreg = REG_HMEBOX_EXT_0;
333 break;
334 case 1:
335 box_reg = REG_HMEBOX_1;
336 box_extreg = REG_HMEBOX_EXT_1;
337 break;
338 case 2:
339 box_reg = REG_HMEBOX_2;
340 box_extreg = REG_HMEBOX_EXT_2;
341 break;
342 case 3:
343 box_reg = REG_HMEBOX_3;
344 box_extreg = REG_HMEBOX_EXT_3;
345 break;
346 default:
347 RT_TRACE(COMP_ERR, DBG_EMERG,
348 ("switch case not process \n"));
349 break;
350 }
351
352 isfw_read = false;
353 u1b_tmp = rtl_read_byte(rtlpriv, REG_CR);
354
355 if (u1b_tmp != 0xEA)
356 isfw_read = true;
357 else {
358 if( rtl_read_byte(rtlpriv, REG_TXDMA_STATUS) == 0xEA ||
359 rtl_read_byte(rtlpriv, REG_TXPKT_EMPTY) == 0xEA)
360 rtl_write_byte(rtlpriv, REG_SYS_CFG1 + 3, 0xFF);
361 }
362
363 if (isfw_read == true) {
364 wait_h2c_limmit = 100;
365 isfw_read = _rtl8821ae_check_fw_read_last_h2c(hw, boxnum);
366 while (!isfw_read) {
367 /*wait until Fw read*/
368 wait_h2c_limmit--;
369 if (wait_h2c_limmit == 0) {
370 RT_TRACE(COMP_CMD, DBG_LOUD,
371 ("Wating too long for FW read "
372 "clear HMEBox(%d)!\n", boxnum));
373 break;
374 }
375
376 udelay(10);
377
378 isfw_read = _rtl8821ae_check_fw_read_last_h2c(hw, boxnum);
379 u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
380 RT_TRACE(COMP_CMD, DBG_LOUD,
381 ("Wating for FW read clear HMEBox(%d)!!! "
382 "0x130 = %2x\n", boxnum, u1b_tmp));
383 }
384 }
385
386 if (!isfw_read) {
387 RT_TRACE(COMP_CMD, DBG_LOUD,
388 ("Write H2C register BOX[%d] fail!!!!! "
389 "Fw do not read. \n", boxnum));
390 break;
391 }
392
393 memset(boxcontent, 0, sizeof(boxcontent));
394 memset(boxextcontent, 0, sizeof(boxextcontent));
395 boxcontent[0] = element_id;
396 RT_TRACE(COMP_CMD, DBG_LOUD,
397 ("Write element_id box_reg(%4x) = %2x \n",
398 box_reg, element_id));
399
400 switch (cmd_len) {
401 case 1:
402 case 2:
403 case 3:
404 /*boxcontent[0] &= ~(BIT(7));*/
405 memcpy((u8 *) (boxcontent) + 1,
406 p_cmdbuffer + buf_index, cmd_len);
407
408 for (idx = 0; idx < 4; idx++) {
409 rtl_write_byte(rtlpriv, box_reg + idx,
410 boxcontent[idx]);
411 }
412 break;
413 case 4:
414 case 5:
415 case 6:
416 case 7:
417 /*boxcontent[0] |= (BIT(7));*/
418 memcpy((u8 *) (boxextcontent),
419 p_cmdbuffer + buf_index+3, cmd_len-3);
420 memcpy((u8 *) (boxcontent) + 1,
421 p_cmdbuffer + buf_index, 3);
422
423 for (idx = 0; idx < 4; idx++) {
424 rtl_write_byte(rtlpriv, box_extreg + idx,
425 boxextcontent[idx]);
426 }
427
428 for (idx = 0; idx < 4; idx++) {
429 rtl_write_byte(rtlpriv, box_reg + idx,
430 boxcontent[idx]);
431 }
432 break;
433 default:
434 RT_TRACE(COMP_ERR, DBG_EMERG,
435 ("switch case not process \n"));
436 break;
437 }
438
439 bwrite_sucess = true;
440
441 rtlhal->last_hmeboxnum = boxnum + 1;
442 if (rtlhal->last_hmeboxnum == 4)
443 rtlhal->last_hmeboxnum = 0;
444
445 RT_TRACE(COMP_CMD, DBG_LOUD,
446 ("pHalData->last_hmeboxnum = %d\n",
447 rtlhal->last_hmeboxnum));
448 }
449
450 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
451 rtlhal->b_h2c_setinprogress = false;
452 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
453
454 RT_TRACE(COMP_CMD, DBG_LOUD, ("go out\n"));
455}
456
457void rtl8821ae_fill_h2c_cmd(struct ieee80211_hw *hw,
458 u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
459{
460 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
461 u32 tmp_cmdbuf[2];
462
463 if (rtlhal->bfw_ready == false) {
464 RT_ASSERT(false, ("return H2C cmd because of Fw "
465 "download fail!!!\n"));
466 return;
467 }
468
469 memset(tmp_cmdbuf, 0, 8);
470 memcpy(tmp_cmdbuf, p_cmdbuffer, cmd_len);
471 _rtl8821ae_fill_h2c_command(hw, element_id, cmd_len, (u8 *) & tmp_cmdbuf);
472
473 return;
474}
475
476void rtl8821ae_firmware_selfreset(struct ieee80211_hw *hw)
477{
478 u8 u1b_tmp;
479 struct rtl_priv *rtlpriv = rtl_priv(hw);
480 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
481
482 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
483 {
484 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
485 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
486 }else {
487 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
488 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(0))));
489 }
490
491 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
492 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
493 udelay(50);
494
495 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
496 {
497 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
498 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
499 }else {
500 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
501 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(0)));
502 }
503
504 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
505 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp | BIT(2)));
506
507 RT_TRACE(COMP_INIT, DBG_LOUD, (" _8051Reset8812ae(): 8051 reset success .\n"));
508
509}
510
511void rtl8821ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
512{
513 struct rtl_priv *rtlpriv = rtl_priv(hw);
514 u8 u1_h2c_set_pwrmode[H2C_8821AE_PWEMODE_LENGTH] = { 0 };
515 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
516 u8 rlbm,power_state = 0;
517 RT_TRACE(COMP_POWER, DBG_LOUD, ("FW LPS mode = %d\n", mode));
518
519 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
520 rlbm = 0;/*YJ,temp,120316. FW now not support RLBM=2.*/
521 SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
522 SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode, (rtlpriv->mac80211.p2p) ? ppsc->smart_ps : 1);
523 SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode, ppsc->reg_max_lps_awakeintvl);
524 SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
525 if(mode == FW_PS_ACTIVE_MODE)
526 {
527 power_state |= FW_PWR_STATE_ACTIVE;
528 }
529 else
530 {
531 power_state |= FW_PWR_STATE_RF_OFF;
532 }
533 SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
534
535 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
536 "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode \n",
537 u1_h2c_set_pwrmode, H2C_8821AE_PWEMODE_LENGTH);
538 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_SETPWRMODE, H2C_8821AE_PWEMODE_LENGTH, u1_h2c_set_pwrmode);
539
540}
541
542void rtl8821ae_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
543{
544 u8 u1_joinbssrpt_parm[1] = { 0 };
545
546 SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
547
548 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_JOINBSSRPT, 1, u1_joinbssrpt_parm);
549}
550
551void rtl8821ae_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw, u8 ap_offload_enable)
552{
553 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
554 u8 u1_apoffload_parm[H2C_8821AE_AP_OFFLOAD_LENGTH] = { 0 };
555
556 SET_H2CCMD_AP_OFFLOAD_ON(u1_apoffload_parm, ap_offload_enable);
557 SET_H2CCMD_AP_OFFLOAD_HIDDEN(u1_apoffload_parm, mac->bhiddenssid);
558 SET_H2CCMD_AP_OFFLOAD_DENYANY(u1_apoffload_parm, 0);
559
560 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_AP_OFFLOAD, H2C_8821AE_AP_OFFLOAD_LENGTH, u1_apoffload_parm);
561
562}
563
564static bool _rtl8821ae_cmd_send_packet(struct ieee80211_hw *hw,
565 struct sk_buff *skb)
566{
567 struct rtl_priv *rtlpriv = rtl_priv(hw);
568 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
569 struct rtl8192_tx_ring *ring;
570 struct rtl_tx_desc *pdesc;
571 u8 own;
572 unsigned long flags;
573 struct sk_buff *pskb = NULL;
574
575 ring = &rtlpci->tx_ring[BEACON_QUEUE];
576
577 pskb = __skb_dequeue(&ring->queue);
578 if (pskb)
579 kfree_skb(pskb);
580
581 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
582
583 pdesc = &ring->desc[0];
584 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc, true, HW_DESC_OWN);
585
586 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
587
588 __skb_queue_tail(&ring->queue, skb);
589
590 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
591
592 rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
593
594 return true;
595}
596
597#define BEACON_PG 0 /* ->1 */
598#define PSPOLL_PG 2
599#define NULL_PG 3
600#define PROBERSP_PG 4 /* ->5 */
601
602#define BEACON_PG_8812 0
603#define PSPOLL_PG_8812 1
604#define NULL_PG_8812 2
605#define PROBERSP_PG_8812 3
606
607#define BEACON_PG_8821 0
608#define PSPOLL_PG_8821 1
609#define NULL_PG_8821 2
610#define PROBERSP_PG_8821 3
611
612#define TOTAL_RESERVED_PKT_LEN_8812 2048
613#define TOTAL_RESERVED_PKT_LEN_8821 1024
614
615
616static u8 reserved_page_packet_8821[TOTAL_RESERVED_PKT_LEN_8821] = {
617 /* page 0 */
618 0x80, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
619 0xff, 0xff, 0x00, 0xe0, 0x4c, 0x02, 0xe2, 0x64,
620 0x40, 0x16, 0x9f, 0x23, 0xd4, 0x46, 0x20, 0x00,
621 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
622 0x64, 0x00, 0x20, 0x04, 0x00, 0x06, 0x64, 0x6c,
623 0x69, 0x6e, 0x6b, 0x31, 0x01, 0x08, 0x82, 0x84,
624 0x8b, 0x96, 0x0c, 0x18, 0x30, 0x48, 0x03, 0x01,
625 0x0b, 0x06, 0x02, 0x00, 0x00, 0x2a, 0x01, 0x8b,
626 0x32, 0x04, 0x12, 0x24, 0x60, 0x6c, 0x00, 0x00,
627 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
628 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
629 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
630 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
631 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
632 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
633 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
634 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
636 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
637 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
638 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
639 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
640 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
641 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
642 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
643 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
644 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
645 0x10, 0x00, 0x28, 0x8c, 0x00, 0x12, 0x00, 0x00,
646 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
647 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
648 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
649 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
650 /* page 1 */
651 0xa4, 0x10, 0x01, 0xc0, 0x40, 0x16, 0x9f, 0x23,
652 0xd4, 0x46, 0x00, 0xe0, 0x4c, 0x02, 0xe2, 0x64,
653 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
654 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
655 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
656 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
657 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
658 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
659 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
660 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
661 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
662 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
663 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
664 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
666 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
667 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
668 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
669 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
670 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
671 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
672 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
673 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
674 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
675 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
676 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
677 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
678 0x18, 0x00, 0x28, 0x8c, 0x00, 0x12, 0x00, 0x00,
679 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
680 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
681 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
682 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
683 /* page 2 */
684 0x48, 0x01, 0x00, 0x00, 0x40, 0x16, 0x9f, 0x23,
685 0xd4, 0x46, 0x00, 0xe0, 0x4c, 0x02, 0xe2, 0x64,
686 0x40, 0x16, 0x9f, 0x23, 0xd4, 0x46, 0x00, 0x00,
687 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
688 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
689 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
690 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
691 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
692 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
693 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
694 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
695 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
696 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
697 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
698 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
699 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
700 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
701 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
702 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
703 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
704 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
706 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
707 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
708 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
709 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
710 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
711 0x1a, 0x00, 0x28, 0x8c, 0x00, 0x12, 0x00, 0x00,
712 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
713 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
714 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
715 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
716 /* page 3 */
717 0xc8, 0x01, 0x00, 0x00, 0x40, 0x16, 0x9f, 0x23,
718 0xd4, 0x46, 0x00, 0xe0, 0x4c, 0x02, 0xe2, 0x64,
719 0x40, 0x16, 0x9f, 0x23, 0xd4, 0x46, 0x00, 0x00,
720 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
721 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
722 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
723 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
724 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
725 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
726 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
727 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
728 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
729 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
730 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
731 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
732 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
733 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
734 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
735 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
736 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
737 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
738 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
739 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
740 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
741 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
742 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
743 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
744 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
745 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
746 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
747 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
748 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
749};
750
751
752static u8 reserved_page_packet_8812[TOTAL_RESERVED_PKT_LEN_8812] = {
753 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
754 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x02, 0x53, 0xE5,
755 0xE0, 0x46, 0x9A, 0x57, 0x71, 0x30, 0x20, 0x00,
756 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
757 0x64, 0x00, 0x30, 0x04, 0x00, 0x0C, 0x4E, 0x45,
758 0x54, 0x47, 0x45, 0x41, 0x52, 0x5F, 0x31, 0x35,
759 0x30, 0x4E, 0x01, 0x08, 0x82, 0x84, 0x8B, 0x96,
760 0x0C, 0x12, 0x18, 0x24, 0x03, 0x01, 0x03, 0x06,
761 0x02, 0x00, 0x00, 0x2A, 0x01, 0x8A, 0x32, 0x04,
762 0x30, 0x48, 0x60, 0x6C, 0xDD, 0x18, 0x00, 0x50,
763 0xF2, 0x01, 0x01, 0x00, 0x00, 0x50, 0xF2, 0x02,
764 0x01, 0x00, 0x00, 0x50, 0xF2, 0x02, 0x01, 0x00,
765 0x00, 0x50, 0xF2, 0x02, 0x00, 0x00, 0x00, 0x00,
766 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
767 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
768 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
769 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
770 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
771 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
772 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
773 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
774 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
775 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
776 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
777 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
778 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
779 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
780 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
781 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
782 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
783 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
784 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
785 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
786 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
787 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
788 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
789 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
790 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
791 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
792 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
793 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
794 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
795 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
796 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
797 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
798 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
799 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
800 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
801 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
802 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
803 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
804 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
805 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
806 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
808 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
809 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
810 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
811 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
812 0x10, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
813 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
814 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
815 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
816 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
817
818 0xA4, 0x10, 0x02, 0xC0, 0xE0, 0x46, 0x9A, 0x57,
819 0x71, 0x30, 0x00, 0xE0, 0x4C, 0x02, 0x53, 0xE5,
820 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
821 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
822 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
823 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
824 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
826 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
827 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
828 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
829 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
830 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
831 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
832 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
833 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
834 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
835 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
836 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
837 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
838 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
839 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
840 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
841 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
842 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
843 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
844 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
846 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
847 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
848 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
849 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
850 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
851 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
852 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
853 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
854 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
855 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
856 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
857 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
858 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
859 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
860 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
861 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
862 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
863 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
864 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
865 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
866 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
867 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
868 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
869 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
870 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
871 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
872 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
873 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
874 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
875 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
876 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
877 0x18, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
878 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
879 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
880 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
881 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
882
883 0x48, 0x01, 0x00, 0x00, 0xE0, 0x46, 0x9A, 0x57,
884 0x71, 0x30, 0x00, 0xE0, 0x4C, 0x02, 0x53, 0xE5,
885 0xE0, 0x46, 0x9A, 0x57, 0x71, 0x30, 0x00, 0x00,
886 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
887 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
888 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
889 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
890 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
891 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
892 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
893 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
894 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
895 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
896 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
897 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
898 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
899 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
900 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
901 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
902 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
903 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
904 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
905 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
906 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
907 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
908 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
909 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
910 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
911 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
912 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
913 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
914 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
916 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
917 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
918 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
919 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
920 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
921 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
922 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
923 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
924 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
925 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
926 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
927 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
928 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
929 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
930 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
931 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
932 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
933 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
934 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
936 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
937 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
938 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
939 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
940 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
941 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
942 0x1A, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
943 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
944 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
945 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
946 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
947
948 0xC8, 0x01, 0x00, 0x00, 0xE0, 0x46, 0x9A, 0x57,
949 0x71, 0x30, 0x00, 0xE0, 0x4C, 0x02, 0x53, 0xE5,
950 0xE0, 0x46, 0x9A, 0x57, 0x71, 0x30, 0x00, 0x00,
951 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
952 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
953 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
954 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
955 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
956 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
957 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
958 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
959 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
960 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
961 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
962 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
963 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
964 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
965 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
966 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
967 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
968 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
969 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
970 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
971 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
972 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
973 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
974 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
975 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
976 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
977 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
978 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
979 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
980 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
981 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
982 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
983 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
984 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
985 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
986 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
987 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
988 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
989 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
990 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
991 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
992 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
993 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
994 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
995 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
996 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
997 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
998 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
999 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1000 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1001 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1002 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1003 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1004 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1005 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1006 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1007 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1008 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1009 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1010 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1011 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1012};
1013
1014void rtl8812ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
1015{
1016 struct rtl_priv *rtlpriv = rtl_priv(hw);
1017 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1018 struct sk_buff *skb = NULL;
1019
1020 u32 totalpacketlen;
1021 bool rtstatus;
1022 u8 u1RsvdPageLoc[5] = { 0 };
1023 bool b_dlok = false;
1024
1025 u8* beacon;
1026 u8* p_pspoll;
1027 u8* nullfunc;
1028 u8* p_probersp;
1029 /*---------------------------------------------------------
1030 (1) beacon
1031 ---------------------------------------------------------*/
1032 beacon = &reserved_page_packet_8812[BEACON_PG_8812 * 512];
1033 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
1034 SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
1035
1036 /*-------------------------------------------------------
1037 (2) ps-poll
1038 --------------------------------------------------------*/
1039 p_pspoll = &reserved_page_packet_8812[PSPOLL_PG_8812 * 512];
1040 SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
1041 SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
1042 SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
1043
1044 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG_8812);
1045
1046 /*--------------------------------------------------------
1047 (3) null data
1048 ---------------------------------------------------------*/
1049 nullfunc = &reserved_page_packet_8812[NULL_PG_8812* 512];
1050 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
1051 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
1052 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
1053
1054 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG_8812);
1055
1056 /*---------------------------------------------------------
1057 (4) probe response
1058 ----------------------------------------------------------*/
1059 p_probersp = &reserved_page_packet_8812[PROBERSP_PG_8812 * 512];
1060 SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
1061 SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
1062 SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
1063
1064 SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG_8812);
1065
1066 totalpacketlen = TOTAL_RESERVED_PKT_LEN_8812;
1067
1068 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
1069 "rtl8821ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL \n",
1070 &reserved_page_packet_8812[0], totalpacketlen);
1071 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
1072 "rtl8821ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL \n",
1073 u1RsvdPageLoc, 3);
1074
1075
1076 skb = dev_alloc_skb(totalpacketlen);
1077 memcpy((u8 *) skb_put(skb, totalpacketlen),
1078 &reserved_page_packet_8812, totalpacketlen);
1079
1080 rtstatus = _rtl8821ae_cmd_send_packet(hw, skb);
1081
1082 if (rtstatus)
1083 b_dlok = true;
1084
1085 if (b_dlok) {
1086 RT_TRACE(COMP_POWER, DBG_LOUD,
1087 ("Set RSVD page location to Fw.\n"));
1088 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
1089 "H2C_RSVDPAGE:\n",
1090 u1RsvdPageLoc, 3);
1091 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RSVDPAGE,
1092 sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
1093 } else
1094 RT_TRACE(COMP_ERR, DBG_WARNING,
1095 ("Set RSVD page location to Fw FAIL!!!!!!.\n"));
1096}
1097
1098void rtl8821ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
1099{
1100 struct rtl_priv *rtlpriv = rtl_priv(hw);
1101 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1102 struct sk_buff *skb = NULL;
1103
1104 u32 totalpacketlen;
1105 bool rtstatus;
1106 u8 u1RsvdPageLoc[5] = { 0 };
1107 bool b_dlok = false;
1108
1109 u8* beacon;
1110 u8* p_pspoll;
1111 u8* nullfunc;
1112 u8* p_probersp;
1113 /*---------------------------------------------------------
1114 (1) beacon
1115 ---------------------------------------------------------*/
1116 beacon = &reserved_page_packet_8821[BEACON_PG_8821 * 256];
1117 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
1118 SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
1119
1120 /*-------------------------------------------------------
1121 (2) ps-poll
1122 --------------------------------------------------------*/
1123 p_pspoll = &reserved_page_packet_8821[PSPOLL_PG_8821 * 256];
1124 SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
1125 SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
1126 SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
1127
1128 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG_8821);
1129
1130 /*--------------------------------------------------------
1131 (3) null data
1132 ---------------------------------------------------------*/
1133 nullfunc = &reserved_page_packet_8821[NULL_PG_8821 * 256];
1134 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
1135 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
1136 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
1137
1138 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG_8821);
1139
1140 /*---------------------------------------------------------
1141 (4) probe response
1142 ----------------------------------------------------------*/
1143 p_probersp = &reserved_page_packet_8821[PROBERSP_PG_8821 * 256];
1144 SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
1145 SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
1146 SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
1147
1148 SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG_8821);
1149
1150 totalpacketlen = TOTAL_RESERVED_PKT_LEN_8821;
1151
1152 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
1153 "rtl8821ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL \n",
1154 &reserved_page_packet_8821[0], totalpacketlen);
1155 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
1156 "rtl8821ae_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL \n",
1157 u1RsvdPageLoc, 3);
1158
1159
1160 skb = dev_alloc_skb(totalpacketlen);
1161 memcpy((u8 *) skb_put(skb, totalpacketlen),
1162 &reserved_page_packet_8821, totalpacketlen);
1163
1164 rtstatus = _rtl8821ae_cmd_send_packet(hw, skb);
1165
1166 if (rtstatus)
1167 b_dlok = true;
1168
1169 if (b_dlok) {
1170 RT_TRACE(COMP_POWER, DBG_LOUD,
1171 ("Set RSVD page location to Fw.\n"));
1172 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
1173 "H2C_RSVDPAGE:\n",
1174 u1RsvdPageLoc, 3);
1175 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RSVDPAGE,
1176 sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
1177 } else
1178 RT_TRACE(COMP_ERR, DBG_WARNING,
1179 ("Set RSVD page location to Fw FAIL!!!!!!.\n"));
1180}
1181
1182/*Shoud check FW support p2p or not.*/
1183void rtl8821ae_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
1184{
1185 u8 u1_ctwindow_period[1] ={ ctwindow};
1186
1187 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
1188
1189}
1190
1191void rtl8821ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
1192{
1193 struct rtl_priv *rtlpriv = rtl_priv(hw);
1194 struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
1195 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1196 struct rtl_p2p_ps_info *p2pinfo = &(rtlps->p2p_ps_info);
1197 struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
1198 u8 i;
1199 u16 ctwindow;
1200 u32 start_time, tsf_low;
1201
1202 switch(p2p_ps_state)
1203 {
1204 case P2P_PS_DISABLE:
1205 RT_TRACE(COMP_FW, DBG_LOUD,("P2P_PS_DISABLE \n"));
1206 memset(p2p_ps_offload, 0, 1);
1207 break;
1208 case P2P_PS_ENABLE:
1209 RT_TRACE(COMP_FW, DBG_LOUD,("P2P_PS_ENABLE \n"));
1210 /* update CTWindow value. */
1211 if( p2pinfo->ctwindow > 0 )
1212 {
1213 p2p_ps_offload->CTWindow_En = 1;
1214 ctwindow = p2pinfo->ctwindow;
1215 rtl8821ae_set_p2p_ctw_period_cmd(hw, ctwindow);
1216 }
1217
1218 /* hw only support 2 set of NoA */
1219 for( i=0 ; i<p2pinfo->noa_num ; i++)
1220 {
1221 /* To control the register setting for which NOA*/
1222 rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
1223 if(i == 0)
1224 p2p_ps_offload->NoA0_En = 1;
1225 else
1226 p2p_ps_offload->NoA1_En = 1;
1227
1228 /* config P2P NoA Descriptor Register */
1229 rtl_write_dword(rtlpriv, 0x5E0, p2pinfo->noa_duration[i]);
1230 rtl_write_dword(rtlpriv, 0x5E4, p2pinfo->noa_interval[i]);
1231
1232 /*Get Current TSF value */
1233 tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1234
1235 start_time = p2pinfo->noa_start_time[i];
1236 if(p2pinfo->noa_count_type[i] != 1)
1237 {
1238 while( start_time <= (tsf_low+(50*1024) ) ) {
1239 start_time += p2pinfo->noa_interval[i];
1240 if(p2pinfo->noa_count_type[i] != 255)
1241 p2pinfo->noa_count_type[i]--;
1242 }
1243 }
1244 rtl_write_dword(rtlpriv, 0x5E8, start_time);
1245 rtl_write_dword(rtlpriv, 0x5EC, p2pinfo->noa_count_type[i] );
1246
1247 }
1248
1249 if( (p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0) )
1250 {
1251 /* rst p2p circuit */
1252 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
1253
1254 p2p_ps_offload->Offload_En = 1;
1255
1256 if(P2P_ROLE_GO == rtlpriv->mac80211.p2p)
1257 {
1258 p2p_ps_offload->role= 1;
1259 p2p_ps_offload->AllStaSleep = 0;
1260 }
1261 else
1262 {
1263 p2p_ps_offload->role= 0;
1264 }
1265
1266 p2p_ps_offload->discovery = 0;
1267 }
1268 break;
1269 case P2P_PS_SCAN:
1270 RT_TRACE(COMP_FW, DBG_LOUD,("P2P_PS_SCAN \n"));
1271 p2p_ps_offload->discovery = 1;
1272 break;
1273 case P2P_PS_SCAN_DONE:
1274 RT_TRACE(COMP_FW, DBG_LOUD,("P2P_PS_SCAN_DONE \n"));
1275 p2p_ps_offload->discovery = 0;
1276 p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
1277 break;
1278 default:
1279 break;
1280 }
1281
1282 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload);
1283
1284}
1285
1286void rtl8812ae_c2h_ra_report_handler(
1287 struct ieee80211_hw *hw,
1288 u8 *cmd_buf,
1289 u8 cmd_len
1290)
1291{
1292 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1293 u8 rate = cmd_buf[0] & 0x3F;
1294
1295 rtlhal->current_ra_rate= rtl8812ae_hw_rate_to_mrate(hw, rate);
1296
1297 rtl8812ae_dm_update_init_rate(hw, rate);
1298}
1299
1300
1301void _rtl8812ae_c2h_content_parsing(
1302 struct ieee80211_hw *hw,
1303 u8 c2h_cmd_id,
1304 u8 c2h_cmd_len,
1305 u8 *tmp_buf
1306)
1307{
1308 struct rtl_priv *rtlpriv = rtl_priv(hw);
1309
1310 switch (c2h_cmd_id) {
1311 case C2H_8812_DBG:
1312 RT_TRACE(COMP_FW, DBG_LOUD,("[C2H], C2H_8812_DBG!!\n"));
1313 break;
1314
1315 case C2H_8812_RA_RPT:
1316 rtl8812ae_c2h_ra_report_handler(hw, tmp_buf, c2h_cmd_len);
1317 break;
1318
1319 default:
1320 break;
1321 }
1322
1323}
1324
1325void rtl8812ae_c2h_packet_handler(
1326 struct ieee80211_hw *hw,
1327 u8 *buffer,
1328 u8 length
1329 )
1330{
1331 struct rtl_priv *rtlpriv = rtl_priv(hw);
1332 u8 c2h_cmd_id=0, c2h_cmd_seq=0, c2h_cmd_len=0;
1333 u8 *tmp_buf=NULL;
1334
1335 c2h_cmd_id = buffer[0];
1336 c2h_cmd_seq = buffer[1];
1337 c2h_cmd_len = length -2;
1338 tmp_buf = buffer + 2;
1339
1340 RT_TRACE(COMP_FW, DBG_LOUD,
1341 ("[C2H packet], c2hCmdId=0x%x, c2hCmdSeq=0x%x, c2hCmdLen=%d\n",
1342 c2h_cmd_id, c2h_cmd_seq, c2h_cmd_len));
1343
1344 RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_LOUD,
1345 "[C2H packet], Content Hex:\n", tmp_buf, c2h_cmd_len);
1346 _rtl8812ae_c2h_content_parsing(hw, c2h_cmd_id, c2h_cmd_len, tmp_buf);
1347}
1348
1349
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/fw.h b/drivers/staging/rtl8821ae/rtl8821ae/fw.h
new file mode 100644
index 000000000000..30eec880026c
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/fw.h
@@ -0,0 +1,321 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 * Larry Finger <Larry.Finger@lwfinger.net>
26 *
27 *****************************************************************************/
28
29#ifndef __RTL8821AE__FW__H__
30#define __RTL8821AE__FW__H__
31
32#define FW_8821AE_SIZE 0x8000
33#define FW_8821AE_START_ADDRESS 0x1000
34#define FW_8821AE_END_ADDRESS 0x5FFF
35#define FW_8821AE_PAGE_SIZE 4096
36#define FW_8821AE_POLLING_DELAY 5
37#define FW_8821AE_POLLING_TIMEOUT_COUNT 6000
38
39#define IS_FW_HEADER_EXIST_8812(_pfwhdr) \
40 ((_pfwhdr->signature&0xFFF0) == 0x9500 )
41
42#define IS_FW_HEADER_EXIST_8821(_pfwhdr) \
43 ((_pfwhdr->signature&0xFFF0) == 0x2100 )
44
45#define USE_OLD_WOWLAN_DEBUG_FW 0
46
47#define H2C_8821AE_RSVDPAGE_LOC_LEN 5
48#define H2C_8821AE_PWEMODE_LENGTH 5
49#define H2C_8821AE_JOINBSSRPT_LENGTH 1
50#define H2C_8821AE_AP_OFFLOAD_LENGTH 3
51#define H2C_8821AE_WOWLAN_LENGTH 3
52#define H2C_8821AE_KEEP_ALIVE_CTRL_LENGTH 3
53#if(USE_OLD_WOWLAN_DEBUG_FW == 0)
54#define H2C_8821AE_REMOTE_WAKE_CTRL_LEN 1
55#else
56#define H2C_8821AE_REMOTE_WAKE_CTRL_LEN 3
57#endif
58#define H2C_8821AE_AOAC_GLOBAL_INFO_LEN 2
59#define H2C_8821AE_AOAC_RSVDPAGE_LOC_LEN 7
60
61
62/* Fw PS state for RPWM.
63*BIT[2:0] = HW state
64*BIT[3] = Protocol PS state, 1: register active state , 0: register sleep state
65*BIT[4] = sub-state
66*/
67#define FW_PS_GO_ON BIT(0)
68#define FW_PS_TX_NULL BIT(1)
69#define FW_PS_RF_ON BIT(2)
70#define FW_PS_REGISTER_ACTIVE BIT(3)
71
72#define FW_PS_DPS BIT(0)
73#define FW_PS_LCLK (FW_PS_DPS)
74#define FW_PS_RF_OFF BIT(1)
75#define FW_PS_ALL_ON BIT(2)
76#define FW_PS_ST_ACTIVE BIT(3)
77#define FW_PS_ISR_ENABLE BIT(4)
78#define FW_PS_IMR_ENABLE BIT(5)
79
80
81#define FW_PS_ACK BIT(6)
82#define FW_PS_TOGGLE BIT(7)
83
84 /* 8821AE RPWM value*/
85 /* BIT[0] = 1: 32k, 0: 40M*/
86#define FW_PS_CLOCK_OFF BIT(0) /* 32k*/
87#define FW_PS_CLOCK_ON 0 /*40M*/
88
89#define FW_PS_STATE_MASK (0x0F)
90#define FW_PS_STATE_HW_MASK (0x07)
91#define FW_PS_STATE_INT_MASK (0x3F) /*ISR_ENABLE, IMR_ENABLE, and PS mode should be inherited.*/
92
93#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x))
94#define FW_PS_STATE_HW(x) (FW_PS_STATE_HW_MASK & (x))
95#define FW_PS_STATE_INT(x) (FW_PS_STATE_INT_MASK & (x))
96#define FW_PS_ISR_VAL(x) ((x) & 0x70)
97#define FW_PS_IMR_MASK(x) ((x) & 0xDF)
98#define FW_PS_KEEP_IMR(x) ((x) & 0x20)
99
100
101#define FW_PS_STATE_S0 (FW_PS_DPS)
102#define FW_PS_STATE_S1 (FW_PS_LCLK)
103#define FW_PS_STATE_S2 (FW_PS_RF_OFF)
104#define FW_PS_STATE_S3 (FW_PS_ALL_ON)
105#define FW_PS_STATE_S4 ((FW_PS_ST_ACTIVE) | (FW_PS_ALL_ON))
106
107#define FW_PS_STATE_ALL_ON_8821AE (FW_PS_CLOCK_ON) /* ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))*/
108#define FW_PS_STATE_RF_ON_8821AE (FW_PS_CLOCK_ON) /* (FW_PS_RF_ON)*/
109#define FW_PS_STATE_RF_OFF_8821AE (FW_PS_CLOCK_ON) /* 0x0*/
110#define FW_PS_STATE_RF_OFF_LOW_PWR_8821AE (FW_PS_CLOCK_OFF) /* (FW_PS_STATE_RF_OFF)*/
111
112#define FW_PS_STATE_ALL_ON_92C (FW_PS_STATE_S4)
113#define FW_PS_STATE_RF_ON_92C (FW_PS_STATE_S3)
114#define FW_PS_STATE_RF_OFF_92C (FW_PS_STATE_S2)
115#define FW_PS_STATE_RF_OFF_LOW_PWR_92C (FW_PS_STATE_S1)
116
117
118/* For 8821AE H2C PwrMode Cmd ID 5.*/
119#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
120#define FW_PWR_STATE_RF_OFF 0
121
122#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK )
123#define FW_PS_IS_CLK_ON(x) ((x) & (FW_PS_RF_OFF |FW_PS_ALL_ON ))
124#define FW_PS_IS_RF_ON(x) ((x) & (FW_PS_ALL_ON))
125#define FW_PS_IS_ACTIVE(x) ((x) & (FW_PS_ST_ACTIVE))
126#define FW_PS_IS_CPWM_INT(x) ((x) & 0x40)
127
128#define FW_CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
129
130#define IS_IN_LOW_POWER_STATE_8821AE(FwPSState) \
131 (FW_PS_STATE(FwPSState) == FW_PS_CLOCK_OFF)
132
133#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
134#define FW_PWR_STATE_RF_OFF 0
135
136struct rtl8821a_firmware_header {
137 u16 signature;
138 u8 category;
139 u8 function;
140 u16 version;
141 u8 subversion;
142 u8 rsvd1;
143 u8 month;
144 u8 date;
145 u8 hour;
146 u8 minute;
147 u16 ramcodeSize;
148 u16 rsvd2;
149 u32 svnindex;
150 u32 rsvd3;
151 u32 rsvd4;
152 u32 rsvd5;
153};
154
155enum rtl8812_c2h_evt{
156 C2H_8812_DBG = 0,
157 C2H_8812_LB = 1,
158 C2H_8812_TXBF = 2,
159 C2H_8812_TX_REPORT = 3,
160 C2H_8812_BT_INFO = 9,
161 C2H_8812_BT_MP = 11,
162 C2H_8812_RA_RPT=12,
163
164 C2H_8812_FW_SWCHNL = 0x10,
165 C2H_8812_IQK_FINISH = 0x11,
166 MAX_8812_C2HEVENT
167};
168
169enum rtl8821a_h2c_cmd {
170 H2C_8821AE_RSVDPAGE = 0,
171 H2C_8821AE_JOINBSSRPT = 1,
172 H2C_8821AE_SCAN = 2,
173 H2C_8821AE_KEEP_ALIVE_CTRL = 3,
174 H2C_8821AE_DISCONNECT_DECISION = 4,
175#if(USE_OLD_WOWLAN_DEBUG_FW == 1)
176 H2C_8821AE_WO_WLAN = 5,
177#endif
178 H2C_8821AE_INIT_OFFLOAD = 6,
179#if(USE_OLD_WOWLAN_DEBUG_FW == 1)
180 H2C_8821AE_REMOTE_WAKE_CTRL = 7,
181#endif
182 H2C_8821AE_AP_OFFLOAD = 8,
183 H2C_8821AE_BCN_RSVDPAGE = 9,
184 H2C_8821AE_PROBERSP_RSVDPAGE = 10,
185
186 H2C_8821AE_SETPWRMODE = 0x20,
187 H2C_8821AE_PS_TUNING_PARA = 0x21,
188 H2C_8821AE_PS_TUNING_PARA2 = 0x22,
189 H2C_8821AE_PS_LPS_PARA = 0x23,
190 H2C_8821AE_P2P_PS_OFFLOAD = 024,
191
192#if(USE_OLD_WOWLAN_DEBUG_FW == 0)
193 H2C_8821AE_WO_WLAN = 0x80,
194 H2C_8821AE_REMOTE_WAKE_CTRL = 0x81,
195 H2C_8821AE_AOAC_GLOBAL_INFO = 0x82,
196 H2C_8821AE_AOAC_RSVDPAGE = 0x83,
197#endif
198 H2C_RSSI_REPORT = 0x42,
199 H2C_8821AE_RA_MASK = 0x40,
200 H2C_8821AE_SELECTIVE_SUSPEND_ROF_CMD,
201 H2C_8821AE_P2P_PS_MODE,
202 H2C_8821AE_PSD_RESULT,
203 /*Not defined CTW CMD for P2P yet*/
204 H2C_8821AE_P2P_PS_CTW_CMD,
205 MAX_8821AE_H2CCMD
206};
207
208#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1:0))
209
210#define SET_8821AE_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) \
211 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
212#define SET_8821AE_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) \
213 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
214#define SET_8821AE_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) \
215 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
216#define SET_8821AE_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) \
217 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
218#define SET_8821AE_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) \
219 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
220#define SET_8821AE_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) \
221 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
222#define SET_8821AE_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) \
223 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
224#define SET_8821AE_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) \
225 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
226#define SET_8821AE_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) \
227 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
228#define SET_8821AE_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) \
229 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
230
231
232#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
233 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
234#define SET_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) \
235 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
236#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) \
237 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
238#define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__pH2CCmd, __Value) \
239 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
240#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) \
241 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
242#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) \
243 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
244#define GET_8821AE_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) \
245 LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
246
247#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
248 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
249#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
250 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
251#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
252 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
253#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
254 SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
255
256/* AP_OFFLOAD */
257#define SET_H2CCMD_AP_OFFLOAD_ON(__pH2CCmd, __Value) \
258 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
259#define SET_H2CCMD_AP_OFFLOAD_HIDDEN(__pH2CCmd, __Value) \
260 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
261#define SET_H2CCMD_AP_OFFLOAD_DENYANY(__pH2CCmd, __Value) \
262 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
263#define SET_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__pH2CCmd, __Value) \
264 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
265
266/* Keep Alive Control*/
267#define SET_8821AE_H2CCMD_KEEP_ALIVE_ENABLE(__pH2CCmd, __Value) \
268 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
269#define SET_8821AE_H2CCMD_KEEP_ALIVE_ACCPEPT_USER_DEFINED(__pH2CCmd, __Value) \
270 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
271#define SET_8821AE_H2CCMD_KEEP_ALIVE_PERIOD(__pH2CCmd, __Value) \
272 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
273
274/*REMOTE_WAKE_CTRL */
275#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_EN(__pH2CCmd, __Value) \
276 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
277#if(USE_OLD_WOWLAN_DEBUG_FW == 0)
278#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) \
279 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
280#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) \
281 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
282#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) \
283 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
284#else
285#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) \
286 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
287#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_GROUP_ENC_ALG(__pH2CCmd, __Value) \
288 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
289#endif
290
291/* GTK_OFFLOAD */
292#define SET_8821AE_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) \
293 SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
294#define SET_8821AE_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) \
295 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
296
297/* AOAC_RSVDPAGE_LOC */
298#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) \
299 SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
300#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) \
301 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
302#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) \
303 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
304#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) \
305 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
306#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) \
307 SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
308
309int rtl8821ae_download_fw(struct ieee80211_hw *hw,
310 bool buse_wake_on_wlan_fw);
311void rtl8821ae_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
312 u32 cmd_len, u8 *p_cmdbuffer);
313void rtl8821ae_firmware_selfreset(struct ieee80211_hw *hw);
314void rtl8821ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
315void rtl8821ae_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
316void rtl8821ae_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw, u8 ap_offload_enable);
317void rtl8821ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
318void rtl8812ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
319void rtl8821ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
320void rtl8812ae_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 length);
321#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/hal_bt_coexist.c b/drivers/staging/rtl8821ae/rtl8821ae/hal_bt_coexist.c
new file mode 100644
index 000000000000..8bee772d766f
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/hal_bt_coexist.c
@@ -0,0 +1,519 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "hal_bt_coexist.h"
31#include "../pci.h"
32#include "dm.h"
33#include "fw.h"
34#include "phy.h"
35#include "reg.h"
36#include "hal_btc.h"
37
38static bool bt_operation_on = false;
39
40void rtl8821ae_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw, bool b_reject)
41{
42#if 0
43 struct rtl_priv rtlpriv = rtl_priv(hw);
44 PRX_TS_RECORD pRxTs = NULL;
45
46 if(b_reject){
47 // Do not allow receiving A-MPDU aggregation.
48 if (rtlpriv->mac80211.vendor == PEER_CISCO) {
49 if (pHTInfo->bAcceptAddbaReq) {
50 RTPRINT(FBT, BT_TRACE, ("BT_Disallow AMPDU \n"));
51 pHTInfo->bAcceptAddbaReq = FALSE;
52 if(GetTs(Adapter, (PTS_COMMON_INFO*)(&pRxTs), pMgntInfo->Bssid, 0, RX_DIR, FALSE))
53 TsInitDelBA(Adapter, (PTS_COMMON_INFO)pRxTs, RX_DIR);
54 }
55 } else {
56 if (!pHTInfo->bAcceptAddbaReq) {
57 RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU BT Idle\n"));
58 pHTInfo->bAcceptAddbaReq = TRUE;
59 }
60 }
61 } else {
62 if(rtlpriv->mac80211.vendor == PEER_CISCO) {
63 if (!pHTInfo->bAcceptAddbaReq) {
64 RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU \n"));
65 pHTInfo->bAcceptAddbaReq = TRUE;
66 }
67 }
68 }
69#endif
70}
71
72void _rtl8821ae_dm_bt_check_wifi_state(struct ieee80211_hw *hw)
73{
74struct rtl_priv *rtlpriv = rtl_priv(hw);
75struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
76struct rtl_phy *rtlphy = &(rtlpriv->phy);
77
78if (rtlpriv->link_info.b_busytraffic) {
79 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_IDLE;
80
81 if(rtlpriv->link_info.b_tx_busy_traffic) {
82 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_UPLINK;
83 } else {
84 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_UPLINK;
85 }
86
87 if(rtlpriv->link_info.b_rx_busy_traffic) {
88 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_DOWNLINK;
89 } else {
90 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_DOWNLINK;
91 }
92} else {
93 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_IDLE;
94 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_UPLINK;
95 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_DOWNLINK;
96}
97
98if (rtlpriv->mac80211.mode == WIRELESS_MODE_G
99 || rtlpriv->mac80211.mode == WIRELESS_MODE_B) {
100 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_LEGACY;
101 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_HT20;
102 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_HT40;
103} else {
104 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_LEGACY;
105 if(rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
106 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_HT40;
107 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_HT20;
108 } else {
109 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_HT20;
110 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_HT40;
111 }
112}
113
114if (bt_operation_on) {
115 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_BT30;
116} else {
117 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_BT30;
118}
119}
120
121
122u8 rtl8821ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
123 u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
124
125{
126 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
127 struct rtl_priv *rtlpriv = rtl_priv(hw);
128 long undecoratedsmoothed_pwdb = 0;
129 u8 bt_rssi_state = 0;
130
131 undecoratedsmoothed_pwdb = rtl8821ae_dm_bt_get_rx_ss(hw);
132
133 if(level_num == 2) {
134 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
135
136 if( (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_LOW) ||
137 (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_LOW)) {
138 if(undecoratedsmoothed_pwdb >= (rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
139 bt_rssi_state = BT_RSSI_STATE_HIGH;
140 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_HIGH;
141 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
142 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state switch to High\n"));
143 } else {
144 bt_rssi_state = BT_RSSI_STATE_STAY_LOW;
145 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state stay at Low\n"));
146 }
147 } else {
148 if(undecoratedsmoothed_pwdb < rssi_thresh) {
149 bt_rssi_state = BT_RSSI_STATE_LOW;
150 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_LOW;
151 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
152 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state switch to Low\n"));
153 } else {
154 bt_rssi_state = BT_RSSI_STATE_STAY_HIGH;
155 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state stay at High\n"));
156 }
157 }
158 } else if(level_num == 3) {
159 if(rssi_thresh > rssi_thresh1) {
160 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 thresh error!!\n"));
161 return rtlpcipriv->btcoexist.bt_pre_rssi_state;
162 }
163
164 if( (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_LOW) ||
165 (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_LOW)) {
166 if(undecoratedsmoothed_pwdb >= (rssi_thresh+BT_FW_COEX_THRESH_TOL)) {
167 bt_rssi_state = BT_RSSI_STATE_MEDIUM;
168 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
169 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
170 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
171 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state switch to Medium\n"));
172 } else {
173 bt_rssi_state = BT_RSSI_STATE_STAY_LOW;
174 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state stay at Low\n"));
175 }
176 } else if( (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_MEDIUM) ||
177 (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_MEDIUM)) {
178 if(undecoratedsmoothed_pwdb >= (rssi_thresh1 + BT_FW_COEX_THRESH_TOL)) {
179 bt_rssi_state = BT_RSSI_STATE_HIGH;
180 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_HIGH;
181 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
182 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
183 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state switch to High\n"));
184 } else if(undecoratedsmoothed_pwdb < rssi_thresh) {
185 bt_rssi_state = BT_RSSI_STATE_LOW;
186 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_LOW;
187 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
188 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
189 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state switch to Low\n"));
190 } else {
191 bt_rssi_state = BT_RSSI_STATE_STAY_MEDIUM;
192 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state stay at Medium\n"));
193 }
194 } else {
195 if(undecoratedsmoothed_pwdb < rssi_thresh1) {
196 bt_rssi_state = BT_RSSI_STATE_MEDIUM;
197 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
198 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
199 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
200 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,("[DM][BT], RSSI_1 state switch to Medium\n"));
201 } else {
202 bt_rssi_state = BT_RSSI_STATE_STAY_HIGH;
203 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state stay at High\n"));
204 }
205 }
206 }
207
208 rtlpcipriv->btcoexist.bt_pre_rssi_state1 = bt_rssi_state;
209
210 return bt_rssi_state;
211}
212
213u8 rtl8821ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
214 u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
215{
216 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
217 struct rtl_priv *rtlpriv = rtl_priv(hw);
218 long undecoratedsmoothed_pwdb = 0;
219 u8 bt_rssi_state = 0;
220
221 undecoratedsmoothed_pwdb = rtl8821ae_dm_bt_get_rx_ss(hw);
222
223 if (level_num == 2) {
224 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
225
226 if ((rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_LOW) ||
227 (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_LOW)){
228 if (undecoratedsmoothed_pwdb
229 >= (rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
230 bt_rssi_state = BT_RSSI_STATE_HIGH;
231 rtlpcipriv->btcoexist.current_state
232 |= BT_COEX_STATE_WIFI_RSSI_HIGH;
233 rtlpcipriv->btcoexist.current_state
234 &= ~BT_COEX_STATE_WIFI_RSSI_LOW;
235 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
236 ("[DM][BT], RSSI state switch to High\n"));
237 } else {
238 bt_rssi_state = BT_RSSI_STATE_STAY_LOW;
239 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
240 ("[DM][BT], RSSI state stay at Low\n"));
241 }
242 } else {
243 if (undecoratedsmoothed_pwdb < rssi_thresh) {
244 bt_rssi_state = BT_RSSI_STATE_LOW;
245 rtlpcipriv->btcoexist.current_state
246 |= BT_COEX_STATE_WIFI_RSSI_LOW;
247 rtlpcipriv->btcoexist.current_state
248 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
249 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
250 ("[DM][BT], RSSI state switch to Low\n"));
251 } else {
252 bt_rssi_state = BT_RSSI_STATE_STAY_HIGH;
253 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
254 ("[DM][BT], RSSI state stay at High\n"));
255 }
256 }
257 }
258 else if (level_num == 3) {
259 if (rssi_thresh > rssi_thresh1) {
260 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
261 ("[DM][BT], RSSI thresh error!!\n"));
262 return rtlpcipriv->btcoexist.bt_pre_rssi_state;
263 }
264 if ((rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_LOW) ||
265 (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_LOW)) {
266 if(undecoratedsmoothed_pwdb
267 >= (rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
268 bt_rssi_state = BT_RSSI_STATE_MEDIUM;
269 rtlpcipriv->btcoexist.current_state
270 |= BT_COEX_STATE_WIFI_RSSI_MEDIUM;
271 rtlpcipriv->btcoexist.current_state
272 &= ~BT_COEX_STATE_WIFI_RSSI_LOW;
273 rtlpcipriv->btcoexist.current_state
274 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
275 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
276 ("[DM][BT], RSSI state switch to Medium\n"));
277 } else {
278 bt_rssi_state = BT_RSSI_STATE_STAY_LOW;
279 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
280 ("[DM][BT], RSSI state stay at Low\n"));
281 }
282 } else if ((rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_MEDIUM) ||
283 (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_MEDIUM)) {
284 if (undecoratedsmoothed_pwdb
285 >= (rssi_thresh1 + BT_FW_COEX_THRESH_TOL)) {
286 bt_rssi_state = BT_RSSI_STATE_HIGH;
287 rtlpcipriv->btcoexist.current_state
288 |= BT_COEX_STATE_WIFI_RSSI_HIGH;
289 rtlpcipriv->btcoexist.current_state
290 &= ~BT_COEX_STATE_WIFI_RSSI_LOW;
291 rtlpcipriv->btcoexist.current_state
292 &= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
293 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
294 ("[DM][BT], RSSI state switch to High\n"));
295 } else if(undecoratedsmoothed_pwdb < rssi_thresh)
296 {
297 bt_rssi_state = BT_RSSI_STATE_LOW;
298 rtlpcipriv->btcoexist.current_state
299 |= BT_COEX_STATE_WIFI_RSSI_LOW;
300 rtlpcipriv->btcoexist.current_state
301 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
302 rtlpcipriv->btcoexist.current_state
303 &= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
304 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
305 ("[DM][BT], RSSI state switch to Low\n"));
306 } else {
307 bt_rssi_state = BT_RSSI_STATE_STAY_MEDIUM;
308 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
309 ("[DM][BT], RSSI state stay at Medium\n"));
310 }
311 } else {
312 if(undecoratedsmoothed_pwdb < rssi_thresh1) {
313 bt_rssi_state = BT_RSSI_STATE_MEDIUM;
314 rtlpcipriv->btcoexist.current_state
315 |= BT_COEX_STATE_WIFI_RSSI_MEDIUM;
316 rtlpcipriv->btcoexist.current_state
317 &= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
318 rtlpcipriv->btcoexist.current_state
319 &= ~BT_COEX_STATE_WIFI_RSSI_LOW;
320 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
321 ("[DM][BT], RSSI state switch to Medium\n"));
322 } else {
323 bt_rssi_state = BT_RSSI_STATE_STAY_HIGH;
324 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
325 ("[DM][BT], RSSI state stay at High\n"));
326 }
327 }
328 }
329
330 rtlpcipriv->btcoexist.bt_pre_rssi_state = bt_rssi_state;
331 return bt_rssi_state;
332}
333long rtl8821ae_dm_bt_get_rx_ss(struct ieee80211_hw *hw)
334{
335 struct rtl_priv *rtlpriv = rtl_priv(hw);
336 long undecoratedsmoothed_pwdb = 0;
337
338 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
339 undecoratedsmoothed_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
340 } else {
341 undecoratedsmoothed_pwdb
342 = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
343 }
344 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
345 ("rtl8821ae_dm_bt_get_rx_ss() = %ld\n", undecoratedsmoothed_pwdb));
346
347 return undecoratedsmoothed_pwdb;
348}
349
350void rtl8821ae_dm_bt_balance(struct ieee80211_hw *hw,
351 bool b_balance_on, u8 ms0, u8 ms1)
352{
353 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
354 struct rtl_priv *rtlpriv = rtl_priv(hw);
355 u8 h2c_parameter[3] ={0};
356
357 if (b_balance_on) {
358 h2c_parameter[2] = 1;
359 h2c_parameter[1] = ms1;
360 h2c_parameter[0] = ms0;
361 rtlpcipriv->btcoexist.b_fw_coexist_all_off = false;
362 } else {
363 h2c_parameter[2] = 0;
364 h2c_parameter[1] = 0;
365 h2c_parameter[0] = 0;
366 }
367 rtlpcipriv->btcoexist.b_balance_on = b_balance_on;
368
369 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
370 ("[DM][BT], Balance=[%s:%dms:%dms], write 0xc=0x%x\n",
371 b_balance_on?"ON":"OFF", ms0, ms1,
372 h2c_parameter[0]<<16 | h2c_parameter[1]<<8 | h2c_parameter[2]));
373
374 rtl8821ae_fill_h2c_cmd(hw, 0xc, 3, h2c_parameter);
375}
376
377
378void rtl8821ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type)
379{
380 struct rtl_priv *rtlpriv = rtl_priv(hw);
381 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
382
383 if (type == BT_AGCTABLE_OFF) {
384 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BT]AGCTable Off!\n"));
385 rtl_write_dword(rtlpriv, 0xc78,0x641c0001);
386 rtl_write_dword(rtlpriv, 0xc78,0x631d0001);
387 rtl_write_dword(rtlpriv, 0xc78,0x621e0001);
388 rtl_write_dword(rtlpriv, 0xc78,0x611f0001);
389 rtl_write_dword(rtlpriv, 0xc78,0x60200001);
390
391 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
392 RF_RX_AGC_HP, 0xfffff, 0x32000);
393 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
394 RF_RX_AGC_HP, 0xfffff, 0x71000);
395 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
396 RF_RX_AGC_HP, 0xfffff, 0xb0000);
397 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
398 RF_RX_AGC_HP, 0xfffff, 0xfc000);
399 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
400 RF_RX_G1, 0xfffff, 0x30355);
401 } else if (type == BT_AGCTABLE_ON) {
402 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BT]AGCTable On!\n"));
403 rtl_write_dword(rtlpriv, 0xc78,0x4e1c0001);
404 rtl_write_dword(rtlpriv, 0xc78,0x4d1d0001);
405 rtl_write_dword(rtlpriv, 0xc78,0x4c1e0001);
406 rtl_write_dword(rtlpriv, 0xc78,0x4b1f0001);
407 rtl_write_dword(rtlpriv, 0xc78,0x4a200001);
408
409 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
410 RF_RX_AGC_HP, 0xfffff, 0xdc000);
411 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
412 RF_RX_AGC_HP, 0xfffff, 0x90000);
413 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
414 RF_RX_AGC_HP, 0xfffff, 0x51000);
415 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
416 RF_RX_AGC_HP, 0xfffff, 0x12000);
417 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
418 RF_RX_G1, 0xfffff, 0x00355);
419
420 rtlpcipriv->btcoexist.b_sw_coexist_all_off = false;
421 }
422}
423
424void rtl8821ae_dm_bt_bb_back_off_level(struct ieee80211_hw *hw, u8 type)
425{
426 struct rtl_priv *rtlpriv = rtl_priv(hw);
427 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
428
429 if (type == BT_BB_BACKOFF_OFF) {
430 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BT]BBBackOffLevel Off!\n"));
431 rtl_write_dword(rtlpriv, 0xc04,0x3a05611);
432 } else if (type == BT_BB_BACKOFF_ON) {
433 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BT]BBBackOffLevel On!\n"));
434 rtl_write_dword(rtlpriv, 0xc04,0x3a07611);
435 rtlpcipriv->btcoexist.b_sw_coexist_all_off = false;
436 }
437}
438
439void rtl8821ae_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw)
440{
441 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
442 struct rtl_priv *rtlpriv = rtl_priv(hw);
443 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
444 ("rtl8821ae_dm_bt_fw_coex_all_off()\n"));
445
446 if(rtlpcipriv->btcoexist.b_fw_coexist_all_off)
447 return;
448
449 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
450 ("rtl8821ae_dm_bt_fw_coex_all_off(), real Do\n"));
451 rtl8821ae_dm_bt_fw_coex_all_off_8723a(hw);
452 rtlpcipriv->btcoexist.b_fw_coexist_all_off = true;
453}
454
455void rtl8821ae_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw)
456{
457 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
458 struct rtl_priv *rtlpriv = rtl_priv(hw);
459
460 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
461 ("rtl8821ae_dm_bt_sw_coex_all_off()\n"));
462
463 if(rtlpcipriv->btcoexist.b_sw_coexist_all_off)
464 return;
465
466 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
467 ("rtl8821ae_dm_bt_sw_coex_all_off(), real Do\n"));
468 rtl8821ae_dm_bt_sw_coex_all_off_8723a(hw);
469 rtlpcipriv->btcoexist.b_sw_coexist_all_off = true;
470}
471
472void rtl8821ae_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw)
473{
474 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
475 struct rtl_priv *rtlpriv = rtl_priv(hw);
476
477 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
478 ("rtl8821ae_dm_bt_hw_coex_all_off()\n"));
479
480 if(rtlpcipriv->btcoexist.b_hw_coexist_all_off)
481 return;
482 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
483 ("rtl8821ae_dm_bt_hw_coex_all_off(), real Do\n"));
484
485 rtl8821ae_dm_bt_hw_coex_all_off_8723a(hw);
486
487 rtlpcipriv->btcoexist.b_hw_coexist_all_off = true;
488}
489
490void rtl8821ae_btdm_coex_all_off(struct ieee80211_hw *hw)
491{
492 rtl8821ae_dm_bt_fw_coex_all_off(hw);
493 rtl8821ae_dm_bt_sw_coex_all_off(hw);
494 rtl8821ae_dm_bt_hw_coex_all_off(hw);
495}
496
497bool rtl8821ae_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw)
498{
499 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
500
501 if((rtlpcipriv->btcoexist.previous_state
502 == rtlpcipriv->btcoexist.current_state)
503 && (rtlpcipriv->btcoexist.previous_state_h
504 == rtlpcipriv->btcoexist.current_state_h))
505 return false;
506 else
507 return true;
508}
509
510bool rtl8821ae_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw)
511{
512 struct rtl_priv *rtlpriv = rtl_priv(hw);
513
514 if (rtlpriv->link_info.b_tx_busy_traffic)
515 return true;
516 else
517 return false;
518}
519
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/hal_bt_coexist.h b/drivers/staging/rtl8821ae/rtl8821ae/hal_bt_coexist.h
new file mode 100644
index 000000000000..799cc6f95cc1
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/hal_bt_coexist.h
@@ -0,0 +1,169 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 * Larry Finger <Larry.Finger@lwfinger.net>
26 *
27 *****************************************************************************/
28
29#ifndef __RTL8821AE_HAL_BT_COEXIST_H__
30#define __RTL8821AE_HAL_BT_COEXIST_H__
31
32#include "../wifi.h"
33
34/* The reg define is for 8723 */
35#define REG_HIGH_PRIORITY_TXRX 0x770
36#define REG_LOW_PRIORITY_TXRX 0x774
37
38#define BT_FW_COEX_THRESH_TOL 6
39#define BT_FW_COEX_THRESH_20 20
40#define BT_FW_COEX_THRESH_23 23
41#define BT_FW_COEX_THRESH_25 25
42#define BT_FW_COEX_THRESH_30 30
43#define BT_FW_COEX_THRESH_35 35
44#define BT_FW_COEX_THRESH_40 40
45#define BT_FW_COEX_THRESH_45 45
46#define BT_FW_COEX_THRESH_47 47
47#define BT_FW_COEX_THRESH_50 50
48#define BT_FW_COEX_THRESH_55 55
49
50#define BT_COEX_STATE_BT30 BIT(0)
51#define BT_COEX_STATE_WIFI_HT20 BIT(1)
52#define BT_COEX_STATE_WIFI_HT40 BIT(2)
53#define BT_COEX_STATE_WIFI_LEGACY BIT(3)
54
55#define BT_COEX_STATE_WIFI_RSSI_LOW BIT(4)
56#define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5)
57#define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6)
58#define BT_COEX_STATE_DEC_BT_POWER BIT(7)
59
60#define BT_COEX_STATE_WIFI_IDLE BIT(8)
61#define BT_COEX_STATE_WIFI_UPLINK BIT(9)
62#define BT_COEX_STATE_WIFI_DOWNLINK BIT(10)
63
64#define BT_COEX_STATE_BT_INQ_PAGE BIT(11)
65#define BT_COEX_STATE_BT_IDLE BIT(12)
66#define BT_COEX_STATE_BT_UPLINK BIT(13)
67#define BT_COEX_STATE_BT_DOWNLINK BIT(14)
68
69#define BT_COEX_STATE_HOLD_FOR_BT_OPERATION BIT(15)
70#define BT_COEX_STATE_BT_RSSI_LOW BIT(19)
71
72#define BT_COEX_STATE_PROFILE_HID BIT(20)
73#define BT_COEX_STATE_PROFILE_A2DP BIT(21)
74#define BT_COEX_STATE_PROFILE_PAN BIT(22)
75#define BT_COEX_STATE_PROFILE_SCO BIT(23)
76
77#define BT_COEX_STATE_WIFI_RSSI_1_LOW BIT(24)
78#define BT_COEX_STATE_WIFI_RSSI_1_MEDIUM BIT(25)
79#define BT_COEX_STATE_WIFI_RSSI_1_HIGH BIT(26)
80
81#define BT_COEX_STATE_BTINFO_COMMON BIT(30)
82#define BT_COEX_STATE_BTINFO_B_HID_SCOESCO BIT(31)
83#define BT_COEX_STATE_BTINFO_B_FTP_A2DP BIT(29)
84
85#define BT_COEX_STATE_BT_CNT_LEVEL_0 BIT(0)
86#define BT_COEX_STATE_BT_CNT_LEVEL_1 BIT(1)
87#define BT_COEX_STATE_BT_CNT_LEVEL_2 BIT(2)
88#define BT_COEX_STATE_BT_CNT_LEVEL_3 BIT(3)
89
90#define BT_RSSI_STATE_HIGH 0
91#define BT_RSSI_STATE_MEDIUM 1
92#define BT_RSSI_STATE_LOW 2
93#define BT_RSSI_STATE_STAY_HIGH 3
94#define BT_RSSI_STATE_STAY_MEDIUM 4
95#define BT_RSSI_STATE_STAY_LOW 5
96
97#define BT_AGCTABLE_OFF 0
98#define BT_AGCTABLE_ON 1
99#define BT_BB_BACKOFF_OFF 0
100#define BT_BB_BACKOFF_ON 1
101#define BT_FW_NAV_OFF 0
102#define BT_FW_NAV_ON 1
103
104#define BT_COEX_MECH_NONE 0
105#define BT_COEX_MECH_SCO 1
106#define BT_COEX_MECH_HID 2
107#define BT_COEX_MECH_A2DP 3
108#define BT_COEX_MECH_PAN 4
109#define BT_COEX_MECH_HID_A2DP 5
110#define BT_COEX_MECH_HID_PAN 6
111#define BT_COEX_MECH_PAN_A2DP 7
112#define BT_COEX_MECH_HID_SCO_ESCO 8
113#define BT_COEX_MECH_FTP_A2DP 9
114#define BT_COEX_MECH_COMMON 10
115#define BT_COEX_MECH_MAX 11
116
117#define BT_DBG_PROFILE_NONE 0
118#define BT_DBG_PROFILE_SCO 1
119#define BT_DBG_PROFILE_HID 2
120#define BT_DBG_PROFILE_A2DP 3
121#define BT_DBG_PROFILE_PAN 4
122#define BT_DBG_PROFILE_HID_A2DP 5
123#define BT_DBG_PROFILE_HID_PAN 6
124#define BT_DBG_PROFILE_PAN_A2DP 7
125#define BT_DBG_PROFILE_MAX 9
126
127#define BTINFO_B_FTP BIT(7)
128#define BTINFO_B_A2DP BIT(6)
129#define BTINFO_B_HID BIT(5)
130#define BTINFO_B_SCO_BUSY BIT(4)
131#define BTINFO_B_ACL_BUSY BIT(3)
132#define BTINFO_B_INQ_PAGE BIT(2)
133#define BTINFO_B_SCO_ESCO BIT(1)
134#define BTINFO_B_CONNECTION BIT(0)
135
136
137void rtl8821ae_btdm_coex_all_off(struct ieee80211_hw *hw);
138void rtl8821ae_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw);
139
140void rtl8821ae_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw);
141void rtl8821ae_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw);
142long rtl8821ae_dm_bt_get_rx_ss(struct ieee80211_hw *hw);
143void rtl8821ae_dm_bt_balance(struct ieee80211_hw *hw,
144 bool b_balance_on, u8 ms0, u8 ms1);
145void rtl8821ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 tyep);
146void rtl8821ae_dm_bt_bb_back_off_level(struct ieee80211_hw *hw, u8 type);
147u8 rtl8821ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
148 u8 level_num, u8 rssi_thresh, u8 rssi_thresh1);
149u8 rtl8821ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
150 u8 level_num, u8 rssi_thresh, u8 rssi_thresh1);
151void _rtl8821ae_dm_bt_check_wifi_state(struct ieee80211_hw *hw);
152void rtl8821ae_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw,
153 bool b_reject);
154
155#if 0
156VOID
157BTDM_PWDBMonitor(
158 PADAPTER Adapter
159 );
160
161BOOLEAN
162BTDM_DIGByBTRSSI(
163 PADAPTER Adapter
164 );
165#endif
166bool rtl8821ae_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw);
167bool rtl8821ae_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw);
168#endif
169
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/hal_btc.c b/drivers/staging/rtl8821ae/rtl8821ae/hal_btc.c
new file mode 100644
index 000000000000..79386ee142f9
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/hal_btc.c
@@ -0,0 +1,2069 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29#include "hal_btc.h"
30#include "../pci.h"
31#include "phy.h"
32#include "fw.h"
33#include "reg.h"
34#include "def.h"
35#include "../btcoexist/rtl_btc.h"
36
37static struct bt_coexist_8821ae hal_coex_8821ae;
38
39void rtl8821ae_dm_bt_turn_off_bt_coexist_before_enter_lps(struct ieee80211_hw *hw)
40{
41 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
43 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
44
45 if(!rtlpcipriv->btcoexist.bt_coexistence)
46 return;
47
48 if(ppsc->b_inactiveps) {
49 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,("[BT][DM], Before enter IPS, turn off all Coexist DM\n"));
50 rtlpcipriv->btcoexist.current_state = 0;
51 rtlpcipriv->btcoexist.previous_state = 0;
52 rtlpcipriv->btcoexist.current_state_h = 0;
53 rtlpcipriv->btcoexist.previous_state_h = 0;
54 rtl8821ae_btdm_coex_all_off(hw);
55 }
56}
57
58
59enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw)
60{
61 struct rtl_priv *rtlpriv = rtl_priv(hw);
62 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
63 enum rt_media_status m_status = RT_MEDIA_DISCONNECT;
64
65 u8 bibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ? 1 : 0;
66
67 if(bibss || rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
68 m_status = RT_MEDIA_CONNECT;
69 }
70
71 return m_status;
72}
73
74void rtl_8821ae_bt_wifi_media_status_notify(struct ieee80211_hw *hw, bool mstatus)
75{
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
77 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
78 struct rtl_phy *rtlphy = &(rtlpriv->phy);
79 u8 h2c_parameter[3] ={0};
80 u8 chnl;
81
82 if(!rtlpcipriv->btcoexist.bt_coexistence)
83 return;
84
85 if(RT_MEDIA_CONNECT == mstatus)
86 h2c_parameter[0] = 0x1; // 0: disconnected, 1:connected
87 else
88 h2c_parameter[0] = 0x0;
89
90 if(mgnt_link_status_query(hw)) {
91 chnl = rtlphy->current_channel;
92 h2c_parameter[1] = chnl;
93 }
94
95 if(rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40){
96 h2c_parameter[2] = 0x30;
97 } else {
98 h2c_parameter[2] = 0x20;
99 }
100
101 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,("[BTCoex], FW write 0x19=0x%x\n",
102 h2c_parameter[0]<<16|h2c_parameter[1]<<8|h2c_parameter[2]));
103
104 rtl8821ae_fill_h2c_cmd(hw, 0x19, 3, h2c_parameter);
105
106}
107
108
109bool rtl8821ae_dm_bt_is_wifi_busy(struct ieee80211_hw *hw)
110{
111 struct rtl_priv *rtlpriv = rtl_priv(hw);
112 if(rtlpriv->link_info.b_busytraffic ||
113 rtlpriv->link_info.b_rx_busy_traffic ||
114 rtlpriv->link_info.b_tx_busy_traffic)
115 return true;
116 else
117 return false;
118}
119void rtl8821ae_dm_bt_set_fw_3a(struct ieee80211_hw *hw,
120 u8 byte1, u8 byte2, u8 byte3, u8 byte4, u8 byte5)
121{
122 struct rtl_priv *rtlpriv = rtl_priv(hw);
123 u8 h2c_parameter[5] ={0};
124 h2c_parameter[0] = byte1;
125 h2c_parameter[1] = byte2;
126 h2c_parameter[2] = byte3;
127 h2c_parameter[3] = byte4;
128 h2c_parameter[4] = byte5;
129 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], FW write 0x3a(4bytes)=0x%x%8x\n",
130 h2c_parameter[0], h2c_parameter[1]<<24 | h2c_parameter[2]<<16 | h2c_parameter[3]<<8 | h2c_parameter[4]));
131 rtl8821ae_fill_h2c_cmd(hw, 0x3a, 5, h2c_parameter);
132}
133
134bool rtl8821ae_dm_bt_need_to_dec_bt_pwr(struct ieee80211_hw *hw)
135{
136 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
137 struct rtl_priv *rtlpriv = rtl_priv(hw);
138
139 if (mgnt_link_status_query(hw) == RT_MEDIA_CONNECT) {
140 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Need to decrease bt power\n"));
141 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_DEC_BT_POWER;
142 return true;
143 }
144
145 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_DEC_BT_POWER;
146 return false;
147}
148
149
150bool rtl8821ae_dm_bt_is_same_coexist_state(struct ieee80211_hw *hw)
151{
152 struct rtl_priv *rtlpriv = rtl_priv(hw);
153 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
154
155 if ((rtlpcipriv->btcoexist.previous_state
156 == rtlpcipriv->btcoexist.current_state)
157 &&(rtlpcipriv->btcoexist.previous_state_h
158 == rtlpcipriv->btcoexist.current_state_h)) {
159 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
160 ("[DM][BT], Coexist state do not chang!!\n"));
161 return true;
162 } else {
163 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
164 ("[DM][BT], Coexist state changed!!\n"));
165 return false;
166 }
167}
168
169void rtl8821ae_dm_bt_set_coex_table(struct ieee80211_hw *hw,
170 u32 val_0x6c0, u32 val_0x6c8, u32 val_0x6cc)
171{
172 struct rtl_priv *rtlpriv = rtl_priv(hw);
173
174 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("set coex table, set 0x6c0=0x%x\n", val_0x6c0));
175 rtl_write_dword(rtlpriv, 0x6c0, val_0x6c0);
176
177 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("set coex table, set 0x6c8=0x%x\n", val_0x6c8));
178 rtl_write_dword(rtlpriv, 0x6c8, val_0x6c8);
179
180 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("set coex table, set 0x6cc=0x%x\n", val_0x6cc));
181 rtl_write_byte(rtlpriv, 0x6cc, val_0x6cc);
182}
183
184void rtl8821ae_dm_bt_set_hw_pta_mode(struct ieee80211_hw *hw, bool b_mode)
185{
186 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
187 struct rtl_priv *rtlpriv = rtl_priv(hw);
188
189 if (BT_PTA_MODE_ON == b_mode) {
190 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("PTA mode on, "));
191 /* Enable GPIO 0/1/2/3/8 pins for bt */
192 rtl_write_byte(rtlpriv, 0x40, 0x20);
193 rtlpcipriv->btcoexist.b_hw_coexist_all_off = false;
194 } else {
195 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("PTA mode off\n"));
196 rtl_write_byte(rtlpriv, 0x40, 0x0);
197 }
198}
199
200void rtl8821ae_dm_bt_set_sw_rf_rx_lpf_corner(struct ieee80211_hw *hw, u8 type)
201{
202 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
203 struct rtl_priv *rtlpriv = rtl_priv(hw);
204
205 if (BT_RF_RX_LPF_CORNER_SHRINK == type) {
206 /* Shrink RF Rx LPF corner, 0x1e[7:4]=1111 ==> [11:4] by Jenyu */
207 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Shrink RF Rx LPF corner!!\n"));
208 /* PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)PathA, 0x1e, 0xf0, 0xf); */
209 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A, 0x1e, 0xfffff, 0xf0ff7);
210 rtlpcipriv->btcoexist.b_sw_coexist_all_off = false;
211 } else if(BT_RF_RX_LPF_CORNER_RESUME == type) {
212 /*Resume RF Rx LPF corner*/
213 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Resume RF Rx LPF corner!!\n"));
214 /* PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)PathA, 0x1e, 0xf0,
215 * pHalData->btcoexist.BtRfRegOrigin1E); */
216 rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A, 0x1e, 0xfffff,
217 rtlpcipriv->btcoexist.bt_rfreg_origin_1e);
218 }
219}
220
221void rtl8821ae_dm_bt_set_sw_penalty_tx_rate_adaptive(struct ieee80211_hw *hw,
222 u8 ra_type)
223{
224 struct rtl_priv *rtlpriv = rtl_priv(hw);
225 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
226 u8 tmp_u1;
227
228 tmp_u1 = rtl_read_byte(rtlpriv, 0x4fd);
229 tmp_u1 |= BIT(0);
230 if (BT_TX_RATE_ADAPTIVE_LOW_PENALTY == ra_type) {
231 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Tx rate adaptive, set low penalty!!\n"));
232 tmp_u1 &= ~BIT(2);
233 rtlpcipriv->btcoexist.b_sw_coexist_all_off = false;
234 } else if(BT_TX_RATE_ADAPTIVE_NORMAL == ra_type) {
235 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Tx rate adaptive, set normal!!\n"));
236 tmp_u1 |= BIT(2);
237 }
238
239 rtl_write_byte(rtlpriv, 0x4fd, tmp_u1);
240}
241
242void rtl8821ae_dm_bt_btdm_structure_reload(struct ieee80211_hw *hw,
243 struct btdm_8821ae *p_btdm)
244{
245 p_btdm->b_all_off = false;
246 p_btdm->b_agc_table_en = false;
247 p_btdm->b_adc_back_off_on = false;
248 p_btdm->b2_ant_hid_en = false;
249 p_btdm->b_low_penalty_rate_adaptive = false;
250 p_btdm->b_rf_rx_lpf_shrink = false;
251 p_btdm->b_reject_aggre_pkt= false;
252
253 p_btdm->b_tdma_on = false;
254 p_btdm->tdma_ant = TDMA_2ANT;
255 p_btdm->tdma_nav = TDMA_NAV_OFF;
256 p_btdm->tdma_dac_swing = TDMA_DAC_SWING_OFF;
257 p_btdm->fw_dac_swing_lvl = 0x20;
258
259 p_btdm->b_tra_tdma_on = false;
260 p_btdm->tra_tdma_ant = TDMA_2ANT;
261 p_btdm->tra_tdma_nav = TDMA_NAV_OFF;
262 p_btdm->b_ignore_wlan_act = false;
263
264 p_btdm->b_ps_tdma_on = false;
265 p_btdm->ps_tdma_byte[0] = 0x0;
266 p_btdm->ps_tdma_byte[1] = 0x0;
267 p_btdm->ps_tdma_byte[2] = 0x0;
268 p_btdm->ps_tdma_byte[3] = 0x8;
269 p_btdm->ps_tdma_byte[4] = 0x0;
270
271 p_btdm->b_pta_on = true;
272 p_btdm->val_0x6c0 = 0x5a5aaaaa;
273 p_btdm->val_0x6c8 = 0xcc;
274 p_btdm->val_0x6cc = 0x3;
275
276 p_btdm->b_sw_dac_swing_on = false;
277 p_btdm->sw_dac_swing_lvl = 0xc0;
278 p_btdm->wlan_act_hi = 0x20;
279 p_btdm->wlan_act_lo = 0x10;
280 p_btdm->bt_retry_index = 2;
281
282 p_btdm->b_dec_bt_pwr = false;
283}
284
285void rtl8821ae_dm_bt_btdm_structure_reload_all_off(struct ieee80211_hw *hw,
286 struct btdm_8821ae *p_btdm)
287{
288 rtl8821ae_dm_bt_btdm_structure_reload(hw, p_btdm);
289 p_btdm->b_all_off = true;
290 p_btdm->b_pta_on = false;
291 p_btdm->wlan_act_hi = 0x10;
292}
293
294bool rtl8821ae_dm_bt_is_2_ant_common_action(struct ieee80211_hw *hw)
295{
296 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
297 struct rtl_priv *rtlpriv = rtl_priv(hw);
298 struct btdm_8821ae btdm8821ae;
299 bool b_common = false;
300
301 rtl8821ae_dm_bt_btdm_structure_reload(hw, &btdm8821ae);
302
303 if(!rtl8821ae_dm_bt_is_wifi_busy(hw)
304 && !rtlpcipriv->btcoexist.b_bt_busy) {
305 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
306 ("Wifi idle + Bt idle, bt coex mechanism always off!!\n"));
307 rtl8821ae_dm_bt_btdm_structure_reload_all_off(hw, &btdm8821ae);
308 b_common = true;
309 } else if (rtl8821ae_dm_bt_is_wifi_busy(hw)
310 && !rtlpcipriv->btcoexist.b_bt_busy) {
311 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
312 ("Wifi non-idle + Bt disabled/idle!!\n"));
313 btdm8821ae.b_low_penalty_rate_adaptive = true;
314 btdm8821ae.b_rf_rx_lpf_shrink = false;
315 btdm8821ae.b_reject_aggre_pkt = false;
316
317 /* sw mechanism */
318 btdm8821ae.b_agc_table_en = false;
319 btdm8821ae.b_adc_back_off_on = false;
320 btdm8821ae.b_sw_dac_swing_on = false;
321
322 btdm8821ae.b_pta_on = true;
323 btdm8821ae.val_0x6c0 = 0x5a5aaaaa;
324 btdm8821ae.val_0x6c8 = 0xcccc;
325 btdm8821ae.val_0x6cc = 0x3;
326
327 btdm8821ae.b_tdma_on = false;
328 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_OFF;
329 btdm8821ae.b2_ant_hid_en = false;
330
331 b_common = true;
332 }else if (rtlpcipriv->btcoexist.b_bt_busy) {
333 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
334 ("Bt non-idle!\n"));
335 if(mgnt_link_status_query(hw) == RT_MEDIA_CONNECT){
336 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi connection exist\n"))
337 b_common = false;
338 } else {
339 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
340 ("No Wifi connection!\n"));
341 btdm8821ae.b_rf_rx_lpf_shrink = true;
342 btdm8821ae.b_low_penalty_rate_adaptive = false;
343 btdm8821ae.b_reject_aggre_pkt = false;
344
345 /* sw mechanism */
346 btdm8821ae.b_agc_table_en = false;
347 btdm8821ae.b_adc_back_off_on = false;
348 btdm8821ae.b_sw_dac_swing_on = false;
349
350 btdm8821ae.b_pta_on = true;
351 btdm8821ae.val_0x6c0 = 0x55555555;
352 btdm8821ae.val_0x6c8 = 0x0000ffff;
353 btdm8821ae.val_0x6cc = 0x3;
354
355 btdm8821ae.b_tdma_on = false;
356 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_OFF;
357 btdm8821ae.b2_ant_hid_en = false;
358
359 b_common = true;
360 }
361 }
362
363 if (rtl8821ae_dm_bt_need_to_dec_bt_pwr(hw)) {
364 btdm8821ae.b_dec_bt_pwr = true;
365 }
366
367 if(b_common)
368 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_BTINFO_COMMON;
369
370 if (b_common && rtl8821ae_dm_bt_is_coexist_state_changed(hw))
371 rtl8821ae_dm_bt_set_bt_dm(hw, &btdm8821ae);
372
373 return b_common;
374}
375
376void rtl8821ae_dm_bt_set_sw_full_time_dac_swing(
377 struct ieee80211_hw * hw, bool b_sw_dac_swing_on, u32 sw_dac_swing_lvl)
378{
379 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
380 struct rtl_priv *rtlpriv = rtl_priv(hw);
381
382 if (b_sw_dac_swing_on) {
383 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
384 ("[BTCoex], SwDacSwing = 0x%x\n", sw_dac_swing_lvl));
385 rtl8821ae_phy_set_bb_reg(hw, 0x880, 0xff000000, sw_dac_swing_lvl);
386 rtlpcipriv->btcoexist.b_sw_coexist_all_off = false;
387 } else {
388 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], SwDacSwing Off!\n"));
389 rtl8821ae_phy_set_bb_reg(hw, 0x880, 0xff000000, 0xc0);
390 }
391}
392
393void rtl8821ae_dm_bt_set_fw_dec_bt_pwr(
394 struct ieee80211_hw *hw, bool b_dec_bt_pwr)
395{
396 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
397 struct rtl_priv *rtlpriv = rtl_priv(hw);
398 u8 h2c_parameter[1] ={0};
399
400 h2c_parameter[0] = 0;
401
402 if (b_dec_bt_pwr) {
403 h2c_parameter[0] |= BIT(1);
404 rtlpcipriv->btcoexist.b_fw_coexist_all_off = false;
405 }
406
407 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
408 ("[BTCoex], decrease Bt Power : %s, write 0x21=0x%x\n",
409 (b_dec_bt_pwr? "Yes!!":"No!!"), h2c_parameter[0]));
410
411 rtl8821ae_fill_h2c_cmd(hw, 0x21, 1, h2c_parameter);
412}
413
414
415void rtl8821ae_dm_bt_set_fw_2_ant_hid(struct ieee80211_hw *hw,
416 bool b_enable, bool b_dac_swing_on)
417{
418 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
419 struct rtl_priv *rtlpriv = rtl_priv(hw);
420 u8 h2c_parameter[1] ={0};
421
422 if (b_enable) {
423 h2c_parameter[0] |= BIT(0);
424 rtlpcipriv->btcoexist.b_fw_coexist_all_off = false;
425 }
426 if (b_dac_swing_on) {
427 h2c_parameter[0] |= BIT(1); /* Dac Swing default enable */
428 }
429 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
430 ("[BTCoex], turn 2-Ant+HID mode %s, DACSwing:%s, write 0x15=0x%x\n",
431 (b_enable ? "ON!!":"OFF!!"), (b_dac_swing_on ? "ON":"OFF"),
432 h2c_parameter[0]));
433
434 rtl8821ae_fill_h2c_cmd(hw, 0x15, 1, h2c_parameter);
435}
436
437void rtl8821ae_dm_bt_set_fw_tdma_ctrl(struct ieee80211_hw *hw,
438 bool b_enable, u8 ant_num, u8 nav_en, u8 dac_swing_en)
439{
440 struct rtl_priv *rtlpriv = rtl_priv(hw);
441 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
442 u8 h2c_parameter[1] ={0};
443 u8 h2c_parameter1[1] = {0};
444
445 h2c_parameter[0] = 0;
446 h2c_parameter1[0] = 0;
447
448 if(b_enable) {
449 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
450 ("[BTCoex], set BT PTA update manager to trigger update!!\n"));
451 h2c_parameter1[0] |= BIT(0);
452
453 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
454 ("[BTCoex], turn TDMA mode ON!!\n"));
455 h2c_parameter[0] |= BIT(0); /* function enable */
456 if (TDMA_1ANT == ant_num) {
457 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], TDMA_1ANT\n"));
458 h2c_parameter[0] |= BIT(1);
459 } else if(TDMA_2ANT == ant_num) {
460 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], TDMA_2ANT\n"));
461 } else {
462 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], Unknown Ant\n"));
463 }
464
465 if (TDMA_NAV_OFF == nav_en) {
466 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], TDMA_NAV_OFF\n"));
467 } else if (TDMA_NAV_ON == nav_en) {
468 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], TDMA_NAV_ON\n"));
469 h2c_parameter[0] |= BIT(2);
470 }
471
472 if (TDMA_DAC_SWING_OFF == dac_swing_en) {
473 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
474 ("[BTCoex], TDMA_DAC_SWING_OFF\n"));
475 } else if(TDMA_DAC_SWING_ON == dac_swing_en) {
476 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
477 ("[BTCoex], TDMA_DAC_SWING_ON\n"));
478 h2c_parameter[0] |= BIT(4);
479 }
480 rtlpcipriv->btcoexist.b_fw_coexist_all_off = false;
481 } else {
482 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
483 ("[BTCoex], set BT PTA update manager to no update!!\n"));
484 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
485 ("[BTCoex], turn TDMA mode OFF!!\n"));
486 }
487
488 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
489 ("[BTCoex], FW2AntTDMA, write 0x26=0x%x\n", h2c_parameter1[0]));
490 rtl8821ae_fill_h2c_cmd(hw, 0x26, 1, h2c_parameter1);
491
492 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
493 ("[BTCoex], FW2AntTDMA, write 0x14=0x%x\n", h2c_parameter[0]));
494 rtl8821ae_fill_h2c_cmd(hw, 0x14, 1, h2c_parameter);
495
496 if (!b_enable) {
497 /* delay_ms(2);
498 * PlatformEFIOWrite1Byte(Adapter, 0x778, 0x1); */
499 }
500}
501
502
503void rtl8821ae_dm_bt_set_fw_ignore_wlan_act( struct ieee80211_hw *hw, bool b_enable)
504{
505 struct rtl_priv *rtlpriv = rtl_priv(hw);
506 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
507 u8 h2c_parameter[1] ={0};
508
509 if (b_enable) {
510 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], BT Ignore Wlan_Act !!\n"));
511 h2c_parameter[0] |= BIT(0); // function enable
512 rtlpcipriv->btcoexist.b_fw_coexist_all_off = false;
513 } else {
514 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], BT don't ignore Wlan_Act !!\n"));
515 }
516
517 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, write 0x25=0x%x\n",
518 h2c_parameter[0]));
519
520 rtl8821ae_fill_h2c_cmd(hw, 0x25, 1, h2c_parameter);
521}
522
523
524void rtl8821ae_dm_bt_set_fw_tra_tdma_ctrl(struct ieee80211_hw *hw,
525 bool b_enable, u8 ant_num, u8 nav_en
526 )
527{
528 struct rtl_priv *rtlpriv = rtl_priv(hw);
529 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
530 //struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
531
532 u8 h2c_parameter[2] ={0};
533
534
535 if (b_enable) {
536 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
537 ("[BTCoex], turn TTDMA mode ON!!\n"));
538 h2c_parameter[0] |= BIT(0); // function enable
539 if (TDMA_1ANT == ant_num) {
540 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], TTDMA_1ANT\n"));
541 h2c_parameter[0] |= BIT(1);
542 } else if (TDMA_2ANT == ant_num) {
543 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], TTDMA_2ANT\n"));
544 } else {
545 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], Unknown Ant\n"));
546 }
547
548 if (TDMA_NAV_OFF == nav_en) {
549 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], TTDMA_NAV_OFF\n"));
550 } else if (TDMA_NAV_ON == nav_en) {
551 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], TTDMA_NAV_ON\n"));
552 h2c_parameter[1] |= BIT(0);
553 }
554
555 rtlpcipriv->btcoexist.b_fw_coexist_all_off = false;
556 } else {
557 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
558 ("[BTCoex], turn TTDMA mode OFF!!\n"));
559 }
560
561 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
562 ("[BTCoex], FW Traditional TDMA, write 0x33=0x%x\n",
563 h2c_parameter[0] << 8| h2c_parameter[1]));
564
565 rtl8821ae_fill_h2c_cmd(hw, 0x33, 2, h2c_parameter);
566}
567
568
569void rtl8821ae_dm_bt_set_fw_dac_swing_level(struct ieee80211_hw *hw,
570 u8 dac_swing_lvl)
571{
572 struct rtl_priv *rtlpriv = rtl_priv(hw);
573 u8 h2c_parameter[1] ={0};
574 h2c_parameter[0] = dac_swing_lvl;
575
576 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
577 ("[BTCoex], Set Dac Swing Level=0x%x\n", dac_swing_lvl));
578 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
579 ("[BTCoex], write 0x29=0x%x\n", h2c_parameter[0]));
580
581 rtl8821ae_fill_h2c_cmd(hw, 0x29, 1, h2c_parameter);
582}
583
584void rtl8821ae_dm_bt_set_fw_bt_hid_info(struct ieee80211_hw *hw, bool b_enable)
585{
586 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
587 struct rtl_priv *rtlpriv = rtl_priv(hw);
588 u8 h2c_parameter[1] ={0};
589 h2c_parameter[0] = 0;
590
591 if(b_enable){
592 h2c_parameter[0] |= BIT(0);
593 rtlpcipriv->btcoexist.b_fw_coexist_all_off = false;
594 }
595 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
596 ("[BTCoex], Set BT HID information=0x%x\n", b_enable));
597 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
598 ("[BTCoex], write 0x24=0x%x\n", h2c_parameter[0]));
599
600 rtl8821ae_fill_h2c_cmd(hw, 0x24, 1, h2c_parameter);
601}
602
603void rtl8821ae_dm_bt_set_fw_bt_retry_index(struct ieee80211_hw *hw,
604 u8 retry_index)
605{
606 struct rtl_priv *rtlpriv = rtl_priv(hw);
607 u8 h2c_parameter[1] ={0};
608 h2c_parameter[0] = retry_index;
609
610 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
611 ("[BTCoex], Set BT Retry Index=%d\n", retry_index));
612 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
613 ("[BTCoex], write 0x23=0x%x\n", h2c_parameter[0]));
614
615 rtl8821ae_fill_h2c_cmd(hw, 0x23, 1, h2c_parameter);
616}
617
618void rtl8821ae_dm_bt_set_fw_wlan_act(struct ieee80211_hw *hw,
619 u8 wlan_act_hi, u8 wlan_act_lo)
620{
621 struct rtl_priv *rtlpriv = rtl_priv(hw);
622 u8 h2c_parameter_hi[1] ={0};
623 u8 h2c_parameter_lo[1] ={0};
624 h2c_parameter_hi[0] = wlan_act_hi;
625 h2c_parameter_lo[0] = wlan_act_lo;
626
627 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
628 ("[BTCoex], Set WLAN_ACT Hi:Lo=0x%x/0x%x\n", wlan_act_hi, wlan_act_lo));
629 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
630 ("[BTCoex], write 0x22=0x%x\n", h2c_parameter_hi[0]));
631 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
632 ("[BTCoex], write 0x11=0x%x\n", h2c_parameter_lo[0]));
633
634 /* WLAN_ACT = High duration, unit:ms */
635 rtl8821ae_fill_h2c_cmd(hw, 0x22, 1, h2c_parameter_hi);
636 /* WLAN_ACT = Low duration, unit:3*625us */
637 rtl8821ae_fill_h2c_cmd(hw, 0x11, 1, h2c_parameter_lo);
638}
639
640void rtl8821ae_dm_bt_set_bt_dm(struct ieee80211_hw *hw, struct btdm_8821ae *p_btdm)
641{
642 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
643 struct rtl_priv *rtlpriv = rtl_priv(hw);
644 struct btdm_8821ae *p_btdm_8821ae = &hal_coex_8821ae.btdm;
645 u8 i;
646
647 bool b_fw_current_inpsmode = false;
648 bool b_fw_ps_awake = true;
649
650 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
651 (u8 *) (&b_fw_current_inpsmode));
652 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
653 (u8 *) (&b_fw_ps_awake));
654
655 // check new setting is different with the old one,
656 // if all the same, don't do the setting again.
657 if (memcmp(p_btdm_8821ae, p_btdm, sizeof(struct btdm_8821ae)) == 0) {
658 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
659 ("[BTCoex], the same coexist setting, return!!\n"));
660 return;
661 } else { //save the new coexist setting
662 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
663 ("[BTCoex], UPDATE TO NEW COEX SETTING!!\n"));
664 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
665 ("[BTCoex], original/new bAllOff=0x%x/ 0x%x \n",
666 p_btdm_8821ae->b_all_off, p_btdm->b_all_off));
667 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
668 ("[BTCoex], original/new b_agc_table_en=0x%x/ 0x%x \n",
669 p_btdm_8821ae->b_agc_table_en, p_btdm->b_agc_table_en));
670 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
671 ("[BTCoex], original/new b_adc_back_off_on=0x%x/ 0x%x \n",
672 p_btdm_8821ae->b_adc_back_off_on, p_btdm->b_adc_back_off_on));
673 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
674 ("[BTCoex], original/new b2_ant_hid_en=0x%x/ 0x%x \n",
675 p_btdm_8821ae->b2_ant_hid_en, p_btdm->b2_ant_hid_en));
676 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
677 ("[BTCoex], original/new bLowPenaltyRateAdaptive=0x%x/ 0x%x \n",
678 p_btdm_8821ae->b_low_penalty_rate_adaptive,
679 p_btdm->b_low_penalty_rate_adaptive));
680 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
681 ("[BTCoex], original/new bRfRxLpfShrink=0x%x/ 0x%x \n",
682 p_btdm_8821ae->b_rf_rx_lpf_shrink, p_btdm->b_rf_rx_lpf_shrink));
683 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
684 ("[BTCoex], original/new bRejectAggrePkt=0x%x/ 0x%x \n",
685 p_btdm_8821ae->b_reject_aggre_pkt, p_btdm->b_reject_aggre_pkt));
686 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
687 ("[BTCoex], original/new b_tdma_on=0x%x/ 0x%x \n",
688 p_btdm_8821ae->b_tdma_on, p_btdm->b_tdma_on));
689 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
690 ("[BTCoex], original/new tdmaAnt=0x%x/ 0x%x \n",
691 p_btdm_8821ae->tdma_ant, p_btdm->tdma_ant));
692 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
693 ("[BTCoex], original/new tdmaNav=0x%x/ 0x%x \n",
694 p_btdm_8821ae->tdma_nav, p_btdm->tdma_nav));
695 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
696 ("[BTCoex], original/new tdma_dac_swing=0x%x/ 0x%x \n",
697 p_btdm_8821ae->tdma_dac_swing, p_btdm->tdma_dac_swing));
698 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
699 ("[BTCoex], original/new fw_dac_swing_lvl=0x%x/ 0x%x \n",
700 p_btdm_8821ae->fw_dac_swing_lvl, p_btdm->fw_dac_swing_lvl));
701
702 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
703 ("[BTCoex], original/new bTraTdmaOn=0x%x/ 0x%x \n",
704 p_btdm_8821ae->b_tra_tdma_on, p_btdm->b_tra_tdma_on));
705 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
706 ("[BTCoex], original/new traTdmaAnt=0x%x/ 0x%x \n",
707 p_btdm_8821ae->tra_tdma_ant, p_btdm->tra_tdma_ant));
708 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
709 ("[BTCoex], original/new traTdmaNav=0x%x/ 0x%x \n",
710 p_btdm_8821ae->tra_tdma_nav, p_btdm->tra_tdma_nav));
711 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
712 ("[BTCoex], original/new bPsTdmaOn=0x%x/ 0x%x \n",
713 p_btdm_8821ae->b_ps_tdma_on, p_btdm->b_ps_tdma_on));
714 for(i=0; i<5; i++)
715 {
716 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
717 ("[BTCoex], original/new psTdmaByte[i]=0x%x/ 0x%x \n",
718 p_btdm_8821ae->ps_tdma_byte[i], p_btdm->ps_tdma_byte[i]));
719 }
720 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
721 ("[BTCoex], original/new bIgnoreWlanAct=0x%x/ 0x%x \n",
722 p_btdm_8821ae->b_ignore_wlan_act, p_btdm->b_ignore_wlan_act));
723
724
725 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
726 ("[BTCoex], original/new bPtaOn=0x%x/ 0x%x \n",
727 p_btdm_8821ae->b_pta_on, p_btdm->b_pta_on));
728 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
729 ("[BTCoex], original/new val_0x6c0=0x%x/ 0x%x \n",
730 p_btdm_8821ae->val_0x6c0, p_btdm->val_0x6c0));
731 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
732 ("[BTCoex], original/new val_0x6c8=0x%x/ 0x%x \n",
733 p_btdm_8821ae->val_0x6c8, p_btdm->val_0x6c8));
734 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
735 ("[BTCoex], original/new val_0x6cc=0x%x/ 0x%x \n",
736 p_btdm_8821ae->val_0x6cc, p_btdm->val_0x6cc));
737 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
738 ("[BTCoex], original/new b_sw_dac_swing_on=0x%x/ 0x%x \n",
739 p_btdm_8821ae->b_sw_dac_swing_on, p_btdm->b_sw_dac_swing_on));
740 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
741 ("[BTCoex], original/new sw_dac_swing_lvl=0x%x/ 0x%x \n",
742 p_btdm_8821ae->sw_dac_swing_lvl, p_btdm->sw_dac_swing_lvl));
743 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
744 ("[BTCoex], original/new wlanActHi=0x%x/ 0x%x \n",
745 p_btdm_8821ae->wlan_act_hi, p_btdm->wlan_act_hi));
746 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
747 ("[BTCoex], original/new wlanActLo=0x%x/ 0x%x \n",
748 p_btdm_8821ae->wlan_act_lo, p_btdm->wlan_act_lo));
749 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
750 ("[BTCoex], original/new btRetryIndex=0x%x/ 0x%x \n",
751 p_btdm_8821ae->bt_retry_index, p_btdm->bt_retry_index));
752
753 memcpy(p_btdm_8821ae, p_btdm, sizeof(struct btdm_8821ae));
754 }
755 /*
756 * Here we only consider when Bt Operation
757 * inquiry/paging/pairing is ON
758 * we only need to turn off TDMA */
759
760 if (rtlpcipriv->btcoexist.b_hold_for_bt_operation) {
761 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
762 ("[BTCoex], set to ignore wlanAct for BT OP!!\n"));
763 rtl8821ae_dm_bt_set_fw_ignore_wlan_act(hw, true);
764 return;
765 }
766
767 if (p_btdm->b_all_off) {
768 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
769 ("[BTCoex], disable all coexist mechanism !!\n"));
770 rtl8821ae_btdm_coex_all_off(hw);
771 return;
772 }
773
774 rtl8821ae_dm_bt_reject_ap_aggregated_packet(hw, p_btdm->b_reject_aggre_pkt);
775
776 if(p_btdm->b_low_penalty_rate_adaptive)
777 rtl8821ae_dm_bt_set_sw_penalty_tx_rate_adaptive(hw,
778 BT_TX_RATE_ADAPTIVE_LOW_PENALTY);
779 else
780 rtl8821ae_dm_bt_set_sw_penalty_tx_rate_adaptive(hw,
781 BT_TX_RATE_ADAPTIVE_NORMAL);
782
783 if(p_btdm->b_rf_rx_lpf_shrink)
784 rtl8821ae_dm_bt_set_sw_rf_rx_lpf_corner(hw, BT_RF_RX_LPF_CORNER_SHRINK);
785 else
786 rtl8821ae_dm_bt_set_sw_rf_rx_lpf_corner(hw, BT_RF_RX_LPF_CORNER_RESUME);
787
788 if(p_btdm->b_agc_table_en)
789 rtl8821ae_dm_bt_agc_table(hw, BT_AGCTABLE_ON);
790 else
791 rtl8821ae_dm_bt_agc_table(hw, BT_AGCTABLE_OFF);
792
793 if(p_btdm->b_adc_back_off_on)
794 rtl8821ae_dm_bt_bb_back_off_level(hw, BT_BB_BACKOFF_ON);
795 else
796 rtl8821ae_dm_bt_bb_back_off_level(hw, BT_BB_BACKOFF_OFF);
797
798 rtl8821ae_dm_bt_set_fw_bt_retry_index(hw, p_btdm->bt_retry_index);
799
800 rtl8821ae_dm_bt_set_fw_dac_swing_level(hw, p_btdm->fw_dac_swing_lvl);
801 rtl8821ae_dm_bt_set_fw_wlan_act(hw, p_btdm->wlan_act_hi, p_btdm->wlan_act_lo);
802
803 rtl8821ae_dm_bt_set_coex_table(hw, p_btdm->val_0x6c0,
804 p_btdm->val_0x6c8, p_btdm->val_0x6cc);
805 rtl8821ae_dm_bt_set_hw_pta_mode(hw, p_btdm->b_pta_on);
806
807 /*
808 * Note: There is a constraint between TDMA and 2AntHID
809 * Only one of 2AntHid and tdma can be turn on
810 * We should turn off those mechanisms should be turned off first
811 * and then turn on those mechanisms should be turned on.
812 */
813#if 1
814 if(p_btdm->b2_ant_hid_en) {
815 // turn off tdma
816 rtl8821ae_dm_bt_set_fw_tra_tdma_ctrl(hw, p_btdm->b_tra_tdma_on,
817 p_btdm->tra_tdma_ant, p_btdm->tra_tdma_nav);
818 rtl8821ae_dm_bt_set_fw_tdma_ctrl(hw, false, p_btdm->tdma_ant,
819 p_btdm->tdma_nav, p_btdm->tdma_dac_swing);
820
821 // turn off Pstdma
822 rtl8821ae_dm_bt_set_fw_ignore_wlan_act(hw, p_btdm->b_ignore_wlan_act);
823 rtl8821ae_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); // Antenna control by PTA, 0x870 = 0x300.
824
825 // turn on 2AntHid
826 rtl8821ae_dm_bt_set_fw_bt_hid_info(hw, true);
827 rtl8821ae_dm_bt_set_fw_2_ant_hid(hw, true, true);
828 } else if(p_btdm->b_tdma_on) {
829 // turn off 2AntHid
830 rtl8821ae_dm_bt_set_fw_bt_hid_info(hw, false);
831 rtl8821ae_dm_bt_set_fw_2_ant_hid(hw, false, false);
832
833 // turn off pstdma
834 rtl8821ae_dm_bt_set_fw_ignore_wlan_act(hw, p_btdm->b_ignore_wlan_act);
835 rtl8821ae_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); // Antenna control by PTA, 0x870 = 0x300.
836
837 // turn on tdma
838 rtl8821ae_dm_bt_set_fw_tra_tdma_ctrl(hw, p_btdm->b_tra_tdma_on, p_btdm->tra_tdma_ant, p_btdm->tra_tdma_nav);
839 rtl8821ae_dm_bt_set_fw_tdma_ctrl(hw, true, p_btdm->tdma_ant, p_btdm->tdma_nav, p_btdm->tdma_dac_swing);
840 } else if(p_btdm->b_ps_tdma_on) {
841 // turn off 2AntHid
842 rtl8821ae_dm_bt_set_fw_bt_hid_info(hw, false);
843 rtl8821ae_dm_bt_set_fw_2_ant_hid(hw, false, false);
844
845 // turn off tdma
846 rtl8821ae_dm_bt_set_fw_tra_tdma_ctrl(hw, p_btdm->b_tra_tdma_on, p_btdm->tra_tdma_ant, p_btdm->tra_tdma_nav);
847 rtl8821ae_dm_bt_set_fw_tdma_ctrl(hw, false, p_btdm->tdma_ant, p_btdm->tdma_nav, p_btdm->tdma_dac_swing);
848
849 // turn on pstdma
850 rtl8821ae_dm_bt_set_fw_ignore_wlan_act(hw, p_btdm->b_ignore_wlan_act);
851 rtl8821ae_dm_bt_set_fw_3a(hw,
852 p_btdm->ps_tdma_byte[0],
853 p_btdm->ps_tdma_byte[1],
854 p_btdm->ps_tdma_byte[2],
855 p_btdm->ps_tdma_byte[3],
856 p_btdm->ps_tdma_byte[4]);
857 } else {
858 // turn off 2AntHid
859 rtl8821ae_dm_bt_set_fw_bt_hid_info(hw, false);
860 rtl8821ae_dm_bt_set_fw_2_ant_hid(hw, false, false);
861
862 // turn off tdma
863 rtl8821ae_dm_bt_set_fw_tra_tdma_ctrl(hw, p_btdm->b_tra_tdma_on, p_btdm->tra_tdma_ant, p_btdm->tra_tdma_nav);
864 rtl8821ae_dm_bt_set_fw_tdma_ctrl(hw, false, p_btdm->tdma_ant, p_btdm->tdma_nav, p_btdm->tdma_dac_swing);
865
866 // turn off pstdma
867 rtl8821ae_dm_bt_set_fw_ignore_wlan_act(hw, p_btdm->b_ignore_wlan_act);
868 rtl8821ae_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0); // Antenna control by PTA, 0x870 = 0x300.
869 }
870#else
871 if (p_btdm->b_tdma_on) {
872 if(p_btdm->b_ps_tdma_on) {
873 } else {
874 rtl8821ae_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0);
875 }
876 /* Turn off 2AntHID first then turn tdma ON */
877 rtl8821ae_dm_bt_set_fw_bt_hid_info(hw, false);
878 rtl8821ae_dm_bt_set_fw_2_ant_hid(hw, false, false);
879 rtl8821ae_dm_bt_set_fw_tra_tdma_ctrl(hw, p_btdm->b_tra_tdma_on, p_btdm->tra_tdma_ant, p_btdm->tra_tdma_nav);
880 rtl8821ae_dm_bt_set_fw_tdma_ctrl(hw, true,
881 p_btdm->tdma_ant, p_btdm->tdma_nav, p_btdm->tdma_dac_swing);
882 } else {
883 /* Turn off tdma first then turn 2AntHID ON if need */
884 rtl8821ae_dm_bt_set_fw_tra_tdma_ctrl(hw, p_btdm->b_tra_tdma_on, p_btdm->tra_tdma_ant, p_btdm->tra_tdma_nav);
885 rtl8821ae_dm_bt_set_fw_tdma_ctrl(hw, false, p_btdm->tdma_ant,
886 p_btdm->tdma_nav, p_btdm->tdma_dac_swing);
887 if (p_btdm->b2_ant_hid_en) {
888 rtl8821ae_dm_bt_set_fw_bt_hid_info(hw, true);
889 rtl8821ae_dm_bt_set_fw_2_ant_hid(hw, true, true);
890 } else {
891 rtl8821ae_dm_bt_set_fw_bt_hid_info(hw, false);
892 rtl8821ae_dm_bt_set_fw_2_ant_hid(hw, false, false);
893 }
894 if(p_btdm->b_ps_tdma_on) {
895 rtl8821ae_dm_bt_set_fw_3a(hw, p_btdm->ps_tdma_byte[0], p_btdm->ps_tdma_byte[1],
896 p_btdm->ps_tdma_byte[2], p_btdm->ps_tdma_byte[3], p_btdm->ps_tdma_byte[4]);
897 } else {
898 rtl8821ae_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0);
899 }
900 }
901#endif
902
903 /*
904 * Note:
905 * We should add delay for making sure sw DacSwing can be set sucessfully.
906 * because of that rtl8821ae_dm_bt_set_fw_2_ant_hid() and rtl8821ae_dm_bt_set_fw_tdma_ctrl()
907 * will overwrite the reg 0x880.
908 */
909 mdelay(30);
910 rtl8821ae_dm_bt_set_sw_full_time_dac_swing(hw,
911 p_btdm->b_sw_dac_swing_on, p_btdm->sw_dac_swing_lvl);
912 rtl8821ae_dm_bt_set_fw_dec_bt_pwr(hw, p_btdm->b_dec_bt_pwr);
913}
914
915void rtl8821ae_dm_bt_bt_state_update_2_ant_hid(struct ieee80211_hw *hw)
916{
917 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
918 struct rtl_priv *rtlpriv = rtl_priv(hw);
919
920 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], HID busy!!\n"));
921 rtlpcipriv->btcoexist.b_bt_busy = true;
922 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_BT_IDLE;
923}
924
925void rtl8821ae_dm_bt_bt_state_update_2_ant_pan(struct ieee80211_hw *hw)
926{
927 struct rtl_priv *rtlpriv = rtl_priv(hw);
928 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
929 bool b_idle = false;
930
931 if (hal_coex_8821ae.low_priority_tx >=
932 hal_coex_8821ae.low_priority_rx) {
933 if((hal_coex_8821ae.low_priority_tx/
934 hal_coex_8821ae.low_priority_rx) > 10) {
935 b_idle = true;
936 }
937 } else {
938 if((hal_coex_8821ae.low_priority_rx/
939 hal_coex_8821ae.low_priority_tx) > 10) {
940 b_idle = true;
941 }
942 }
943
944 if(!b_idle) {
945 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], PAN busy!!\n"));
946 rtlpcipriv->btcoexist.b_bt_busy = true;
947 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_BT_IDLE;
948 } else {
949 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], PAN idle!!\n"));
950 }
951}
952
953void rtl8821ae_dm_bt_2_ant_sco_action(struct ieee80211_hw *hw)
954{
955 struct rtl_priv *rtlpriv = rtl_priv(hw);
956 struct rtl_phy *rtlphy = &(rtlpriv->phy);
957 struct btdm_8821ae btdm8821ae;
958 u8 bt_rssi_state;
959
960 rtl8821ae_dm_bt_btdm_structure_reload(hw, &btdm8821ae);
961 btdm8821ae.b_rf_rx_lpf_shrink = true;
962 btdm8821ae.b_low_penalty_rate_adaptive = true;
963 btdm8821ae.b_reject_aggre_pkt = false;
964
965 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
966 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("HT40\n"));
967 /* coex table */
968 btdm8821ae.val_0x6c0 = 0x5a5aaaaa;
969 btdm8821ae.val_0x6c8 = 0xcc;
970 btdm8821ae.val_0x6cc = 0x3;
971 /* sw mechanism */
972 btdm8821ae.b_agc_table_en = false;
973 btdm8821ae.b_adc_back_off_on = true;
974 btdm8821ae.b_sw_dac_swing_on = false;
975 /* fw mechanism */
976 btdm8821ae.b_tdma_on = false;
977 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_OFF;
978 } else {
979 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("HT20 or Legacy\n"));
980 bt_rssi_state
981 = rtl8821ae_dm_bt_check_coex_rssi_state(hw, 2, BT_FW_COEX_THRESH_47, 0);
982
983 /* coex table */
984 btdm8821ae.val_0x6c0 = 0x5a5aaaaa;
985 btdm8821ae.val_0x6c8 = 0xcc;
986 btdm8821ae.val_0x6cc = 0x3;
987 /* sw mechanism */
988 if ((bt_rssi_state == BT_RSSI_STATE_HIGH) ||
989 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH) ) {
990 btdm8821ae.b_agc_table_en = true;
991 btdm8821ae.b_adc_back_off_on = true;
992 btdm8821ae.b_sw_dac_swing_on = false;
993 } else {
994 btdm8821ae.b_agc_table_en = false;
995 btdm8821ae.b_adc_back_off_on = false;
996 btdm8821ae.b_sw_dac_swing_on = false;
997 }
998 /* fw mechanism */
999 btdm8821ae.b_tdma_on = false;
1000 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_OFF;
1001 }
1002
1003 if (rtl8821ae_dm_bt_need_to_dec_bt_pwr(hw)) {
1004 btdm8821ae.b_dec_bt_pwr = true;
1005 }
1006
1007 if(rtl8821ae_dm_bt_is_coexist_state_changed(hw))
1008 rtl8821ae_dm_bt_set_bt_dm(hw, &btdm8821ae);
1009}
1010
1011void rtl8821ae_dm_bt_2_ant_hid_action(struct ieee80211_hw *hw)
1012{
1013 struct rtl_priv *rtlpriv = rtl_priv(hw);
1014 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1015 struct btdm_8821ae btdm8821ae;
1016 u8 bt_rssi_state;
1017
1018 rtl8821ae_dm_bt_btdm_structure_reload(hw, &btdm8821ae);
1019
1020 btdm8821ae.b_rf_rx_lpf_shrink = true;
1021 btdm8821ae.b_low_penalty_rate_adaptive = true;
1022 btdm8821ae.b_reject_aggre_pkt = false;
1023
1024 // coex table
1025 btdm8821ae.val_0x6c0 = 0x55555555;
1026 btdm8821ae.val_0x6c8 = 0xffff;
1027 btdm8821ae.val_0x6cc = 0x3;
1028 btdm8821ae.b_ignore_wlan_act = true;
1029
1030 if(rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
1031 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("HT40\n"));
1032 // sw mechanism
1033 btdm8821ae.b_agc_table_en = false;
1034 btdm8821ae.b_adc_back_off_on = false;
1035 btdm8821ae.b_sw_dac_swing_on = false;
1036
1037 // fw mechanism
1038 btdm8821ae.b_ps_tdma_on = true;
1039 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1040 btdm8821ae.ps_tdma_byte[1] = 0xf;
1041 btdm8821ae.ps_tdma_byte[2] = 0xf;
1042 btdm8821ae.ps_tdma_byte[3] = 0x0;
1043 btdm8821ae.ps_tdma_byte[4] = 0x80;
1044
1045 btdm8821ae.b_tra_tdma_on = false;
1046 btdm8821ae.b_tdma_on = false;
1047 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_OFF;
1048 btdm8821ae.b2_ant_hid_en = false;
1049 } else {
1050 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("HT20 or Legacy\n"));
1051 bt_rssi_state =
1052 rtl8821ae_dm_bt_check_coex_rssi_state(hw, 2, 47, 0);
1053
1054 if( (bt_rssi_state == BT_RSSI_STATE_HIGH) ||
1055 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH) ) {
1056 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi high \n"));
1057 // sw mechanism
1058 btdm8821ae.b_agc_table_en = false;
1059 btdm8821ae.b_adc_back_off_on = false;
1060 btdm8821ae.b_sw_dac_swing_on = true;
1061 btdm8821ae.sw_dac_swing_lvl = 0x20;
1062
1063 // fw mechanism
1064 btdm8821ae.b_ps_tdma_on = false;
1065 btdm8821ae.b_tdma_on = false;
1066 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_OFF;
1067 btdm8821ae.b2_ant_hid_en = false;
1068 } else {
1069 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi low \n"));
1070 // sw mechanism
1071 btdm8821ae.b_agc_table_en = false;
1072 btdm8821ae.b_adc_back_off_on = false;
1073 btdm8821ae.b_sw_dac_swing_on = false;
1074
1075 // fw mechanism
1076 btdm8821ae.b_ps_tdma_on = false;
1077 btdm8821ae.b_tdma_on = false;
1078 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_OFF;
1079 btdm8821ae.b2_ant_hid_en = true;
1080 btdm8821ae.fw_dac_swing_lvl = 0x20;
1081 }
1082 }
1083
1084 if (rtl8821ae_dm_bt_need_to_dec_bt_pwr(hw)) {
1085 btdm8821ae.b_dec_bt_pwr = true;
1086 }
1087
1088 if (rtl8821ae_dm_bt_is_coexist_state_changed(hw)) {
1089 rtl8821ae_dm_bt_set_bt_dm(hw, &btdm8821ae);
1090 }
1091}
1092
1093
1094void rtl8821ae_dm_bt_2_ant_2_dp_action_no_profile(struct ieee80211_hw *hw)
1095{
1096 struct rtl_priv *rtlpriv = rtl_priv(hw);
1097 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1098 struct btdm_8821ae btdm8821ae;
1099 u8 bt_rssi_state;
1100
1101 rtl8821ae_dm_bt_btdm_structure_reload(hw, &btdm8821ae);
1102
1103 btdm8821ae.b_rf_rx_lpf_shrink = true;
1104 btdm8821ae.b_low_penalty_rate_adaptive = true;
1105 btdm8821ae.b_reject_aggre_pkt = false;
1106
1107 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
1108 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("HT40\n"));
1109 if (rtl8821ae_dm_bt_is_wifi_up_link(hw)) {
1110 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Wifi Uplink\n"));
1111 /* coex table */
1112 btdm8821ae.val_0x6c0 = 0x5a5a5a5a;
1113 btdm8821ae.val_0x6c8 = 0xcccc;
1114 btdm8821ae.val_0x6cc = 0x3;
1115 // sw mechanism
1116 btdm8821ae.b_agc_table_en = false;
1117 btdm8821ae.b_adc_back_off_on = true;
1118 btdm8821ae.b_sw_dac_swing_on = false;
1119 // fw mechanism
1120 btdm8821ae.b_tra_tdma_on = true;
1121 btdm8821ae.b_tdma_on = true;
1122 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_ON;
1123 btdm8821ae.b2_ant_hid_en = false;
1124 //btSpec = BTHCI_GetBTCoreSpecByProf(Adapter, BT_PROFILE_A2DP);
1125 //if(btSpec >= BT_SPEC_2_1_EDR)
1126 {
1127 btdm8821ae.wlan_act_hi = 0x10;
1128 btdm8821ae.wlan_act_lo = 0x10;
1129 }
1130 //else
1131 //{
1132 //btdm8821ae.wlanActHi = 0x20;
1133 //btdm8821ae.wlanActLo = 0x20;
1134 //}
1135 btdm8821ae.bt_retry_index = 2;
1136 btdm8821ae.fw_dac_swing_lvl = 0x18;
1137 } else {
1138 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Wifi Downlink\n"));
1139 // coex table
1140 btdm8821ae.val_0x6c0 = 0x5a5a5a5a;
1141 btdm8821ae.val_0x6c8 = 0xcc;
1142 btdm8821ae.val_0x6cc = 0x3;
1143 // sw mechanism
1144 btdm8821ae.b_agc_table_en = false;
1145 btdm8821ae.b_adc_back_off_on = true;
1146 btdm8821ae.b_sw_dac_swing_on = false;
1147 // fw mechanism
1148 btdm8821ae.b_tra_tdma_on = true;
1149 btdm8821ae.b_tdma_on = true;
1150 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_ON;
1151 btdm8821ae.b2_ant_hid_en = false;
1152 //btSpec = BTHCI_GetBTCoreSpecByProf(Adapter, BT_PROFILE_A2DP);
1153 //if(btSpec >= BT_SPEC_2_1_EDR)
1154 {
1155 btdm8821ae.wlan_act_hi = 0x10;
1156 btdm8821ae.wlan_act_lo = 0x10;
1157 }
1158 //else
1159 //{
1160 // btdm8821ae.wlanActHi = 0x20;
1161 // btdm8821ae.wlanActLo = 0x20;
1162 //}
1163 btdm8821ae.bt_retry_index = 2;
1164 btdm8821ae.fw_dac_swing_lvl = 0x40;
1165 }
1166 } else {
1167 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("HT20 or Legacy\n"));
1168 bt_rssi_state = rtl8821ae_dm_bt_check_coex_rssi_state(hw, 2, BT_FW_COEX_THRESH_47, 0);
1169
1170 if(rtl8821ae_dm_bt_is_wifi_up_link(hw))
1171 {
1172 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Wifi Uplink\n"));
1173 // coex table
1174 btdm8821ae.val_0x6c0 = 0x5a5a5a5a;
1175 btdm8821ae.val_0x6c8 = 0xcccc;
1176 btdm8821ae.val_0x6cc = 0x3;
1177 // sw mechanism
1178 if( (bt_rssi_state == BT_RSSI_STATE_HIGH) ||
1179 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH) )
1180 {
1181 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Wifi rssi high \n"));
1182 btdm8821ae.b_agc_table_en = true;
1183 btdm8821ae.b_adc_back_off_on = true;
1184 btdm8821ae.b_sw_dac_swing_on = false;
1185 } else {
1186 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Wifi rssi low \n"));
1187 btdm8821ae.b_agc_table_en = false;
1188 btdm8821ae.b_adc_back_off_on = false;
1189 btdm8821ae.b_sw_dac_swing_on = false;
1190 }
1191 // fw mechanism
1192 btdm8821ae.b_tra_tdma_on = true;
1193 btdm8821ae.b_tdma_on = true;
1194 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_ON;
1195 btdm8821ae.b2_ant_hid_en = false;
1196 //btSpec = BTHCI_GetBTCoreSpecByProf(Adapter, BT_PROFILE_A2DP);
1197 //if(btSpec >= BT_SPEC_2_1_EDR)
1198 {
1199 btdm8821ae.wlan_act_hi = 0x10;
1200 btdm8821ae.wlan_act_lo = 0x10;
1201 }
1202 //else
1203 //{
1204 //btdm8821ae.wlanActHi = 0x20;
1205 //btdm8821ae.wlanActLo = 0x20;
1206 //}
1207 btdm8821ae.bt_retry_index = 2;
1208 btdm8821ae.fw_dac_swing_lvl = 0x18;
1209 }
1210 else
1211 {
1212 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Wifi Downlink\n"));
1213 // coex table
1214 btdm8821ae.val_0x6c0 = 0x5a5a5a5a;
1215 btdm8821ae.val_0x6c8 = 0xcc;
1216 btdm8821ae.val_0x6cc = 0x3;
1217 // sw mechanism
1218 if( (bt_rssi_state == BT_RSSI_STATE_HIGH) ||
1219 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH) )
1220 {
1221 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Wifi rssi high \n"));
1222 btdm8821ae.b_agc_table_en = true;
1223 btdm8821ae.b_adc_back_off_on = true;
1224 btdm8821ae.b_sw_dac_swing_on = false;
1225 }
1226 else
1227 {
1228 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("Wifi rssi low \n"));
1229 btdm8821ae.b_agc_table_en = false;
1230 btdm8821ae.b_adc_back_off_on = false;
1231 btdm8821ae.b_sw_dac_swing_on = false;
1232 }
1233 // fw mechanism
1234 btdm8821ae.b_tra_tdma_on = true;
1235 btdm8821ae.b_tdma_on = true;
1236 btdm8821ae.tdma_dac_swing = TDMA_DAC_SWING_ON;
1237 btdm8821ae.b2_ant_hid_en = false;
1238 //btSpec = BTHCI_GetBTCoreSpecByProf(Adapter, BT_PROFILE_A2DP);
1239 //if(btSpec >= BT_SPEC_2_1_EDR)
1240 {
1241 btdm8821ae.wlan_act_hi = 0x10;
1242 btdm8821ae.wlan_act_lo = 0x10;
1243 }
1244 //else
1245 //{
1246 //btdm8821ae.wlanActHi = 0x20;
1247 //btdm8821ae.wlanActLo = 0x20;
1248 //}
1249 btdm8821ae.bt_retry_index = 2;
1250 btdm8821ae.fw_dac_swing_lvl = 0x40;
1251 }
1252 }
1253
1254 if (rtl8821ae_dm_bt_need_to_dec_bt_pwr(hw)) {
1255 btdm8821ae.b_dec_bt_pwr = true;
1256 }
1257
1258 if (rtl8821ae_dm_bt_is_coexist_state_changed(hw)) {
1259 rtl8821ae_dm_bt_set_bt_dm(hw, &btdm8821ae);
1260 }
1261}
1262
1263
1264//============================================================
1265// extern function start with BTDM_
1266//============================================================
1267u32 rtl8821ae_dm_bt_tx_rx_couter_h(struct ieee80211_hw *hw)
1268{
1269 u32 counters=0;
1270
1271 counters = hal_coex_8821ae.high_priority_tx + hal_coex_8821ae.high_priority_rx ;
1272 return counters;
1273}
1274
1275u32 rtl8821ae_dm_bt_tx_rx_couter_l(struct ieee80211_hw *hw)
1276{
1277 u32 counters=0;
1278
1279 counters = hal_coex_8821ae.low_priority_tx + hal_coex_8821ae.low_priority_rx ;
1280 return counters;
1281}
1282
1283u8 rtl8821ae_dm_bt_bt_tx_rx_counter_level(struct ieee80211_hw *hw)
1284{
1285 struct rtl_priv *rtlpriv = rtl_priv(hw);
1286 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1287 u32 bt_tx_rx_cnt = 0;
1288 u8 bt_tx_rx_cnt_lvl = 0;
1289
1290 bt_tx_rx_cnt = rtl8821ae_dm_bt_tx_rx_couter_h(hw)
1291 + rtl8821ae_dm_bt_tx_rx_couter_l(hw);
1292 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1293 ("[BTCoex], BT TxRx Counters = %d\n", bt_tx_rx_cnt));
1294
1295 rtlpcipriv->btcoexist.current_state_h &= ~\
1296 (BT_COEX_STATE_BT_CNT_LEVEL_0 | BT_COEX_STATE_BT_CNT_LEVEL_1|
1297 BT_COEX_STATE_BT_CNT_LEVEL_2);
1298
1299 if (bt_tx_rx_cnt >= BT_TXRX_CNT_THRES_3) {
1300 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1301 ("[BTCoex], BT TxRx Counters at level 3\n"));
1302 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_3;
1303 rtlpcipriv->btcoexist.current_state_h |= BT_COEX_STATE_BT_CNT_LEVEL_3;
1304 } else if(bt_tx_rx_cnt >= BT_TXRX_CNT_THRES_2) {
1305 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1306 ("[BTCoex], BT TxRx Counters at level 2\n"));
1307 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_2;
1308 rtlpcipriv->btcoexist.current_state_h |= BT_COEX_STATE_BT_CNT_LEVEL_2;
1309 } else if(bt_tx_rx_cnt >= BT_TXRX_CNT_THRES_1) {
1310 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1311 ("[BTCoex], BT TxRx Counters at level 1\n"));
1312 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_1;
1313 rtlpcipriv->btcoexist.current_state_h |= BT_COEX_STATE_BT_CNT_LEVEL_1;
1314 } else {
1315 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1316 ("[BTCoex], BT TxRx Counters at level 0\n"));
1317 bt_tx_rx_cnt_lvl = BT_TXRX_CNT_LEVEL_0;
1318 rtlpcipriv->btcoexist.current_state_h |= BT_COEX_STATE_BT_CNT_LEVEL_0;
1319 }
1320 return bt_tx_rx_cnt_lvl;
1321}
1322
1323
1324void rtl8821ae_dm_bt_2_ant_hid_sco_esco(struct ieee80211_hw *hw)
1325{
1326 struct rtl_priv *rtlpriv = rtl_priv(hw);
1327 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1328 struct btdm_8821ae btdm8821ae;
1329
1330 u8 bt_rssi_state, bt_rssi_state1;
1331 u8 bt_tx_rx_cnt_lvl = 0;
1332
1333 rtl8821ae_dm_bt_btdm_structure_reload(hw, &btdm8821ae);
1334
1335
1336 btdm8821ae.b_rf_rx_lpf_shrink = true;
1337 btdm8821ae.b_low_penalty_rate_adaptive = true;
1338 btdm8821ae.b_reject_aggre_pkt = false;
1339
1340 bt_tx_rx_cnt_lvl = rtl8821ae_dm_bt_bt_tx_rx_counter_level(hw);
1341 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters = %d\n", bt_tx_rx_cnt_lvl));
1342
1343 if(rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
1344 {
1345 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("HT40\n"));
1346 // coex table
1347 btdm8821ae.val_0x6c0 = 0x55555555;
1348 btdm8821ae.val_0x6c8 = 0xffff;
1349 btdm8821ae.val_0x6cc = 0x3;
1350
1351 // sw mechanism
1352 btdm8821ae.b_agc_table_en = false;
1353 btdm8821ae.b_adc_back_off_on = false;
1354 btdm8821ae.b_sw_dac_swing_on = false;
1355
1356 // fw mechanism
1357 btdm8821ae.b_ps_tdma_on = true;
1358 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) {
1359 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1400\n"));
1360 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1361 btdm8821ae.ps_tdma_byte[1] = 0x5;
1362 btdm8821ae.ps_tdma_byte[2] = 0x5;
1363 btdm8821ae.ps_tdma_byte[3] = 0x2;
1364 btdm8821ae.ps_tdma_byte[4] = 0x80;
1365 } else if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_1) {
1366 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1200 && < 1400\n"));
1367 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1368 btdm8821ae.ps_tdma_byte[1] = 0xa;
1369 btdm8821ae.ps_tdma_byte[2] = 0xa;
1370 btdm8821ae.ps_tdma_byte[3] = 0x2;
1371 btdm8821ae.ps_tdma_byte[4] = 0x80;
1372 } else {
1373 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters < 1200\n"));
1374 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1375 btdm8821ae.ps_tdma_byte[1] = 0xf;
1376 btdm8821ae.ps_tdma_byte[2] = 0xf;
1377 btdm8821ae.ps_tdma_byte[3] = 0x2;
1378 btdm8821ae.ps_tdma_byte[4] = 0x80;
1379 }
1380 } else {
1381 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("HT20 or Legacy\n"));
1382 bt_rssi_state = rtl8821ae_dm_bt_check_coex_rssi_state(hw, 2, 47, 0);
1383 bt_rssi_state1 = rtl8821ae_dm_bt_check_coex_rssi_state1(hw, 2, 27, 0);
1384
1385 // coex table
1386 btdm8821ae.val_0x6c0 = 0x55555555;
1387 btdm8821ae.val_0x6c8 = 0xffff;
1388 btdm8821ae.val_0x6cc = 0x3;
1389
1390 // sw mechanism
1391 if( (bt_rssi_state == BT_RSSI_STATE_HIGH) ||
1392 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH) ) {
1393 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi high \n"));
1394 btdm8821ae.b_agc_table_en = true;
1395 btdm8821ae.b_adc_back_off_on = true;
1396 btdm8821ae.b_sw_dac_swing_on = false;
1397 } else {
1398 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi low \n"));
1399 btdm8821ae.b_agc_table_en = false;
1400 btdm8821ae.b_adc_back_off_on = false;
1401 btdm8821ae.b_sw_dac_swing_on = false;
1402 }
1403
1404 // fw mechanism
1405 btdm8821ae.b_ps_tdma_on = true;
1406 if( (bt_rssi_state1 == BT_RSSI_STATE_HIGH) ||
1407 (bt_rssi_state1 == BT_RSSI_STATE_STAY_HIGH) ) {
1408 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,("Wifi rssi-1 high \n"));
1409 // only rssi high we need to do this,
1410 // when rssi low, the value will modified by fw
1411 rtl_write_byte(rtlpriv, 0x883, 0x40);
1412 if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) {
1413 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1400\n"));
1414 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1415 btdm8821ae.ps_tdma_byte[1] = 0x5;
1416 btdm8821ae.ps_tdma_byte[2] = 0x5;
1417 btdm8821ae.ps_tdma_byte[3] = 0x83;
1418 btdm8821ae.ps_tdma_byte[4] = 0x80;
1419 } else if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_1) {
1420 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1200 && < 1400\n"));
1421 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1422 btdm8821ae.ps_tdma_byte[1] = 0xa;
1423 btdm8821ae.ps_tdma_byte[2] = 0xa;
1424 btdm8821ae.ps_tdma_byte[3] = 0x83;
1425 btdm8821ae.ps_tdma_byte[4] = 0x80;
1426 } else {
1427 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters < 1200\n"));
1428 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1429 btdm8821ae.ps_tdma_byte[1] = 0xf;
1430 btdm8821ae.ps_tdma_byte[2] = 0xf;
1431 btdm8821ae.ps_tdma_byte[3] = 0x83;
1432 btdm8821ae.ps_tdma_byte[4] = 0x80;
1433 }
1434 } else {
1435 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi-1 low \n"));
1436 if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2)
1437 {
1438 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1400\n"));
1439 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1440 btdm8821ae.ps_tdma_byte[1] = 0x5;
1441 btdm8821ae.ps_tdma_byte[2] = 0x5;
1442 btdm8821ae.ps_tdma_byte[3] = 0x2;
1443 btdm8821ae.ps_tdma_byte[4] = 0x80;
1444 } else if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_1) {
1445 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1200 && < 1400\n"));
1446 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1447 btdm8821ae.ps_tdma_byte[1] = 0xa;
1448 btdm8821ae.ps_tdma_byte[2] = 0xa;
1449 btdm8821ae.ps_tdma_byte[3] = 0x2;
1450 btdm8821ae.ps_tdma_byte[4] = 0x80;
1451 } else {
1452 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters < 1200\n"));
1453 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1454 btdm8821ae.ps_tdma_byte[1] = 0xf;
1455 btdm8821ae.ps_tdma_byte[2] = 0xf;
1456 btdm8821ae.ps_tdma_byte[3] = 0x2;
1457 btdm8821ae.ps_tdma_byte[4] = 0x80;
1458 }
1459 }
1460 }
1461
1462 if (rtl8821ae_dm_bt_need_to_dec_bt_pwr(hw)) {
1463 btdm8821ae.b_dec_bt_pwr = true;
1464 }
1465
1466 // Always ignore WlanAct if bHid|bSCOBusy|bSCOeSCO
1467
1468 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1469 ("[BTCoex], BT btInqPageStartTime = 0x%x, btTxRxCntLvl = %d\n",
1470 hal_coex_8821ae.bt_inq_page_start_time, bt_tx_rx_cnt_lvl));
1471 if( (hal_coex_8821ae.bt_inq_page_start_time) ||
1472 (BT_TXRX_CNT_LEVEL_3 == bt_tx_rx_cnt_lvl) ) {
1473 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1474 ("[BTCoex], Set BT inquiry / page scan 0x3a setting\n"));
1475 btdm8821ae.b_ps_tdma_on = true;
1476 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1477 btdm8821ae.ps_tdma_byte[1] = 0x5;
1478 btdm8821ae.ps_tdma_byte[2] = 0x5;
1479 btdm8821ae.ps_tdma_byte[3] = 0x2;
1480 btdm8821ae.ps_tdma_byte[4] = 0x80;
1481 }
1482
1483 if(rtl8821ae_dm_bt_is_coexist_state_changed(hw)) {
1484 rtl8821ae_dm_bt_set_bt_dm(hw, &btdm8821ae);
1485 }
1486}
1487
1488void rtl8821ae_dm_bt_2_ant_ftp_a2dp(struct ieee80211_hw *hw)
1489{
1490 struct rtl_priv *rtlpriv = rtl_priv(hw);
1491 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1492 struct btdm_8821ae btdm8821ae;
1493
1494 u8 bt_rssi_state, bt_rssi_state1;
1495 u32 bt_tx_rx_cnt_lvl = 0;
1496
1497 rtl8821ae_dm_bt_btdm_structure_reload(hw, &btdm8821ae);
1498
1499 btdm8821ae.b_rf_rx_lpf_shrink = true;
1500 btdm8821ae.b_low_penalty_rate_adaptive = true;
1501 btdm8821ae.b_reject_aggre_pkt = false;
1502
1503 bt_tx_rx_cnt_lvl = rtl8821ae_dm_bt_bt_tx_rx_counter_level(hw);
1504
1505 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters = %d\n", bt_tx_rx_cnt_lvl));
1506
1507 if(rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
1508 {
1509 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("HT40\n"));
1510 bt_rssi_state = rtl8821ae_dm_bt_check_coex_rssi_state(hw, 2, 37, 0);
1511
1512 // coex table
1513 btdm8821ae.val_0x6c0 = 0x55555555;
1514 btdm8821ae.val_0x6c8 = 0xffff;
1515 btdm8821ae.val_0x6cc = 0x3;
1516
1517 // sw mechanism
1518 btdm8821ae.b_agc_table_en = false;
1519 btdm8821ae.b_adc_back_off_on = true;
1520 btdm8821ae.b_sw_dac_swing_on = false;
1521
1522 // fw mechanism
1523 btdm8821ae.b_ps_tdma_on = true;
1524 if ((bt_rssi_state == BT_RSSI_STATE_HIGH) ||
1525 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH) ) {
1526 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi high \n"));
1527 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) {
1528 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1400\n"));
1529 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1530 btdm8821ae.ps_tdma_byte[1] = 0x5;
1531 btdm8821ae.ps_tdma_byte[2] = 0x5;
1532 btdm8821ae.ps_tdma_byte[3] = 0x81;
1533 btdm8821ae.ps_tdma_byte[4] = 0x80;
1534 } else if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_1) {
1535 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1200 && < 1400\n"));
1536 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1537 btdm8821ae.ps_tdma_byte[1] = 0xa;
1538 btdm8821ae.ps_tdma_byte[2] = 0xa;
1539 btdm8821ae.ps_tdma_byte[3] = 0x81;
1540 btdm8821ae.ps_tdma_byte[4] = 0x80;
1541 } else {
1542 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters < 1200\n"));
1543 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1544 btdm8821ae.ps_tdma_byte[1] = 0xf;
1545 btdm8821ae.ps_tdma_byte[2] = 0xf;
1546 btdm8821ae.ps_tdma_byte[3] = 0x81;
1547 btdm8821ae.ps_tdma_byte[4] = 0x80;
1548 }
1549 } else {
1550 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi low \n"));
1551 if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) {
1552 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1400\n"));
1553 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1554 btdm8821ae.ps_tdma_byte[1] = 0x5;
1555 btdm8821ae.ps_tdma_byte[2] = 0x5;
1556 btdm8821ae.ps_tdma_byte[3] = 0x0;
1557 btdm8821ae.ps_tdma_byte[4] = 0x80;
1558 } else if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_1) {
1559 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1200 && < 1400\n"));
1560 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1561 btdm8821ae.ps_tdma_byte[1] = 0xa;
1562 btdm8821ae.ps_tdma_byte[2] = 0xa;
1563 btdm8821ae.ps_tdma_byte[3] = 0x0;
1564 btdm8821ae.ps_tdma_byte[4] = 0x80;
1565 } else {
1566 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters < 1200\n"));
1567 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1568 btdm8821ae.ps_tdma_byte[1] = 0xf;
1569 btdm8821ae.ps_tdma_byte[2] = 0xf;
1570 btdm8821ae.ps_tdma_byte[3] = 0x0;
1571 btdm8821ae.ps_tdma_byte[4] = 0x80;
1572 }
1573 }
1574 } else {
1575 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("HT20 or Legacy\n"));
1576 bt_rssi_state = rtl8821ae_dm_bt_check_coex_rssi_state(hw, 2, 47, 0);
1577 bt_rssi_state1 = rtl8821ae_dm_bt_check_coex_rssi_state1(hw, 2, 27, 0);
1578
1579 // coex table
1580 btdm8821ae.val_0x6c0 = 0x55555555;
1581 btdm8821ae.val_0x6c8 = 0xffff;
1582 btdm8821ae.val_0x6cc = 0x3;
1583
1584 // sw mechanism
1585 if( (bt_rssi_state == BT_RSSI_STATE_HIGH) ||
1586 (bt_rssi_state == BT_RSSI_STATE_STAY_HIGH) ) {
1587 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi high \n"));
1588 btdm8821ae.b_agc_table_en = true;
1589 btdm8821ae.b_adc_back_off_on = true;
1590 btdm8821ae.b_sw_dac_swing_on = false;
1591 } else {
1592 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi low \n"));
1593 btdm8821ae.b_agc_table_en = false;
1594 btdm8821ae.b_adc_back_off_on = false;
1595 btdm8821ae.b_sw_dac_swing_on = false;
1596 }
1597
1598 // fw mechanism
1599 btdm8821ae.b_ps_tdma_on = true;
1600 if( (bt_rssi_state1 == BT_RSSI_STATE_HIGH) ||
1601 (bt_rssi_state1 == BT_RSSI_STATE_STAY_HIGH) ) {
1602 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi-1 high \n"));
1603 // only rssi high we need to do this,
1604 // when rssi low, the value will modified by fw
1605 rtl_write_byte(rtlpriv, 0x883, 0x40);
1606 if (bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) {
1607 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1400\n"));
1608 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1609 btdm8821ae.ps_tdma_byte[1] = 0x5;
1610 btdm8821ae.ps_tdma_byte[2] = 0x5;
1611 btdm8821ae.ps_tdma_byte[3] = 0x81;
1612 btdm8821ae.ps_tdma_byte[4] = 0x80;
1613 } else if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_1) {
1614 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1200 && < 1400\n"));
1615 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1616 btdm8821ae.ps_tdma_byte[1] = 0xa;
1617 btdm8821ae.ps_tdma_byte[2] = 0xa;
1618 btdm8821ae.ps_tdma_byte[3] = 0x81;
1619 btdm8821ae.ps_tdma_byte[4] = 0x80;
1620 } else {
1621 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters < 1200\n"));
1622 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1623 btdm8821ae.ps_tdma_byte[1] = 0xf;
1624 btdm8821ae.ps_tdma_byte[2] = 0xf;
1625 btdm8821ae.ps_tdma_byte[3] = 0x81;
1626 btdm8821ae.ps_tdma_byte[4] = 0x80;
1627 }
1628 } else {
1629 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Wifi rssi-1 low \n"));
1630 if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_2) {
1631 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1400\n"));
1632 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1633 btdm8821ae.ps_tdma_byte[1] = 0x5;
1634 btdm8821ae.ps_tdma_byte[2] = 0x5;
1635 btdm8821ae.ps_tdma_byte[3] = 0x0;
1636 btdm8821ae.ps_tdma_byte[4] = 0x80;
1637 } else if(bt_tx_rx_cnt_lvl == BT_TXRX_CNT_LEVEL_1) {
1638 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters >= 1200 && < 1400\n"));
1639 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1640 btdm8821ae.ps_tdma_byte[1] = 0xa;
1641 btdm8821ae.ps_tdma_byte[2] = 0xa;
1642 btdm8821ae.ps_tdma_byte[3] = 0x0;
1643 btdm8821ae.ps_tdma_byte[4] = 0x80;
1644 } else {
1645 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT TxRx Counters < 1200\n"));
1646 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1647 btdm8821ae.ps_tdma_byte[1] = 0xf;
1648 btdm8821ae.ps_tdma_byte[2] = 0xf;
1649 btdm8821ae.ps_tdma_byte[3] = 0x0;
1650 btdm8821ae.ps_tdma_byte[4] = 0x80;
1651 }
1652 }
1653 }
1654
1655 if(rtl8821ae_dm_bt_need_to_dec_bt_pwr(hw)) {
1656 btdm8821ae.b_dec_bt_pwr = true;
1657 }
1658
1659 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1660 ("[BTCoex], BT btInqPageStartTime = 0x%x, btTxRxCntLvl = %d\n",
1661 hal_coex_8821ae.bt_inq_page_start_time, bt_tx_rx_cnt_lvl));
1662
1663 if( (hal_coex_8821ae.bt_inq_page_start_time) ||
1664 (BT_TXRX_CNT_LEVEL_3 == bt_tx_rx_cnt_lvl) )
1665 {
1666 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1667 ("[BTCoex], Set BT inquiry / page scan 0x3a setting\n"));
1668 btdm8821ae.b_ps_tdma_on = true;
1669 btdm8821ae.ps_tdma_byte[0] = 0xa3;
1670 btdm8821ae.ps_tdma_byte[1] = 0x5;
1671 btdm8821ae.ps_tdma_byte[2] = 0x5;
1672 btdm8821ae.ps_tdma_byte[3] = 0x83;
1673 btdm8821ae.ps_tdma_byte[4] = 0x80;
1674 }
1675
1676 if(rtl8821ae_dm_bt_is_coexist_state_changed(hw)){
1677 rtl8821ae_dm_bt_set_bt_dm(hw, &btdm8821ae);
1678 }
1679}
1680
1681void rtl8821ae_dm_bt_inq_page_monitor(struct ieee80211_hw *hw)
1682{
1683 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1684 struct rtl_priv *rtlpriv = rtl_priv(hw);
1685 u32 cur_time;
1686 cur_time = jiffies;
1687 if (hal_coex_8821ae.b_c2h_bt_inquiry_page) {
1688 //pHalData->btcoexist.halCoex8821ae.btInquiryPageCnt++;
1689 // bt inquiry or page is started.
1690 if(hal_coex_8821ae.bt_inq_page_start_time == 0){
1691 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_BT_INQ_PAGE;
1692 hal_coex_8821ae.bt_inq_page_start_time = cur_time;
1693 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1694 ("[BTCoex], BT Inquiry/page is started at time : 0x%x \n",
1695 hal_coex_8821ae.bt_inq_page_start_time));
1696 }
1697 }
1698 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1699 ("[BTCoex], BT Inquiry/page started time : 0x%x, cur_time : 0x%x \n",
1700 hal_coex_8821ae.bt_inq_page_start_time, cur_time));
1701
1702 if (hal_coex_8821ae.bt_inq_page_start_time) {
1703 if ((((long)cur_time - (long)hal_coex_8821ae.bt_inq_page_start_time) / HZ) >= 10) {
1704 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BT Inquiry/page >= 10sec!!!"));
1705 hal_coex_8821ae.bt_inq_page_start_time = 0;
1706 rtlpcipriv->btcoexist.current_state &=~ BT_COEX_STATE_BT_INQ_PAGE;
1707 }
1708 }
1709
1710#if 0
1711 if (hal_coex_8821ae.b_c2h_bt_inquiry_page) {
1712 hal_coex_8821ae.b_c2h_bt_inquiry_page++;
1713 // bt inquiry or page is started.
1714 } if(hal_coex_8821ae.b_c2h_bt_inquiry_page) {
1715 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_BT_INQ_PAGE;
1716 if(hal_coex_8821ae.bt_inquiry_page_cnt >= 4)
1717 hal_coex_8821ae.bt_inquiry_page_cnt = 0;
1718 hal_coex_8821ae.bt_inquiry_page_cnt++;
1719 } else {
1720 rtlpcipriv->btcoexist.current_state &=~ BT_COEX_STATE_BT_INQ_PAGE;
1721 }
1722#endif
1723}
1724
1725void rtl8821ae_dm_bt_reset_action_profile_state(struct ieee80211_hw *hw)
1726{
1727 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1728
1729 rtlpcipriv->btcoexist.current_state &= ~\
1730 (BT_COEX_STATE_PROFILE_HID | BT_COEX_STATE_PROFILE_A2DP|
1731 BT_COEX_STATE_PROFILE_PAN | BT_COEX_STATE_PROFILE_SCO);
1732
1733 rtlpcipriv->btcoexist.current_state &= ~\
1734 (BT_COEX_STATE_BTINFO_COMMON | BT_COEX_STATE_BTINFO_B_HID_SCOESCO|
1735 BT_COEX_STATE_BTINFO_B_FTP_A2DP);
1736}
1737
1738void _rtl8821ae_dm_bt_coexist_2_ant(struct ieee80211_hw *hw)
1739{
1740 struct rtl_priv *rtlpriv = rtl_priv(hw);
1741 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1742 u8 bt_retry_cnt;
1743 u8 bt_info_original;
1744 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex] Get bt info by fw!!\n"));
1745
1746 _rtl8821ae_dm_bt_check_wifi_state(hw);
1747
1748 if (hal_coex_8821ae.b_c2h_bt_info_req_sent) {
1749 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
1750 ("[BTCoex] c2h for bt_info not rcvd yet!!\n"));
1751 }
1752
1753 bt_retry_cnt = hal_coex_8821ae.bt_retry_cnt;
1754 bt_info_original = hal_coex_8821ae.c2h_bt_info_original;
1755
1756 // when bt inquiry or page scan, we have to set h2c 0x25
1757 // ignore wlanact for continuous 4x2secs
1758 rtl8821ae_dm_bt_inq_page_monitor(hw);
1759 rtl8821ae_dm_bt_reset_action_profile_state(hw);
1760
1761 if(rtl8821ae_dm_bt_is_2_ant_common_action(hw)) {
1762 rtlpcipriv->btcoexist.bt_profile_case = BT_COEX_MECH_COMMON;
1763 rtlpcipriv->btcoexist.bt_profile_action= BT_COEX_MECH_COMMON;
1764 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("Action 2-Ant common.\n"));
1765 } else {
1766 if( (bt_info_original & BTINFO_B_HID) ||
1767 (bt_info_original & BTINFO_B_SCO_BUSY) ||
1768 (bt_info_original & BTINFO_B_SCO_ESCO) ) {
1769 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_BTINFO_B_HID_SCOESCO;
1770 rtlpcipriv->btcoexist.bt_profile_case = BT_COEX_MECH_HID_SCO_ESCO;
1771 rtlpcipriv->btcoexist.bt_profile_action = BT_COEX_MECH_HID_SCO_ESCO;
1772 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BTInfo: bHid|bSCOBusy|bSCOeSCO\n"));
1773 rtl8821ae_dm_bt_2_ant_hid_sco_esco(hw);
1774 } else if( (bt_info_original & BTINFO_B_FTP) ||
1775 (bt_info_original & BTINFO_B_A2DP) ) {
1776 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_BTINFO_B_FTP_A2DP;
1777 rtlpcipriv->btcoexist.bt_profile_case = BT_COEX_MECH_FTP_A2DP;
1778 rtlpcipriv->btcoexist.bt_profile_action = BT_COEX_MECH_FTP_A2DP;
1779 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("BTInfo: bFTP|bA2DP\n"));
1780 rtl8821ae_dm_bt_2_ant_ftp_a2dp(hw);
1781 } else {
1782 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_BTINFO_B_HID_SCOESCO;
1783 rtlpcipriv->btcoexist.bt_profile_case = BT_COEX_MECH_NONE;
1784 rtlpcipriv->btcoexist.bt_profile_action= BT_COEX_MECH_NONE;
1785 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], BTInfo: undefined case!!!!\n"));
1786 rtl8821ae_dm_bt_2_ant_hid_sco_esco(hw);
1787 }
1788 }
1789}
1790
1791void _rtl8821ae_dm_bt_coexist_1_ant(struct ieee80211_hw *hw)
1792{
1793 return;
1794}
1795
1796void rtl8821ae_dm_bt_hw_coex_all_off_8723a(struct ieee80211_hw *hw)
1797{
1798 rtl8821ae_dm_bt_set_coex_table(hw, 0x5a5aaaaa, 0xcc, 0x3);
1799 rtl8821ae_dm_bt_set_hw_pta_mode(hw, true);
1800}
1801
1802void rtl8821ae_dm_bt_fw_coex_all_off_8723a(struct ieee80211_hw *hw)
1803{
1804 rtl8821ae_dm_bt_set_fw_ignore_wlan_act(hw, false);
1805 rtl8821ae_dm_bt_set_fw_3a(hw, 0x0, 0x0, 0x0, 0x8, 0x0);
1806 rtl8821ae_dm_bt_set_fw_2_ant_hid(hw, false, false);
1807 rtl8821ae_dm_bt_set_fw_tra_tdma_ctrl(hw, false, TDMA_2ANT, TDMA_NAV_OFF);
1808 rtl8821ae_dm_bt_set_fw_tdma_ctrl(hw, false, TDMA_2ANT,
1809 TDMA_NAV_OFF, TDMA_DAC_SWING_OFF);
1810 rtl8821ae_dm_bt_set_fw_dac_swing_level(hw, 0);
1811 rtl8821ae_dm_bt_set_fw_bt_hid_info(hw, false);
1812 rtl8821ae_dm_bt_set_fw_bt_retry_index(hw, 2);
1813 rtl8821ae_dm_bt_set_fw_wlan_act(hw, 0x10, 0x10);
1814 rtl8821ae_dm_bt_set_fw_dec_bt_pwr(hw, false);
1815}
1816
1817void rtl8821ae_dm_bt_sw_coex_all_off_8723a(struct ieee80211_hw *hw)
1818{
1819 rtl8821ae_dm_bt_agc_table(hw, BT_AGCTABLE_OFF);
1820 rtl8821ae_dm_bt_bb_back_off_level(hw, BT_BB_BACKOFF_OFF);
1821 rtl8821ae_dm_bt_reject_ap_aggregated_packet(hw, false);
1822
1823 rtl8821ae_dm_bt_set_sw_penalty_tx_rate_adaptive(hw,
1824 BT_TX_RATE_ADAPTIVE_NORMAL);
1825 rtl8821ae_dm_bt_set_sw_rf_rx_lpf_corner(hw, BT_RF_RX_LPF_CORNER_RESUME);
1826 rtl8821ae_dm_bt_set_sw_full_time_dac_swing(hw, false, 0xc0);
1827}
1828
1829void rtl8821ae_dm_bt_query_bt_information(struct ieee80211_hw *hw)
1830{
1831 struct rtl_priv *rtlpriv = rtl_priv(hw);
1832 u8 h2c_parameter[1] = {0};
1833
1834 hal_coex_8821ae.b_c2h_bt_info_req_sent = true;
1835
1836 h2c_parameter[0] |= BIT(0);
1837
1838 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
1839 ("Query Bt information, write 0x38=0x%x\n", h2c_parameter[0]));
1840
1841 rtl8821ae_fill_h2c_cmd(hw, 0x38, 1, h2c_parameter);
1842}
1843
1844void rtl8821ae_dm_bt_bt_hw_counters_monitor(struct ieee80211_hw *hw)
1845{
1846 struct rtl_priv *rtlpriv = rtl_priv(hw);
1847 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1848 u32 reg_hp_tx_rx, reg_lp_tx_rx, u32_tmp;
1849 u32 reg_hp_tx=0, reg_hp_rx=0, reg_lp_tx=0, reg_lp_rx=0;
1850
1851 reg_hp_tx_rx = REG_HIGH_PRIORITY_TXRX;
1852 reg_lp_tx_rx = REG_LOW_PRIORITY_TXRX;
1853
1854 u32_tmp = rtl_read_dword(rtlpriv, reg_hp_tx_rx);
1855 reg_hp_tx = u32_tmp & MASKLWORD;
1856 reg_hp_rx = (u32_tmp & MASKHWORD)>>16;
1857
1858 u32_tmp = rtl_read_dword(rtlpriv, reg_lp_tx_rx);
1859 reg_lp_tx = u32_tmp & MASKLWORD;
1860 reg_lp_rx = (u32_tmp & MASKHWORD)>>16;
1861
1862 if(rtlpcipriv->btcoexist.lps_counter > 1) {
1863 reg_hp_tx %= rtlpcipriv->btcoexist.lps_counter;
1864 reg_hp_rx %= rtlpcipriv->btcoexist.lps_counter;
1865 reg_lp_tx %= rtlpcipriv->btcoexist.lps_counter;
1866 reg_lp_rx %= rtlpcipriv->btcoexist.lps_counter;
1867 }
1868
1869 hal_coex_8821ae.high_priority_tx = reg_hp_tx;
1870 hal_coex_8821ae.high_priority_rx = reg_hp_rx;
1871 hal_coex_8821ae.low_priority_tx = reg_lp_tx;
1872 hal_coex_8821ae.low_priority_rx = reg_lp_rx;
1873
1874 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1875 ("High Priority Tx/Rx (reg 0x%x)=%x(%d)/%x(%d)\n",
1876 reg_hp_tx_rx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx));
1877 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1878 ("Low Priority Tx/Rx (reg 0x%x)=%x(%d)/%x(%d)\n",
1879 reg_lp_tx_rx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx));
1880 rtlpcipriv->btcoexist.lps_counter = 0;
1881 //rtl_write_byte(rtlpriv, 0x76e, 0xc);
1882}
1883
1884void rtl8821ae_dm_bt_bt_enable_disable_check(struct ieee80211_hw *hw)
1885{
1886 struct rtl_priv *rtlpriv = rtl_priv(hw);
1887 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1888 bool bt_alife = true;
1889
1890 if (hal_coex_8821ae.high_priority_tx == 0 &&
1891 hal_coex_8821ae.high_priority_rx == 0 &&
1892 hal_coex_8821ae.low_priority_tx == 0 &&
1893 hal_coex_8821ae.low_priority_rx == 0) {
1894 bt_alife = false;
1895 }
1896 if (hal_coex_8821ae.high_priority_tx == 0xeaea &&
1897 hal_coex_8821ae.high_priority_rx == 0xeaea &&
1898 hal_coex_8821ae.low_priority_tx == 0xeaea &&
1899 hal_coex_8821ae.low_priority_rx == 0xeaea) {
1900 bt_alife = false;
1901 }
1902 if (hal_coex_8821ae.high_priority_tx == 0xffff &&
1903 hal_coex_8821ae.high_priority_rx == 0xffff &&
1904 hal_coex_8821ae.low_priority_tx == 0xffff &&
1905 hal_coex_8821ae.low_priority_rx == 0xffff) {
1906 bt_alife = false;
1907 }
1908 if (bt_alife) {
1909 rtlpcipriv->btcoexist.bt_active_zero_cnt = 0;
1910 rtlpcipriv->btcoexist.b_cur_bt_disabled = false;
1911 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("8821AE BT is enabled !!\n"));
1912 } else {
1913 rtlpcipriv->btcoexist.bt_active_zero_cnt++;
1914 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
1915 ("8821AE bt all counters=0, %d times!!\n",
1916 rtlpcipriv->btcoexist.bt_active_zero_cnt));
1917 if (rtlpcipriv->btcoexist.bt_active_zero_cnt >= 2) {
1918 rtlpcipriv->btcoexist.b_cur_bt_disabled = true;
1919 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("8821AE BT is disabled !!\n"));
1920 }
1921 }
1922 if (rtlpcipriv->btcoexist.b_pre_bt_disabled !=
1923 rtlpcipriv->btcoexist.b_cur_bt_disabled) {
1924 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("8821AE BT is from %s to %s!!\n",
1925 (rtlpcipriv->btcoexist.b_pre_bt_disabled ? "disabled":"enabled"),
1926 (rtlpcipriv->btcoexist.b_cur_bt_disabled ? "disabled":"enabled")));
1927 rtlpcipriv->btcoexist.b_pre_bt_disabled
1928 = rtlpcipriv->btcoexist.b_cur_bt_disabled;
1929 }
1930}
1931
1932
1933void rtl8821ae_dm_bt_coexist(struct ieee80211_hw *hw)
1934{
1935 struct rtl_priv *rtlpriv = rtl_priv(hw);
1936 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1937
1938 rtl8821ae_dm_bt_query_bt_information(hw);
1939 rtl8821ae_dm_bt_bt_hw_counters_monitor(hw);
1940 rtl8821ae_dm_bt_bt_enable_disable_check(hw);
1941
1942 if (rtlpcipriv->btcoexist.bt_ant_num == ANT_X2) {
1943 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTCoex], 2 Ant mechanism\n"));
1944 _rtl8821ae_dm_bt_coexist_2_ant(hw);
1945 } else {
1946 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BTCoex], 1 Ant mechanism\n"));
1947 _rtl8821ae_dm_bt_coexist_1_ant(hw);
1948 }
1949
1950 if (!rtl8821ae_dm_bt_is_same_coexist_state(hw)) {
1951 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1952 ("[BTCoex], Coexist State[bitMap] change from 0x%x%8x to 0x%x%8x\n",
1953 rtlpcipriv->btcoexist.previous_state_h,
1954 rtlpcipriv->btcoexist.previous_state,
1955 rtlpcipriv->btcoexist.current_state_h,
1956 rtlpcipriv->btcoexist.current_state));
1957 rtlpcipriv->btcoexist.previous_state
1958 = rtlpcipriv->btcoexist.current_state;
1959 rtlpcipriv->btcoexist.previous_state_h
1960 = rtlpcipriv->btcoexist.current_state_h;
1961 }
1962}
1963
1964void rtl8821ae_dm_bt_parse_bt_info(struct ieee80211_hw *hw, u8 * tmp_buf, u8 len)
1965{
1966 struct rtl_priv *rtlpriv = rtl_priv(hw);
1967 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1968 u8 bt_info;
1969 u8 i;
1970
1971 hal_coex_8821ae.b_c2h_bt_info_req_sent = false;
1972 hal_coex_8821ae.bt_retry_cnt = 0;
1973 for (i = 0; i < len; i++) {
1974 if (i == 0) {
1975 hal_coex_8821ae.c2h_bt_info_original = tmp_buf[i];
1976 } else if (i == 1) {
1977 hal_coex_8821ae.bt_retry_cnt = tmp_buf[i];
1978 }
1979 if(i == len-1) {
1980 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("0x%2x]", tmp_buf[i]));
1981 } else {
1982 RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("0x%2x, ", tmp_buf[i]));
1983 }
1984 }
1985 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG,
1986 ("BT info bt_info (Data)= 0x%x\n",hal_coex_8821ae.c2h_bt_info_original));
1987 bt_info = hal_coex_8821ae.c2h_bt_info_original;
1988
1989 if(bt_info & BIT(2)){
1990 hal_coex_8821ae.b_c2h_bt_inquiry_page = true;
1991 } else {
1992 hal_coex_8821ae.b_c2h_bt_inquiry_page = false;
1993 }
1994
1995 if (bt_info & BTINFO_B_CONNECTION) {
1996 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTC2H], BTInfo: bConnect=true\n"));
1997 rtlpcipriv->btcoexist.b_bt_busy = true;
1998 rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_BT_IDLE;
1999 } else {
2000 RT_TRACE(COMP_BT_COEXIST, DBG_DMESG, ("[BTC2H], BTInfo: bConnect=false\n"));
2001 rtlpcipriv->btcoexist.b_bt_busy = false;
2002 rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_BT_IDLE;
2003 }
2004}
2005void rtl_8821ae_c2h_command_handle(struct ieee80211_hw *hw)
2006{
2007 struct rtl_priv *rtlpriv = rtl_priv(hw);
2008 struct c2h_evt_hdr c2h_event;
2009 u8 * ptmp_buf = NULL;
2010 u8 index = 0;
2011 u8 u1b_tmp = 0;
2012 memset(&c2h_event, 0, sizeof(c2h_event));
2013 u1b_tmp = rtl_read_byte(rtlpriv, REG_C2HEVT_MSG_NORMAL);
2014 RT_TRACE(COMP_FW, DBG_DMESG,
2015 ("&&&&&&: REG_C2HEVT_MSG_NORMAL is 0x%x\n", u1b_tmp));
2016 c2h_event.cmd_id = u1b_tmp & 0xF;
2017 c2h_event.cmd_len = (u1b_tmp & 0xF0) >> 4;
2018 c2h_event.cmd_seq = rtl_read_byte(rtlpriv, REG_C2HEVT_MSG_NORMAL + 1);
2019 RT_TRACE(COMP_FW, DBG_DMESG, ("cmd_id: %d, cmd_len: %d, cmd_seq: %d\n",
2020 c2h_event.cmd_id , c2h_event.cmd_len, c2h_event.cmd_seq));
2021 u1b_tmp = rtl_read_byte(rtlpriv, 0x01AF);
2022 if (u1b_tmp == C2H_EVT_HOST_CLOSE) {
2023 return;
2024 } else if (u1b_tmp != C2H_EVT_FW_CLOSE) {
2025 rtl_write_byte(rtlpriv, 0x1AF, 0x00);
2026 return;
2027 }
2028 ptmp_buf = (u8 *) kmalloc(c2h_event.cmd_len, GFP_KERNEL);
2029 if(ptmp_buf == NULL) {
2030 RT_TRACE(COMP_FW, DBG_TRACE, ("malloc cmd buf failed\n"));
2031 return;
2032 }
2033
2034 /* Read the content */
2035 for (index = 0; index < c2h_event.cmd_len; index ++) {
2036 ptmp_buf[index] = rtl_read_byte(rtlpriv, REG_C2HEVT_MSG_NORMAL + 2+ index);
2037 }
2038
2039 switch(c2h_event.cmd_id) {
2040 case C2H_BT_RSSI:
2041 break;
2042
2043 case C2H_BT_OP_MODE:
2044 break;
2045
2046 case BT_INFO:
2047 RT_TRACE(COMP_FW, DBG_TRACE,
2048 ("BT info Byte[0] (ID) is 0x%x\n", c2h_event.cmd_id));
2049 RT_TRACE(COMP_FW, DBG_TRACE,
2050 ("BT info Byte[1] (Seq) is 0x%x\n", c2h_event.cmd_seq));
2051 RT_TRACE(COMP_FW, DBG_TRACE,
2052 ("BT info Byte[2] (Data)= 0x%x\n", ptmp_buf[0]));
2053
2054 if (rtlpriv->cfg->ops->get_btc_status()){
2055 rtlpriv->btcoexist.btc_ops->btc_btinfo_notify(rtlpriv, ptmp_buf, c2h_event.cmd_len);
2056 }
2057 break;
2058 default:
2059 break;
2060 }
2061
2062 if(ptmp_buf)
2063 kfree(ptmp_buf);
2064
2065 rtl_write_byte(rtlpriv, 0x01AF, C2H_EVT_HOST_CLOSE);
2066}
2067
2068
2069
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/hal_btc.h b/drivers/staging/rtl8821ae/rtl8821ae/hal_btc.h
new file mode 100644
index 000000000000..a94474faca49
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/hal_btc.h
@@ -0,0 +1,160 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 * Larry Finger <Larry.Finger@lwfinger.net>
26 *
27 *****************************************************************************/
28
29#ifndef __RTL8821AE_HAL_BTC_H__
30#define __RTL8821AE_HAL_BTC_H__
31
32#include "../wifi.h"
33#include "btc.h"
34#include "hal_bt_coexist.h"
35
36#define BT_TXRX_CNT_THRES_1 1200
37#define BT_TXRX_CNT_THRES_2 1400
38#define BT_TXRX_CNT_THRES_3 3000
39#define BT_TXRX_CNT_LEVEL_0 0 // < 1200
40#define BT_TXRX_CNT_LEVEL_1 1 // >= 1200 && < 1400
41#define BT_TXRX_CNT_LEVEL_2 2 // >= 1400
42#define BT_TXRX_CNT_LEVEL_3 3
43
44
45
46#define BT_COEX_DISABLE 0
47#define BT_Q_PKT_OFF 0
48#define BT_Q_PKT_ON 1
49
50#define BT_TX_PWR_OFF 0
51#define BT_TX_PWR_ON 1
52
53/* TDMA mode definition */
54#define TDMA_2ANT 0
55#define TDMA_1ANT 1
56#define TDMA_NAV_OFF 0
57#define TDMA_NAV_ON 1
58#define TDMA_DAC_SWING_OFF 0
59#define TDMA_DAC_SWING_ON 1
60
61/* PTA mode related definition */
62#define BT_PTA_MODE_OFF 0
63#define BT_PTA_MODE_ON 1
64
65/* Penalty Tx Rate Adaptive */
66#define BT_TX_RATE_ADAPTIVE_NORMAL 0
67#define BT_TX_RATE_ADAPTIVE_LOW_PENALTY 1
68
69/* RF Corner */
70#define BT_RF_RX_LPF_CORNER_RESUME 0
71#define BT_RF_RX_LPF_CORNER_SHRINK 1
72
73#define C2H_EVT_HOST_CLOSE 0x00
74#define C2H_EVT_FW_CLOSE 0xFF
75
76enum bt_traffic_mode {
77 BT_MOTOR_EXT_BE = 0x00,
78 BT_MOTOR_EXT_GUL = 0x01,
79 BT_MOTOR_EXT_GUB = 0x02,
80 BT_MOTOR_EXT_GULB = 0x03
81};
82
83enum bt_traffic_mode_profile {
84 BT_PROFILE_NONE,
85 BT_PROFILE_A2DP,
86 BT_PROFILE_PAN,
87 BT_PROFILE_HID,
88 BT_PROFILE_SCO
89};
90
91enum hci_ext_bt_operation {
92 HCI_BT_OP_NONE = 0x0,
93 HCI_BT_OP_INQUIRE_START = 0x1,
94 HCI_BT_OP_INQUIRE_FINISH = 0x2,
95 HCI_BT_OP_PAGING_START = 0x3,
96 HCI_BT_OP_PAGING_SUCCESS = 0x4,
97 HCI_BT_OP_PAGING_UNSUCCESS = 0x5,
98 HCI_BT_OP_PAIRING_START = 0x6,
99 HCI_BT_OP_PAIRING_FINISH = 0x7,
100 HCI_BT_OP_BT_DEV_ENABLE = 0x8,
101 HCI_BT_OP_BT_DEV_DISABLE = 0x9,
102 HCI_BT_OP_MAX,
103};
104
105enum bt_spec {
106 BT_SPEC_1_0_b = 0x00,
107 BT_SPEC_1_1 = 0x01,
108 BT_SPEC_1_2 = 0x02,
109 BT_SPEC_2_0_EDR = 0x03,
110 BT_SPEC_2_1_EDR = 0x04,
111 BT_SPEC_3_0_HS = 0x05,
112 BT_SPEC_4_0 = 0x06
113};
114
115struct c2h_evt_hdr {
116 u8 cmd_id;
117 u8 cmd_len;
118 u8 cmd_seq;
119};
120
121enum bt_state{
122 BT_INFO_STATE_DISABLED = 0,
123 BT_INFO_STATE_NO_CONNECTION = 1,
124 BT_INFO_STATE_CONNECT_IDLE = 2,
125 BT_INFO_STATE_INQ_OR_PAG = 3,
126 BT_INFO_STATE_ACL_ONLY_BUSY = 4,
127 BT_INFO_STATE_SCO_ONLY_BUSY = 5,
128 BT_INFO_STATE_ACL_SCO_BUSY = 6,
129 BT_INFO_STATE_HID_BUSY = 7,
130 BT_INFO_STATE_HID_SCO_BUSY = 8,
131 BT_INFO_STATE_MAX = 7
132};
133
134enum rtl8723be_c2h_evt {
135 C2H_DBG = 0,
136 C2H_TSF = 1,
137 C2H_AP_RPT_RSP = 2,
138 C2H_CCX_TX_RPT = 3, // The FW notify the report of the specific tx packet.
139 C2H_BT_RSSI = 4,
140 C2H_BT_OP_MODE = 5,
141 C2H_HW_INFO_EXCH = 10,
142 C2H_C2H_H2C_TEST = 11,
143 BT_INFO = 9,
144 MAX_C2HEVENT
145};
146
147
148
149void rtl8821ae_dm_bt_fw_coex_all_off_8723a(struct ieee80211_hw *hw);
150void rtl8821ae_dm_bt_sw_coex_all_off_8723a(struct ieee80211_hw *hw);
151void rtl8821ae_dm_bt_hw_coex_all_off_8723a(struct ieee80211_hw *hw);
152void rtl8821ae_dm_bt_coexist(struct ieee80211_hw *hw);
153void rtl8821ae_dm_bt_set_bt_dm(struct ieee80211_hw *hw, struct btdm_8821ae *p_btdm);
154void rtl_8821ae_c2h_command_handle(struct ieee80211_hw * hw);
155void rtl_8821ae_bt_wifi_media_status_notify(struct ieee80211_hw * hw, bool mstatus);
156void rtl8821ae_dm_bt_turn_off_bt_coexist_before_enter_lps(struct ieee80211_hw *hw);
157
158
159
160#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/hw.c b/drivers/staging/rtl8821ae/rtl8821ae/hw.c
new file mode 100644
index 000000000000..5ed7a114c56b
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/hw.c
@@ -0,0 +1,3346 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../regd.h"
34#include "../cam.h"
35#include "../ps.h"
36#include "../pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "dm.h"
41#include "fw.h"
42#include "led.h"
43#include "hw.h"
44#include "pwrseqcmd.h"
45#include "pwrseq.h"
46#include "btc.h"
47#include "../btcoexist/rtl_btc.h"
48
49#define LLT_CONFIG 5
50
51static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
52{
53 struct rtl_priv *rtlpriv = rtl_priv(hw);
54 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
55 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
56
57 while (skb_queue_len(&ring->queue)) {
58 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
59 struct sk_buff *skb = __skb_dequeue(&ring->queue);
60
61 pci_unmap_single(rtlpci->pdev,
62 le32_to_cpu(rtlpriv->cfg->ops->get_desc(
63 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR)),
64 skb->len, PCI_DMA_TODEVICE);
65 kfree_skb(skb);
66 ring->idx = (ring->idx + 1) % ring->entries;
67 }
68
69}
70
71static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
72 u8 set_bits, u8 clear_bits)
73{
74 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
75 struct rtl_priv *rtlpriv = rtl_priv(hw);
76
77 rtlpci->reg_bcn_ctrl_val |= set_bits;
78 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
79
80 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
81}
82
83void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
84{
85 struct rtl_priv *rtlpriv = rtl_priv(hw);
86 u8 tmp1byte;
87
88 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
89 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
91 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
92 tmp1byte &= ~(BIT(0));
93 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
94}
95
96void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
97{
98 struct rtl_priv *rtlpriv = rtl_priv(hw);
99 u8 tmp1byte;
100
101 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
102 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
103 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
104 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
105 tmp1byte |= BIT(0);
106 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
107}
108
109static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
110{
111 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
112}
113
114static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
115{
116 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
117}
118
119static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
120 u8 rpwm_val, bool b_need_turn_off_ckk)
121{
122 struct rtl_priv *rtlpriv = rtl_priv(hw);
123 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
124 bool b_support_remote_wake_up;
125 u32 count = 0,isr_regaddr,content;
126 bool b_schedule_timer = b_need_turn_off_ckk;
127 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
128 (u8 *) (&b_support_remote_wake_up));
129
130 if (!rtlhal->bfw_ready)
131 return;
132 if (!rtlpriv->psc.b_fw_current_inpsmode)
133 return;
134
135 while (1) {
136 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
137 if (rtlhal->bfw_clk_change_in_progress) {
138 while (rtlhal->bfw_clk_change_in_progress) {
139 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
140 count++;
141 udelay(100);
142 if (count > 1000)
143 return;
144 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
145 }
146 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
147 } else {
148 rtlhal->bfw_clk_change_in_progress = false;
149 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
150 }
151 }
152
153 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
154 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
155 (u8 *) (&rpwm_val));
156 if (FW_PS_IS_ACK(rpwm_val)) {
157 isr_regaddr = REG_HISR;
158 content = rtl_read_dword(rtlpriv, isr_regaddr);
159 while (!(content & IMR_CPWM) && (count < 500)) {
160 udelay(50);
161 count++;
162 content = rtl_read_dword(rtlpriv, isr_regaddr);
163 }
164
165 if (content & IMR_CPWM) {
166 rtl_write_word(rtlpriv,isr_regaddr, 0x0100);
167 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
168 RT_TRACE(COMP_POWER, DBG_LOUD, ("Receive CPWM INT!!! Set pHalData->FwPSState = %X\n", rtlhal->fw_ps_state));
169 }
170 }
171
172 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
173 rtlhal->bfw_clk_change_in_progress = false;
174 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
175 if (b_schedule_timer) {
176 mod_timer(&rtlpriv->works.fw_clockoff_timer,
177 jiffies + MSECS(10));
178 }
179
180 } else {
181 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
182 rtlhal->bfw_clk_change_in_progress = false;
183 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
184 }
185
186
187}
188
189static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
190 u8 rpwm_val)
191{
192 struct rtl_priv *rtlpriv = rtl_priv(hw);
193 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
194 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
195 struct rtl8192_tx_ring *ring;
196 enum rf_pwrstate rtstate;
197 bool b_schedule_timer = false;
198 u8 queue;
199
200 if (!rtlhal->bfw_ready)
201 return;
202 if (!rtlpriv->psc.b_fw_current_inpsmode)
203 return;
204 if (!rtlhal->ballow_sw_to_change_hwclc)
205 return;
206 rtlpriv->cfg->ops->get_hw_reg(hw,HW_VAR_RF_STATE,(u8 *)(&rtstate));
207 if (rtstate == ERFOFF ||rtlpriv->psc.inactive_pwrstate ==ERFOFF)
208 return;
209
210 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
211 ring = &rtlpci->tx_ring[queue];
212 if (skb_queue_len(&ring->queue)) {
213 b_schedule_timer = true;
214 break;
215 }
216 }
217
218 if (b_schedule_timer) {
219 mod_timer(&rtlpriv->works.fw_clockoff_timer,
220 jiffies + MSECS(10));
221 return;
222 }
223
224 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
225 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
226 if (!rtlhal->bfw_clk_change_in_progress) {
227 rtlhal->bfw_clk_change_in_progress = true;
228 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
229 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
230 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
231 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
232 (u8 *) (&rpwm_val));
233 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
234 rtlhal->bfw_clk_change_in_progress = false;
235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
236 } else {
237 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
238 mod_timer(&rtlpriv->works.fw_clockoff_timer,
239 jiffies + MSECS(10));
240 }
241 }
242
243}
244
245static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
246{
247 u8 rpwm_val = 0;
248 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
249 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
250}
251
252static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
253{
254 struct rtl_priv *rtlpriv = rtl_priv(hw);
255 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
256 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
257 bool b_fw_current_inps = false;
258 u8 rpwm_val = 0,fw_pwrmode = FW_PS_ACTIVE_MODE;
259
260 if (ppsc->b_low_power_enable){
261 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
262 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
263 rtlhal->ballow_sw_to_change_hwclc = false;
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
265 (u8 *) (&fw_pwrmode));
266 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
267 (u8 *) (&b_fw_current_inps));
268 } else {
269 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */
270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
271 (u8 *) (&rpwm_val));
272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
273 (u8 *) (&fw_pwrmode));
274 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
275 (u8 *) (&b_fw_current_inps));
276 }
277
278}
279
280static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
281{
282 struct rtl_priv *rtlpriv = rtl_priv(hw);
283 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
284 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
285 bool b_fw_current_inps = true;
286 u8 rpwm_val;
287
288 if (ppsc->b_low_power_enable){
289 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */
290 rtlpriv->cfg->ops->set_hw_reg(hw,
291 HW_VAR_FW_PSMODE_STATUS,
292 (u8 *) (&b_fw_current_inps));
293 rtlpriv->cfg->ops->set_hw_reg(hw,
294 HW_VAR_H2C_FW_PWRMODE,
295 (u8 *) (&ppsc->fwctrl_psmode));
296 rtlhal->ballow_sw_to_change_hwclc = true;
297 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
298
299
300 } else {
301 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */
302 rtlpriv->cfg->ops->set_hw_reg(hw,
303 HW_VAR_FW_PSMODE_STATUS,
304 (u8 *) (&b_fw_current_inps));
305 rtlpriv->cfg->ops->set_hw_reg(hw,
306 HW_VAR_H2C_FW_PWRMODE,
307 (u8 *) (&ppsc->fwctrl_psmode));
308 rtlpriv->cfg->ops->set_hw_reg(hw,
309 HW_VAR_SET_RPWM,
310 (u8 *) (&rpwm_val));
311 }
312
313}
314
315void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
316{
317 struct rtl_priv *rtlpriv = rtl_priv(hw);
318 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
319 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
320 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
321
322 switch (variable) {
323 case HW_VAR_ETHER_ADDR:
324 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
325 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
326 break;
327 case HW_VAR_BSSID:
328 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
329 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
330 break;
331 case HW_VAR_MEDIA_STATUS:
332 val[0] = rtl_read_byte(rtlpriv, REG_CR+2) & 0x3;
333 break;
334 case HW_VAR_SLOT_TIME:
335 *((u8 *)(val)) = mac->slot_time;
336 break;
337 case HW_VAR_BEACON_INTERVAL:
338 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
339 break;
340 case HW_VAR_ATIM_WINDOW:
341 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND);
342 break;
343 case HW_VAR_RCR:
344 *((u32 *) (val)) = rtlpci->receive_config;
345 break;
346 case HW_VAR_RF_STATE:
347 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
348 break;
349 case HW_VAR_FWLPS_RF_ON:{
350 enum rf_pwrstate rfState;
351 u32 val_rcr;
352
353 rtlpriv->cfg->ops->get_hw_reg(hw,
354 HW_VAR_RF_STATE,
355 (u8 *) (&rfState));
356 if (rfState == ERFOFF) {
357 *((bool *) (val)) = true;
358 } else {
359 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
360 val_rcr &= 0x00070000;
361 if (val_rcr)
362 *((bool *) (val)) = false;
363 else
364 *((bool *) (val)) = true;
365 }
366 break;
367 }
368 case HW_VAR_FW_PSMODE_STATUS:
369 *((bool *) (val)) = ppsc->b_fw_current_inpsmode;
370 break;
371 case HW_VAR_CORRECT_TSF:{
372 u64 tsf;
373 u32 *ptsf_low = (u32 *) & tsf;
374 u32 *ptsf_high = ((u32 *) & tsf) + 1;
375
376 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
377 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
378
379 *((u64 *) (val)) = tsf;
380
381 break;
382 }
383 default:
384 RT_TRACE(COMP_ERR, DBG_EMERG,
385 ("switch case not process %x\n",variable));
386 break;
387 }
388}
389
390
391void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
392{
393 struct rtl_priv *rtlpriv = rtl_priv(hw);
394 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
395 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
396 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
397 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
398 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
399 u8 idx;
400
401 switch (variable) {
402 case HW_VAR_ETHER_ADDR:{
403 for (idx = 0; idx < ETH_ALEN; idx++) {
404 rtl_write_byte(rtlpriv, (REG_MACID + idx),
405 val[idx]);
406 }
407 break;
408 }
409 case HW_VAR_BASIC_RATE:{
410 u16 b_rate_cfg = ((u16 *) val)[0];
411 u8 rate_index = 0;
412 b_rate_cfg = b_rate_cfg & 0x15f;
413 b_rate_cfg |= 0x01;
414 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
415 rtl_write_byte(rtlpriv, REG_RRSR + 1,
416 (b_rate_cfg >> 8) & 0xff);
417 while (b_rate_cfg > 0x1) {
418 b_rate_cfg = (b_rate_cfg >> 1);
419 rate_index++;
420 }
421 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
422 rate_index);
423 break;
424 }
425 case HW_VAR_BSSID:{
426 for (idx = 0; idx < ETH_ALEN; idx++) {
427 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
428 val[idx]);
429 }
430 break;
431 }
432 case HW_VAR_SIFS:{
433 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
434 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
435
436 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
437 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
438
439 if (!mac->ht_enable)
440 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
441 0x0e0e);
442 else
443 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
444 *((u16 *) val));
445 break;
446 }
447 case HW_VAR_SLOT_TIME:{
448 u8 e_aci;
449
450 RT_TRACE(COMP_MLME, DBG_LOUD,
451 ("HW_VAR_SLOT_TIME %x\n", val[0]));
452
453 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
454
455 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
456 rtlpriv->cfg->ops->set_hw_reg(hw,
457 HW_VAR_AC_PARAM,
458 (u8 *) (&e_aci));
459 }
460 break;
461 }
462 case HW_VAR_ACK_PREAMBLE:{
463 u8 reg_tmp;
464 u8 short_preamble = (bool) (*(u8 *) val);
465 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
466 if (short_preamble){
467 reg_tmp |= BIT(1);
468 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
469 } else {
470 reg_tmp &= (~BIT(1));
471 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
472 }
473 break;
474 }
475 case HW_VAR_WPA_CONFIG:
476 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
477 break;
478 case HW_VAR_AMPDU_MIN_SPACE:{
479 u8 min_spacing_to_set;
480 u8 sec_min_space;
481
482 min_spacing_to_set = *((u8 *) val);
483 if (min_spacing_to_set <= 7) {
484 sec_min_space = 0;
485
486 if (min_spacing_to_set < sec_min_space)
487 min_spacing_to_set = sec_min_space;
488
489 mac->min_space_cfg = ((mac->min_space_cfg &
490 0xf8) |
491 min_spacing_to_set);
492
493 *val = min_spacing_to_set;
494
495 RT_TRACE(COMP_MLME, DBG_LOUD,
496 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
497 mac->min_space_cfg));
498
499 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
500 mac->min_space_cfg);
501 }
502 break;
503 }
504 case HW_VAR_SHORTGI_DENSITY:{
505 u8 density_to_set;
506
507 density_to_set = *((u8 *) val);
508 mac->min_space_cfg |= (density_to_set << 3);
509
510 RT_TRACE(COMP_MLME, DBG_LOUD,
511 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
512 mac->min_space_cfg));
513
514 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
515 mac->min_space_cfg);
516
517 break;
518 }
519 case HW_VAR_AMPDU_FACTOR:{
520 u32 ampdu_len = (*((u8 *)val));
521 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
522 if(ampdu_len < VHT_AGG_SIZE_128K)
523 ampdu_len = (0x2000 << (*((u8 *)val))) -1;
524 else
525 ampdu_len = 0x1ffff;
526 } else if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
527 if(ampdu_len < HT_AGG_SIZE_64K)
528 ampdu_len = (0x2000 << (*((u8 *)val))) -1;
529 else
530 ampdu_len = 0xffff;
531 }
532 ampdu_len |= BIT(31);
533
534 rtl_write_dword(rtlpriv,
535 REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
536 break;
537 }
538 case HW_VAR_AC_PARAM:{
539 u8 e_aci = *((u8 *) val);
540 rtl8821ae_dm_init_edca_turbo(hw);
541
542 if (rtlpci->acm_method != eAcmWay2_SW)
543 rtlpriv->cfg->ops->set_hw_reg(hw,
544 HW_VAR_ACM_CTRL,
545 (u8 *) (&e_aci));
546 break;
547 }
548 case HW_VAR_ACM_CTRL:{
549 u8 e_aci = *((u8 *) val);
550 union aci_aifsn *p_aci_aifsn =
551 (union aci_aifsn *)(&(mac->ac[0].aifs));
552 u8 acm = p_aci_aifsn->f.acm;
553 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
554
555 acm_ctrl =
556 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
557
558 if (acm) {
559 switch (e_aci) {
560 case AC0_BE:
561 acm_ctrl |= AcmHw_BeqEn;
562 break;
563 case AC2_VI:
564 acm_ctrl |= AcmHw_ViqEn;
565 break;
566 case AC3_VO:
567 acm_ctrl |= AcmHw_VoqEn;
568 break;
569 default:
570 RT_TRACE(COMP_ERR, DBG_WARNING,
571 ("HW_VAR_ACM_CTRL acm set "
572 "failed: eACI is %d\n", acm));
573 break;
574 }
575 } else {
576 switch (e_aci) {
577 case AC0_BE:
578 acm_ctrl &= (~AcmHw_BeqEn);
579 break;
580 case AC2_VI:
581 acm_ctrl &= (~AcmHw_ViqEn);
582 break;
583 case AC3_VO:
584 acm_ctrl &= (~AcmHw_BeqEn);
585 break;
586 default:
587 RT_TRACE(COMP_ERR, DBG_EMERG,
588 ("switch case not process \n"));
589 break;
590 }
591 }
592
593 RT_TRACE(COMP_QOS, DBG_TRACE,
594 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
595 "Write 0x%X\n", acm_ctrl));
596 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
597 break;
598 }
599 case HW_VAR_RCR:{
600 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
601 rtlpci->receive_config = ((u32 *) (val))[0];
602 break;
603 }
604 case HW_VAR_RETRY_LIMIT:{
605 u8 retry_limit = ((u8 *) (val))[0];
606
607 rtl_write_word(rtlpriv, REG_RL,
608 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
609 retry_limit << RETRY_LIMIT_LONG_SHIFT);
610 break;
611 }
612 case HW_VAR_DUAL_TSF_RST:
613 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
614 break;
615 case HW_VAR_EFUSE_BYTES:
616 rtlefuse->efuse_usedbytes = *((u16 *) val);
617 break;
618 case HW_VAR_EFUSE_USAGE:
619 rtlefuse->efuse_usedpercentage = *((u8 *) val);
620 break;
621 case HW_VAR_IO_CMD:
622 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
623 break;
624 case HW_VAR_SET_RPWM:{
625 u8 rpwm_val;
626
627 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
628 udelay(1);
629
630 if (rpwm_val & BIT(7)) {
631 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
632 (*(u8 *) val));
633 } else {
634 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
635 ((*(u8 *) val) | BIT(7)));
636 }
637
638 break;
639 }
640 case HW_VAR_H2C_FW_PWRMODE:{
641 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
642 break;
643 }
644 case HW_VAR_FW_PSMODE_STATUS:
645 ppsc->b_fw_current_inpsmode = *((bool *) val);
646 break;
647
648 case HW_VAR_RESUME_CLK_ON:
649 _rtl8821ae_set_fw_ps_rf_on(hw);
650 break;
651
652 case HW_VAR_FW_LPS_ACTION:{
653 bool b_enter_fwlps = *((bool *) val);
654
655 if (b_enter_fwlps)
656 _rtl8821ae_fwlps_enter(hw);
657 else
658 _rtl8821ae_fwlps_leave(hw);
659
660 break;
661 }
662
663 case HW_VAR_H2C_FW_JOINBSSRPT:{
664 u8 mstatus = (*(u8 *) val);
665 u8 tmp_regcr, tmp_reg422,bcnvalid_reg;
666 u8 count = 0, dlbcn_count = 0;
667 bool b_recover = false;
668
669 if (mstatus == RT_MEDIA_CONNECT) {
670 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
671 NULL);
672
673 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
674 rtl_write_byte(rtlpriv, REG_CR + 1,
675 (tmp_regcr | BIT(0)));
676
677 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
678 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
679
680 tmp_reg422 =
681 rtl_read_byte(rtlpriv,
682 REG_FWHW_TXQ_CTRL + 2);
683 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
684 tmp_reg422 & (~BIT(6)));
685 if (tmp_reg422 & BIT(6))
686 b_recover = true;
687
688 do {
689 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
690 rtl_write_byte(rtlpriv, REG_TDECTRL+2,(bcnvalid_reg | BIT(0)));
691 _rtl8821ae_return_beacon_queue_skb(hw);
692
693 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
694 rtl8812ae_set_fw_rsvdpagepkt(hw, 0);
695 else
696 rtl8821ae_set_fw_rsvdpagepkt(hw, 0);
697 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
698 count = 0;
699 while (!(bcnvalid_reg & BIT(0)) && count <20){
700 count++;
701 udelay(10);
702 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL+2);
703 }
704 dlbcn_count++;
705 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count <5);
706
707 if (bcnvalid_reg & BIT(0))
708 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
709
710 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
711 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
712
713 if (b_recover) {
714 rtl_write_byte(rtlpriv,
715 REG_FWHW_TXQ_CTRL + 2,
716 tmp_reg422);
717 }
718
719 rtl_write_byte(rtlpriv, REG_CR + 1,
720 (tmp_regcr & ~(BIT(0))));
721 }
722 rtl8821ae_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
723
724 break;
725 }
726 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{
727 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *) val));
728 break;
729 }
730
731 case HW_VAR_AID:{
732 u16 u2btmp;
733 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
734 u2btmp &= 0xC000;
735 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
736 mac->assoc_id));
737
738 break;
739 }
740 case HW_VAR_CORRECT_TSF:{
741 u8 btype_ibss = ((u8 *) (val))[0];
742
743 if (btype_ibss == true)
744 _rtl8821ae_stop_tx_beacon(hw);
745
746 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
747
748 rtl_write_dword(rtlpriv, REG_TSFTR,
749 (u32) (mac->tsf & 0xffffffff));
750 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
751 (u32) ((mac->tsf >> 32) & 0xffffffff));
752
753 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
754
755 if (btype_ibss == true)
756 _rtl8821ae_resume_tx_beacon(hw);
757
758 break;
759
760 }
761 case HW_VAR_NAV_UPPER: {
762 u32 us_nav_upper = ((u32)*val);
763
764 if(us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF)
765 {
766 RT_TRACE(COMP_INIT , DBG_WARNING,
767 ("The setting value (0x%08X us) of NAV_UPPER"
768 " is larger than (%d * 0xFF)!!!\n",
769 us_nav_upper, HAL_92C_NAV_UPPER_UNIT));
770 break;
771 }
772 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
773 ((u8)((us_nav_upper + HAL_92C_NAV_UPPER_UNIT - 1) / HAL_92C_NAV_UPPER_UNIT)));
774 break;
775 }
776 case HW_VAR_KEEP_ALIVE: {
777 u8 array[2];
778 array[0] = 0xff;
779 array[1] = *((u8 *)val);
780 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2, array);
781 }
782 default:
783 RT_TRACE(COMP_ERR, DBG_EMERG, ("switch case "
784 "not process %x\n",variable));
785 break;
786 }
787}
788
789static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
790{
791 struct rtl_priv *rtlpriv = rtl_priv(hw);
792 bool status = true;
793 long count = 0;
794 u32 value = _LLT_INIT_ADDR(address) |
795 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
796
797 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
798
799 do {
800 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
801 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
802 break;
803
804 if (count > POLLING_LLT_THRESHOLD) {
805 RT_TRACE(COMP_ERR, DBG_EMERG,
806 ("Failed to polling write LLT done at "
807 "address %d!\n", address));
808 status = false;
809 break;
810 }
811 } while (++count);
812
813 return status;
814}
815
816static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
817{
818 struct rtl_priv *rtlpriv = rtl_priv(hw);
819 unsigned short i;
820 u8 txpktbuf_bndy;
821 u8 maxPage;
822 bool status;
823
824 maxPage = 255;
825 txpktbuf_bndy = 0xF8;
826
827
828 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
829 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
830
831 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
832
833 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
834 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
835
836 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
837 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
838
839 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
840 status = _rtl8821ae_llt_write(hw, i, i + 1);
841 if (true != status)
842 return status;
843 }
844
845 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
846 if (true != status)
847 return status;
848
849 for (i = txpktbuf_bndy; i < maxPage; i++) {
850 status = _rtl8821ae_llt_write(hw, i, (i + 1));
851 if (true != status)
852 return status;
853 }
854
855 status = _rtl8821ae_llt_write(hw, maxPage, txpktbuf_bndy);
856 if (true != status)
857 return status;
858
859 rtl_write_dword(rtlpriv, REG_RQPN, 0x80e70808);
860 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
861
862 return true;
863}
864
865static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
866{
867 struct rtl_priv *rtlpriv = rtl_priv(hw);
868 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
869 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
870 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
871 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
872
873 if (rtlpriv->rtlhal.up_first_time)
874 return;
875
876 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
877 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
878 rtl8812ae_sw_led_on(hw, pLed0);
879 else
880 rtl8821ae_sw_led_on(hw, pLed0);
881 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
882 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
883 rtl8812ae_sw_led_on(hw, pLed0);
884 else
885 rtl8821ae_sw_led_on(hw, pLed0);
886 else
887 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
888 rtl8812ae_sw_led_off(hw, pLed0);
889 else
890 rtl8821ae_sw_led_off(hw, pLed0);
891}
892
893static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
894{
895 struct rtl_priv *rtlpriv = rtl_priv(hw);
896 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
897 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
898
899 u8 bytetmp = 0;
900 u16 wordtmp = 0;
901 bool b_mac_func_enable = rtlhal->b_mac_func_enable;
902
903 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
904
905 /*Auto Power Down to CHIP-off State*/
906 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
907 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
908
909 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
910 /* HW Power on sequence*/
911 if(!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
912 PWR_INTF_PCI_MSK, RTL8812_NIC_ENABLE_FLOW)) {
913 RT_TRACE(COMP_INIT,DBG_LOUD,("init 8812 MAC Fail as power on failure\n"));
914 return false;
915 }
916 } else {
917 /* HW Power on sequence */
918 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK, PWR_FAB_ALL_MSK,
919 PWR_INTF_PCI_MSK, RTL8821A_NIC_ENABLE_FLOW)){
920 RT_TRACE(COMP_INIT,DBG_LOUD,("init 8821 MAC Fail as power on failure\n"));
921 return false;
922 }
923 }
924
925 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
926 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
927
928 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
929 bytetmp = 0xff;
930 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
931 mdelay(2);
932
933 bytetmp |= 0x7f;
934 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
935 mdelay(2);
936
937 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
938 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
939 if (bytetmp & BIT(0)) {
940 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
941 bytetmp |= BIT(6);
942 rtl_write_byte(rtlpriv, 0x7c, bytetmp);
943 }
944 }
945
946 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
947 bytetmp &= ~BIT(4);
948 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
949
950 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
951
952 if (!b_mac_func_enable) {
953 if (!_rtl8821ae_llt_table_init(hw))
954 return false;
955 }
956
957 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
958 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
959
960 /* Enable FW Beamformer Interrupt */
961 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
962 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
963
964 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
965 wordtmp &= 0xf;
966 wordtmp |= 0xF5B1;
967 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
968
969 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
970 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
971 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
972 /*low address*/
973 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
974 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
975 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
976 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
977 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
978 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
979 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
980 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
981 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
982 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
983 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
984 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
985 rtl_write_dword(rtlpriv, REG_HQ_DESA,
986 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
987 rtl_write_dword(rtlpriv, REG_RX_DESA,
988 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
989
990 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
991
992 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
993
994 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
995 _rtl8821ae_gen_refresh_led_state(hw);
996
997 return true;
998}
999
1000static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1001{
1002 struct rtl_priv *rtlpriv = rtl_priv(hw);
1003 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1004 u32 reg_rrsr;
1005
1006 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1007
1008 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1009 /* ARFB table 9 for 11ac 5G 2SS */
1010 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1011 /* ARFB table 10 for 11ac 5G 1SS */
1012 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1013 /* ARFB table 11 for 11ac 24G 1SS */
1014 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1015 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1016 /* ARFB table 12 for 11ac 24G 1SS */
1017 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1018 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1019 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1020 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1021 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1022
1023 /*Set retry limit*/
1024 rtl_write_word(rtlpriv, REG_RL, 0x0707);
1025
1026
1027 /* Set Data / Response auto rate fallack retry count*/
1028 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1029 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1030 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1031 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1032
1033 rtlpci->reg_bcn_ctrl_val = 0x1d;
1034 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1035
1036 /* TBTT prohibit hold time. Suggested by designer TimChen. */
1037 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1,0xff); // 8 ms
1038
1039 /* AGGR_BK_TIME Reg51A 0x16 */
1040 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1041
1042 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1043 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1044
1045 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1046 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1047 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1048}
1049
1050static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1051{
1052 u16 ret = 0;
1053 u8 tmp = 0, count = 0;
1054
1055 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1056 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6) ;
1057 count = 0;
1058 while (tmp && count < 20) {
1059 udelay(10);
1060 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1061 count++;
1062 }
1063 if (0 == tmp)
1064 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1065
1066 return ret;
1067}
1068
1069void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1070{
1071 u8 tmp = 0, count = 0;
1072
1073 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1074 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1075 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5) ;
1076 count = 0;
1077 while (tmp && count < 20) {
1078 udelay(10);
1079 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1080 count++;
1081 }
1082}
1083
1084static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1085{
1086 u16 read_addr = addr & 0xfffc;
1087 u8 tmp = 0, count = 0, ret = 0;
1088
1089 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1090 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1091 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1092 count = 0;
1093 while (tmp && count < 20) {
1094 udelay(10);
1095 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1096 count++;
1097 }
1098 if (0 == tmp) {
1099 read_addr = REG_DBI_RDATA + addr % 4;
1100 ret = rtl_read_word(rtlpriv, read_addr);
1101 }
1102 return ret;
1103}
1104
1105void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1106{
1107 u8 tmp = 0, count = 0;
1108 u16 wrtie_addr, remainder = addr % 4;
1109
1110 wrtie_addr = REG_DBI_WDATA + remainder;
1111 rtl_write_byte(rtlpriv, wrtie_addr, data);
1112
1113 wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1114 rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1115
1116 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1117
1118 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1119 count = 0;
1120 while (tmp && count < 20) {
1121 udelay(10);
1122 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1123 count++;
1124 }
1125
1126}
1127
1128static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1129{
1130 struct rtl_priv *rtlpriv = rtl_priv(hw);
1131 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1132 u8 tmp;
1133
1134 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1135 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1136 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1137
1138 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1139 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1140 }
1141
1142 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1143 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7));
1144
1145 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1146 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1147
1148 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1149 {
1150 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1151 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1152 }
1153}
1154
1155void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1156{
1157 struct rtl_priv *rtlpriv = rtl_priv(hw);
1158 u8 sec_reg_value;
1159 u8 tmp;
1160
1161 RT_TRACE(COMP_INIT, DBG_DMESG,
1162 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1163 rtlpriv->sec.pairwise_enc_algorithm,
1164 rtlpriv->sec.group_enc_algorithm));
1165
1166 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1167 RT_TRACE(COMP_SEC, DBG_DMESG, ("not open hw encryption\n"));
1168 return;
1169 }
1170
1171 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1172
1173 if (rtlpriv->sec.use_defaultkey) {
1174 sec_reg_value |= SCR_TxUseDK;
1175 sec_reg_value |= SCR_RxUseDK;
1176 }
1177
1178 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1179
1180 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1181 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1182
1183 RT_TRACE(COMP_SEC, DBG_DMESG,
1184 ("The SECR-value %x \n", sec_reg_value));
1185
1186 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1187
1188}
1189
1190#if 0
1191bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1192{
1193 struct rtl_priv *rtlpriv = rtl_priv(hw);
1194 u8 tmp;
1195 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL+3);
1196 if (!(tmp&BIT(2))) {
1197 rtl_write_byte(rtlpriv, REG_DBI_CTRL+3, tmp|BIT(2));
1198 mdelay(100);
1199 }
1200
1201 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL+3);
1202 if (tmp&BIT(0) || tmp&BIT(1)) {
1203 RT_TRACE(COMP_INIT, DBG_LOUD,
1204 ("rtl8821ae_check_pcie_dma_hang(): TRUE! Reset PCIE DMA!\n"));
1205 return true;
1206 } else {
1207 return false;
1208 }
1209}
1210
1211void _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1212 bool mac_power_on, bool watch_dog)
1213{
1214 struct rtl_priv *rtlpriv = rtl_priv(hw);
1215 u8 tmp;
1216 bool release_mac_rx_pause;
1217 u8 backup_pcie_dma_pause;
1218
1219 RT_TRACE(COMP_INIT, DBG_LOUD, ("_rtl8821ae_reset_pcie_interface_dma()\n"));
1220
1221 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1222 tmp &= ~BIT(1);
1223 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1224 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1225 tmp |= BIT2;
1226 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1227
1228 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1229 if (tmp & BIT(2)) {
1230 release_mac_rx_pause = false;
1231 } else {
1232 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp | BIT(2));
1233 release_mac_rx_pause = true;
1234 }
1235 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+1);
1236 if (backup_pcie_dma_pause != 0xFF)
1237 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1238
1239 if (mac_power_on)
1240 rtl_write_byte(rtlpriv, REG_CR, 0);
1241
1242 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1243 tmp &= ~BIT(0);
1244 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, tmp);
1245
1246 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1247 tmp |= ~BIT(0);
1248 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, tmp);
1249
1250 if (mac_power_on)
1251 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1252
1253 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL+2);
1254 tmp |= BIT1;
1255 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL+2, tmp);
1256
1257 if (watch_dog) {
1258 u32 rqpn = 0;
1259 u32 rqpn_npq = 0;
1260 u8 tx_page_boundary = _RQPN_Init_8812E(Adapter, &rqpn_npq, &rqpn);
1261
1262 if(LLT_table_init_8812(Adapter, TX_PAGE_BOUNDARY, RQPN, RQPN_NPQ) == RT_STATUS_FAILURE)
1263 return false;
1264
1265 PlatformAcquireSpinLock(Adapter, RT_RX_SPINLOCK);
1266 PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
1267
1268 // <1> Reset Tx descriptor
1269 Adapter->HalFunc.ResetTxDescHandler(Adapter,Adapter->NumTxDesc);
1270
1271 // <2> Reset Rx descriptor
1272 Adapter->HalFunc.ResetRxDescHandler(Adapter,Adapter->NumRxDesc);
1273
1274 // <3> Reset RFDs
1275 FreeRFDs( Adapter, TRUE);
1276
1277 // <4> Reset TCBs
1278 FreeTCBs( Adapter, TRUE);
1279
1280 // We should set all Rx desc own bit to 1 to prevent from RDU after enable Rx DMA. 2013.02.18, by tynli.
1281 PrepareAllRxDescBuffer(Adapter);
1282
1283 PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
1284 PlatformReleaseSpinLock(Adapter, RT_RX_SPINLOCK);
1285
1286 //
1287 // Initialize TRx DMA address.
1288 //
1289 // Because set 0x100 to 0x0 will cause the Rx descriptor address 0x340 be cleared to zero on 88EE,
1290 // we should re-initialize Rx desc. address before enable DMA. 2012.11.07. by tynli.
1291 InitTRxDescHwAddress8812AE(Adapter);
1292 }
1293
1294 // In MAC power on state, BB and RF maybe in ON state, if we release TRx DMA here
1295 // it will cause packets to be started to Tx/Rx, so we release Tx/Rx DMA later.
1296 if(!bInMACPowerOn || bInWatchDog)
1297 {
1298 // 8. release TRX DMA
1299 //write 0x284 bit[18] = 1'b0
1300 //write 0x301 = 0x00
1301 if(bReleaseMACRxPause)
1302 {
1303 u1Tmp = PlatformEFIORead1Byte(Adapter, REG_RXDMA_CONTROL);
1304 PlatformEFIOWrite1Byte(Adapter, REG_RXDMA_CONTROL, (u1Tmp&~BIT2));
1305 }
1306 PlatformEFIOWrite1Byte(Adapter, REG_PCIE_CTRL_REG+1, BackUpPcieDMAPause);
1307 }
1308
1309 if(IS_HARDWARE_TYPE_8821E(Adapter))
1310 {
1311 //9. lock system register
1312 // write 0xCC bit[2] = 1'b0
1313 u1Tmp = PlatformEFIORead1Byte(Adapter, REG_PMC_DBG_CTRL2_8723B);
1314 u1Tmp &= ~(BIT2);
1315 PlatformEFIOWrite1Byte(Adapter, REG_PMC_DBG_CTRL2_8723B, u1Tmp);
1316 }
1317
1318 return RT_STATUS_SUCCESS;
1319}
1320#endif
1321
1322// Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ----------
1323#define MAC_ID_STATIC_FOR_DEFAULT_PORT 0
1324#define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1
1325#define MAC_ID_STATIC_FOR_BT_CLIENT_START 2
1326#define MAC_ID_STATIC_FOR_BT_CLIENT_END 3
1327// -----------------------------------------------------------
1328
1329void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1330{
1331 struct rtl_priv *rtlpriv = rtl_priv(hw);
1332 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1, \
1333 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, \
1334 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1335
1336 rtlpriv->cfg->ops->set_hw_reg(hw, \
1337 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1338
1339 RT_TRACE(COMP_INIT,DBG_LOUD, \
1340 ("Initialize MacId media status: from %d to %d\n", \
1341 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST, \
1342 MAC_ID_STATIC_FOR_BT_CLIENT_END));
1343}
1344
1345int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1346{
1347 struct rtl_priv *rtlpriv = rtl_priv(hw);
1348 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1349 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1350 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1351 bool rtstatus = true;
1352 int err;
1353 u8 tmp_u1b;
1354 u32 nav_upper = WIFI_NAV_UPPER_US;
1355
1356 rtlpriv->rtlhal.being_init_adapter = true;
1357 rtlpriv->intf_ops->disable_aspm(hw);
1358
1359 /*YP wowlan not considered*/
1360
1361 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1362 if (tmp_u1b!=0 && tmp_u1b != 0xEA) {
1363 rtlhal->b_mac_func_enable = true;
1364 RT_TRACE(COMP_INIT,DBG_LOUD,(" MAC has already power on.\n"));
1365 } else {
1366 rtlhal->b_mac_func_enable = false;
1367 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1368 }
1369
1370/* if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1371 _rtl8821ae_reset_pcie_interface_dma(hw,rtlhal->b_mac_func_enable,false);
1372 rtlhal->b_mac_func_enable = false;
1373 } */
1374
1375 rtstatus = _rtl8821ae_init_mac(hw);
1376 if (rtstatus != true) {
1377 RT_TRACE(COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
1378 err = 1;
1379 return err;
1380 }
1381
1382 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1383 tmp_u1b &= 0x7F;
1384 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1385
1386 err = rtl8821ae_download_fw(hw, false);
1387 if (err) {
1388 RT_TRACE(COMP_ERR, DBG_WARNING,
1389 ("Failed to download FW. Init HW "
1390 "without FW now..\n"));
1391 err = 1;
1392 rtlhal->bfw_ready = false;
1393 return err;
1394 } else {
1395 rtlhal->bfw_ready = true;
1396 }
1397 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1398 rtlhal->bfw_clk_change_in_progress = false;
1399 rtlhal->ballow_sw_to_change_hwclc = false;
1400 rtlhal->last_hmeboxnum = 0;
1401
1402 /*SIC_Init(Adapter);
1403 if(pHalData->AMPDUBurstMode)
1404 PlatformEFIOWrite1Byte(Adapter,REG_AMPDU_BURST_MODE_8812, 0x7F);*/
1405
1406 rtl8821ae_phy_mac_config(hw);
1407 /* because last function modify RCR, so we update
1408 * rcr var here, or TP will unstable for receive_config
1409 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1410 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1411 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1412 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1413 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1414 rtl8821ae_phy_bb_config(hw);
1415
1416 rtl8821ae_phy_rf_config(hw);
1417
1418 _rtl8821ae_hw_configure(hw);
1419
1420 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1421
1422 /*set wireless mode*/
1423
1424 rtlhal->b_mac_func_enable = true;
1425
1426 rtl_cam_reset_all_entry(hw);
1427
1428 rtl8821ae_enable_hw_security_config(hw);
1429
1430 ppsc->rfpwr_state = ERFON;
1431
1432 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1433 _rtl8821ae_enable_aspm_back_door(hw);
1434 rtlpriv->intf_ops->enable_aspm(hw);
1435
1436 //rtl8821ae_bt_hw_init(hw);
1437 rtlpriv->rtlhal.being_init_adapter = false;
1438
1439 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
1440
1441 //rtl8821ae_dm_check_txpower_tracking(hw);
1442 //rtl8821ae_phy_lc_calibrate(hw);
1443
1444 /* Release Rx DMA*/
1445 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1446 if (tmp_u1b & BIT(2)) {
1447 /* Release Rx DMA if needed*/
1448 tmp_u1b &= ~BIT(2);
1449 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1450 }
1451
1452 /* Release Tx/Rx PCIE DMA if*/
1453 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1454
1455 rtl8821ae_dm_init(hw);
1456 rtl8821ae_macid_initialize_mediastatus(hw);
1457
1458 RT_TRACE(COMP_INIT, DBG_LOUD, ("rtl8821ae_hw_init() <====\n"));
1459 return err;
1460}
1461
1462static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
1463{
1464 struct rtl_priv *rtlpriv = rtl_priv(hw);
1465 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1466 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1467 enum version_8821ae version = VERSION_UNKNOWN;
1468 u32 value32;
1469
1470 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1471 RT_TRACE(COMP_INIT, DBG_LOUD, ("ReadChipVersion8812A 0xF0 = 0x%x \n", value32));
1472
1473
1474
1475 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1476 rtlphy->rf_type = RF_2T2R;
1477 else if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
1478 rtlphy->rf_type = RF_1T1R;
1479
1480 RT_TRACE(COMP_INIT, DBG_LOUD, ("RF_Type is %x!!\n", rtlphy->rf_type));
1481
1482
1483 if (value32 & TRP_VAUX_EN)
1484 {
1485 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1486 {
1487 if(rtlphy->rf_type == RF_2T2R)
1488 version = VERSION_TEST_CHIP_2T2R_8812;
1489 else
1490 version = VERSION_TEST_CHIP_1T1R_8812;
1491 }
1492 else
1493 version = VERSION_TEST_CHIP_8821;
1494 } else {
1495 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1496 {
1497 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) +1 ;
1498
1499 if(rtlphy->rf_type == RF_2T2R)
1500 version = (enum version_8821ae)(CHIP_8812 | NORMAL_CHIP | RF_TYPE_2T2R);
1501 else
1502 version = (enum version_8821ae)(CHIP_8812 | NORMAL_CHIP);
1503
1504 version = (enum version_8821ae)(version| (rtl_id << 12));
1505 }
1506 else if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
1507 {
1508 u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
1509
1510 version = (enum version_8821ae)(CHIP_8821 | NORMAL_CHIP | rtl_id);
1511 }
1512 }
1513
1514 RT_TRACE(COMP_INIT, DBG_LOUD,
1515 ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1516 "RF_2T2R" : "RF_1T1R"));
1517
1518 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
1519 {
1520 /*WL_HWROF_EN.*/
1521 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
1522 rtlphy->hw_rof_enable= ((value32 & WL_HWROF_EN) ? 1 : 0);
1523 }
1524
1525 switch(version)
1526 {
1527 case VERSION_TEST_CHIP_1T1R_8812:
1528 RT_TRACE(COMP_INIT, DBG_LOUD,
1529 ("Chip Version ID: VERSION_TEST_CHIP_1T1R_8812.\n"));
1530 break;
1531 case VERSION_TEST_CHIP_2T2R_8812:
1532 RT_TRACE(COMP_INIT, DBG_LOUD,
1533 ("Chip Version ID: VERSION_TEST_CHIP_2T2R_8812.\n"));
1534 break;
1535 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
1536 RT_TRACE(COMP_INIT, DBG_LOUD,
1537 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812.\n"));
1538 break;
1539 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
1540 RT_TRACE(COMP_INIT, DBG_LOUD,
1541 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812.\n"));
1542 break;
1543 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
1544 RT_TRACE(COMP_INIT, DBG_LOUD,
1545 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT.\n"));
1546 break;
1547 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
1548 RT_TRACE(COMP_INIT, DBG_LOUD,
1549 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT.\n"));
1550 break;
1551 case VERSION_TEST_CHIP_8821:
1552 RT_TRACE(COMP_INIT, DBG_LOUD,
1553 ("Chip Version ID: VERSION_TEST_CHIP_8821.\n"));
1554 break;
1555 case VERSION_NORMAL_TSMC_CHIP_8821:
1556 RT_TRACE(COMP_INIT, DBG_LOUD,
1557 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT.\n"));
1558 break;
1559 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
1560 RT_TRACE(COMP_INIT, DBG_LOUD,
1561 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT.\n"));
1562 break;
1563 default:
1564 RT_TRACE(COMP_INIT, DBG_LOUD,
1565 ("Chip Version ID: Unknow (0x%X).\n", version));
1566 break;
1567 }
1568
1569 return version;
1570}
1571
1572static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
1573 enum nl80211_iftype type)
1574{
1575 struct rtl_priv *rtlpriv = rtl_priv(hw);
1576 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1577 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1578 bt_msr &= 0xfc;
1579
1580 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1581 RT_TRACE(COMP_BEACON, DBG_LOUD,
1582 ("clear 0x550 when set HW_VAR_MEDIA_STATUS\n"));
1583
1584 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1585 type == NL80211_IFTYPE_STATION) {
1586 _rtl8821ae_stop_tx_beacon(hw);
1587 _rtl8821ae_enable_bcn_sub_func(hw);
1588 } else if (type == NL80211_IFTYPE_ADHOC ||
1589 type == NL80211_IFTYPE_AP) {
1590 _rtl8821ae_resume_tx_beacon(hw);
1591 _rtl8821ae_disable_bcn_sub_func(hw);
1592 } else {
1593 RT_TRACE(COMP_ERR, DBG_WARNING,("Set HW_VAR_MEDIA_STATUS: "
1594 "No such media status(%x).\n", type));
1595 }
1596
1597 switch (type) {
1598 case NL80211_IFTYPE_UNSPECIFIED:
1599 bt_msr |= MSR_NOLINK;
1600 ledaction = LED_CTL_LINK;
1601 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to NO LINK!\n"));
1602 break;
1603 case NL80211_IFTYPE_ADHOC:
1604 bt_msr |= MSR_ADHOC;
1605 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to Ad Hoc!\n"));
1606 break;
1607 case NL80211_IFTYPE_STATION:
1608 bt_msr |= MSR_INFRA;
1609 ledaction = LED_CTL_LINK;
1610 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to STA!\n"));
1611 break;
1612 case NL80211_IFTYPE_AP:
1613 bt_msr |= MSR_AP;
1614 RT_TRACE(COMP_INIT, DBG_TRACE, ("Set Network type to AP!\n"));
1615 break;
1616 default:
1617 RT_TRACE(COMP_ERR, DBG_EMERG, ("Network type %d not support!\n", type));
1618 return 1;
1619 break;
1620
1621 }
1622
1623 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1624 rtlpriv->cfg->ops->led_control(hw, ledaction);
1625 if ((bt_msr & 0xfc) == MSR_AP)
1626 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1627 else
1628 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1629
1630 return 0;
1631}
1632
1633void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1634{
1635 struct rtl_priv *rtlpriv = rtl_priv(hw);
1636 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1637 u32 reg_rcr = rtlpci->receive_config;
1638
1639 if (rtlpriv->psc.rfpwr_state != ERFON)
1640 return;
1641
1642 if (check_bssid == true) {
1643 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1644 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1645 (u8 *) (&reg_rcr));
1646 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
1647 } else if (check_bssid == false) {
1648 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1649 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
1650 rtlpriv->cfg->ops->set_hw_reg(hw,
1651 HW_VAR_RCR, (u8 *) (&reg_rcr));
1652 }
1653
1654}
1655
1656int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1657{
1658 struct rtl_priv *rtlpriv = rtl_priv(hw);
1659
1660 RT_TRACE(COMP_INIT, DBG_LOUD, ("rtl8821ae_set_network_type!\n"));
1661
1662 if (_rtl8821ae_set_media_status(hw, type))
1663 return -EOPNOTSUPP;
1664
1665 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1666 if (type != NL80211_IFTYPE_AP)
1667 rtl8821ae_set_check_bssid(hw, true);
1668 } else {
1669 rtl8821ae_set_check_bssid(hw, false);
1670 }
1671
1672 return 0;
1673}
1674
1675/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1676void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
1677{
1678 struct rtl_priv *rtlpriv = rtl_priv(hw);
1679 rtl8821ae_dm_init_edca_turbo(hw);
1680 switch (aci) {
1681 case AC1_BK:
1682 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1683 break;
1684 case AC0_BE:
1685 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1686 break;
1687 case AC2_VI:
1688 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1689 break;
1690 case AC3_VO:
1691 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1692 break;
1693 default:
1694 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1695 break;
1696 }
1697}
1698
1699void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
1700{
1701 struct rtl_priv *rtlpriv = rtl_priv(hw);
1702 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1703
1704 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1705 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1706 rtlpci->irq_enabled = true;
1707 /* there are some C2H CMDs have been sent before system interrupt is enabled, e.g., C2H, CPWM.
1708 *So we need to clear all C2H events that FW has notified, otherwise FW won't schedule any commands anymore.
1709 */
1710 //rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1711 /*enable system interrupt*/
1712 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1713}
1714
1715void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
1716{
1717 struct rtl_priv *rtlpriv = rtl_priv(hw);
1718 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1719
1720 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1721 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1722 rtlpci->irq_enabled = false;
1723 synchronize_irq(rtlpci->pdev->irq);
1724}
1725
1726static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1727{
1728 struct rtl_priv *rtlpriv = rtl_priv(hw);
1729 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1730 u8 u1b_tmp;
1731
1732 rtlhal->b_mac_func_enable = false;
1733
1734 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1735 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1736 /* 1. Run LPS WL RFOFF flow */
1737 //RT_TRACE(COMP_INIT, DBG_LOUD, ("=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n"));
1738 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1739 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1740 }
1741 /* 2. 0x1F[7:0] = 0 */
1742 /* turn off RF */
1743 //rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1744 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1745 rtlhal->bfw_ready ) {
1746 rtl8821ae_firmware_selfreset(hw);
1747 }
1748
1749 /* Reset MCU. Suggested by Filen. */
1750 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1751 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1752
1753 /* g. MCUFWDL 0x80[1:0]=0 */
1754 /* reset MCU ready status */
1755 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1756
1757 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1758 /* HW card disable configuration. */
1759 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1760 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1761 } else {
1762 /* HW card disable configuration. */
1763 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1764 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1765 }
1766
1767 /* Reset MCU IO Wrapper */
1768 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1769 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1770 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1771 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1772
1773 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1774 /* lock ISO/CLK/Power control register */
1775 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1776}
1777
1778void rtl8821ae_card_disable(struct ieee80211_hw *hw)
1779{
1780 struct rtl_priv *rtlpriv = rtl_priv(hw);
1781 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1782 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1783 enum nl80211_iftype opmode;
1784
1785 RT_TRACE(COMP_INIT, DBG_LOUD,
1786 ("rtl8821ae_card_disable.\n"));
1787
1788 mac->link_state = MAC80211_NOLINK;
1789 opmode = NL80211_IFTYPE_UNSPECIFIED;
1790 _rtl8821ae_set_media_status(hw, opmode);
1791 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1792 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1793 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1794 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1795 _rtl8821ae_poweroff_adapter(hw);
1796
1797 /* after power off we should do iqk again */
1798 rtlpriv->phy.iqk_initialized = false;
1799}
1800
1801void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
1802 u32 *p_inta, u32 *p_intb)
1803{
1804 struct rtl_priv *rtlpriv = rtl_priv(hw);
1805 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1806
1807 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1808 rtl_write_dword(rtlpriv, ISR, *p_inta);
1809
1810
1811 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1812 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1813
1814}
1815
1816
1817void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
1818{
1819
1820 struct rtl_priv *rtlpriv = rtl_priv(hw);
1821 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1822 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1823 u16 bcn_interval, atim_window;
1824
1825 bcn_interval = mac->beacon_interval;
1826 atim_window = 2; /*FIX MERGE */
1827 rtl8821ae_disable_interrupt(hw);
1828 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1829 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1830 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1831 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1832 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1833 rtl_write_byte(rtlpriv, 0x606, 0x30);
1834 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1835 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1836 rtl8821ae_enable_interrupt(hw);
1837}
1838
1839void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
1840{
1841 struct rtl_priv *rtlpriv = rtl_priv(hw);
1842 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1843 u16 bcn_interval = mac->beacon_interval;
1844
1845 RT_TRACE(COMP_BEACON, DBG_DMESG,
1846 ("beacon_interval:%d\n", bcn_interval));
1847 rtl8821ae_disable_interrupt(hw);
1848 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1849 rtl8821ae_enable_interrupt(hw);
1850}
1851
1852void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
1853 u32 add_msr, u32 rm_msr)
1854{
1855 struct rtl_priv *rtlpriv = rtl_priv(hw);
1856 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1857
1858 RT_TRACE(COMP_INTR, DBG_LOUD,
1859 ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1860
1861 if (add_msr)
1862 rtlpci->irq_mask[0] |= add_msr;
1863 if (rm_msr)
1864 rtlpci->irq_mask[0] &= (~rm_msr);
1865 rtl8821ae_disable_interrupt(hw);
1866 rtl8821ae_enable_interrupt(hw);
1867}
1868
1869static u8 _rtl8821ae_get_chnl_group(u8 chnl)
1870{
1871 u8 group = 0;
1872
1873 if (chnl <= 14) {
1874 if (1 <= chnl && chnl <= 2 )
1875 group = 0;
1876 else if (3 <= chnl && chnl <= 5 )
1877 group = 1;
1878 else if (6 <= chnl && chnl <= 8 )
1879 group = 2;
1880 else if (9 <= chnl && chnl <= 11)
1881 group = 3;
1882 else /*if (12 <= chnl && chnl <= 14)*/
1883 group = 4;
1884 } else {
1885 if (36 <= chnl && chnl <= 42)
1886 group = 0;
1887 else if (44 <= chnl && chnl <= 48)
1888 group = 1;
1889 else if (50 <= chnl && chnl <= 58)
1890 group = 2;
1891 else if (60 <= chnl && chnl <= 64)
1892 group = 3;
1893 else if (100 <= chnl && chnl <= 106)
1894 group = 4;
1895 else if (108 <= chnl && chnl <= 114)
1896 group = 5;
1897 else if (116 <= chnl && chnl <= 122)
1898 group = 6;
1899 else if (124 <= chnl && chnl <= 130)
1900 group = 7;
1901 else if (132 <= chnl && chnl <= 138)
1902 group = 8;
1903 else if (140 <= chnl && chnl <= 144)
1904 group = 9;
1905 else if (149 <= chnl && chnl <= 155)
1906 group = 10;
1907 else if (157 <= chnl && chnl <= 161)
1908 group = 11;
1909 else if (165 <= chnl && chnl <= 171)
1910 group = 12;
1911 else if (173 <= chnl && chnl <= 177)
1912 group = 13;
1913 else
1914 /*RT_TRACE(COMP_EFUSE,DBG_LOUD,
1915 ("5G, Channel %d in Group not found \n",chnl));*/
1916 RT_ASSERT(!COMP_EFUSE,
1917 ("5G, Channel %d in Group not found \n",chnl));
1918 }
1919 return group;
1920}
1921
1922static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
1923 struct txpower_info_2g *pwrinfo24g,
1924 struct txpower_info_5g *pwrinfo5g,
1925 bool autoload_fail,
1926 u8 *hwinfo)
1927{
1928 struct rtl_priv *rtlpriv = rtl_priv(hw);
1929 u32 rfPath, eeAddr=EEPROM_TX_PWR_INX, group,TxCount=0;
1930
1931 RT_TRACE(COMP_INIT, DBG_LOUD, ("hal_ReadPowerValueFromPROM8821ae(): PROMContent[0x%x]=0x%x\n", (eeAddr+1), hwinfo[eeAddr+1]));
1932 if (0xFF == hwinfo[eeAddr+1]) /*YJ,add,120316*/
1933 autoload_fail = true;
1934
1935 if (autoload_fail)
1936 {
1937 RT_TRACE(COMP_INIT, DBG_LOUD, ("auto load fail : Use Default value!\n"));
1938 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
1939 /*2.4G default value*/
1940 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1941 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
1942 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
1943 }
1944 for (TxCount = 0;TxCount < MAX_TX_COUNT;TxCount++) {
1945 if (TxCount == 0) {
1946 pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
1947 pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
1948 } else {
1949 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
1950 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
1951 pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
1952 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
1953 }
1954 }
1955 /*5G default value*/
1956 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
1957 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
1958
1959 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
1960 if (TxCount == 0) {
1961 pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
1962 pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
1963 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
1964 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
1965 } else {
1966 pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
1967 pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
1968 pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
1969 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
1970 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
1971 }
1972 }
1973 }
1974 return;
1975 }
1976
1977 rtl_priv(hw)->efuse.b_txpwr_fromeprom = true;
1978
1979 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
1980 /*2.4G default value*/
1981 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1982 pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
1983 if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
1984 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
1985 }
1986 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
1987 pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
1988 if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
1989 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
1990 }
1991 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount ++) {
1992 if (TxCount == 0) {
1993 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
1994 if (hwinfo[eeAddr] == 0xFF) {
1995 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0x02;
1996 } else {
1997 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
1998 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3)) /*bit sign number to 8 bit sign number*/
1999 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2000 }
2001
2002 if (hwinfo[eeAddr] == 0xFF) {
2003 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0x04;
2004 } else {
2005 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2006 if(pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3)) /*bit sign number to 8 bit sign number*/
2007 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2008 }
2009 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2010 eeAddr++;
2011 } else {
2012 if (hwinfo[eeAddr] == 0xFF) {
2013 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2014 } else {
2015 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2016 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2017 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2018 }
2019
2020 if (hwinfo[eeAddr] == 0xFF) {
2021 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2022 } else {
2023 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2024 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2025 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2026 }
2027
2028 eeAddr++;
2029
2030 if (hwinfo[eeAddr] == 0xFF) {
2031 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2032 } else {
2033 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2034 if(pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2035 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2036 }
2037
2038 if (hwinfo[eeAddr] == 0xFF) {
2039 pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2040 } else {
2041 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2042 if(pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2043 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2044 }
2045 eeAddr++;
2046 }
2047 }
2048
2049 /*5G default value*/
2050 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group ++) {
2051 pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2052 if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2053 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2054 }
2055
2056 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2057 if (TxCount == 0) {
2058 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2059 if (hwinfo[eeAddr] == 0xFF) {
2060 pwrinfo5g->bw20_diff[rfPath][TxCount] = 0x0;
2061 } else {
2062 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2063 if(pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2064 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2065 }
2066
2067 if (hwinfo[eeAddr] == 0xFF) {
2068 pwrinfo5g->ofdm_diff[rfPath][TxCount] = 0x4;
2069 } else {
2070 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2071 if(pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2072 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2073 }
2074 eeAddr++;
2075 } else {
2076 if (hwinfo[eeAddr] == 0xFF) {
2077 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0xFE;
2078 } else {
2079 pwrinfo5g->bw40_diff[rfPath][TxCount]= (hwinfo[eeAddr] & 0xf0) >> 4;
2080 if(pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2081 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2082 }
2083
2084 if (hwinfo[eeAddr] == 0xFF) {
2085 pwrinfo5g->bw20_diff[rfPath][TxCount] = 0xFE;
2086 } else {
2087 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2088 if(pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2089 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2090 }
2091 eeAddr++;
2092 }
2093 }
2094
2095 if (hwinfo[eeAddr] == 0xFF) {
2096 pwrinfo5g->ofdm_diff[rfPath][1] = 0xFE;
2097 pwrinfo5g->ofdm_diff[rfPath][2] = 0xFE;
2098 } else {
2099 pwrinfo5g->ofdm_diff[rfPath][1] = (hwinfo[eeAddr] & 0xf0) >> 4;
2100 pwrinfo5g->ofdm_diff[rfPath][2] = (hwinfo[eeAddr] & 0x0f);
2101 }
2102 eeAddr++;
2103 if (hwinfo[eeAddr] == 0xFF)
2104 pwrinfo5g->ofdm_diff[rfPath][3] = 0xFE;
2105 else
2106 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2107
2108 eeAddr++;
2109
2110 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2111 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] == 0xFF)
2112 pwrinfo5g->ofdm_diff[rfPath][TxCount] = 0xFE;
2113 else if(pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2114 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2115 }
2116 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2117 if (hwinfo[eeAddr] == 0xFF) {
2118 pwrinfo5g->bw80_diff[rfPath][TxCount] = 0xFE;
2119 } else {
2120 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2121 if(pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3)) //4bit sign number to 8 bit sign number
2122 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2123 }
2124
2125 if (hwinfo[eeAddr] == 0xFF) {
2126 pwrinfo5g->bw160_diff[rfPath][TxCount] = 0xFE;
2127 } else {
2128 pwrinfo5g->bw160_diff[rfPath][TxCount]= (hwinfo[eeAddr] & 0x0f);
2129 if(pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3)) //4bit sign number to 8 bit sign number
2130 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2131 }
2132 eeAddr++;
2133 }
2134 }
2135}
2136
2137static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2138 bool autoload_fail,
2139 u8 *hwinfo)
2140{
2141 struct rtl_priv *rtlpriv = rtl_priv(hw);
2142 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2143 struct txpower_info_2g pwrinfo24g;
2144 struct txpower_info_5g pwrinfo5g;
2145 u8 channel5g[CHANNEL_MAX_NUMBER_5G] =
2146 {36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,
2147 114,116,118,120,122,124,126,128,130,132,134,136,138,140,142,144,149,151,
2148 153,155,157,159,161,163,165,167,168,169,171,173,175,177};
2149 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2150 u8 rf_path, index;
2151 u8 i;
2152
2153 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, &pwrinfo5g, autoload_fail, hwinfo);
2154
2155 for (rf_path = 0; rf_path < 2; rf_path++) {
2156 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2157 index = _rtl8821ae_get_chnl_group(i + 1);
2158
2159 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2160 rtlefuse->txpwrlevel_cck[rf_path][i] =
2161 pwrinfo24g.index_cck_base[rf_path][5];
2162 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2163 pwrinfo24g.index_bw40_base[rf_path][index];
2164 } else {
2165 rtlefuse->txpwrlevel_cck[rf_path][i] =
2166 pwrinfo24g.index_cck_base[rf_path][index];
2167 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2168 pwrinfo24g.index_bw40_base[rf_path][index];
2169 }
2170 }
2171
2172 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2173 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2174 rtlefuse->txpwr_5g_bw40base[rf_path][i] = pwrinfo5g.index_bw40_base[rf_path][index];
2175 }
2176 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2177 u8 upper, lower;
2178 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2179 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2180 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2181
2182 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2183 }
2184 for (i = 0; i < MAX_TX_COUNT; i++) {
2185 rtlefuse->txpwr_cckdiff[rf_path][i] = pwrinfo24g.cck_diff[rf_path][i];
2186 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = pwrinfo24g.ofdm_diff[rf_path][i];
2187 rtlefuse->txpwr_ht20diff[rf_path][i] = pwrinfo24g.bw20_diff[rf_path][i];
2188 rtlefuse->txpwr_ht40diff[rf_path][i] = pwrinfo24g.bw40_diff[rf_path][i];
2189
2190 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = pwrinfo5g.ofdm_diff[rf_path][i];
2191 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = pwrinfo5g.bw20_diff[rf_path][i];
2192 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = pwrinfo5g.bw40_diff[rf_path][i];
2193 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = pwrinfo5g.bw80_diff[rf_path][i];
2194 }
2195 }
2196
2197 if (!autoload_fail){
2198 rtlefuse->eeprom_regulatory =
2199 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2200 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2201 rtlefuse->eeprom_regulatory = 0;
2202 } else {
2203 rtlefuse->eeprom_regulatory = 0;
2204 }
2205
2206 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
2207 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory ));
2208}
2209
2210static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2211 bool autoload_fail,
2212 u8 *hwinfo)
2213{
2214 struct rtl_priv *rtlpriv = rtl_priv(hw);
2215 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2216 struct txpower_info_2g pwrinfo24g;
2217 struct txpower_info_5g pwrinfo5g;
2218 u8 channel5g[CHANNEL_MAX_NUMBER_5G] =
2219 {36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,
2220 114,116,118,120,122,124,126,128,130,132,134,136,138,140,142,144,149,151,
2221 153,155,157,159,161,163,165,167,168,169,171,173,175,177};
2222 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2223 u8 rf_path, index;
2224 u8 i;
2225
2226 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g, &pwrinfo5g, autoload_fail, hwinfo);
2227
2228 for (rf_path = 0; rf_path < 2; rf_path++) {
2229 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2230 index = _rtl8821ae_get_chnl_group(i + 1);
2231
2232 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2233 rtlefuse->txpwrlevel_cck[rf_path][i] = pwrinfo24g.index_cck_base[rf_path][5];
2234 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = pwrinfo24g.index_bw40_base[rf_path][index];
2235 } else {
2236 rtlefuse->txpwrlevel_cck[rf_path][i] = pwrinfo24g.index_cck_base[rf_path][index];
2237 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = pwrinfo24g.index_bw40_base[rf_path][index];
2238 }
2239 }
2240
2241 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2242 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2243 rtlefuse->txpwr_5g_bw40base[rf_path][i] = pwrinfo5g.index_bw40_base[rf_path][index];
2244 }
2245 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2246 u8 upper, lower;
2247 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2248 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2249 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2250
2251 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2252 }
2253 for (i = 0; i < MAX_TX_COUNT; i++) {
2254 rtlefuse->txpwr_cckdiff[rf_path][i] = pwrinfo24g.cck_diff[rf_path][i];
2255 rtlefuse->txpwr_legacyhtdiff[rf_path][i] = pwrinfo24g.ofdm_diff[rf_path][i];
2256 rtlefuse->txpwr_ht20diff[rf_path][i] = pwrinfo24g.bw20_diff[rf_path][i];
2257 rtlefuse->txpwr_ht40diff[rf_path][i] = pwrinfo24g.bw40_diff[rf_path][i];
2258
2259 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] = pwrinfo5g.ofdm_diff[rf_path][i];
2260 rtlefuse->txpwr_5g_bw20diff[rf_path][i] = pwrinfo5g.bw20_diff[rf_path][i];
2261 rtlefuse->txpwr_5g_bw40diff[rf_path][i] = pwrinfo5g.bw40_diff[rf_path][i];
2262 rtlefuse->txpwr_5g_bw80diff[rf_path][i] = pwrinfo5g.bw80_diff[rf_path][i];
2263 }
2264 }
2265
2266 if (!autoload_fail){
2267 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2268 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2269 rtlefuse->eeprom_regulatory = 0;
2270 } else {
2271 rtlefuse->eeprom_regulatory = 0;
2272 }
2273
2274 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
2275 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory ));
2276}
2277
2278static void _rtl8812ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test )
2279{
2280 struct rtl_priv *rtlpriv = rtl_priv(hw);
2281 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2282 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2283 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2284 u16 i, usvalue;
2285 u8 hwinfo[HWSET_MAX_SIZE];
2286 u16 eeprom_id;
2287
2288 if (b_pseudo_test) {
2289 /* need add */
2290 }
2291
2292 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2293 rtl_efuse_shadow_map_update(hw);
2294 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2295 HWSET_MAX_SIZE);
2296 } else if (rtlefuse->epromtype == EEPROM_93C46) {
2297 RT_TRACE(COMP_ERR, DBG_EMERG,
2298 ("RTL819X Not boot from eeprom, check it !!"));
2299 }
2300
2301 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP \n"),
2302 hwinfo, HWSET_MAX_SIZE);
2303
2304 eeprom_id = *((u16 *) & hwinfo[0]);
2305 if (eeprom_id != RTL_EEPROM_ID) {
2306 RT_TRACE(COMP_ERR, DBG_WARNING,
2307 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
2308 rtlefuse->autoload_failflag = true;
2309 } else {
2310 RT_TRACE(COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
2311 rtlefuse->autoload_failflag = false;
2312 }
2313
2314 if (rtlefuse->autoload_failflag == true) {
2315 RT_TRACE(COMP_ERR, DBG_EMERG,
2316 ("RTL8812AE autoload_failflag, check it !!"));
2317 return;
2318 }
2319
2320 rtlefuse->eeprom_version = *(u8 *) & hwinfo[EEPROM_VERSION];
2321 if (rtlefuse->eeprom_version == 0xff)
2322 rtlefuse->eeprom_version = 0;
2323
2324 RT_TRACE(COMP_INIT, DBG_LOUD,
2325 ("EEPROM version: 0x%2x\n", rtlefuse->eeprom_version));
2326
2327 rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID];
2328 rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID];
2329 rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID];
2330 rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID];
2331 RT_TRACE(COMP_INIT, DBG_LOUD,
2332 ("EEPROMId = 0x%4x\n", eeprom_id));
2333 RT_TRACE(COMP_INIT, DBG_LOUD,
2334 ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
2335 RT_TRACE(COMP_INIT, DBG_LOUD,
2336 ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
2337 RT_TRACE(COMP_INIT, DBG_LOUD,
2338 ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
2339 RT_TRACE(COMP_INIT, DBG_LOUD,
2340 ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
2341
2342 /*customer ID*/
2343 rtlefuse->eeprom_oemid = *(u8 *) & hwinfo[EEPROM_CUSTOMER_ID];
2344 if (rtlefuse->eeprom_oemid == 0xFF)
2345 rtlefuse->eeprom_oemid = 0;
2346
2347 RT_TRACE(COMP_INIT, DBG_LOUD,
2348 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
2349
2350 for (i = 0; i < 6; i += 2) {
2351 usvalue = *(u16 *) & hwinfo[EEPROM_MAC_ADDR + i];
2352 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
2353 }
2354
2355 RT_TRACE(COMP_INIT, DBG_DMESG,
2356 ("dev_addr: %pM\n", rtlefuse->dev_addr));
2357
2358 _rtl8812ae_read_txpower_info_from_hwpg(hw,
2359 rtlefuse->autoload_failflag, hwinfo);
2360
2361 /*board type*/
2362 rtlefuse->board_type = (((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) & 0xE0 ) >> 5);
2363 if ((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) == 0xff )
2364 rtlefuse->board_type = 0;
2365 rtlhal->boad_type = rtlefuse->board_type;
2366
2367 rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
2368 rtlefuse->autoload_failflag, hwinfo);
2369
2370 rtlefuse->eeprom_channelplan = *(u8 *) & hwinfo[EEPROM_CHANNELPLAN];
2371 if (rtlefuse->eeprom_channelplan == 0xff)
2372 rtlefuse->eeprom_channelplan = 0x7F;
2373
2374 /* set channel paln to world wide 13 */
2375 //rtlefuse->channel_plan = (u8) rtlefuse->eeprom_channelplan;
2376
2377 /*parse xtal*/
2378 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
2379 if ( rtlefuse->crystalcap == 0xFF )
2380 rtlefuse->crystalcap = 0x20;
2381
2382 rtlefuse->eeprom_thermalmeter = *(u8 *) & hwinfo[EEPROM_THERMAL_METER];
2383 if ((rtlefuse->eeprom_thermalmeter == 0xff) ||rtlefuse->autoload_failflag )
2384 {
2385 rtlefuse->b_apk_thermalmeterignore = true;
2386 rtlefuse->eeprom_thermalmeter = 0xff;
2387 }
2388
2389 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2390 RT_TRACE(COMP_INIT, DBG_LOUD,
2391 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
2392
2393 if (rtlefuse->autoload_failflag == false) {
2394 rtlefuse->antenna_div_cfg = *(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18 >> 3;
2395 if (*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
2396 rtlefuse->antenna_div_cfg = 0x00;
2397 /*if (BT_1ant())
2398 rtlefuse->antenna_div_cfg = 0;*/
2399 rtlefuse->antenna_div_type = *(u8 *) & hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
2400 if (rtlefuse->antenna_div_type == 0xFF)
2401 {
2402 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
2403 }
2404 } else {
2405 rtlefuse->antenna_div_cfg = 0;
2406 rtlefuse->antenna_div_type = 0;
2407 }
2408
2409 RT_TRACE(COMP_INIT, DBG_LOUD,
2410 ("SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
2411 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type));
2412
2413 /*Hal_ReadPAType_8821A()*/
2414 /*Hal_EfuseParseRateIndicationOption8821A()*/
2415 /*Hal_ReadEfusePCIeCap8821AE()*/
2416
2417 pcipriv->ledctl.bled_opendrain = true;
2418
2419 if (rtlhal->oem_id == RT_CID_DEFAULT) {
2420 switch (rtlefuse->eeprom_oemid) {
2421 case RT_CID_DEFAULT:
2422 break;
2423 case EEPROM_CID_TOSHIBA:
2424 rtlhal->oem_id = RT_CID_TOSHIBA;
2425 break;
2426 case EEPROM_CID_CCX:
2427 rtlhal->oem_id = RT_CID_CCX;
2428 break;
2429 case EEPROM_CID_QMI:
2430 rtlhal->oem_id = RT_CID_819x_QMI;
2431 break;
2432 case EEPROM_CID_WHQL:
2433 break;
2434 default:
2435 break;
2436
2437 }
2438 }
2439}
2440
2441static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test )
2442{
2443 struct rtl_priv *rtlpriv = rtl_priv(hw);
2444 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2445 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2446 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2447 u16 i, usvalue;
2448 u8 hwinfo[HWSET_MAX_SIZE];
2449 u16 eeprom_id;
2450
2451 if (b_pseudo_test) {
2452 /* need add */
2453 }
2454
2455 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
2456 rtl_efuse_shadow_map_update(hw);
2457 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
2458 HWSET_MAX_SIZE);
2459 } else if (rtlefuse->epromtype == EEPROM_93C46) {
2460 RT_TRACE(COMP_ERR, DBG_EMERG,
2461 ("RTL819X Not boot from eeprom, check it !!"));
2462 }
2463
2464 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP \n"),
2465 hwinfo, HWSET_MAX_SIZE);
2466
2467 eeprom_id = *((u16 *) & hwinfo[0]);
2468 if (eeprom_id != RTL_EEPROM_ID) {
2469 RT_TRACE(COMP_ERR, DBG_WARNING,
2470 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
2471 rtlefuse->autoload_failflag = true;
2472 } else {
2473 RT_TRACE(COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
2474 rtlefuse->autoload_failflag = false;
2475 }
2476
2477 if (rtlefuse->autoload_failflag == true) {
2478 RT_TRACE(COMP_ERR, DBG_EMERG,
2479 ("RTL8812AE autoload_failflag, check it !!"));
2480 return;
2481 }
2482
2483 rtlefuse->eeprom_version = *(u8 *) & hwinfo[EEPROM_VERSION];
2484 if (rtlefuse->eeprom_version == 0xff)
2485 rtlefuse->eeprom_version = 0;
2486
2487 RT_TRACE(COMP_INIT, DBG_LOUD,
2488 ("EEPROM version: 0x%2x\n", rtlefuse->eeprom_version));
2489
2490 rtlefuse->eeprom_vid = *(u16 *) &hwinfo[EEPROM_VID];
2491 rtlefuse->eeprom_did = *(u16 *) &hwinfo[EEPROM_DID];
2492 rtlefuse->eeprom_svid = *(u16 *) &hwinfo[EEPROM_SVID];
2493 rtlefuse->eeprom_smid = *(u16 *) &hwinfo[EEPROM_SMID];
2494 RT_TRACE(COMP_INIT, DBG_LOUD,
2495 ("EEPROMId = 0x%4x\n", eeprom_id));
2496 RT_TRACE(COMP_INIT, DBG_LOUD,
2497 ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
2498 RT_TRACE(COMP_INIT, DBG_LOUD,
2499 ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
2500 RT_TRACE(COMP_INIT, DBG_LOUD,
2501 ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
2502 RT_TRACE(COMP_INIT, DBG_LOUD,
2503 ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
2504
2505 /*customer ID*/
2506 rtlefuse->eeprom_oemid = *(u8 *) & hwinfo[EEPROM_CUSTOMER_ID];
2507 if (rtlefuse->eeprom_oemid == 0xFF)
2508 rtlefuse->eeprom_oemid = 0;
2509
2510 RT_TRACE(COMP_INIT, DBG_LOUD,
2511 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
2512
2513 for (i = 0; i < 6; i += 2) {
2514 usvalue = *(u16 *) & hwinfo[EEPROM_MAC_ADDR + i];
2515 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
2516 }
2517
2518 RT_TRACE(COMP_INIT, DBG_DMESG,
2519 ("dev_addr: %pM\n", rtlefuse->dev_addr));
2520
2521 _rtl8821ae_read_txpower_info_from_hwpg(hw,
2522 rtlefuse->autoload_failflag, hwinfo);
2523
2524 /*board type*/
2525 rtlefuse->board_type = (((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) & 0xE0 ) >> 5);
2526 if ((*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION]) == 0xff )
2527 rtlefuse->board_type = 0;
2528 rtlhal->boad_type = rtlefuse->board_type;
2529
2530 rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
2531 rtlefuse->autoload_failflag, hwinfo);
2532
2533 rtlefuse->eeprom_channelplan = *(u8 *) & hwinfo[EEPROM_CHANNELPLAN];
2534 if (rtlefuse->eeprom_channelplan == 0xff)
2535 rtlefuse->eeprom_channelplan = 0x7F;
2536
2537 /* set channel paln to world wide 13 */
2538 //rtlefuse->channel_plan = (u8) rtlefuse->eeprom_channelplan;
2539
2540 /*parse xtal*/
2541 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
2542 if ( rtlefuse->crystalcap == 0xFF )
2543 rtlefuse->crystalcap = 0x20;
2544
2545 rtlefuse->eeprom_thermalmeter = *(u8 *) & hwinfo[EEPROM_THERMAL_METER];
2546 if ((rtlefuse->eeprom_thermalmeter == 0xff) ||rtlefuse->autoload_failflag )
2547 {
2548 rtlefuse->b_apk_thermalmeterignore = true;
2549 rtlefuse->eeprom_thermalmeter = 0x18;
2550 }
2551
2552 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2553 RT_TRACE(COMP_INIT, DBG_LOUD,
2554 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
2555
2556 if (rtlefuse->autoload_failflag == false) {
2557 rtlefuse->antenna_div_cfg = (*(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION] & BIT(3))?true:false;
2558 /*if (BT_1ant())
2559 rtlefuse->antenna_div_cfg = 0;*/
2560
2561 rtlefuse->antenna_div_type = CG_TRX_HW_ANTDIV;
2562 } else {
2563 rtlefuse->antenna_div_cfg = 0;
2564 rtlefuse->antenna_div_type = 0;
2565 }
2566
2567 RT_TRACE(COMP_INIT, DBG_LOUD,
2568 ("SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
2569 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type));
2570
2571 pcipriv->ledctl.bled_opendrain = true;
2572
2573 if (rtlhal->oem_id == RT_CID_DEFAULT) {
2574 switch (rtlefuse->eeprom_oemid) {
2575 case RT_CID_DEFAULT:
2576 break;
2577 case EEPROM_CID_TOSHIBA:
2578 rtlhal->oem_id = RT_CID_TOSHIBA;
2579 break;
2580 case EEPROM_CID_CCX:
2581 rtlhal->oem_id = RT_CID_CCX;
2582 break;
2583 case EEPROM_CID_QMI:
2584 rtlhal->oem_id = RT_CID_819x_QMI;
2585 break;
2586 case EEPROM_CID_WHQL:
2587 break;
2588 default:
2589 break;
2590 }
2591 }
2592}
2593
2594
2595/*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
2596{
2597 struct rtl_priv *rtlpriv = rtl_priv(hw);
2598 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2599 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2600
2601 pcipriv->ledctl.bled_opendrain = true;
2602 switch (rtlhal->oem_id) {
2603 case RT_CID_819x_HP:
2604 pcipriv->ledctl.bled_opendrain = true;
2605 break;
2606 case RT_CID_819x_Lenovo:
2607 case RT_CID_DEFAULT:
2608 case RT_CID_TOSHIBA:
2609 case RT_CID_CCX:
2610 case RT_CID_819x_Acer:
2611 case RT_CID_WHQL:
2612 default:
2613 break;
2614 }
2615 RT_TRACE(COMP_INIT, DBG_DMESG,
2616 ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
2617}*/
2618
2619void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
2620{
2621 struct rtl_priv *rtlpriv = rtl_priv(hw);
2622 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2623 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2624 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2625 u8 tmp_u1b;
2626
2627 rtlhal->version = _rtl8821ae_read_chip_version(hw);
2628
2629 if (get_rf_type(rtlphy) == RF_1T1R)
2630 rtlpriv->dm.brfpath_rxenable[0] = true;
2631 else
2632 rtlpriv->dm.brfpath_rxenable[0] =
2633 rtlpriv->dm.brfpath_rxenable[1] = true;
2634 RT_TRACE(COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
2635 rtlhal->version));
2636
2637 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2638 if (tmp_u1b & BIT(4)) {
2639 RT_TRACE(COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
2640 rtlefuse->epromtype = EEPROM_93C46;
2641 } else {
2642 RT_TRACE(COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
2643 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2644 }
2645
2646 if (tmp_u1b & BIT(5)) {
2647 RT_TRACE(COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
2648 rtlefuse->autoload_failflag = false;
2649 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2650 _rtl8812ae_read_adapter_info(hw, false);
2651 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2652 _rtl8821ae_read_adapter_info(hw, false);
2653 } else {
2654 RT_TRACE(COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
2655 }
2656 /*hal_ReadRFType_8812A()*/
2657 //_rtl8821ae_hal_customized_behavior(hw);
2658}
2659
2660static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
2661 struct ieee80211_sta *sta)
2662{
2663 struct rtl_priv *rtlpriv = rtl_priv(hw);
2664 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2665 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2666 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2667 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2668 u32 ratr_value;
2669 u8 ratr_index = 0;
2670 u8 b_nmode = mac->ht_enable;
2671 u8 mimo_ps = IEEE80211_SMPS_OFF;
2672 u16 shortgi_rate;
2673 u32 tmp_ratr_value;
2674 u8 b_curtxbw_40mhz = mac->bw_40;
2675 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2676 1 : 0;
2677 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2678 1 : 0;
2679 enum wireless_mode wirelessmode = mac->mode;
2680
2681 if (rtlhal->current_bandtype == BAND_ON_5G)
2682 ratr_value = sta->supp_rates[1] << 4;
2683 else
2684 ratr_value = sta->supp_rates[0];
2685 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2686 ratr_value = 0xfff;
2687 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2688 sta->ht_cap.mcs.rx_mask[0] << 12);
2689 switch (wirelessmode) {
2690 case WIRELESS_MODE_B:
2691 if (ratr_value & 0x0000000c)
2692 ratr_value &= 0x0000000d;
2693 else
2694 ratr_value &= 0x0000000f;
2695 break;
2696 case WIRELESS_MODE_G:
2697 ratr_value &= 0x00000FF5;
2698 break;
2699 case WIRELESS_MODE_N_24G:
2700 case WIRELESS_MODE_N_5G:
2701 b_nmode = 1;
2702 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2703 ratr_value &= 0x0007F005;
2704 } else {
2705 u32 ratr_mask;
2706
2707 if (get_rf_type(rtlphy) == RF_1T2R ||
2708 get_rf_type(rtlphy) == RF_1T1R)
2709 ratr_mask = 0x000ff005;
2710 else
2711 ratr_mask = 0x0f0ff005;
2712
2713 ratr_value &= ratr_mask;
2714 }
2715 break;
2716 default:
2717 if (rtlphy->rf_type == RF_1T2R)
2718 ratr_value &= 0x000ff0ff;
2719 else
2720 ratr_value &= 0x0f0ff0ff;
2721
2722 break;
2723 }
2724
2725 if ( (rtlpcipriv->btcoexist.bt_coexistence) &&
2726 (rtlpcipriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2727 (rtlpcipriv->btcoexist.bt_cur_state) &&
2728 (rtlpcipriv->btcoexist.bt_ant_isolation) &&
2729 ((rtlpcipriv->btcoexist.bt_service == BT_SCO)||
2730 (rtlpcipriv->btcoexist.bt_service == BT_BUSY)) )
2731 ratr_value &= 0x0fffcfc0;
2732 else
2733 ratr_value &= 0x0FFFFFFF;
2734
2735 if (b_nmode && ((b_curtxbw_40mhz &&
2736 b_curshortgi_40mhz) || (!b_curtxbw_40mhz &&
2737 b_curshortgi_20mhz))) {
2738
2739 ratr_value |= 0x10000000;
2740 tmp_ratr_value = (ratr_value >> 12);
2741
2742 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2743 if ((1 << shortgi_rate) & tmp_ratr_value)
2744 break;
2745 }
2746
2747 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2748 (shortgi_rate << 4) | (shortgi_rate);
2749 }
2750
2751 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2752
2753 RT_TRACE(COMP_RATR, DBG_DMESG,
2754 ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
2755}
2756
2757
2758static u8 _rtl8821ae_mrate_idx_to_arfr_id(
2759 struct ieee80211_hw *hw, u8 rate_index,
2760 enum wireless_mode wirelessmode)
2761{
2762 struct rtl_priv *rtlpriv = rtl_priv(hw);
2763 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2764 u8 ret = 0;
2765 switch(rate_index){
2766 case RATR_INX_WIRELESS_NGB:
2767 if(rtlphy->rf_type == RF_1T1R)
2768 ret = 1;
2769 else
2770 ret = 0;
2771 ;break;
2772 case RATR_INX_WIRELESS_N:
2773 case RATR_INX_WIRELESS_NG:
2774 if(rtlphy->rf_type == RF_1T1R)
2775 ret = 5;
2776 else
2777 ret = 4;
2778 ;break;
2779 case RATR_INX_WIRELESS_NB:
2780 if(rtlphy->rf_type == RF_1T1R)
2781 ret = 3;
2782 else
2783 ret = 2;
2784 ;break;
2785 case RATR_INX_WIRELESS_GB:
2786 ret = 6;
2787 break;
2788 case RATR_INX_WIRELESS_G:
2789 ret = 7;
2790 break;
2791 case RATR_INX_WIRELESS_B:
2792 ret = 8;
2793 break;
2794 case RATR_INX_WIRELESS_MC:
2795 if ((wirelessmode == WIRELESS_MODE_B)
2796 || (wirelessmode == WIRELESS_MODE_G)
2797 || (wirelessmode == WIRELESS_MODE_N_24G)
2798 || (wirelessmode == WIRELESS_MODE_AC_24G))
2799 ret = 6;
2800 else
2801 ret = 7;
2802 case RATR_INX_WIRELESS_AC_5N:
2803 if(rtlphy->rf_type == RF_1T1R)
2804 ret = 10;
2805 else
2806 ret = 9;
2807 break;
2808 case RATR_INX_WIRELESS_AC_24N:
2809 if(rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
2810 {
2811 if(rtlphy->rf_type == RF_1T1R)
2812 ret = 10;
2813 else
2814 ret = 9;
2815 } else {
2816 if(rtlphy->rf_type == RF_1T1R)
2817 ret = 11;
2818 else
2819 ret = 12;
2820 }
2821 break;
2822 default:
2823 ret = 0;break;
2824 }
2825 return ret;
2826}
2827
2828static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
2829 struct ieee80211_sta *sta, u8 rssi_level)
2830{
2831 struct rtl_priv *rtlpriv = rtl_priv(hw);
2832 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2833 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2834 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2835 struct rtl_sta_info * sta_entry = NULL;
2836 u32 ratr_bitmap;
2837 u8 ratr_index;
2838 u8 b_curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2839 ? 1 : 0;
2840 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2841 1 : 0;
2842 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2843 1 : 0;
2844 enum wireless_mode wirelessmode = 0;
2845 bool b_shortgi = false;
2846 u8 rate_mask[7];
2847 u8 macid = 0;
2848 u8 mimo_ps = IEEE80211_SMPS_OFF;
2849
2850 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2851 wirelessmode = sta_entry->wireless_mode;
2852 if (mac->opmode == NL80211_IFTYPE_STATION ||
2853 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2854 b_curtxbw_40mhz = mac->bw_40;
2855 else if (mac->opmode == NL80211_IFTYPE_AP ||
2856 mac->opmode == NL80211_IFTYPE_ADHOC)
2857 macid = sta->aid + 1;
2858
2859 ratr_bitmap = sta->supp_rates[0];
2860
2861 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2862 ratr_bitmap = 0xfff;
2863
2864 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2865 sta->ht_cap.mcs.rx_mask[0] << 12);
2866/*mac id owner*/
2867 switch (wirelessmode) {
2868 case WIRELESS_MODE_B:
2869 ratr_index = RATR_INX_WIRELESS_B;
2870 if (ratr_bitmap & 0x0000000c)
2871 ratr_bitmap &= 0x0000000d;
2872 else
2873 ratr_bitmap &= 0x0000000f;
2874 break;
2875 case WIRELESS_MODE_G:
2876 ratr_index = RATR_INX_WIRELESS_GB;
2877
2878 if (rssi_level == 1)
2879 ratr_bitmap &= 0x00000f00;
2880 else if (rssi_level == 2)
2881 ratr_bitmap &= 0x00000ff0;
2882 else
2883 ratr_bitmap &= 0x00000ff5;
2884 break;
2885 case WIRELESS_MODE_A:
2886 ratr_index = RATR_INX_WIRELESS_G;
2887 ratr_bitmap &= 0x00000ff0;
2888 break;
2889 case WIRELESS_MODE_N_24G:
2890 case WIRELESS_MODE_N_5G:
2891 if (wirelessmode == WIRELESS_MODE_N_24G)
2892 ratr_index = RATR_INX_WIRELESS_NGB;
2893 else
2894 ratr_index = RATR_INX_WIRELESS_NG;
2895
2896 if (mimo_ps == IEEE80211_SMPS_STATIC || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
2897 if (rssi_level == 1)
2898 ratr_bitmap &= 0x00070000;
2899 else if (rssi_level == 2)
2900 ratr_bitmap &= 0x0007f000;
2901 else
2902 ratr_bitmap &= 0x0007f005;
2903 } else {
2904 if ( rtlphy->rf_type == RF_1T1R) {
2905 if (b_curtxbw_40mhz) {
2906 if (rssi_level == 1)
2907 ratr_bitmap &= 0x000f0000;
2908 else if (rssi_level == 2)
2909 ratr_bitmap &= 0x000ff000;
2910 else
2911 ratr_bitmap &= 0x000ff015;
2912 } else {
2913 if (rssi_level == 1)
2914 ratr_bitmap &= 0x000f0000;
2915 else if (rssi_level == 2)
2916 ratr_bitmap &= 0x000ff000;
2917 else
2918 ratr_bitmap &= 0x000ff005;
2919 }
2920 } else {
2921 if (b_curtxbw_40mhz) {
2922 if (rssi_level == 1)
2923 ratr_bitmap &= 0x0fff0000;
2924 else if (rssi_level == 2)
2925 ratr_bitmap &= 0x0ffff000;
2926 else
2927 ratr_bitmap &= 0x0ffff015;
2928 } else {
2929 if (rssi_level == 1)
2930 ratr_bitmap &= 0x0fff0000;
2931 else if (rssi_level == 2)
2932 ratr_bitmap &= 0x0ffff000;
2933 else
2934 ratr_bitmap &= 0x0ffff005;
2935 }
2936 }
2937 }
2938 if ((b_curtxbw_40mhz && b_curshortgi_40mhz) ||
2939 (!b_curtxbw_40mhz && b_curshortgi_20mhz)) {
2940
2941 if (macid == 0)
2942 b_shortgi = true;
2943 else if (macid == 1)
2944 b_shortgi = false;
2945 }
2946 break;
2947
2948 case WIRELESS_MODE_AC_24G:
2949 ratr_index = RATR_INX_WIRELESS_AC_24N;
2950 if(rssi_level == 1)
2951 ratr_bitmap &= 0xfc3f0000;
2952 else if(rssi_level == 2)
2953 ratr_bitmap &= 0xfffff000;
2954 else
2955 ratr_bitmap &= 0xffffffff;
2956 break;
2957
2958 case WIRELESS_MODE_AC_5G:
2959 ratr_index = RATR_INX_WIRELESS_AC_5N;
2960
2961 if (rtlphy->rf_type == RF_1T1R)
2962 {
2963 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2964 {
2965 if(rssi_level == 1) /*add by Gary for ac-series*/
2966 ratr_bitmap &= 0x003f8000;
2967 else if (rssi_level == 2)
2968 ratr_bitmap &= 0x003ff000;
2969 else
2970 ratr_bitmap &= 0x003ff010;
2971 }
2972 else
2973 ratr_bitmap &= 0x000ff010;
2974 }
2975 else
2976 {
2977 if(rssi_level == 1) /* add by Gary for ac-series*/
2978 ratr_bitmap &= 0xfe3f8000; /*VHT 2SS MCS3~9*/
2979 else if (rssi_level == 2)
2980 ratr_bitmap &= 0xfffff000; /*VHT 2SS MCS0~9*/
2981 else
2982 ratr_bitmap &= 0xfffff010; /*All*/
2983 }
2984 break;
2985
2986 default:
2987 ratr_index = RATR_INX_WIRELESS_NGB;
2988
2989 if (rtlphy->rf_type == RF_1T2R)
2990 ratr_bitmap &= 0x000ff0ff;
2991 else
2992 ratr_bitmap &= 0x0f0ff0ff;
2993 break;
2994
2995 }
2996
2997 sta_entry->ratr_index = ratr_index;
2998
2999 RT_TRACE(COMP_RATR, DBG_DMESG,
3000 ("ratr_bitmap :%x\n", ratr_bitmap));
3001 *(u32 *) & rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3002 (ratr_index << 28));
3003 rate_mask[0] = macid;
3004 rate_mask[1] = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode) | (b_shortgi ? 0x80 : 0x00);
3005 rate_mask[2] = b_curtxbw_40mhz;
3006 /* if (prox_priv->proxim_modeinfo->power_output > 0)
3007 rate_mask[2] |= BIT(6); */
3008
3009 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3010 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >>8);
3011 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3012 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3013
3014 RT_TRACE(COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
3015 "ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3016 ratr_index, ratr_bitmap,
3017 rate_mask[0], rate_mask[1],
3018 rate_mask[2], rate_mask[3],
3019 rate_mask[4], rate_mask[5],
3020 rate_mask[6]));
3021 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3022 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3023}
3024
3025void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3026 struct ieee80211_sta *sta, u8 rssi_level)
3027{
3028 struct rtl_priv *rtlpriv = rtl_priv(hw);
3029 if (rtlpriv->dm.b_useramask)
3030 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3031 else
3032 /*RT_TRACE(COMP_RATR,DBG_LOUD,("rtl8821ae_update_hal_rate_tbl(): Error! 8821ae FW RA Only"));*/
3033 rtl8821ae_update_hal_rate_table(hw, sta);
3034}
3035
3036void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3037{
3038 struct rtl_priv *rtlpriv = rtl_priv(hw);
3039 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3040 u16 sifs_timer;
3041
3042 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3043 (u8 *) & mac->slot_time);
3044 if (!mac->ht_enable)
3045 sifs_timer = 0x0a0a;
3046 else
3047 sifs_timer = 0x0e0e;
3048 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *) & sifs_timer);
3049}
3050
3051bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
3052{
3053 struct rtl_priv *rtlpriv = rtl_priv(hw);
3054 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3055 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3056 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3057 u8 u1tmp = 0;
3058 bool b_actuallyset = false;
3059
3060 if (rtlpriv->rtlhal.being_init_adapter)
3061 return false;
3062
3063 if (ppsc->b_swrf_processing)
3064 return false;
3065
3066 spin_lock(&rtlpriv->locks.rf_ps_lock);
3067 if (ppsc->rfchange_inprogress) {
3068 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3069 return false;
3070 } else {
3071 ppsc->rfchange_inprogress = true;
3072 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3073 }
3074
3075 cur_rfstate = ppsc->rfpwr_state;
3076
3077 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3078 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3079
3080 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3081
3082 if (rtlphy->polarity_ctl) {
3083 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3084 } else {
3085 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3086 }
3087
3088 if ((ppsc->b_hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
3089 RT_TRACE(COMP_RF, DBG_DMESG,
3090 ("GPIOChangeRF - HW Radio ON, RF ON\n"));
3091
3092 e_rfpowerstate_toset = ERFON;
3093 ppsc->b_hwradiooff = false;
3094 b_actuallyset = true;
3095 } else if ((ppsc->b_hwradiooff == false)
3096 && (e_rfpowerstate_toset == ERFOFF)) {
3097 RT_TRACE(COMP_RF, DBG_DMESG,
3098 ("GPIOChangeRF - HW Radio OFF, RF OFF\n"));
3099
3100 e_rfpowerstate_toset = ERFOFF;
3101 ppsc->b_hwradiooff = true;
3102 b_actuallyset = true;
3103 }
3104
3105 if (b_actuallyset) {
3106 spin_lock(&rtlpriv->locks.rf_ps_lock);
3107 ppsc->rfchange_inprogress = false;
3108 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3109 } else {
3110 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3111 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3112
3113 spin_lock(&rtlpriv->locks.rf_ps_lock);
3114 ppsc->rfchange_inprogress = false;
3115 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3116 }
3117
3118 *valid = 1;
3119 return !ppsc->b_hwradiooff;
3120
3121}
3122
3123void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3124 u8 *p_macaddr, bool is_group, u8 enc_algo,
3125 bool is_wepkey, bool clear_all)
3126{
3127 struct rtl_priv *rtlpriv = rtl_priv(hw);
3128 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3129 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3130 u8 *macaddr = p_macaddr;
3131 u32 entry_id = 0;
3132 bool is_pairwise = false;
3133
3134 static u8 cam_const_addr[4][6] = {
3135 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3136 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3137 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3138 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3139 };
3140 static u8 cam_const_broad[] = {
3141 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3142 };
3143
3144 if (clear_all) {
3145 u8 idx = 0;
3146 u8 cam_offset = 0;
3147 u8 clear_number = 5;
3148
3149 RT_TRACE(COMP_SEC, DBG_DMESG, ("clear_all\n"));
3150
3151 for (idx = 0; idx < clear_number; idx++) {
3152 rtl_cam_mark_invalid(hw, cam_offset + idx);
3153 rtl_cam_empty_entry(hw, cam_offset + idx);
3154
3155 if (idx < 5) {
3156 memset(rtlpriv->sec.key_buf[idx], 0,
3157 MAX_KEY_LEN);
3158 rtlpriv->sec.key_len[idx] = 0;
3159 }
3160 }
3161
3162 } else {
3163 switch (enc_algo) {
3164 case WEP40_ENCRYPTION:
3165 enc_algo = CAM_WEP40;
3166 break;
3167 case WEP104_ENCRYPTION:
3168 enc_algo = CAM_WEP104;
3169 break;
3170 case TKIP_ENCRYPTION:
3171 enc_algo = CAM_TKIP;
3172 break;
3173 case AESCCMP_ENCRYPTION:
3174 enc_algo = CAM_AES;
3175 break;
3176 default:
3177 RT_TRACE(COMP_ERR, DBG_EMERG, ("switch case "
3178 "not process \n"));
3179 enc_algo = CAM_TKIP;
3180 break;
3181 }
3182
3183 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
3184 macaddr = cam_const_addr[key_index];
3185 entry_id = key_index;
3186 } else {
3187 if (is_group) {
3188 macaddr = cam_const_broad;
3189 entry_id = key_index;
3190 } else {
3191 if (mac->opmode == NL80211_IFTYPE_AP) {
3192 entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
3193 if (entry_id >= TOTAL_CAM_ENTRY) {
3194 RT_TRACE(COMP_SEC, DBG_EMERG,
3195 ("Can not find free hw security cam entry\n"));
3196 return;
3197 }
3198 } else {
3199 entry_id = CAM_PAIRWISE_KEY_POSITION;
3200 }
3201
3202 key_index = PAIRWISE_KEYIDX;
3203 is_pairwise = true;
3204 }
3205 }
3206
3207 if (rtlpriv->sec.key_len[key_index] == 0) {
3208 RT_TRACE(COMP_SEC, DBG_DMESG,
3209 ("delete one entry, entry_id is %d\n",entry_id));
3210 if (mac->opmode == NL80211_IFTYPE_AP)
3211 rtl_cam_del_entry(hw, p_macaddr);
3212 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
3213 } else {
3214 RT_TRACE(COMP_SEC, DBG_DMESG, ("add one entry\n"));
3215 if (is_pairwise) {
3216 RT_TRACE(COMP_SEC, DBG_DMESG, ("set Pairwiase key\n"));
3217
3218 rtl_cam_add_one_entry(hw, macaddr, key_index,
3219 entry_id, enc_algo,
3220 CAM_CONFIG_NO_USEDK,
3221 rtlpriv->sec.key_buf[key_index]);
3222 } else {
3223 RT_TRACE(COMP_SEC, DBG_DMESG, ("set group key\n"));
3224
3225 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
3226 rtl_cam_add_one_entry(hw,
3227 rtlefuse->dev_addr,
3228 PAIRWISE_KEYIDX,
3229 CAM_PAIRWISE_KEY_POSITION,
3230 enc_algo,
3231 CAM_CONFIG_NO_USEDK,
3232 rtlpriv->sec.key_buf
3233 [entry_id]);
3234 }
3235
3236 rtl_cam_add_one_entry(hw, macaddr, key_index,
3237 entry_id, enc_algo,
3238 CAM_CONFIG_NO_USEDK,
3239 rtlpriv->sec.key_buf[entry_id]);
3240 }
3241
3242 }
3243 }
3244}
3245
3246
3247void rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3248 bool auto_load_fail, u8 *hwinfo)
3249{
3250 struct rtl_priv *rtlpriv = rtl_priv(hw);
3251 u8 value;
3252
3253 if (!auto_load_fail) {
3254 value = *(u8 *) & hwinfo[EEPROM_RF_BOARD_OPTION];
3255 if (((value & 0xe0) >> 5) == 0x1)
3256 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3257 else
3258 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3259 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3260
3261 value = hwinfo[EEPROM_RF_BT_SETTING];
3262 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3263 } else {
3264 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3265 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3266 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3267 }
3268 /*move BT_InitHalVars() to init_sw_vars*/
3269}
3270
3271void rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3272 bool auto_load_fail, u8 *hwinfo)
3273{
3274 struct rtl_priv *rtlpriv = rtl_priv(hw);
3275 u8 value;
3276 u32 tmpu_32;
3277
3278 if (!auto_load_fail) {
3279 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3280 if(tmpu_32 & BIT(18))
3281 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3282 else
3283 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3284 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3285
3286 value = hwinfo[EEPROM_RF_BT_SETTING];
3287 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3288 } else {
3289 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3290 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3291 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3292 }
3293 /*move BT_InitHalVars() to init_sw_vars*/
3294}
3295
3296void rtl8821ae_bt_reg_init(struct ieee80211_hw* hw)
3297{
3298 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
3299
3300 /* 0:Low, 1:High, 2:From Efuse. */
3301 rtlpcipriv->btcoexist.b_reg_bt_iso = 2;
3302 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
3303 rtlpcipriv->btcoexist.b_reg_bt_sco= 3;
3304 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
3305 rtlpcipriv->btcoexist.b_reg_bt_sco= 0;
3306}
3307
3308
3309void rtl8821ae_bt_hw_init(struct ieee80211_hw* hw)
3310{
3311 struct rtl_priv *rtlpriv = rtl_priv(hw);
3312
3313 if (rtlpriv->cfg->ops->get_btc_status()){
3314 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
3315 }
3316}
3317
3318void rtl8821ae_suspend(struct ieee80211_hw *hw)
3319{
3320}
3321
3322void rtl8821ae_resume(struct ieee80211_hw *hw)
3323{
3324}
3325
3326/* Turn on AAP (RCR:bit 0) for promicuous mode. */
3327void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
3328 bool allow_all_da, bool write_into_reg)
3329{
3330 struct rtl_priv *rtlpriv = rtl_priv(hw);
3331 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3332
3333 if (allow_all_da) /* Set BIT0 */
3334 rtlpci->receive_config |= RCR_AAP;
3335 else /* Clear BIT0 */
3336 rtlpci->receive_config &= ~RCR_AAP;
3337
3338 if(write_into_reg)
3339 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
3340
3341
3342 RT_TRACE(COMP_TURBO | COMP_INIT, DBG_LOUD,
3343 ("receive_config=0x%08X, write_into_reg=%d\n",
3344 rtlpci->receive_config, write_into_reg ));
3345}
3346
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/hw.h b/drivers/staging/rtl8821ae/rtl8821ae/hw.h
new file mode 100644
index 000000000000..4fb6bf0d1da2
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/hw.h
@@ -0,0 +1,75 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8821AE_HW_H__
31#define __RTL8821AE_HW_H__
32
33void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
34void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw);
35
36void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
37 u32 *p_inta, u32 *p_intb);
38int rtl8821ae_hw_init(struct ieee80211_hw *hw);
39void rtl8821ae_card_disable(struct ieee80211_hw *hw);
40void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw);
41void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw);
42int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
43void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
44void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci);
45void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw);
46void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw);
47void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
48 u32 add_msr, u32 rm_msr);
49void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
50void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
51 struct ieee80211_sta *sta,
52 u8 rssi_level);
53void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw);
54bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
55void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw);
56void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
57 u8 *p_macaddr, bool is_group, u8 enc_algo,
58 bool is_wepkey, bool clear_all);
59
60void rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
61 bool autoload_fail,
62 u8* hwinfo);
63void rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
64 bool autoload_fail,
65 u8* hwinfo);
66void rtl8821ae_bt_reg_init(struct ieee80211_hw* hw);
67void rtl8821ae_bt_hw_init(struct ieee80211_hw* hw);
68void rtl8821ae_suspend(struct ieee80211_hw *hw);
69void rtl8821ae_resume(struct ieee80211_hw *hw);
70void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
71 bool allow_all_da,
72 bool write_into_reg);
73void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw);
74void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw);
75#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/led.c b/drivers/staging/rtl8821ae/rtl8821ae/led.c
new file mode 100644
index 000000000000..130a4f4b24a2
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/led.c
@@ -0,0 +1,239 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "reg.h"
33
34static void _rtl8821ae_init_led(struct ieee80211_hw *hw,
35 struct rtl_led *pled,
36 enum rtl_led_pin ledpin)
37{
38 pled->hw = hw;
39 pled->ledpin = ledpin;
40 pled->b_ledon = false;
41}
42
43void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
44{
45 u8 ledcfg;
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47
48 RT_TRACE(COMP_LED, DBG_LOUD,
49 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
50
51 switch (pled->ledpin) {
52 case LED_PIN_GPIO0:
53 break;
54 case LED_PIN_LED0:
55 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
56 ledcfg &= ~BIT(6);
57 rtl_write_byte(rtlpriv,
58 REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5));
59 break;
60 case LED_PIN_LED1:
61 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
62 rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
63 break;
64 default:
65 RT_TRACE(COMP_ERR, DBG_EMERG,
66 ("switch case not process \n"));
67 break;
68 }
69 pled->b_ledon = true;
70}
71
72void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
73{
74 u16 ledreg = REG_LEDCFG1;
75 u8 ledcfg = 0;
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
77
78 switch (pled->ledpin) {
79 case LED_PIN_LED0:
80 ledreg = REG_LEDCFG1;
81 break;
82
83 case LED_PIN_LED1:
84 ledreg = REG_LEDCFG2;
85 break;
86
87 case LED_PIN_GPIO0:
88 default:
89 break;
90 }
91
92 RT_TRACE(COMP_LED, DBG_LOUD, ("In SwLedOn, LedAddr:%X LEDPIN=%d \n", ledreg, pled->ledpin));
93
94 ledcfg = rtl_read_byte(rtlpriv, ledreg);
95 ledcfg |= BIT(5); /*Set 0x4c[21]*/
96 ledcfg &= ~(BIT(7) | BIT(6) | BIT(3) |BIT(2) | BIT(1) |BIT(0));
97 /*Clear 0x4c[23:22] and 0x4c[19:16]*/
98 rtl_write_byte(rtlpriv, ledreg, ledcfg); /*SW control led0 on.*/
99 pled->b_ledon = true;
100}
101
102void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
103{
104 struct rtl_priv *rtlpriv = rtl_priv(hw);
105 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
106 u8 ledcfg;
107
108 RT_TRACE(COMP_LED, DBG_LOUD,
109 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
110
111 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
112
113 switch (pled->ledpin) {
114 case LED_PIN_GPIO0:
115 break;
116 case LED_PIN_LED0:
117 ledcfg &= 0xf0;
118 if (pcipriv->ledctl.bled_opendrain == true) {
119 ledcfg &= 0x90; /* Set to software control. */
120 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3)));
121 ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
122 ledcfg &= 0xFE;
123 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ledcfg);
124 }
125 else {
126 ledcfg &= ~BIT(6);
127 rtl_write_byte(rtlpriv, REG_LEDCFG2,
128 (ledcfg | BIT(3) | BIT(5)));
129 }
130 break;
131 case LED_PIN_LED1:
132 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
133 ledcfg &= 0x10; /* Set to software control. */
134 rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg|BIT(3));
135
136 break;
137 default:
138 RT_TRACE(COMP_ERR, DBG_EMERG,
139 ("switch case not process \n"));
140 break;
141 }
142 pled->b_ledon = false;
143}
144
145void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled){
146 u16 ledreg = REG_LEDCFG1;
147 struct rtl_priv *rtlpriv = rtl_priv(hw);
148 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
149
150 switch(pled->ledpin)
151 {
152 case LED_PIN_LED0:
153 ledreg = REG_LEDCFG1;
154 break;
155
156 case LED_PIN_LED1:
157 ledreg = REG_LEDCFG2;
158 break;
159
160 case LED_PIN_GPIO0:
161 default:
162 break;
163 }
164
165 RT_TRACE(COMP_LED,DBG_LOUD,("In SwLedOff,LedAddr:%X LEDPIN=%d\n", ledreg, pled->ledpin));
166
167 if(pcipriv->ledctl.bled_opendrain == true) /*Open-drain arrangement for controlling the LED*/
168 {
169 u8 ledcfg = rtl_read_byte(rtlpriv, ledreg);
170
171 ledreg &= 0xd0; /* Set to software control.*/
172 rtl_write_byte(rtlpriv, ledreg, (ledcfg | BIT(3)));
173
174 /*Open-drain arrangement*/
175 ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
176 ledcfg &= 0xFE;/*Set GPIO[8] to input mode*/
177 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ledcfg);
178 }
179 else
180 {
181 rtl_write_byte(rtlpriv, ledreg, 0x28);
182 }
183
184 pled->b_ledon = false;
185}
186
187void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw)
188{
189 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
190 _rtl8821ae_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0);
191 _rtl8821ae_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1);
192}
193
194static void _rtl8821ae_sw_led_control(struct ieee80211_hw *hw,
195 enum led_ctl_mode ledaction)
196{
197 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
198 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
200 switch (ledaction) {
201 case LED_CTL_POWER_ON:
202 case LED_CTL_LINK:
203 case LED_CTL_NO_LINK:
204 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
205 rtl8812ae_sw_led_on(hw, pLed0);
206 else
207 rtl8821ae_sw_led_on(hw, pLed0);
208 break;
209 case LED_CTL_POWER_OFF:
210 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)\
211 rtl8812ae_sw_led_off(hw, pLed0);
212 else
213 rtl8821ae_sw_led_off(hw, pLed0);
214 break;
215 default:
216 break;
217 }
218}
219
220void rtl8821ae_led_control(struct ieee80211_hw *hw,
221 enum led_ctl_mode ledaction)
222{
223 struct rtl_priv *rtlpriv = rtl_priv(hw);
224 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
225
226 if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
227 (ledaction == LED_CTL_TX ||
228 ledaction == LED_CTL_RX ||
229 ledaction == LED_CTL_SITE_SURVEY ||
230 ledaction == LED_CTL_LINK ||
231 ledaction == LED_CTL_NO_LINK ||
232 ledaction == LED_CTL_START_TO_LINK ||
233 ledaction == LED_CTL_POWER_ON)) {
234 return;
235 }
236 RT_TRACE(COMP_LED, DBG_LOUD, ("ledaction %d, \n",
237 ledaction));
238 _rtl8821ae_sw_led_control(hw, ledaction);
239}
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/led.h b/drivers/staging/rtl8821ae/rtl8821ae/led.h
new file mode 100644
index 000000000000..44be401ba21f
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/led.h
@@ -0,0 +1,40 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8821AE_LED_H__
31#define __RTL8821AE_LED_H__
32
33void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw);
34void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
35void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
36void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
37void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
38void rtl8821ae_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
39
40#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/phy.c b/drivers/staging/rtl8821ae/rtl8821ae/phy.c
new file mode 100644
index 000000000000..d02fca38a2b2
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/phy.c
@@ -0,0 +1,5525 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "table.h"
39#include "trx.h"
40#include "../btcoexist/halbt_precomp.h"
41#include "hw.h"
42
43#define READ_NEXT_PAIR(array_table,v1, v2, i) do { i += 2; v1 = array_table[i]; v2 = array_table[i+1]; } while(0)
44
45static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
46 enum radio_path rfpath, u32 offset);
47static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
48 enum radio_path rfpath, u32 offset,
49 u32 data);
50static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask);
51static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw);
52static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
53static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
54static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
55 u8 configtype);
56static bool _rtl8812ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
57 u8 configtype);
58static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
59 u8 configtype);
60static bool _rtl8812ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
61 u8 configtype);
62static void _rtl8821ae_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
63
64static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
65 enum wireless_mode wirelessmode,
66 u8 txpwridx);
67static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw);
68static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw);
69
70void rtl8812ae_fixspur(
71 struct ieee80211_hw *hw,
72 enum ht_channel_width band_width,
73 u8 channel
74)
75{
76 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
77
78 /*C cut Item12 ADC FIFO CLOCK*/
79 if(IS_VENDOR_8812A_C_CUT(rtlhal->version))
80 {
81 if(band_width == HT_CHANNEL_WIDTH_20_40 && channel == 11)
82 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x3) ;
83 /* 0x8AC[11:10] = 2'b11*/
84 else
85 rtl_set_bbreg(hw, RRFMOD, 0xC00, 0x2);
86 /* 0x8AC[11:10] = 2'b10*/
87
88
89 /* <20120914, Kordan> A workarould to resolve
90 2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)*/
91 if (band_width == HT_CHANNEL_WIDTH_20 &&
92 (channel == 13 || channel == 14)) {
93 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
94 /*0x8AC[9:8] = 2'b11*/
95 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
96 /* 0x8C4[30] = 1*/
97 } else if (band_width == HT_CHANNEL_WIDTH_20_40 &&
98 channel == 11) {
99 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1);
100 /*0x8C4[30] = 1*/
101 } else if (band_width != HT_CHANNEL_WIDTH_80) {
102 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
103 /*0x8AC[9:8] = 2'b10*/
104 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
105 /*0x8C4[30] = 0*/
106 }
107 }
108 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
109 {
110 /* <20120914, Kordan> A workarould to resolve
111 2480Mhz spur by setting ADC clock as 160M. (Asked by Binson)*/
112 if (band_width == HT_CHANNEL_WIDTH_20 &&
113 (channel == 13 || channel == 14))
114 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x3);
115 /*0x8AC[9:8] = 11*/
116 else if (channel <= 14) /*2.4G only*/
117 rtl_set_bbreg(hw, RRFMOD, 0x300, 0x2);
118 /*0x8AC[9:8] = 10*/
119 }
120
121}
122
123u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
124{
125 struct rtl_priv *rtlpriv = rtl_priv(hw);
126 u32 returnvalue, originalvalue, bitshift;
127
128 RT_TRACE(COMP_RF, DBG_TRACE, ("regaddr(%#x), "
129 "bitmask(%#x)\n", regaddr,
130 bitmask));
131 originalvalue = rtl_read_dword(rtlpriv, regaddr);
132 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
133 returnvalue = (originalvalue & bitmask) >> bitshift;
134
135 RT_TRACE(COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
136 "Addr[0x%x]=0x%x\n", bitmask,
137 regaddr, originalvalue));
138
139 return returnvalue;
140
141}
142
143void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
144 u32 regaddr, u32 bitmask, u32 data)
145{
146 struct rtl_priv *rtlpriv = rtl_priv(hw);
147 u32 originalvalue, bitshift;
148
149 RT_TRACE(COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
150 " data(%#x)\n", regaddr, bitmask,
151 data));
152
153 if (bitmask != MASKDWORD) {
154 originalvalue = rtl_read_dword(rtlpriv, regaddr);
155 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
156 data = ((originalvalue & (~bitmask)) | ((data << bitshift) & bitmask));
157 }
158
159 rtl_write_dword(rtlpriv, regaddr, data);
160
161 RT_TRACE(COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
162 " data(%#x)\n", regaddr, bitmask,
163 data));
164
165}
166
167u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
168 enum radio_path rfpath, u32 regaddr, u32 bitmask)
169{
170 struct rtl_priv *rtlpriv = rtl_priv(hw);
171 u32 original_value, readback_value, bitshift;
172 unsigned long flags;
173
174 RT_TRACE(COMP_RF, DBG_TRACE, ("regaddr(%#x), "
175 "rfpath(%#x), bitmask(%#x)\n",
176 regaddr, rfpath, bitmask));
177
178 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
179
180
181 original_value = _rtl8821ae_phy_rf_serial_read(hw,rfpath, regaddr);
182 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
183 readback_value = (original_value & bitmask) >> bitshift;
184
185 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
186
187 RT_TRACE(COMP_RF, DBG_TRACE,
188 ("regaddr(%#x), rfpath(%#x), "
189 "bitmask(%#x), original_value(%#x)\n",
190 regaddr, rfpath, bitmask, original_value));
191
192 return readback_value;
193}
194
195void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
196 enum radio_path rfpath,
197 u32 regaddr, u32 bitmask, u32 data)
198{
199 struct rtl_priv *rtlpriv = rtl_priv(hw);
200 u32 original_value, bitshift;
201 unsigned long flags;
202
203 RT_TRACE(COMP_RF, DBG_TRACE,
204 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
205 regaddr, bitmask, data, rfpath));
206
207 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
208
209 if (bitmask != RFREG_OFFSET_MASK) {
210 original_value = _rtl8821ae_phy_rf_serial_read(hw,
211 rfpath,
212 regaddr);
213 bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask);
214 data =
215 ((original_value & (~bitmask)) |
216 (data << bitshift));
217 }
218
219 _rtl8821ae_phy_rf_serial_write(hw, rfpath, regaddr, data);
220
221
222 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
223
224 RT_TRACE(COMP_RF, DBG_TRACE, ("regaddr(%#x), "
225 "bitmask(%#x), data(%#x), rfpath(%#x)\n",
226 regaddr, bitmask, data, rfpath));
227
228}
229
230static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
231 enum radio_path rfpath, u32 offset)
232{
233 struct rtl_priv *rtlpriv = rtl_priv(hw);
234 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
235 bool b_is_pi_mode =false;
236 u32 retvalue = 0;
237
238 /* 2009/06/17 MH We can not execute IO for power save or other accident mode.*/
239 if (RT_CANNOT_IO(hw)) {
240 RT_TRACE(COMP_ERR, DBG_EMERG, ("return all one\n"));
241 return 0xFFFFFFFF;
242 }
243
244 /* <20120809, Kordan> CCA OFF(when entering), asked by James to avoid reading the wrong value.
245 <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/
246 if (offset != 0x0 &&
247 !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
248 || (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
249 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 1);
250
251 offset &= 0xff;
252
253 if (rfpath == RF90_PATH_A)
254 b_is_pi_mode = (bool) rtl_get_bbreg(hw, 0xC00, 0x4);
255 else if (rfpath == RF90_PATH_B)
256 b_is_pi_mode = (bool) rtl_get_bbreg(hw, 0xE00, 0x4);
257
258 rtl_set_bbreg(hw, RHSSIREAD_8821AE, 0xff, offset);
259
260 if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
261 || (IS_VENDOR_8812A_C_CUT(rtlhal->version)))
262 udelay(20);
263
264 if (b_is_pi_mode)
265 {
266 if (rfpath == RF90_PATH_A) {
267 retvalue = rtl_get_bbreg(hw, RA_PIREAD_8821A, BLSSIREADBACKDATA);
268 }
269 else if (rfpath == RF90_PATH_B){
270 retvalue = rtl_get_bbreg(hw, RB_PIREAD_8821A, BLSSIREADBACKDATA);
271 }
272 }
273 else
274 {
275 if (rfpath == RF90_PATH_A) {
276 retvalue = rtl_get_bbreg(hw, RA_SIREAD_8821A, BLSSIREADBACKDATA);
277 }
278 else if (rfpath == RF90_PATH_B){
279 retvalue = rtl_get_bbreg(hw, RB_SIREAD_8821A, BLSSIREADBACKDATA);
280 }
281 }
282
283 /*<20120809, Kordan> CCA ON(when exiting), asked by James to avoid reading the wrong value.
284 <20120828, Kordan> Toggling CCA would affect RF 0x0, skip it!*/
285 if (offset != 0x0 && ! ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
286 || (IS_VENDOR_8812A_C_CUT(rtlhal->version))))
287 rtl_set_bbreg(hw, RCCAONSEC, 0x8, 0);
288 return retvalue;
289}
290
291#if 0
292static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw,
293 enum radio_path rfpath, u32 offset)
294{
295 struct rtl_priv *rtlpriv = rtl_priv(hw);
296 struct rtl_phy *rtlphy = &(rtlpriv->phy);
297 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
298 u32 newoffset;
299 u32 tmplong, tmplong2;
300 u8 rfpi_enable = 0;
301 u32 retvalue;
302
303 offset &= 0xff;
304 newoffset = offset;
305 if (RT_CANNOT_IO(hw)) {
306 RT_TRACE(COMP_ERR, DBG_EMERG, ("return all one\n"));
307 return 0xFFFFFFFF;
308 }
309 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
310 if (rfpath == RF90_PATH_A)
311 tmplong2 = tmplong;
312 else
313 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
314 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
315 (newoffset << 23) | BLSSIREADEDGE;
316 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
317 tmplong & (~BLSSIREADEDGE));
318 mdelay(1);
319 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
320 mdelay(1);
321 /*rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
322 tmplong | BLSSIREADEDGE);*/
323 mdelay(1);
324 if (rfpath == RF90_PATH_A)
325 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
326 BIT(8));
327 else if (rfpath == RF90_PATH_B)
328 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
329 BIT(8));
330 if (rfpi_enable)
331 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
332 BLSSIREADBACKDATA);
333 else
334 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
335 BLSSIREADBACKDATA);
336 RT_TRACE(COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
337 rfpath, pphyreg->rflssi_readback,
338 retvalue));
339 return retvalue;
340}
341#endif
342
343static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw,
344 enum radio_path rfpath, u32 offset,
345 u32 data)
346{
347 u32 data_and_addr;
348 u32 newoffset;
349 struct rtl_priv *rtlpriv = rtl_priv(hw);
350 struct rtl_phy *rtlphy = &(rtlpriv->phy);
351 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
352
353 if (RT_CANNOT_IO(hw)) {
354 RT_TRACE(COMP_ERR, DBG_EMERG, ("stop\n"));
355 return;
356 }
357 offset &= 0xff;
358 newoffset = offset;
359 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
360 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
361 RT_TRACE(COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
362 rfpath, pphyreg->rf3wire_offset,
363 data_and_addr));
364}
365
366static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask)
367{
368 u32 i;
369
370 for (i = 0; i <= 31; i++) {
371 if (((bitmask >> i) & 0x1) == 1)
372 break;
373 }
374 return i;
375}
376
377bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw)
378{
379 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
380 bool rtstatus = 0;
381
382 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
383 rtstatus = _rtl8812ae_phy_config_mac_with_headerfile(hw);
384 else
385 rtstatus = _rtl8821ae_phy_config_mac_with_headerfile(hw);
386
387 return rtstatus;
388}
389
390bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw)
391{
392 bool rtstatus = true;
393 struct rtl_priv *rtlpriv = rtl_priv(hw);
394 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
395 struct rtl_phy *rtlphy = &(rtlpriv->phy);
396 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
397 u8 regval;
398 u8 crystal_cap;
399 //u32 tmp;
400
401 _rtl8821ae_phy_init_bb_rf_register_definition(hw);
402
403 regval = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
404 regval |= regval | FEN_PCIEA;
405 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, regval);
406 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
407 regval | FEN_BB_GLB_RSTN | FEN_BBRSTB);
408
409 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x7);/*RF_EN | RF_RSTB | RF_SDMRSTB*/
410 rtl_write_byte(rtlpriv, REG_OPT_CTRL + 2, 0x7);/*RF_EN | RF_RSTB | RF_SDMRSTB*/
411
412 rtstatus = _rtl8821ae_phy_bb8821a_config_parafile(hw);
413
414 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
415 {
416 crystal_cap = rtlefuse->crystalcap & 0x3F;
417 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6)));
418 }else{
419 crystal_cap = rtlefuse->crystalcap & 0x3F;
420 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, (crystal_cap | (crystal_cap << 6)));
421 }
422 rtlphy->reg_837 = rtl_read_byte(rtlpriv, 0x837);
423
424 return rtstatus;
425}
426
427bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw)
428{
429 return rtl8821ae_phy_rf6052_config(hw);
430}
431
432
433u32 phy_get_tx_bb_swing_8812A(
434 struct ieee80211_hw *hw,
435 u8 band,
436 u8 rf_path
437 )
438{
439 struct rtl_priv *rtlpriv = rtl_priv(hw);
440 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
441 struct rtl_dm *rtldm = rtl_dm(rtlpriv);
442 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
443
444 char bb_swing_2g = (char) (-1 * 0xFF);
445 char bb_swing_5g = (char) (-1 * 0xFF);
446 u32 out = 0x200;
447 const char auto_temp = -1;
448
449 RT_TRACE(COMP_SCAN, DBG_LOUD,
450 ("===> PHY_GetTxBBSwing_8812A, bbSwing_2G: %d, bbSwing_5G: %d\n",
451 (int)bb_swing_2g, (int)bb_swing_5g));
452
453 if ( rtlefuse->autoload_failflag) {
454 if ( band == BAND_ON_2_4G ) {
455 rtldm->bb_swing_diff_2g = bb_swing_2g;
456 if (bb_swing_2g == 0) out = 0x200; // 0 dB
457 else if (bb_swing_2g == -3) out = 0x16A; // -3 dB
458 else if (bb_swing_2g == -6) out = 0x101; // -6 dB
459 else if (bb_swing_2g == -9) out = 0x0B6; // -9 dB
460 else {
461 rtldm->bb_swing_diff_2g = 0;
462 out = 0x200;
463 }
464
465 } else if ( band == BAND_ON_5G ) {
466 rtldm->bb_swing_diff_5g = bb_swing_5g;
467 if (bb_swing_5g == 0) out = 0x200; // 0 dB
468 else if (bb_swing_5g == -3) out = 0x16A; // -3 dB
469 else if (bb_swing_5g == -6) out = 0x101; // -6 dB
470 else if (bb_swing_5g == -9) out = 0x0B6; // -9 dB
471 else {
472 if ( rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
473 rtldm->bb_swing_diff_5g = -3;
474 out = 0x16A;
475 } else {
476 rtldm->bb_swing_diff_5g = 0;
477 out = 0x200;
478 }
479 }
480 } else {
481 rtldm->bb_swing_diff_2g = -3;
482 rtldm->bb_swing_diff_5g = -3;
483 out = 0x16A; // -3 dB
484 }
485 }
486 else
487 {
488 u32 swing = 0, swing_a = 0, swing_b = 0;
489
490 if (band == BAND_ON_2_4G)
491 {
492 if (0xFF == auto_temp)
493 {
494 efuse_shadow_read(hw, 1, 0xC6, (u32 *)&swing);
495 swing = (swing == 0xFF) ? 0x00 : swing;
496 }
497 else if (bb_swing_2g == 0) swing = 0x00; // 0 dB
498 else if (bb_swing_2g == -3) swing = 0x05; // -3 dB
499 else if (bb_swing_2g == -6) swing = 0x0A; // -6 dB
500 else if (bb_swing_2g == -9) swing = 0xFF; // -9 dB
501 else swing = 0x00;
502 }
503 else
504 {
505 if (0xFF == auto_temp)
506 {
507 efuse_shadow_read(hw, 1, 0xC7, (u32 *)&swing);
508 swing = (swing == 0xFF) ? 0x00 : swing;
509 }
510 else if (bb_swing_5g == 0) swing = 0x00; // 0 dB
511 else if (bb_swing_5g == -3) swing = 0x05; // -3 dB
512 else if (bb_swing_5g == -6) swing = 0x0A; // -6 dB
513 else if (bb_swing_5g == -9) swing = 0xFF; // -9 dB
514 else swing = 0x00;
515 }
516
517 swing_a = (swing & 0x3) >> 0; // 0xC6/C7[1:0]
518 swing_b = (swing & 0xC) >> 2; // 0xC6/C7[3:2]
519 RT_TRACE(COMP_SCAN, DBG_LOUD,
520 ("===> PHY_GetTxBBSwing_8812A, swingA: 0x%X, swingB: 0x%X\n",
521 swing_a, swing_b));
522
523 //3 Path-A
524 if (swing_a == 0x0) {
525 if (band == BAND_ON_2_4G)
526 rtldm->bb_swing_diff_2g = 0;
527 else
528 rtldm->bb_swing_diff_5g = 0;
529 out = 0x200; // 0 dB
530 } else if (swing_a == 0x1) {
531 if (band == BAND_ON_2_4G)
532 rtldm->bb_swing_diff_2g = -3;
533 else
534 rtldm->bb_swing_diff_5g = -3;
535 out = 0x16A; // -3 dB
536 } else if (swing_a == 0x2) {
537 if (band == BAND_ON_2_4G)
538 rtldm->bb_swing_diff_2g = -6;
539 else
540 rtldm->bb_swing_diff_5g = -6;
541 out = 0x101; // -6 dB
542 } else if (swing_a == 0x3) {
543 if (band == BAND_ON_2_4G)
544 rtldm->bb_swing_diff_2g = -9;
545 else
546 rtldm->bb_swing_diff_5g = -9;
547 out = 0x0B6; // -9 dB
548 }
549
550 //3 Path-B
551 if (swing_b == 0x0) {
552 if (band == BAND_ON_2_4G)
553 rtldm->bb_swing_diff_2g = 0;
554 else
555 rtldm->bb_swing_diff_5g = 0;
556 out = 0x200; // 0 dB
557 } else if (swing_b == 0x1) {
558 if (band == BAND_ON_2_4G)
559 rtldm->bb_swing_diff_2g = -3;
560 else
561 rtldm->bb_swing_diff_5g = -3;
562 out = 0x16A; // -3 dB
563 } else if (swing_b == 0x2) {
564 if (band == BAND_ON_2_4G)
565 rtldm->bb_swing_diff_2g = -6;
566 else
567 rtldm->bb_swing_diff_5g = -6;
568 out = 0x101; // -6 dB
569 } else if (swing_b == 0x3) {
570 if (band == BAND_ON_2_4G)
571 rtldm->bb_swing_diff_2g = -9;
572 else
573 rtldm->bb_swing_diff_5g = -9;
574 out = 0x0B6; // -9 dB
575 }
576 }
577
578 RT_TRACE(COMP_SCAN, DBG_LOUD,
579 ("<=== PHY_GetTxBBSwing_8812A, out = 0x%X\n", out));
580 return out;
581}
582void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
583{
584 struct rtl_priv *rtlpriv = rtl_priv(hw);
585 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
586 struct rtl_dm *rtldm = rtl_dm(rtlpriv);
587 u8 current_band = rtlhal->current_bandtype;
588 u32 txpath, rxpath;
589 //u8 i, value8;
590 char bb_diff_between_band;
591
592 RT_TRACE(COMP_INIT, DBG_LOUD, ("\n"));
593 txpath = rtl8821ae_phy_query_bb_reg(hw, RTXPATH, 0xf0);
594 rxpath = rtl8821ae_phy_query_bb_reg(hw, RCCK_RX, 0x0f000000);
595 rtlhal->current_bandtype = (enum band_type) band;
596 /* reconfig BB/RF according to wireless mode */
597 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
598 /* BB & RF Config */
599 RT_TRACE(COMP_CMD, DBG_DMESG, ("2.4G\n"));
600 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
601
602 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
603 /* 0xCB0[15:12] = 0x7 (LNA_On)*/
604 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x7);
605 /* 0xCB0[7:4] = 0x7 (PAPE_A)*/
606 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x7);
607 }
608
609 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
610 rtl_set_bbreg(hw, 0x830, 0xE, 0x4); /*0x830[3:1] = 0x4*/
611 rtl_set_bbreg(hw, 0x834, 0x3, 0x1); /*0x834[1:0] = 0x1*/
612 }
613
614 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
615 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 0); // 0xC1C[11:8] = 0
616 else
617 rtl_set_bbreg(hw, 0x82c, 0x3, 0); // 0x82C[1:0] = 2b'00
618
619 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
620 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77777777);
621 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77777777);
622 rtl_set_bbreg(hw, RA_RFE_INV, 0x3ff00000, 0x000);
623 rtl_set_bbreg(hw, RB_RFE_INV, 0x3ff00000, 0x000);
624 }
625
626 rtl_set_bbreg(hw, RTXPATH, 0xf0, txpath);
627 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, rxpath);
628
629 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x0);
630 } else {/* 5G band */
631 u16 count, reg_41a;
632 RT_TRACE(COMP_CMD, DBG_DMESG, ("5G\n"));
633
634 if(rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
635 /*0xCB0[15:12] = 0x5 (LNA_On)*/
636 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF000, 0x5);
637 /*0xCB0[7:4] = 0x4 (PAPE_A)*/
638 rtl_set_bbreg(hw, RA_RFE_PINMUX, 0xF0, 0x4);
639 }
640 /*CCK_CHECK_en*/
641 rtl_write_byte(rtlpriv, REG_CCK_CHECK, 0x80);
642
643 count = 0;
644 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
645 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Reg41A value %d", reg_41a));
646 reg_41a &= 0x30;
647 while ((reg_41a!= 0x30) && (count < 50)) {
648 udelay(50);
649 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Delay 50us \n"));
650
651 reg_41a = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
652 reg_41a &= 0x30;
653 count++;
654 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Reg41A value %d", reg_41a));
655 }
656 if (count != 0)
657 RT_TRACE(COMP_MLME, DBG_LOUD,
658 ("PHY_SwitchWirelessBand8812(): Switch to 5G Band. "
659 "Count = %d reg41A=0x%x\n", count, reg_41a));
660
661 // 2012/02/01, Sinda add registry to switch workaround without long-run verification for scan issue.
662 rtl_set_bbreg(hw, ROFDMCCKEN, BOFDMEN|BCCKEN, 0x03);
663
664 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
665 rtl_set_bbreg(hw, 0x830, 0xE, 0x3); /*0x830[3:1] = 0x3*/
666 rtl_set_bbreg(hw, 0x834, 0x3, 0x2); /*0x834[1:0] = 0x2*/
667 }
668
669 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
670 /* AGC table select */
671 rtl_set_bbreg(hw, RA_TXSCALE, 0xF00, 1); /* 0xC1C[11:8] = 1*/
672 } else
673 rtl_set_bbreg(hw, 0x82c, 0x3, 1); // 0x82C[1:0] = 2'b00
674
675 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
676 rtl_set_bbreg(hw, RA_RFE_PINMUX, BMASKDWORD, 0x77337777);
677 rtl_set_bbreg(hw, RB_RFE_PINMUX, BMASKDWORD, 0x77337777);
678 rtl_set_bbreg(hw, RA_RFE_INV, 0x3ff00000, 0x010);
679 rtl_set_bbreg(hw, RB_RFE_INV, 0x3ff00000, 0x010);
680 }
681
682 rtl_set_bbreg(hw, RTXPATH, 0xf0, txpath);
683 rtl_set_bbreg(hw, RCCK_RX, 0x0f000000, rxpath);
684
685 RT_TRACE(COMP_SCAN, DBG_LOUD,
686 ("==>PHY_SwitchWirelessBand8812() BAND_ON_5G settings OFDM index 0x%x\n",
687 rtlpriv->dm.ofdm_index[RF90_PATH_A]));
688 }
689
690 if ((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) ||
691 (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)) {
692 rtl_set_bbreg(hw, RA_TXSCALE, 0xFFE00000,
693 phy_get_tx_bb_swing_8812A(hw, band, RF90_PATH_A)); // 0xC1C[31:21]
694 rtl_set_bbreg(hw, RB_TXSCALE, 0xFFE00000,
695 phy_get_tx_bb_swing_8812A(hw, band, RF90_PATH_B)); // 0xE1C[31:21]
696
697 /* <20121005, Kordan> When TxPowerTrack is ON, we should take care of the change of BB swing.
698 That is, reset all info to trigger Tx power tracking.*/
699 if (band != current_band) {
700 bb_diff_between_band = (rtldm->bb_swing_diff_2g - rtldm->bb_swing_diff_5g);
701 bb_diff_between_band = (band == BAND_ON_2_4G) ? bb_diff_between_band : (-1 * bb_diff_between_band);
702 rtldm->default_ofdm_index += bb_diff_between_band * 2;
703 }
704 rtl8821ae_dm_clear_txpower_tracking_state(hw);
705 }
706
707 RT_TRACE(COMP_SCAN, DBG_TRACE,
708 ("<==rtl8821ae_phy_switch_wirelessband():Switch Band OK.\n"));
709 return;
710}
711
712static bool _rtl8821ae_check_condition(struct ieee80211_hw *hw,
713 const u32 Condition
714 )
715{
716 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
717 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
718 u32 _board = rtlefuse->board_type; /*need efuse define*/
719 u32 _interface = rtlhal->interface;
720 u32 _platform = 0x08;/*SupportPlatform */
721 u32 cond = Condition;
722
723 if ( Condition == 0xCDCDCDCD )
724 return true;
725
726 cond = Condition & 0xFF;
727 if ( (_board != cond) == 0 && cond != 0xFF)
728 return false;
729
730 cond = Condition & 0xFF00;
731 cond = cond >> 8;
732 if ( (_interface & cond) == 0 && cond != 0x07)
733 return false;
734
735 cond = Condition & 0xFF0000;
736 cond = cond >> 16;
737 if ( (_platform & cond) == 0 && cond != 0x0F)
738 return false;
739 return true;
740}
741
742static void _rtl8821ae_config_rf_reg(struct ieee80211_hw *hw,
743 u32 addr,
744 u32 data,
745 enum radio_path rfpath,
746 u32 regaddr
747 )
748{
749 if ( addr == 0xfe || addr == 0xffe) {
750 mdelay(50);
751 } else {
752 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
753 udelay(1);
754 }
755}
756
757static void _rtl8821ae_config_rf_radio_a(struct ieee80211_hw *hw,
758 u32 addr, u32 data)
759{
760 u32 content = 0x1000; /*RF Content: radio_a_txt*/
761 u32 maskforphyset = (u32)(content & 0xE000);
762
763 _rtl8821ae_config_rf_reg(hw, addr, data, RF90_PATH_A, addr | maskforphyset);
764
765}
766
767static void _rtl8821ae_config_rf_radio_b(struct ieee80211_hw *hw,
768 u32 addr, u32 data)
769{
770 u32 content = 0x1001; /*RF Content: radio_b_txt*/
771 u32 maskforphyset = (u32)(content & 0xE000);
772
773 _rtl8821ae_config_rf_reg(hw, addr, data, RF90_PATH_B, addr | maskforphyset);
774
775}
776
777static void _rtl8812ae_config_bb_reg(struct ieee80211_hw *hw,
778 u32 addr, u32 data)
779{
780 if ( addr == 0xfe) {
781 mdelay(50);
782 } else if ( addr == 0xfd)
783 mdelay(5);
784 else if ( addr == 0xfc)
785 mdelay(1);
786 else if ( addr == 0xfb)
787 udelay(50);
788 else if ( addr == 0xfa)
789 udelay(5);
790 else if ( addr == 0xf9)
791 udelay(1);
792 else {
793 rtl_set_bbreg(hw, addr, MASKDWORD,data);
794 }
795 udelay(1);
796}
797
798static void _rtl8821ae_config_bb_reg(struct ieee80211_hw *hw,
799 u32 addr, u32 data)
800{
801 if ( addr == 0xfe) {
802 mdelay(50);
803 } else if ( addr == 0xfd)
804 mdelay(5);
805 else if ( addr == 0xfc)
806 mdelay(1);
807 else if ( addr == 0xfb)
808 udelay(50);
809 else if ( addr == 0xfa)
810 udelay(5);
811 else if ( addr == 0xf9)
812 udelay(1);
813
814 rtl_set_bbreg(hw, addr, MASKDWORD,data);
815 udelay(1);
816}
817
818static void _rtl8821ae_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
819{
820 struct rtl_priv *rtlpriv = rtl_priv(hw);
821 struct rtl_phy *rtlphy = &(rtlpriv->phy);
822
823 u8 band, rfpath, txnum, rate_section;
824
825 for ( band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band )
826 for ( rfpath = 0; rfpath < TX_PWR_BY_RATE_NUM_RF; ++rfpath )
827 for ( txnum = 0; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum )
828 for ( rate_section = 0; rate_section < TX_PWR_BY_RATE_NUM_SECTION; ++rate_section )
829 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = 0;
830}
831
832void _rtl8821ae_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
833 u8 band, u8 path,
834 u8 rate_section,
835 u8 txnum, u8 value)
836{
837 struct rtl_priv *rtlpriv = rtl_priv(hw);
838 struct rtl_phy *rtlphy = &(rtlpriv->phy);
839
840 if (path > RF90_PATH_D) {
841 RT_TRACE(COMP_INIT, DBG_LOUD,
842 ("Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n", path));
843 return;
844 }
845
846 if (band == BAND_ON_2_4G) {
847 switch (rate_section) {
848 case CCK:
849 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
850 break;
851 case OFDM:
852 rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
853 break;
854 case HT_MCS0_MCS7:
855 rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
856 break;
857 case HT_MCS8_MCS15:
858 rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
859 break;
860 case VHT_1SSMCS0_1SSMCS9:
861 rtlphy->txpwr_by_rate_base_24g[path][txnum][4] = value;
862 break;
863 case VHT_2SSMCS0_2SSMCS9:
864 rtlphy->txpwr_by_rate_base_24g[path][txnum][5] = value;
865 break;
866 default:
867 RT_TRACE(COMP_INIT, DBG_LOUD, ( "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
868 rate_section, path, txnum ) );
869 break;
870 };
871 } else if (band == BAND_ON_5G) {
872 switch (rate_section) {
873 case OFDM:
874 rtlphy->txpwr_by_rate_base_5g[path][txnum][0] = value;
875 break;
876 case HT_MCS0_MCS7:
877 rtlphy->txpwr_by_rate_base_5g[path][txnum][1] = value;
878 break;
879 case HT_MCS8_MCS15:
880 rtlphy->txpwr_by_rate_base_5g[path][txnum][2] = value;
881 break;
882 case VHT_1SSMCS0_1SSMCS9:
883 rtlphy->txpwr_by_rate_base_5g[path][txnum][3] = value;
884 break;
885 case VHT_2SSMCS0_2SSMCS9:
886 rtlphy->txpwr_by_rate_base_5g[path][txnum][4] = value;
887 break;
888 default:
889 RT_TRACE(COMP_INIT, DBG_LOUD,
890 ("Invalid RateSection %d in Band 5G, Rf Path %d, "
891 "%dTx in PHY_SetTxPowerByRateBase()\n",
892 rate_section, path, txnum));
893 break;
894 };
895 } else {
896 RT_TRACE(COMP_INIT, DBG_LOUD,
897 ("Invalid Band %d in PHY_SetTxPowerByRateBase()\n", band));
898 }
899
900}
901
902u8 _rtl8821ae_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
903 u8 band, u8 path,
904 u8 txnum, u8 rate_section)
905{
906 struct rtl_priv *rtlpriv = rtl_priv(hw);
907 struct rtl_phy *rtlphy = &(rtlpriv->phy);
908 u8 value = 0;
909
910 if (path > RF90_PATH_D) {
911 RT_TRACE(COMP_INIT, DBG_LOUD,
912 ("Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n", path));
913 return 0;
914 }
915
916 if (band == BAND_ON_2_4G) {
917 switch (rate_section) {
918 case CCK:
919 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
920 break;
921 case OFDM:
922 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
923 break;
924 case HT_MCS0_MCS7:
925 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
926 break;
927 case HT_MCS8_MCS15:
928 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
929 break;
930 case VHT_1SSMCS0_1SSMCS9:
931 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][4];
932 break;
933 case VHT_2SSMCS0_2SSMCS9:
934 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][5];
935 break;
936 default:
937 RT_TRACE(COMP_INIT, DBG_LOUD,
938 ("Invalid RateSection %d in Band 2.4G, Rf Path %d,"
939 " %dTx in PHY_GetTxPowerByRateBase()\n",
940 rate_section, path, txnum));
941 break;
942 };
943 } else if (band == BAND_ON_5G) {
944 switch (rate_section) {
945 case OFDM:
946 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][0];
947 break;
948 case HT_MCS0_MCS7:
949 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][1];
950 break;
951 case HT_MCS8_MCS15:
952 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][2];
953 break;
954 case VHT_1SSMCS0_1SSMCS9:
955 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][3];
956 break;
957 case VHT_2SSMCS0_2SSMCS9:
958 value = rtlphy->txpwr_by_rate_base_5g[path][txnum][4];
959 break;
960 default:
961 RT_TRACE(COMP_INIT, DBG_LOUD,
962 ("Invalid RateSection %d in Band 5G, Rf Path %d,"
963 " %dTx in PHY_GetTxPowerByRateBase()\n",
964 rate_section, path, txnum));
965 break;
966 };
967 } else {
968 RT_TRACE(COMP_INIT, DBG_LOUD,
969 ("Invalid Band %d in PHY_GetTxPowerByRateBase()\n", band));
970 }
971
972 return value;
973
974}
975void _rtl8821ae_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
976{
977 struct rtl_priv *rtlpriv = rtl_priv(hw);
978 struct rtl_phy *rtlphy = &(rtlpriv->phy);
979 u16 rawValue = 0;
980 u8 base = 0, path = 0;
981
982 for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
983 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][0] >> 24) & 0xFF;
984 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
985 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, CCK, RF_1TX, base);
986
987 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][2] >> 24) & 0xFF;
988 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
989 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, OFDM, RF_1TX, base );
990
991 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][4] >> 24) & 0xFF;
992 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
993 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base );
994
995 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][6] >> 24) & 0xFF;
996 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
997 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base );
998
999 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_1TX][8] >> 24) & 0xFF;
1000 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1001 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base );
1002
1003 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][path][RF_2TX][11] >> 8) & 0xFF;
1004 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1005 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base );
1006
1007 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][2] >> 24) & 0xFF;
1008 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1009 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, OFDM, RF_1TX, base );
1010
1011 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][4] >> 24) & 0xFF;
1012 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1013 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base );
1014
1015 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][6] >> 24) & 0xFF;
1016 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1017 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base );
1018
1019 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_1TX][8] >> 24) & 0xFF;
1020 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1021 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base );
1022
1023 rawValue = (u16) (rtlphy->tx_power_by_rate_offset[BAND_ON_5G][path][RF_2TX][11] >> 8) & 0xFF;
1024 base = (rawValue >> 4) * 10 + (rawValue & 0xF);
1025 _rtl8821ae_phy_set_txpower_by_rate_base(hw, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base );
1026 }
1027}
1028
1029void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
1030 u8 end, u8 base_val)
1031{
1032 char i = 0;
1033 u8 temp_value = 0;
1034 u32 temp_data = 0;
1035
1036 for (i = 3; i >= 0; --i)
1037 {
1038 if (i >= start && i <= end) {
1039 // Get the exact value
1040 temp_value = (u8) (*data >> (i * 8)) & 0xF;
1041 temp_value += ((u8) ((*data >> (i * 8 + 4)) & 0xF)) * 10;
1042
1043 // Change the value to a relative value
1044 temp_value = (temp_value > base_val) ? temp_value - base_val : base_val - temp_value;
1045 } else {
1046 temp_value = (u8) (*data >> (i * 8)) & 0xFF;
1047 }
1048 temp_data <<= 8;
1049 temp_data |= temp_value;
1050 }
1051 *data = temp_data;
1052}
1053
1054void _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(struct ieee80211_hw *hw)
1055{
1056 struct rtl_priv *rtlpriv = rtl_priv(hw);
1057 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1058 u8 base = 0, rfPath = 0;
1059
1060 for (rfPath = RF90_PATH_A; rfPath <= RF90_PATH_B; ++rfPath) {
1061 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, CCK);
1062 RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G CCK 1TX: %d\n", base ) );
1063 _phy_convert_txpower_dbm_to_relative_value(
1064 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][0] ),
1065 0, 3, base );
1066
1067 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, OFDM );
1068 RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G OFDM 1TX: %d\n", base ) );
1069 _phy_convert_txpower_dbm_to_relative_value(
1070 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][1] ),
1071 0, 3, base );
1072 _phy_convert_txpower_dbm_to_relative_value(
1073 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][2] ),
1074 0, 3, base );
1075
1076 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, HT_MCS0_MCS7 );
1077 RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G HTMCS0-7 1TX: %d\n", base ) );
1078 _phy_convert_txpower_dbm_to_relative_value(
1079 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][3] ),
1080 0, 3, base );
1081 _phy_convert_txpower_dbm_to_relative_value(
1082 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][4] ),
1083 0, 3, base );
1084
1085 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_2TX, HT_MCS8_MCS15 );
1086 RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G HTMCS8-15 2TX: %d\n", base ) );
1087
1088 _phy_convert_txpower_dbm_to_relative_value(
1089 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][5] ),
1090 0, 3, base );
1091
1092 _phy_convert_txpower_dbm_to_relative_value(
1093 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][6] ),
1094 0, 3, base );
1095
1096 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_1TX, VHT_1SSMCS0_1SSMCS9 );
1097 RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G VHT1SSMCS0-9 1TX: %d\n", base ) );
1098 _phy_convert_txpower_dbm_to_relative_value(
1099 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][7] ),
1100 0, 3, base );
1101 _phy_convert_txpower_dbm_to_relative_value(
1102 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][8] ),
1103 0, 3, base );
1104 _phy_convert_txpower_dbm_to_relative_value(
1105 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][9] ),
1106 0, 1, base );
1107
1108 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_2_4G, rfPath, RF_2TX, VHT_2SSMCS0_2SSMCS9 );
1109 RT_DISP( FPHY, PHY_TXPWR, ( "base of 2.4G VHT2SSMCS0-9 2TX: %d\n", base ) );
1110 _phy_convert_txpower_dbm_to_relative_value(
1111 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_1TX][9] ),
1112 2, 3, base );
1113 _phy_convert_txpower_dbm_to_relative_value(
1114 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][10] ),
1115 0, 3, base );
1116 _phy_convert_txpower_dbm_to_relative_value(
1117 &(rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfPath][RF_2TX][11] ),
1118 0, 3, base );
1119
1120 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, OFDM );
1121 RT_DISP( FPHY, PHY_TXPWR, ( "base of 5G OFDM 1TX: %d\n", base ) );
1122 _phy_convert_txpower_dbm_to_relative_value(
1123 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][1] ),
1124 0, 3, base );
1125 _phy_convert_txpower_dbm_to_relative_value(
1126 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][2] ),
1127 0, 3, base );
1128
1129 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, HT_MCS0_MCS7 );
1130 RT_DISP( FPHY, PHY_TXPWR, ( "base of 5G HTMCS0-7 1TX: %d\n", base ) );
1131 _phy_convert_txpower_dbm_to_relative_value(
1132 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][3] ),
1133 0, 3, base );
1134 _phy_convert_txpower_dbm_to_relative_value(
1135 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][4] ),
1136 0, 3, base );
1137
1138 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_2TX, HT_MCS8_MCS15 );
1139 RT_DISP( FPHY, PHY_TXPWR, ( "base of 5G HTMCS8-15 2TX: %d\n", base ) );
1140 _phy_convert_txpower_dbm_to_relative_value(
1141 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][5] ),
1142 0, 3, base );
1143 _phy_convert_txpower_dbm_to_relative_value(
1144 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][6] ),
1145 0, 3, base );
1146
1147 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_1TX, VHT_1SSMCS0_1SSMCS9 );
1148 RT_DISP( FPHY, PHY_TXPWR, ( "base of 5G VHT1SSMCS0-9 1TX: %d\n", base ) );
1149 _phy_convert_txpower_dbm_to_relative_value(
1150 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][7] ),
1151 0, 3, base );
1152 _phy_convert_txpower_dbm_to_relative_value(
1153 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][8] ),
1154 0, 3, base );
1155 _phy_convert_txpower_dbm_to_relative_value(
1156 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][9] ),
1157 0, 1, base );
1158
1159 base = _rtl8821ae_phy_get_txpower_by_rate_base(hw, BAND_ON_5G, rfPath, RF_2TX, VHT_2SSMCS0_2SSMCS9 );
1160 RT_DISP( FPHY, PHY_TXPWR, ( "base of 5G VHT2SSMCS0-9 2TX: %d\n", base ) );
1161 _phy_convert_txpower_dbm_to_relative_value(
1162 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_1TX][9] ),
1163 2, 3, base );
1164 _phy_convert_txpower_dbm_to_relative_value(
1165 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][10] ),
1166 0, 3, base );
1167 _phy_convert_txpower_dbm_to_relative_value(
1168 &(rtlphy->tx_power_by_rate_offset[BAND_ON_5G][rfPath][RF_2TX][11] ),
1169 0, 3, base );
1170 }
1171
1172 RT_TRACE(COMP_POWER, DBG_TRACE,
1173 ("<===_rtl8821ae_phy_convert_txpower_dbm_to_relative_value()\n"));
1174
1175}
1176
1177void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
1178{
1179 _rtl8821ae_phy_store_txpower_by_rate_base(hw);
1180 _rtl8821ae_phy_convert_txpower_dbm_to_relative_value(hw);
1181}
1182
1183static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw)
1184{
1185 struct rtl_priv *rtlpriv = rtl_priv(hw);
1186 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1187 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1188 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1189 bool rtstatus;
1190
1191 /*TX POWER LIMIT
1192 PHY_InitTxPowerLimit
1193 PHY_ConfigRFWithCustomPowerLimitTableParaFile*/
1194 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1195 rtstatus = _rtl8812ae_phy_config_bb_with_headerfile(hw,
1196 BASEBAND_CONFIG_PHY_REG);
1197 else{
1198 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1199 BASEBAND_CONFIG_PHY_REG);
1200 }
1201 if (rtstatus != true) {
1202 RT_TRACE(COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
1203 return false;
1204 }
1205 _rtl8821ae_phy_init_tx_power_by_rate(hw);
1206 if (rtlefuse->autoload_failflag == false) {
1207 //rtlphy->pwrgroup_cnt = 0;
1208 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1209 rtstatus = _rtl8812ae_phy_config_bb_with_pgheaderfile(hw,
1210 BASEBAND_CONFIG_PHY_REG);
1211 else{
1212 rtstatus = _rtl8821ae_phy_config_bb_with_pgheaderfile(hw,
1213 BASEBAND_CONFIG_PHY_REG);
1214 }
1215 }
1216 if (rtstatus != true) {
1217 RT_TRACE(COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
1218 return false;
1219 }
1220
1221 _rtl8821ae_phy_txpower_by_rate_configuration(hw);
1222
1223 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1224 rtstatus = _rtl8812ae_phy_config_bb_with_headerfile(hw,
1225 BASEBAND_CONFIG_AGC_TAB);
1226 else
1227 rtstatus = _rtl8821ae_phy_config_bb_with_headerfile(hw,
1228 BASEBAND_CONFIG_AGC_TAB);
1229
1230 if (rtstatus != true) {
1231 RT_TRACE(COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
1232 return false;
1233 }
1234 rtlphy->bcck_high_power = (bool) (rtl_get_bbreg(hw,
1235 RFPGA0_XA_HSSIPARAMETER2,
1236 0x200));
1237 return true;
1238}
1239
1240static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
1241{
1242 struct rtl_priv *rtlpriv = rtl_priv(hw);
1243 u32 i, v1, v2;
1244 u32 arraylength;
1245 u32 *ptrarray;
1246
1247 RT_TRACE(COMP_INIT, DBG_TRACE, ("Read rtl8812AE_MAC_REG_Array\n"));
1248 arraylength = RTL8812AEMAC_1T_ARRAYLEN;
1249 ptrarray = RTL8812AE_MAC_REG_ARRAY;
1250 RT_TRACE(COMP_INIT, DBG_LOUD,
1251 ("Img:RTL8812AE_MAC_REG_ARRAY LEN %d\n",arraylength));
1252 for (i = 0; i < arraylength; i += 2) {
1253 v1 = ptrarray[i];
1254 v2 = (u8) ptrarray[i + 1];
1255 if (v1<0xCDCDCDCD) {
1256 rtl_write_byte(rtlpriv, v1, (u8) v2);
1257 } else {
1258 if (!_rtl8821ae_check_condition(hw,v1)) {
1259 /*Discard the following (offset, data) pairs*/
1260 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1261 while (v2 != 0xDEAD &&
1262 v2 != 0xCDEF &&
1263 v2 != 0xCDCD && i < arraylength -2)
1264 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1265
1266 i -= 2; /* prevent from for-loop += 2*/
1267 } else {/*Configure matched pairs and skip to end of if-else.*/
1268 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1269 while (v2 != 0xDEAD &&
1270 v2 != 0xCDEF &&
1271 v2 != 0xCDCD && i < arraylength -2) {
1272 rtl_write_byte(rtlpriv,v1,v2);
1273 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1274 }
1275
1276 while (v2 != 0xDEAD && i < arraylength -2)
1277 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1278 }
1279 }
1280 }
1281 return true;
1282}
1283
1284static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
1285{
1286 struct rtl_priv *rtlpriv = rtl_priv(hw);
1287 u32 i, v1, v2;
1288 u32 arraylength;
1289 u32 *ptrarray;
1290
1291 RT_TRACE(COMP_INIT, DBG_TRACE, ("Read rtl8821AE_MAC_REG_Array\n"));
1292 arraylength = RTL8821AEMAC_1T_ARRAYLEN;
1293 ptrarray = RTL8821AE_MAC_REG_ARRAY;
1294 RT_TRACE(COMP_INIT, DBG_LOUD,
1295 ("Img:RTL8821AE_MAC_REG_ARRAY LEN %d\n",arraylength));
1296 for (i = 0; i < arraylength; i += 2) {
1297 v1 = ptrarray[i];
1298 v2 = (u8) ptrarray[i + 1];
1299 if (v1<0xCDCDCDCD) {
1300 rtl_write_byte(rtlpriv, v1, (u8) v2);
1301 continue;
1302 } else {
1303 if (!_rtl8821ae_check_condition(hw,v1)) {
1304 /*Discard the following (offset, data) pairs*/
1305 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1306 while (v2 != 0xDEAD &&
1307 v2 != 0xCDEF &&
1308 v2 != 0xCDCD && i < arraylength -2)
1309 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1310
1311 i -= 2; /* prevent from for-loop += 2*/
1312 } else {/*Configure matched pairs and skip to end of if-else.*/
1313 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1314 while (v2 != 0xDEAD &&
1315 v2 != 0xCDEF &&
1316 v2 != 0xCDCD && i < arraylength -2) {
1317 rtl_write_byte(rtlpriv,v1,v2);
1318 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1319 }
1320
1321 while (v2 != 0xDEAD && i < arraylength -2)
1322 READ_NEXT_PAIR(ptrarray, v1, v2, i);
1323 }
1324 }
1325 }
1326 return true;
1327}
1328
1329static bool _rtl8812ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
1330 u8 configtype)
1331{
1332 int i;
1333 u32 *array_table;
1334 u16 arraylen;
1335 struct rtl_priv *rtlpriv = rtl_priv(hw);
1336 u32 v1 = 0, v2 = 0;
1337
1338 if (configtype == BASEBAND_CONFIG_PHY_REG) {
1339 arraylen = RTL8812AEPHY_REG_1TARRAYLEN;
1340 array_table = RTL8812AE_PHY_REG_ARRAY;
1341
1342 for (i = 0; i < arraylen; i += 2) {
1343 v1 = array_table[i];
1344 v2 = array_table[i+1];
1345 if (v1<0xCDCDCDCD) {
1346 _rtl8812ae_config_bb_reg(hw, v1, v2);
1347 continue;
1348 } else {/*This line is the start line of branch.*/
1349 if (!_rtl8821ae_check_condition(hw,v1)) {
1350 /*Discard the following (offset, data) pairs*/
1351 READ_NEXT_PAIR(array_table,v1, v2, i);
1352 while (v2 != 0xDEAD &&
1353 v2 != 0xCDEF &&
1354 v2 != 0xCDCD && i < arraylen -2)
1355 READ_NEXT_PAIR(array_table,v1, v2, i);
1356
1357 i -= 2; /* prevent from for-loop += 2*/
1358 } else {/*Configure matched pairs and skip to end of if-else.*/
1359 READ_NEXT_PAIR(array_table,v1, v2, i);
1360 while (v2 != 0xDEAD &&
1361 v2 != 0xCDEF &&
1362 v2 != 0xCDCD && i < arraylen -2) {
1363 _rtl8812ae_config_bb_reg(hw,v1,v2);
1364 READ_NEXT_PAIR(array_table,v1, v2, i);
1365 }
1366
1367 while (v2 != 0xDEAD && i < arraylen -2)
1368 READ_NEXT_PAIR(array_table,v1, v2, i);
1369 }
1370 }
1371 }
1372 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
1373 arraylen = RTL8812AEAGCTAB_1TARRAYLEN;
1374 array_table = RTL8812AE_AGC_TAB_ARRAY;
1375
1376 for (i = 0; i < arraylen; i = i + 2) {
1377 v1 = array_table[i];
1378 v2 = array_table[i+1];
1379 if (v1 < 0xCDCDCDCD) {
1380 rtl_set_bbreg(hw, v1, MASKDWORD, v2);
1381 udelay(1);
1382 continue;
1383 } else {/*This line is the start line of branch.*/
1384 if (!_rtl8821ae_check_condition(hw,v1)) {
1385 /*Discard the following (offset, data) pairs*/
1386 READ_NEXT_PAIR(array_table,v1, v2, i);
1387 while (v2 != 0xDEAD &&
1388 v2 != 0xCDEF &&
1389 v2 != 0xCDCD && i < arraylen -2)
1390 READ_NEXT_PAIR(array_table,v1, v2, i);
1391
1392 i -= 2; /* prevent from for-loop += 2*/
1393 }else{/*Configure matched pairs and skip to end of if-else.*/
1394 READ_NEXT_PAIR(array_table,v1, v2, i);
1395 while (v2 != 0xDEAD &&
1396 v2 != 0xCDEF &&
1397 v2 != 0xCDCD && i < arraylen -2)
1398 {
1399 rtl_set_bbreg(hw, v1, MASKDWORD, v2);
1400 udelay(1);
1401 READ_NEXT_PAIR(array_table,v1, v2, i);
1402 }
1403
1404 while (v2 != 0xDEAD && i < arraylen -2)
1405 READ_NEXT_PAIR(array_table,v1, v2, i);
1406 }
1407 }
1408 RT_TRACE(COMP_INIT, DBG_TRACE,
1409 ("The agctab_array_table[0] is "
1410 "%x Rtl818EEPHY_REGArray[1] is %x \n",
1411 array_table[i],
1412 array_table[i + 1]));
1413 }
1414 }
1415 return true;
1416}
1417
1418static bool _rtl8821ae_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
1419 u8 configtype)
1420{
1421 int i;
1422 u32 *array_table;
1423 u16 arraylen;
1424 struct rtl_priv *rtlpriv = rtl_priv(hw);
1425 u32 v1 = 0, v2 = 0;
1426
1427 if (configtype == BASEBAND_CONFIG_PHY_REG) {
1428 arraylen = RTL8821AEPHY_REG_1TARRAYLEN;
1429 array_table = RTL8821AE_PHY_REG_ARRAY;
1430
1431 for (i = 0; i < arraylen; i += 2) {
1432 v1 = array_table[i];
1433 v2 = array_table[i+1];
1434 if (v1<0xCDCDCDCD) {
1435 _rtl8821ae_config_bb_reg(hw, v1, v2);
1436 continue;
1437 } else {/*This line is the start line of branch.*/
1438 if (!_rtl8821ae_check_condition(hw,v1)) {
1439 /*Discard the following (offset, data) pairs*/
1440 READ_NEXT_PAIR(array_table, v1, v2, i);
1441 while (v2 != 0xDEAD &&
1442 v2 != 0xCDEF &&
1443 v2 != 0xCDCD && i < arraylen -2)
1444 READ_NEXT_PAIR(array_table, v1, v2, i);
1445
1446 i -= 2; /* prevent from for-loop += 2*/
1447 } else {/*Configure matched pairs and skip to end of if-else.*/
1448 READ_NEXT_PAIR(array_table, v1, v2, i);
1449 while (v2 != 0xDEAD &&
1450 v2 != 0xCDEF &&
1451 v2 != 0xCDCD && i < arraylen -2) {
1452 _rtl8821ae_config_bb_reg(hw,v1,v2);
1453 READ_NEXT_PAIR(array_table, v1, v2, i);
1454 }
1455
1456 while (v2 != 0xDEAD && i < arraylen -2)
1457 READ_NEXT_PAIR(array_table, v1, v2, i);
1458 }
1459 }
1460 }
1461 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
1462 arraylen = RTL8821AEAGCTAB_1TARRAYLEN;
1463 array_table = RTL8821AE_AGC_TAB_ARRAY;
1464
1465 for (i = 0; i < arraylen; i = i + 2) {
1466 v1 = array_table[i];
1467 v2 = array_table[i+1];
1468 if (v1 < 0xCDCDCDCD) {
1469 rtl_set_bbreg(hw, v1, MASKDWORD, v2);
1470 udelay(1);
1471 continue;
1472 } else {/*This line is the start line of branch.*/
1473 if (!_rtl8821ae_check_condition(hw,v1)) {
1474 /*Discard the following (offset, data) pairs*/
1475 READ_NEXT_PAIR(array_table, v1, v2, i);
1476 while (v2 != 0xDEAD &&
1477 v2 != 0xCDEF &&
1478 v2 != 0xCDCD && i < arraylen -2)
1479 READ_NEXT_PAIR(array_table, v1, v2, i);
1480
1481 i -= 2; /* prevent from for-loop += 2*/
1482 }else{/*Configure matched pairs and skip to end of if-else.*/
1483 READ_NEXT_PAIR(array_table, v1, v2, i);
1484 while (v2 != 0xDEAD &&
1485 v2 != 0xCDEF &&
1486 v2 != 0xCDCD && i < arraylen -2)
1487 {
1488 rtl_set_bbreg(hw, v1, MASKDWORD, v2);
1489 udelay(1);
1490 READ_NEXT_PAIR(array_table, v1, v2, i);
1491 }
1492
1493 while (v2 != 0xDEAD && i < arraylen -2)
1494 READ_NEXT_PAIR(array_table, v1, v2, i);
1495 }
1496 }
1497 RT_TRACE(COMP_INIT, DBG_TRACE,
1498 ("The agctab_array_table[0] is "
1499 "%x Rtl818EEPHY_REGArray[1] is %x \n",
1500 array_table[i],
1501 array_table[i + 1]));
1502 }
1503 }
1504 return true;
1505}
1506
1507static u8 _rtl8821ae_get_rate_selection_index(u32 regaddr)
1508{
1509 u8 index = 0;
1510
1511 regaddr &= 0xFFF;
1512 if (regaddr >= 0xC20 && regaddr <= 0xC4C)
1513 index = (u8) ((regaddr - 0xC20) / 4);
1514 else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
1515 index = (u8) ((regaddr - 0xE20) / 4);
1516 else
1517 RT_ASSERT(!COMP_INIT,
1518 ("Invalid RegAddr 0x%x in"
1519 "PHY_GetRateSectionIndexOfTxPowerByRate()\n",regaddr));
1520
1521 return index;
1522}
1523
1524static void _rtl8821ae_store_tx_power_by_rate(struct ieee80211_hw *hw,
1525 u32 band, u32 rfpath,
1526 u32 txnum, u32 regaddr,
1527 u32 bitmask, u32 data)
1528{
1529 struct rtl_priv *rtlpriv = rtl_priv(hw);
1530 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1531 u8 rate_section = _rtl8821ae_get_rate_selection_index(regaddr);
1532
1533 if (band != BAND_ON_2_4G && band != BAND_ON_5G)
1534 RT_TRACE(COMP_INIT, DBG_WARNING, ("Invalid Band %d\n", band));
1535
1536 if (rfpath > MAX_RF_PATH)
1537 RT_TRACE(COMP_INIT, DBG_WARNING, ("Invalid RfPath %d\n", rfpath));
1538
1539 if (txnum > MAX_RF_PATH)
1540 RT_TRACE(COMP_INIT, DBG_WARNING, ("Invalid TxNum %d\n", txnum ) );
1541
1542 rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section] = data;
1543 RT_TRACE(COMP_INIT, DBG_WARNING,( "pHalData->TxPwrByRateOffset[Band %d][RfPath %d][TxNum %d][RateSection %d] = 0x%x\n",
1544 band, rfpath, txnum, rate_section, rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][rate_section]));
1545
1546}
1547
1548static bool _rtl8812ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
1549 u8 configtype)
1550{
1551 struct rtl_priv *rtlpriv = rtl_priv(hw);
1552 int i;
1553 u32 *phy_regarray_table_pg;
1554 u16 phy_regarray_pg_len;
1555 u32 v1, v2, v3, v4, v5, v6;
1556
1557 phy_regarray_pg_len = RTL8812AEPHY_REG_ARRAY_PGLEN;
1558 phy_regarray_table_pg = RTL8812AE_PHY_REG_ARRAY_PG;
1559
1560 if (configtype == BASEBAND_CONFIG_PHY_REG) {
1561 for (i = 0; i < phy_regarray_pg_len; i += 6) {
1562 v1 = phy_regarray_table_pg[i];
1563 v2 = phy_regarray_table_pg[i+1];
1564 v3 = phy_regarray_table_pg[i+2];
1565 v4 = phy_regarray_table_pg[i+3];
1566 v5 = phy_regarray_table_pg[i+4];
1567 v6 = phy_regarray_table_pg[i+5];
1568
1569 if (v1<0xCDCDCDCD) {
1570 if ( (v4 == 0xfe) || (v4 == 0xffe))
1571 mdelay(50);
1572 else
1573 /*_rtl8821ae_store_pwrIndex_diffrate_offset*/
1574 _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3, v4, v5, v6);
1575 continue;
1576 } else {
1577 if (!_rtl8821ae_check_condition(hw,v1)) { /*don't need the hw_body*/
1578 i += 2; /* skip the pair of expression*/
1579 v1 = phy_regarray_table_pg[i];
1580 v2 = phy_regarray_table_pg[i+1];
1581 v3 = phy_regarray_table_pg[i+2];
1582 while (v2 != 0xDEAD) {
1583 i += 3;
1584 v1 = phy_regarray_table_pg[i];
1585 v2 = phy_regarray_table_pg[i+1];
1586 v3 = phy_regarray_table_pg[i+2];
1587 }
1588 }
1589 }
1590 }
1591 } else {
1592
1593 RT_TRACE(COMP_SEND, DBG_TRACE,
1594 ("configtype != BaseBand_Config_PHY_REG\n"));
1595 }
1596 return true;
1597}
1598
1599static bool _rtl8821ae_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
1600 u8 configtype)
1601{
1602 struct rtl_priv *rtlpriv = rtl_priv(hw);
1603 int i;
1604 u32 *phy_regarray_table_pg;
1605 u16 phy_regarray_pg_len;
1606 u32 v1, v2, v3, v4, v5, v6;
1607
1608 phy_regarray_pg_len = RTL8821AEPHY_REG_ARRAY_PGLEN;
1609 phy_regarray_table_pg = RTL8821AE_PHY_REG_ARRAY_PG;
1610
1611 if (configtype == BASEBAND_CONFIG_PHY_REG) {
1612 for (i = 0; i < phy_regarray_pg_len; i += 6) {
1613 v1 = phy_regarray_table_pg[i];
1614 v2 = phy_regarray_table_pg[i+1];
1615 v3 = phy_regarray_table_pg[i+2];
1616 v4 = phy_regarray_table_pg[i+3];
1617 v5 = phy_regarray_table_pg[i+4];
1618 v6 = phy_regarray_table_pg[i+5];
1619
1620 if (v1<0xCDCDCDCD) {
1621 if (v4 == 0xfe)
1622 mdelay(50);
1623 else if (v4 == 0xfd)
1624 mdelay(5);
1625 else if (v4 == 0xfc)
1626 mdelay(1);
1627 else if (v4 == 0xfb)
1628 udelay(50);
1629 else if (v4 == 0xfa)
1630 udelay(5);
1631 else if (v4 == 0xf9)
1632 udelay(1);
1633
1634 /*_rtl8821ae_store_pwrIndex_diffrate_offset*/
1635 _rtl8821ae_store_tx_power_by_rate(hw, v1, v2, v3, v4, v5, v6);
1636 continue;
1637 } else {
1638 if (!_rtl8821ae_check_condition(hw,v1)) { /*don't need the hw_body*/
1639 i += 2; /* skip the pair of expression*/
1640 v1 = phy_regarray_table_pg[i];
1641 v2 = phy_regarray_table_pg[i+1];
1642 v3 = phy_regarray_table_pg[i+2];
1643 while (v2 != 0xDEAD) {
1644 i += 3;
1645 v1 = phy_regarray_table_pg[i];
1646 v2 = phy_regarray_table_pg[i+1];
1647 v3 = phy_regarray_table_pg[i+2];
1648 }
1649 }
1650 }
1651 }
1652 } else {
1653
1654 RT_TRACE(COMP_SEND, DBG_TRACE,
1655 ("configtype != BaseBand_Config_PHY_REG\n"));
1656 }
1657 return true;
1658}
1659
1660bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw * hw,
1661 enum radio_path rfpath)
1662{
1663 #define READ_NEXT_RF_PAIR_8812(radioa_array_table,v1, v2, i) do { i += 2; v1 = radioa_array_table[i]; v2 = radioa_array_table[i+1]; } while(0)
1664
1665 int i;
1666 bool rtstatus = true;
1667 u32 *radioa_array_table_a, *radioa_array_table_b;
1668 u16 radioa_arraylen_a, radioa_arraylen_b;
1669 struct rtl_priv *rtlpriv = rtl_priv(hw);
1670 u32 v1 = 0, v2 = 0;
1671
1672 radioa_arraylen_a = RTL8812AE_RADIOA_1TARRAYLEN;
1673 radioa_array_table_a= RTL8812AE_RADIOA_ARRAY;
1674 radioa_arraylen_b= RTL8812AE_RADIOB_1TARRAYLEN;
1675 radioa_array_table_b = RTL8812AE_RADIOB_ARRAY;
1676 RT_TRACE(COMP_INIT, DBG_LOUD,
1677 ("Radio_A:RTL8821AE_RADIOA_ARRAY %d\n",radioa_arraylen_a));
1678 RT_TRACE(COMP_INIT, DBG_LOUD, ("Radio No %x\n", rfpath));
1679 rtstatus = true;
1680 switch (rfpath) {
1681 case RF90_PATH_A:
1682 for (i = 0; i < radioa_arraylen_a; i = i + 2) {
1683 v1 = radioa_array_table_a[i];
1684 v2 = radioa_array_table_a[i+1];
1685 if (v1<0xcdcdcdcd) {
1686 _rtl8821ae_config_rf_radio_a(hw,v1,v2);
1687 continue;
1688 }else{/*This line is the start line of branch.*/
1689 if(!_rtl8821ae_check_condition(hw,v1)){
1690 /*Discard the following (offset, data) pairs*/
1691 READ_NEXT_RF_PAIR_8812(radioa_array_table_a,v1, v2, i);
1692 while (v2 != 0xDEAD &&
1693 v2 != 0xCDEF &&
1694 v2 != 0xCDCD && i < radioa_arraylen_a-2)
1695 READ_NEXT_RF_PAIR_8812(radioa_array_table_a,v1, v2, i);
1696
1697 i -= 2; /* prevent from for-loop += 2*/
1698 } else {/*Configure matched pairs and skip to end of if-else.*/
1699 READ_NEXT_RF_PAIR_8812(radioa_array_table_a,v1, v2, i);
1700 while (v2 != 0xDEAD &&
1701 v2 != 0xCDEF &&
1702 v2 != 0xCDCD && i < radioa_arraylen_a -2) {
1703 _rtl8821ae_config_rf_radio_a(hw,v1,v2);
1704 READ_NEXT_RF_PAIR_8812(radioa_array_table_a,v1, v2, i);
1705 }
1706
1707 while (v2 != 0xDEAD && i < radioa_arraylen_a-2)
1708 READ_NEXT_RF_PAIR_8812(radioa_array_table_a,v1, v2, i);
1709 }
1710 }
1711 }
1712 break;
1713 case RF90_PATH_B:
1714 for (i = 0; i < radioa_arraylen_b; i = i + 2) {
1715 v1 = radioa_array_table_b[i];
1716 v2 = radioa_array_table_b[i+1];
1717 if (v1<0xcdcdcdcd) {
1718 _rtl8821ae_config_rf_radio_b(hw,v1,v2);
1719 continue;
1720 }else{/*This line is the start line of branch.*/
1721 if(!_rtl8821ae_check_condition(hw,v1)){
1722 /*Discard the following (offset, data) pairs*/
1723 READ_NEXT_RF_PAIR_8812(radioa_array_table_b,v1, v2, i);
1724 while (v2 != 0xDEAD &&
1725 v2 != 0xCDEF &&
1726 v2 != 0xCDCD && i < radioa_arraylen_b-2)
1727 READ_NEXT_RF_PAIR_8812(radioa_array_table_b,v1, v2, i);
1728
1729 i -= 2; /* prevent from for-loop += 2*/
1730 } else {/*Configure matched pairs and skip to end of if-else.*/
1731 READ_NEXT_RF_PAIR_8812(radioa_array_table_b,v1, v2, i);
1732 while (v2 != 0xDEAD &&
1733 v2 != 0xCDEF &&
1734 v2 != 0xCDCD && i < radioa_arraylen_b-2) {
1735 _rtl8821ae_config_rf_radio_b(hw,v1,v2);
1736 READ_NEXT_RF_PAIR_8812(radioa_array_table_b,v1, v2, i);
1737 }
1738
1739 while (v2 != 0xDEAD && i < radioa_arraylen_b-2)
1740 READ_NEXT_RF_PAIR_8812(radioa_array_table_b,v1, v2, i);
1741 }
1742 }
1743 }
1744 break;
1745 case RF90_PATH_C:
1746 RT_TRACE(COMP_ERR, DBG_EMERG,
1747 ("switch case not process \n"));
1748 break;
1749 case RF90_PATH_D:
1750 RT_TRACE(COMP_ERR, DBG_EMERG,
1751 ("switch case not process \n"));
1752 break;
1753 }
1754 return true;
1755}
1756
1757
1758bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw * hw,
1759 enum radio_path rfpath)
1760{
1761 #define READ_NEXT_RF_PAIR(v1, v2, i) do { i += 2; v1 = radioa_array_table[i]; v2 = radioa_array_table[i+1]; } while(0)
1762
1763 int i;
1764 bool rtstatus = true;
1765 u32 *radioa_array_table;
1766 u16 radioa_arraylen;
1767 struct rtl_priv *rtlpriv = rtl_priv(hw);
1768 //struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1769 u32 v1 = 0, v2 = 0;
1770
1771 radioa_arraylen = RTL8821AE_RADIOA_1TARRAYLEN;
1772 radioa_array_table = RTL8821AE_RADIOA_ARRAY;
1773 RT_TRACE(COMP_INIT, DBG_LOUD,
1774 ("Radio_A:RTL8821AE_RADIOA_ARRAY %d\n",radioa_arraylen));
1775 RT_TRACE(COMP_INIT, DBG_LOUD, ("Radio No %x\n", rfpath));
1776 rtstatus = true;
1777 switch (rfpath) {
1778 case RF90_PATH_A:
1779 for (i = 0; i < radioa_arraylen; i = i + 2) {
1780 v1 = radioa_array_table[i];
1781 v2 = radioa_array_table[i+1];
1782 if (v1<0xcdcdcdcd) {
1783 _rtl8821ae_config_rf_radio_a(hw,v1,v2);
1784 }else{/*This line is the start line of branch.*/
1785 if(!_rtl8821ae_check_condition(hw,v1)){
1786 /*Discard the following (offset, data) pairs*/
1787 READ_NEXT_RF_PAIR(v1, v2, i);
1788 while (v2 != 0xDEAD &&
1789 v2 != 0xCDEF &&
1790 v2 != 0xCDCD && i < radioa_arraylen -2)
1791 READ_NEXT_RF_PAIR(v1, v2, i);
1792
1793 i -= 2; /* prevent from for-loop += 2*/
1794 } else {/*Configure matched pairs and skip to end of if-else.*/
1795 READ_NEXT_RF_PAIR(v1, v2, i);
1796 while (v2 != 0xDEAD &&
1797 v2 != 0xCDEF &&
1798 v2 != 0xCDCD && i < radioa_arraylen -2) {
1799 _rtl8821ae_config_rf_radio_a(hw,v1,v2);
1800 READ_NEXT_RF_PAIR(v1, v2, i);
1801 }
1802
1803 while (v2 != 0xDEAD && i < radioa_arraylen -2)
1804 READ_NEXT_RF_PAIR(v1, v2, i);
1805 }
1806 }
1807 }
1808 break;
1809
1810 case RF90_PATH_B:
1811 RT_TRACE(COMP_ERR, DBG_EMERG,
1812 ("switch case not process \n"));
1813 break;
1814 case RF90_PATH_C:
1815 RT_TRACE(COMP_ERR, DBG_EMERG,
1816 ("switch case not process \n"));
1817 break;
1818 case RF90_PATH_D:
1819 RT_TRACE(COMP_ERR, DBG_EMERG,
1820 ("switch case not process \n"));
1821 break;
1822 }
1823 return true;
1824}
1825
1826void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1827{
1828 struct rtl_priv *rtlpriv = rtl_priv(hw);
1829 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1830
1831 rtlphy->default_initialgain[0] =
1832 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
1833 rtlphy->default_initialgain[1] =
1834 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
1835 rtlphy->default_initialgain[2] =
1836 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
1837 rtlphy->default_initialgain[3] =
1838 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
1839
1840 RT_TRACE(COMP_INIT, DBG_TRACE,
1841 ("Default initial gain (c50=0x%x, "
1842 "c58=0x%x, c60=0x%x, c68=0x%x \n",
1843 rtlphy->default_initialgain[0],
1844 rtlphy->default_initialgain[1],
1845 rtlphy->default_initialgain[2],
1846 rtlphy->default_initialgain[3]));
1847
1848 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
1849 ROFDM0_RXDETECTOR3, MASKBYTE0);
1850 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
1851 ROFDM0_RXDETECTOR2, MASKDWORD);
1852
1853 RT_TRACE(COMP_INIT, DBG_TRACE,
1854 ("Default framesync (0x%x) = 0x%x \n",
1855 ROFDM0_RXDETECTOR3, rtlphy->framesync));
1856}
1857
1858static void _rtl8821ae_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
1859{
1860 struct rtl_priv *rtlpriv = rtl_priv(hw);
1861 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1862
1863 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1864 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1865
1866 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
1867 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
1868
1869 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
1870 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
1871
1872 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = RA_LSSIWRITE_8821A;
1873 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = RB_LSSIWRITE_8821A;
1874
1875 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RHSSIREAD_8821AE;
1876 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RHSSIREAD_8821AE;
1877
1878 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback = RA_SIREAD_8821A;
1879 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback = RB_SIREAD_8821A;
1880
1881 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi = RA_PIREAD_8821A;
1882 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi = RB_PIREAD_8821A;
1883}
1884
1885void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
1886{
1887 struct rtl_priv *rtlpriv = rtl_priv(hw);
1888 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1889 u8 txpwr_level;
1890 long txpwr_dbm;
1891
1892 txpwr_level = rtlphy->cur_cck_txpwridx;
1893 txpwr_dbm = _rtl8821ae_phy_txpwr_idx_to_dbm(hw,
1894 WIRELESS_MODE_B, txpwr_level);
1895 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1896 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
1897 WIRELESS_MODE_G,
1898 txpwr_level) > txpwr_dbm)
1899 txpwr_dbm =
1900 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
1901 txpwr_level);
1902 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1903 if (_rtl8821ae_phy_txpwr_idx_to_dbm(hw,
1904 WIRELESS_MODE_N_24G,
1905 txpwr_level) > txpwr_dbm)
1906 txpwr_dbm =
1907 _rtl8821ae_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
1908 txpwr_level);
1909 *powerlevel = txpwr_dbm;
1910}
1911
1912static bool _rtl8821ae_phy_get_chnl_index(u8 channel, u8 *chnl_index)
1913{
1914 u8 channel_5g[CHANNEL_MAX_NUMBER_5G] =
1915 {36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,
1916 114,116,118,120,122,124,126,128,130,132,134,136,138,140,142,144,149,151,
1917 153,155,157,159,161,163,165,167,168,169,171,173,175,177};
1918 u8 i = 0;
1919 bool in_24g = true;
1920
1921 if (channel <= 14) {
1922 in_24g = true;
1923 *chnl_index = channel - 1;
1924 } else {
1925 in_24g = false;
1926
1927 for (i = 0; i < sizeof(channel_5g) / sizeof(u8); ++i) {
1928 if (channel_5g[i] == channel) {
1929 *chnl_index = i;
1930 return in_24g;
1931 }
1932 }
1933 }
1934 return in_24g;
1935}
1936
1937static char _rtl8821ae_phy_get_ratesection_intxpower_byrate(u8 path, u8 rate)
1938{
1939 char rate_section = 0;
1940 switch (rate) {
1941 case DESC_RATE1M:
1942 case DESC_RATE2M:
1943 case DESC_RATE5_5M:
1944 case DESC_RATE11M:
1945 rate_section = 0;
1946 break;
1947
1948 case DESC_RATE6M:
1949 case DESC_RATE9M:
1950 case DESC_RATE12M:
1951 case DESC_RATE18M:
1952 rate_section = 1;
1953 break;
1954
1955 case DESC_RATE24M:
1956 case DESC_RATE36M:
1957 case DESC_RATE48M:
1958 case DESC_RATE54M:
1959 rate_section = 2;
1960 break;
1961
1962 case DESC_RATEMCS0:
1963 case DESC_RATEMCS1:
1964 case DESC_RATEMCS2:
1965 case DESC_RATEMCS3:
1966 rate_section = 3;
1967 break;
1968
1969 case DESC_RATEMCS4:
1970 case DESC_RATEMCS5:
1971 case DESC_RATEMCS6:
1972 case DESC_RATEMCS7:
1973 rate_section = 4;
1974 break;
1975
1976 case DESC_RATEMCS8:
1977 case DESC_RATEMCS9:
1978 case DESC_RATEMCS10:
1979 case DESC_RATEMCS11:
1980 rate_section = 5;
1981 break;
1982
1983 case DESC_RATEMCS12:
1984 case DESC_RATEMCS13:
1985 case DESC_RATEMCS14:
1986 case DESC_RATEMCS15:
1987 rate_section = 6;
1988 break;
1989
1990 case DESC_RATEVHT1SS_MCS0:
1991 case DESC_RATEVHT1SS_MCS1:
1992 case DESC_RATEVHT1SS_MCS2:
1993 case DESC_RATEVHT1SS_MCS3:
1994 rate_section = 7;
1995 break;
1996
1997 case DESC_RATEVHT1SS_MCS4:
1998 case DESC_RATEVHT1SS_MCS5:
1999 case DESC_RATEVHT1SS_MCS6:
2000 case DESC_RATEVHT1SS_MCS7:
2001 rate_section = 8;
2002 break;
2003
2004 case DESC_RATEVHT1SS_MCS8:
2005 case DESC_RATEVHT1SS_MCS9:
2006 case DESC_RATEVHT2SS_MCS0:
2007 case DESC_RATEVHT2SS_MCS1:
2008 rate_section = 9;
2009 break;
2010
2011 case DESC_RATEVHT2SS_MCS2:
2012 case DESC_RATEVHT2SS_MCS3:
2013 case DESC_RATEVHT2SS_MCS4:
2014 case DESC_RATEVHT2SS_MCS5:
2015 rate_section = 10;
2016 break;
2017
2018 case DESC_RATEVHT2SS_MCS6:
2019 case DESC_RATEVHT2SS_MCS7:
2020 case DESC_RATEVHT2SS_MCS8:
2021 case DESC_RATEVHT2SS_MCS9:
2022 rate_section = 11;
2023 break;
2024
2025 default:
2026 RT_ASSERT(true, ("Rate_Section is Illegal\n"));
2027 break;
2028 }
2029
2030 return rate_section;
2031}
2032
2033static char _rtl8821ae_phy_get_txpower_by_rate(struct ieee80211_hw *hw,
2034 u8 band, u8 path, u8 rate)
2035{
2036 struct rtl_priv *rtlpriv = rtl_priv(hw);
2037 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2038 u8 shift = 0, rate_section, tx_num;
2039 char tx_pwr_diff = 0;
2040
2041 rate_section = _rtl8821ae_phy_get_ratesection_intxpower_byrate(path, rate);
2042 tx_num = RF_TX_NUM_NONIMPLEMENT;
2043
2044 if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
2045 if ((rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15 ) ||
2046 (rate >= DESC_RATEVHT2SS_MCS2 && rate <= DESC_RATEVHT2SS_MCS9))
2047 tx_num = RF_2TX;
2048 else
2049 tx_num = RF_1TX;
2050 }
2051
2052 switch (rate) {
2053 case DESC_RATE1M: shift = 0; break;
2054 case DESC_RATE2M: shift = 8; break;
2055 case DESC_RATE5_5M: shift = 16; break;
2056 case DESC_RATE11M: shift = 24; break;
2057
2058 case DESC_RATE6M: shift = 0; break;
2059 case DESC_RATE9M: shift = 8; break;
2060 case DESC_RATE12M: shift = 16; break;
2061 case DESC_RATE18M: shift = 24; break;
2062
2063 case DESC_RATE24M: shift = 0; break;
2064 case DESC_RATE36M: shift = 8; break;
2065 case DESC_RATE48M: shift = 16; break;
2066 case DESC_RATE54M: shift = 24; break;
2067
2068 case DESC_RATEMCS0: shift = 0; break;
2069 case DESC_RATEMCS1: shift = 8; break;
2070 case DESC_RATEMCS2: shift = 16; break;
2071 case DESC_RATEMCS3: shift = 24; break;
2072
2073 case DESC_RATEMCS4: shift = 0; break;
2074 case DESC_RATEMCS5: shift = 8; break;
2075 case DESC_RATEMCS6: shift = 16; break;
2076 case DESC_RATEMCS7: shift = 24; break;
2077
2078 case DESC_RATEMCS8: shift = 0; break;
2079 case DESC_RATEMCS9: shift = 8; break;
2080 case DESC_RATEMCS10: shift = 16; break;
2081 case DESC_RATEMCS11: shift = 24; break;
2082
2083 case DESC_RATEMCS12: shift = 0; break;
2084 case DESC_RATEMCS13: shift = 8; break;
2085 case DESC_RATEMCS14: shift = 16; break;
2086 case DESC_RATEMCS15: shift = 24; break;
2087
2088 case DESC_RATEVHT1SS_MCS0: shift = 0; break;
2089 case DESC_RATEVHT1SS_MCS1: shift = 8; break;
2090 case DESC_RATEVHT1SS_MCS2: shift = 16; break;
2091 case DESC_RATEVHT1SS_MCS3: shift = 24; break;
2092
2093 case DESC_RATEVHT1SS_MCS4: shift = 0; break;
2094 case DESC_RATEVHT1SS_MCS5: shift = 8; break;
2095 case DESC_RATEVHT1SS_MCS6: shift = 16; break;
2096 case DESC_RATEVHT1SS_MCS7: shift = 24; break;
2097
2098 case DESC_RATEVHT1SS_MCS8: shift = 0; break;
2099 case DESC_RATEVHT1SS_MCS9: shift = 8; break;
2100 case DESC_RATEVHT2SS_MCS0: shift = 16; break;
2101 case DESC_RATEVHT2SS_MCS1: shift = 24; break;
2102
2103 case DESC_RATEVHT2SS_MCS2: shift = 0; break;
2104 case DESC_RATEVHT2SS_MCS3: shift = 8; break;
2105 case DESC_RATEVHT2SS_MCS4: shift = 16; break;
2106 case DESC_RATEVHT2SS_MCS5: shift = 24; break;
2107
2108 case DESC_RATEVHT2SS_MCS6: shift = 0; break;
2109 case DESC_RATEVHT2SS_MCS7: shift = 8; break;
2110 case DESC_RATEVHT2SS_MCS8: shift = 16; break;
2111 case DESC_RATEVHT2SS_MCS9: shift = 24; break;
2112
2113 default:
2114 RT_ASSERT(true, ("Rate_Section is Illegal\n"));
2115 break;
2116 }
2117
2118 tx_pwr_diff = (u8) (rtlphy->tx_power_by_rate_offset[band][path][tx_num][rate_section] >> shift) & 0xff;
2119
2120 return tx_pwr_diff;
2121}
2122
2123static u8 _rtl8821ae_get_txpower_index(struct ieee80211_hw *hw, u8 path,
2124 u8 rate, u8 bandwidth, u8 channel)
2125{
2126 struct rtl_priv *rtlpriv = rtl_priv(hw);
2127 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2128 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2129 u8 index = (channel - 1);
2130 u8 txpower = 0;
2131 bool in_24g = false;
2132 char powerdiff_byrate = 0;
2133
2134 if (((rtlhal->current_bandtype == BAND_ON_2_4G) && (channel > 14 || channel < 1)) ||
2135 ((rtlhal->current_bandtype == BAND_ON_5G) && (channel <= 14))) {
2136 index = 0;
2137 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("Illegal channel!!\n"));
2138 }
2139
2140 in_24g = _rtl8821ae_phy_get_chnl_index(channel, &index);
2141 if (in_24g) {
2142 if (RX_HAL_IS_CCK_RATE(rate))
2143 txpower = rtlefuse->txpwrlevel_cck[path][index];
2144 else if ( DESC_RATE6M <= rate )
2145 txpower = rtlefuse->txpwrlevel_ht40_1s[path][index];
2146 else
2147 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("invalid rate\n"));
2148
2149 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M && !RX_HAL_IS_CCK_RATE(rate))
2150 txpower += rtlefuse->txpwr_legacyhtdiff[path][TX_1S];
2151
2152 if (bandwidth == HT_CHANNEL_WIDTH_20) {
2153 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2154 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2155 txpower += rtlefuse->txpwr_ht20diff[path][TX_1S];
2156 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2157 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2158 txpower += rtlefuse->txpwr_ht20diff[path][TX_2S];
2159 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2160 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2161 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2162 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2163 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2164 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2165 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2166 } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2167 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2168 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2169 txpower += rtlefuse->txpwr_ht40diff[path][TX_1S];
2170 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2171 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2172 txpower += rtlefuse->txpwr_ht40diff[path][TX_2S];
2173 }
2174
2175 } else {
2176 if (DESC_RATE6M <= rate)
2177 txpower = rtlefuse->txpwr_5g_bw40base[path][index];
2178 else
2179 RT_TRACE(COMP_POWER_TRACKING, DBG_WARNING,("INVALID Rate.\n"));
2180
2181 if (DESC_RATE6M <= rate && rate <= DESC_RATE54M && !RX_HAL_IS_CCK_RATE(rate))
2182 txpower += rtlefuse->txpwr_5g_ofdmdiff[path][TX_1S];
2183
2184 if (bandwidth == HT_CHANNEL_WIDTH_20) {
2185 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2186 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2187 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_1S];
2188 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2189 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2190 txpower += rtlefuse->txpwr_5g_bw20diff[path][TX_2S];
2191 } else if (bandwidth == HT_CHANNEL_WIDTH_20_40) {
2192 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2193 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2194 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_1S];
2195 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2196 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2197 txpower += rtlefuse->txpwr_5g_bw40diff[path][TX_2S];
2198 } else if (bandwidth == HT_CHANNEL_WIDTH_80) {
2199 u8 channel_5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2200 u8 i = 0;
2201 for (i = 0; i < sizeof(channel_5g_80m) / sizeof(u8); ++i)
2202 if (channel_5g_80m[i] == channel)
2203 index = i;
2204
2205 if ((DESC_RATEMCS0 <= rate && rate <= DESC_RATEMCS15) ||
2206 (DESC_RATEVHT1SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2207 txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2208 + rtlefuse->txpwr_5g_bw80diff[path][TX_1S];
2209 if ((DESC_RATEMCS8 <= rate && rate <= DESC_RATEMCS15) ||
2210 (DESC_RATEVHT2SS_MCS0 <= rate && rate <= DESC_RATEVHT2SS_MCS9))
2211 txpower = rtlefuse->txpwr_5g_bw80base[path][index]
2212 + rtlefuse->txpwr_5g_bw80diff[path][TX_1S]
2213 + rtlefuse->txpwr_5g_bw80diff[path][TX_2S];
2214 }
2215 }
2216 if (rtlefuse->eeprom_regulatory != 2)
2217 powerdiff_byrate = _rtl8821ae_phy_get_txpower_by_rate(hw,
2218 (u8)(!in_24g), path, rate);
2219
2220 if (rate == DESC_RATEVHT1SS_MCS8 || rate == DESC_RATEVHT1SS_MCS9 ||
2221 rate == DESC_RATEVHT2SS_MCS8 || rate == DESC_RATEVHT2SS_MCS9)
2222 txpower -= powerdiff_byrate;
2223 else
2224 txpower += powerdiff_byrate;
2225
2226 if (rate > DESC_RATE11M)
2227 txpower += rtlpriv->dm.remnant_ofdm_swing_idx[path];
2228 else
2229 txpower += rtlpriv->dm.remnant_cck_idx;
2230
2231 if (txpower > MAX_POWER_INDEX)
2232 txpower = MAX_POWER_INDEX;
2233
2234 return txpower;
2235}
2236
2237static void _rtl8821ae_phy_set_txpower_index(struct ieee80211_hw *hw,
2238 u8 power_index, u8 path, u8 rate)
2239{
2240 struct rtl_priv* rtlpriv = rtl_priv(hw);
2241
2242 if (path == RF90_PATH_A) {
2243 switch (rate) {
2244 case DESC_RATE1M:
2245 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKBYTE0, power_index);
2246 break;
2247 case DESC_RATE2M:
2248 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKBYTE1, power_index);
2249 break;
2250 case DESC_RATE5_5M:
2251 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKBYTE2, power_index);
2252 break;
2253 case DESC_RATE11M:
2254 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKBYTE3, power_index);
2255 break;
2256
2257 case DESC_RATE6M:
2258 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, MASKBYTE0, power_index);
2259 break;
2260 case DESC_RATE9M:
2261 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, MASKBYTE1, power_index);
2262 break;
2263 case DESC_RATE12M:
2264 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, MASKBYTE2, power_index);
2265 break;
2266 case DESC_RATE18M:
2267 rtl_set_bbreg(hw, RTXAGC_A_OFDM18_OFDM6, MASKBYTE3, power_index);
2268 break;
2269
2270 case DESC_RATE24M:
2271 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, MASKBYTE0, power_index);
2272 break;
2273 case DESC_RATE36M:
2274 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, MASKBYTE1, power_index);
2275 break;
2276 case DESC_RATE48M:
2277 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, MASKBYTE2, power_index);
2278 break;
2279 case DESC_RATE54M:
2280 rtl_set_bbreg(hw, RTXAGC_A_OFDM54_OFDM24, MASKBYTE3, power_index);
2281 break;
2282
2283 case DESC_RATEMCS0:
2284 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE0, power_index);
2285 break;
2286 case DESC_RATEMCS1:
2287 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE1, power_index);
2288 break;
2289 case DESC_RATEMCS2:
2290 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2, power_index);
2291 break;
2292 case DESC_RATEMCS3:
2293 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE3, power_index);
2294 break;
2295
2296 case DESC_RATEMCS4:
2297 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0, power_index);
2298 break;
2299 case DESC_RATEMCS5:
2300 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1, power_index);
2301 break;
2302 case DESC_RATEMCS6:
2303 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2, power_index);
2304 break;
2305 case DESC_RATEMCS7:
2306 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3, power_index);
2307 break;
2308
2309 case DESC_RATEMCS8:
2310 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE0, power_index);
2311 break;
2312 case DESC_RATEMCS9:
2313 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE1, power_index);
2314 break;
2315 case DESC_RATEMCS10:
2316 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2, power_index);
2317 break;
2318 case DESC_RATEMCS11:
2319 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE3, power_index);
2320 break;
2321
2322 case DESC_RATEMCS12:
2323 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE0, power_index);
2324 break;
2325 case DESC_RATEMCS13:
2326 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE1, power_index);
2327 break;
2328 case DESC_RATEMCS14:
2329 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2, power_index);
2330 break;
2331 case DESC_RATEMCS15:
2332 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE3, power_index);
2333 break;
2334
2335 case DESC_RATEVHT1SS_MCS0:
2336 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, MASKBYTE0, power_index);
2337 break;
2338 case DESC_RATEVHT1SS_MCS1:
2339 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, MASKBYTE1, power_index);
2340 break;
2341 case DESC_RATEVHT1SS_MCS2:
2342 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, MASKBYTE2, power_index);
2343 break;
2344 case DESC_RATEVHT1SS_MCS3:
2345 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX3_NSS1INDEX0, MASKBYTE3, power_index);
2346 break;
2347
2348 case DESC_RATEVHT1SS_MCS4:
2349 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, MASKBYTE0, power_index);
2350 break;
2351 case DESC_RATEVHT1SS_MCS5:
2352 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, MASKBYTE1, power_index);
2353 break;
2354 case DESC_RATEVHT1SS_MCS6:
2355 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, MASKBYTE2, power_index);
2356 break;
2357 case DESC_RATEVHT1SS_MCS7:
2358 rtl_set_bbreg(hw, RTXAGC_A_NSS1INDEX7_NSS1INDEX4, MASKBYTE3, power_index);
2359 break;
2360
2361 case DESC_RATEVHT1SS_MCS8:
2362 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, MASKBYTE0, power_index);
2363 break;
2364 case DESC_RATEVHT1SS_MCS9:
2365 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, MASKBYTE1, power_index);
2366 break;
2367 case DESC_RATEVHT2SS_MCS0:
2368 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, MASKBYTE2, power_index);
2369 break;
2370 case DESC_RATEVHT2SS_MCS1:
2371 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX1_NSS1INDEX8, MASKBYTE3, power_index);
2372 break;
2373
2374 case DESC_RATEVHT2SS_MCS2:
2375 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, MASKBYTE0, power_index);
2376 break;
2377 case DESC_RATEVHT2SS_MCS3:
2378 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, MASKBYTE1, power_index);
2379 break;
2380 case DESC_RATEVHT2SS_MCS4:
2381 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, MASKBYTE2, power_index);
2382 break;
2383 case DESC_RATEVHT2SS_MCS5:
2384 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX5_NSS2INDEX2, MASKBYTE3, power_index);
2385 break;
2386
2387 case DESC_RATEVHT2SS_MCS6:
2388 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, MASKBYTE0, power_index);
2389 break;
2390 case DESC_RATEVHT2SS_MCS7:
2391 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, MASKBYTE1, power_index);
2392 break;
2393 case DESC_RATEVHT2SS_MCS8:
2394 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, MASKBYTE2, power_index);
2395 break;
2396 case DESC_RATEVHT2SS_MCS9:
2397 rtl_set_bbreg(hw, RTXAGC_A_NSS2INDEX9_NSS2INDEX6, MASKBYTE3, power_index);
2398 break;
2399
2400 default:
2401 RT_TRACE(COMP_POWER, DBG_LOUD, ("Invalid Rate!!\n"));
2402 break;
2403 }
2404 } else if (path == RF90_PATH_B) {
2405 switch (rate) {
2406 case DESC_RATE1M:
2407 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKBYTE0, power_index);
2408 break;
2409 case DESC_RATE2M:
2410 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKBYTE1, power_index);
2411 break;
2412 case DESC_RATE5_5M:
2413 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKBYTE2, power_index);
2414 break;
2415 case DESC_RATE11M:
2416 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKBYTE3, power_index);
2417 break;
2418
2419 case DESC_RATE6M:
2420 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, MASKBYTE0, power_index);
2421 break;
2422 case DESC_RATE9M:
2423 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, MASKBYTE1, power_index);
2424 break;
2425 case DESC_RATE12M:
2426 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, MASKBYTE2, power_index);
2427 break;
2428 case DESC_RATE18M:
2429 rtl_set_bbreg(hw, RTXAGC_B_OFDM18_OFDM6, MASKBYTE3, power_index);
2430 break;
2431
2432 case DESC_RATE24M:
2433 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, MASKBYTE0, power_index);
2434 break;
2435 case DESC_RATE36M:
2436 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, MASKBYTE1, power_index);
2437 break;
2438 case DESC_RATE48M:
2439 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, MASKBYTE2, power_index);
2440 break;
2441 case DESC_RATE54M:
2442 rtl_set_bbreg(hw, RTXAGC_B_OFDM54_OFDM24, MASKBYTE3, power_index);
2443 break;
2444
2445 case DESC_RATEMCS0:
2446 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE0, power_index);
2447 break;
2448 case DESC_RATEMCS1:
2449 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE1, power_index);
2450 break;
2451 case DESC_RATEMCS2:
2452 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2, power_index);
2453 break;
2454 case DESC_RATEMCS3:
2455 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE3, power_index);
2456 break;
2457
2458 case DESC_RATEMCS4:
2459 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE0, power_index);
2460 break;
2461 case DESC_RATEMCS5:
2462 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE1, power_index);
2463 break;
2464 case DESC_RATEMCS6:
2465 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2, power_index);
2466 break;
2467 case DESC_RATEMCS7:
2468 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE3, power_index);
2469 break;
2470
2471 case DESC_RATEMCS8:
2472 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE0, power_index);
2473 break;
2474 case DESC_RATEMCS9:
2475 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE1, power_index);
2476 break;
2477 case DESC_RATEMCS10:
2478 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2, power_index);
2479 break;
2480 case DESC_RATEMCS11:
2481 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE3, power_index);
2482 break;
2483
2484 case DESC_RATEMCS12:
2485 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE0, power_index);
2486 break;
2487 case DESC_RATEMCS13:
2488 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE1, power_index);
2489 break;
2490 case DESC_RATEMCS14:
2491 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2, power_index);
2492 break;
2493 case DESC_RATEMCS15:
2494 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE3, power_index);
2495 break;
2496
2497 case DESC_RATEVHT1SS_MCS0:
2498 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, MASKBYTE0, power_index);
2499 break;
2500 case DESC_RATEVHT1SS_MCS1:
2501 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, MASKBYTE1, power_index);
2502 break;
2503 case DESC_RATEVHT1SS_MCS2:
2504 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, MASKBYTE2, power_index);
2505 break;
2506 case DESC_RATEVHT1SS_MCS3:
2507 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX3_NSS1INDEX0, MASKBYTE3, power_index);
2508 break;
2509
2510 case DESC_RATEVHT1SS_MCS4:
2511 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, MASKBYTE0, power_index);
2512 break;
2513 case DESC_RATEVHT1SS_MCS5:
2514 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, MASKBYTE1, power_index);
2515 break;
2516 case DESC_RATEVHT1SS_MCS6:
2517 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, MASKBYTE2, power_index);
2518 break;
2519 case DESC_RATEVHT1SS_MCS7:
2520 rtl_set_bbreg(hw, RTXAGC_B_NSS1INDEX7_NSS1INDEX4, MASKBYTE3, power_index);
2521 break;
2522
2523 case DESC_RATEVHT1SS_MCS8:
2524 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, MASKBYTE0, power_index);
2525 break;
2526 case DESC_RATEVHT1SS_MCS9:
2527 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, MASKBYTE1, power_index);
2528 break;
2529 case DESC_RATEVHT2SS_MCS0:
2530 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, MASKBYTE2, power_index);
2531 break;
2532 case DESC_RATEVHT2SS_MCS1:
2533 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX1_NSS1INDEX8, MASKBYTE3, power_index);
2534 break;
2535
2536 case DESC_RATEVHT2SS_MCS2:
2537 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, MASKBYTE0, power_index);
2538 break;
2539 case DESC_RATEVHT2SS_MCS3:
2540 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, MASKBYTE1, power_index);
2541 break;
2542 case DESC_RATEVHT2SS_MCS4:
2543 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, MASKBYTE2, power_index);
2544 break;
2545 case DESC_RATEVHT2SS_MCS5:
2546 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX5_NSS2INDEX2, MASKBYTE3, power_index);
2547 break;
2548
2549 case DESC_RATEVHT2SS_MCS6:
2550 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, MASKBYTE0, power_index);
2551 break;
2552 case DESC_RATEVHT2SS_MCS7:
2553 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, MASKBYTE1, power_index);
2554 break;
2555 case DESC_RATEVHT2SS_MCS8:
2556 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, MASKBYTE2, power_index);
2557 break;
2558 case DESC_RATEVHT2SS_MCS9:
2559 rtl_set_bbreg(hw, RTXAGC_B_NSS2INDEX9_NSS2INDEX6, MASKBYTE3, power_index);
2560 break;
2561
2562 default:
2563 RT_TRACE(COMP_POWER, DBG_LOUD, ("Invalid Rate!!\n"));
2564 break;
2565 }
2566 } else {
2567 RT_TRACE(COMP_POWER, DBG_LOUD, ("Invalid RFPath!!\n"));
2568 }
2569}
2570
2571void _rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw,
2572 u8 *array, u8 path, u8 channel,
2573 u8 size)
2574{
2575 struct rtl_phy *rtlphy = &(rtl_priv(hw)->phy);
2576 u8 i;
2577 u8 power_index;
2578 for (i = 0; i < size; i ++) {
2579 power_index = _rtl8821ae_get_txpower_index(hw, path, array[i],
2580 rtlphy->current_chan_bw, channel);
2581 _rtl8821ae_phy_set_txpower_index(hw, power_index, path, array[i]);
2582 }
2583}
2584
2585static void _rtl8821ae_phy_txpower_training_by_path(struct ieee80211_hw *hw,
2586 u8 bw, u8 channel, u8 path)
2587{
2588 struct rtl_priv *rtlpriv = rtl_priv(hw);
2589 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2590
2591 u8 i;
2592 u32 power_level, data, offset;
2593
2594 if(path >= rtlphy->num_total_rfpath)
2595 return;
2596
2597 data = 0;
2598 if (path == RF90_PATH_A) {
2599 power_level =
2600 _rtl8821ae_get_txpower_index(hw, RF90_PATH_A,
2601 DESC_RATEMCS7, bw, channel);
2602 offset = RA_TXPWRTRAING;
2603 } else {
2604 power_level =
2605 _rtl8821ae_get_txpower_index(hw, RF90_PATH_A,
2606 DESC_RATEMCS7, bw, channel);
2607 offset = RB_TXPWRTRAING;
2608 }
2609
2610 for (i = 0; i < 3; i++) {
2611 if (i == 0)
2612 power_level = power_level - 10;
2613 else if (i == 1)
2614 power_level = power_level - 8;
2615 else
2616 power_level = power_level - 6;
2617
2618 data |= (((power_level > 2) ? (power_level) : 2) << (i * 8));
2619 }
2620 rtl_set_bbreg(hw, offset, 0xffffff, data);
2621}
2622
2623void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, u8 channel, u8 path)
2624{
2625 //struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2626 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2627 struct rtl_phy *rtlphy = &(rtl_priv(hw)->phy);
2628 u8 cck_rates[] = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M};
2629 u8 ofdm_rates[] = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, DESC_RATE18M,
2630 DESC_RATE24M, DESC_RATE36M, DESC_RATE48M, DESC_RATE54M};
2631 u8 ht_rates_1t[] = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, DESC_RATEMCS3,
2632 DESC_RATEMCS4, DESC_RATEMCS5, DESC_RATEMCS6, DESC_RATEMCS7};
2633 u8 ht_rates_2t[] = {DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10, DESC_RATEMCS11,
2634 DESC_RATEMCS12, DESC_RATEMCS13, DESC_RATEMCS14, DESC_RATEMCS15};
2635 u8 vht_rates_1t[] = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, DESC_RATEVHT1SS_MCS2,
2636 DESC_RATEVHT1SS_MCS3, DESC_RATEVHT1SS_MCS4,
2637 DESC_RATEVHT1SS_MCS5, DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
2638 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9};
2639 u8 vht_rates_2t[] = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, DESC_RATEVHT2SS_MCS2,
2640 DESC_RATEVHT2SS_MCS3, DESC_RATEVHT2SS_MCS4,
2641 DESC_RATEVHT2SS_MCS5, DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
2642 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9};
2643 //u8 i,size;
2644 //u8 power_index;
2645
2646 if (rtlhal->current_bandtype == BAND_ON_2_4G)
2647 _rtl8821ae_phy_set_txpower_level_by_path(hw,cck_rates,path,channel,
2648 sizeof(cck_rates) / sizeof(u8));
2649
2650 _rtl8821ae_phy_set_txpower_level_by_path(hw,ofdm_rates,path,channel,
2651 sizeof(ofdm_rates) / sizeof(u8));
2652 _rtl8821ae_phy_set_txpower_level_by_path(hw,ht_rates_1t,path,channel,
2653 sizeof(ht_rates_1t) / sizeof(u8));
2654 _rtl8821ae_phy_set_txpower_level_by_path(hw,vht_rates_1t,path,channel,
2655 sizeof(vht_rates_1t) / sizeof(u8));
2656
2657 if (rtlphy->num_total_rfpath >= 2) {
2658 _rtl8821ae_phy_set_txpower_level_by_path(hw,ht_rates_2t,path,channel,
2659 sizeof(ht_rates_2t) / sizeof(u8));
2660 _rtl8821ae_phy_set_txpower_level_by_path(hw,vht_rates_2t,path,channel,
2661 sizeof(vht_rates_2t) / sizeof(u8));
2662 }
2663
2664 _rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw, channel, path);
2665}
2666/*just in case, write txpower in DW, to reduce time*/
2667#if 0
2668void _rtl8821ae_phy_get_txpower_index_by_rate_array(struct ieee80211_hw *hw, u8 channel,
2669 u8 *rate, u8 path, u8 bw, u8 *power_index, u8 size)
2670{
2671 u8 i;
2672 for (i = 0; i < size; i++)
2673 power_index[i] = _rtl8821ae_get_txpower_index(hw, path, rate[i], bw, channel);
2674}
2675
2676void rtl8821ae_phy_set_txpower_level_by_path2(struct ieee80211_hw *hw, u8 channel, u8 path)
2677{
2678 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2679 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2680 struct rtl_phy *rtlphy = &(rtl_priv(hw)->phy);
2681 u8 cck_rates[] = {DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M};
2682 u8 ofdm_rates[] = {DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, DESC_RATE18M,
2683 DESC_RATE24M, DESC_RATE36M, DESC_RATE48M, DESC_RATE54M};
2684 u8 ht_rates_1t[] = {DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, DESC_RATEMCS3,
2685 DESC_RATEMCS4, DESC_RATEMCS5, DESC_RATEMCS6, DESC_RATEMCS7};
2686 u8 ht_rates_2t[] = {DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10, DESC_RATEMCS11,
2687 DESC_RATEMCS12, DESC_RATEMCS13, DESC_RATEMCS14, DESC_RATEMCS15};
2688 u8 vht_rates_1t[] = {DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3, DESC_RATEVHT1SS_MCS4,
2689 DESC_RATEVHT1SS_MCS5, DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7, DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9};
2690 u8 vht_rates_2t[] = {DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3, DESC_RATEVHT2SS_MCS4,
2691 DESC_RATEVHT2SS_MCS5, DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7, DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9};
2692 u8 i, j;
2693 u8 pwridx[48] = {0};
2694 u8 cs = sizeof(cck_rates) / sizeof(u8);
2695 u8 os = sizeof(ofdm_rates) / sizeof(u8);
2696 u8 h1s = sizeof(ht_rates_1t) / sizeof(u8);
2697 u8 h2s = sizeof(ht_rates_2t) / sizeof(u8);
2698 u8 v1s = sizeof(vht_rates_1t) / sizeof(u8);
2699 u8 v2s = sizeof(vht_rates_2t) / sizeof(u8);
2700
2701 u8 len, start;
2702 u32 reg_addr, power_index;
2703 u8 bw = rtlphy->current_chan_bw;
2704
2705 _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2706 ofdm_rates, path, bw, &pwridx[cs], os);
2707
2708 _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2709 ht_rates_1t, path, bw, &pwridx[cs+os], h1s);
2710
2711 _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2712 vht_rates_1t, path, bw, &pwridx[cs+os+h1s+h2s], v1s);
2713
2714
2715 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2716 _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2717 cck_rates, path, bw, pwridx, cs);
2718
2719 start = 0;
2720 } else {
2721 start = cs;
2722 }
2723
2724 reg_addr = (path == 0) ? RTXAGC_A_CCK11_CCK1 : RTXAGC_B_CCK11_CCK1;
2725 reg_addr += start;
2726
2727 len = cs + os + h1s + h2s + v1s;
2728 if (rtlphy->num_total_rfpath >= 2) {
2729 _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2730 ht_rates_2t, path, bw, &pwridx[cs+os+h1s], h2s);
2731
2732 _rtl8821ae_phy_get_txpower_index_by_rate_array(hw, channel,
2733 vht_rates_2t, path, bw, &pwridx[cs+os+h1s+h2s+v1s], v2s);
2734
2735 len += v2s;
2736 }
2737 for (i = start; i < len; i += 4) {
2738 power_index = 0;
2739 for (j = 0; j < 4; j++)
2740 power_index |= (pwridx[i+j] << (j*8));
2741 rtl_set_bbreg(hw, reg_addr + i, MASKDWORD, power_index);
2742 }
2743
2744 _rtl8821ae_phy_txpower_training_by_path(hw, rtlphy->current_chan_bw, channel, path);
2745}
2746#endif
2747
2748void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
2749{
2750 struct rtl_priv *rtlpriv = rtl_priv(hw);
2751 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2752 u8 path = 0;
2753
2754 for (path = RF90_PATH_A; path < rtlphy->num_total_rfpath; ++path )
2755 rtl8821ae_phy_set_txpower_level_by_path(hw, channel, path);
2756}
2757
2758static long _rtl8821ae_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
2759 enum wireless_mode wirelessmode,
2760 u8 txpwridx)
2761{
2762 long offset;
2763 long pwrout_dbm;
2764
2765 switch (wirelessmode) {
2766 case WIRELESS_MODE_B:
2767 offset = -7;
2768 break;
2769 case WIRELESS_MODE_G:
2770 case WIRELESS_MODE_N_24G:
2771 offset = -8;
2772 break;
2773 default:
2774 offset = -8;
2775 break;
2776 }
2777 pwrout_dbm = txpwridx / 2 + offset;
2778 return pwrout_dbm;
2779}
2780
2781void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
2782{
2783 struct rtl_priv *rtlpriv = rtl_priv(hw);
2784 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2785 enum io_type iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
2786
2787 if (!is_hal_stop(rtlhal)) {
2788 switch (operation) {
2789 case SCAN_OPT_BACKUP_BAND0:
2790 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
2791 rtlpriv->cfg->ops->set_hw_reg(hw,
2792 HW_VAR_IO_CMD,
2793 (u8 *) & iotype);
2794
2795 break;
2796 case SCAN_OPT_BACKUP_BAND1:
2797 iotype = IO_CMD_PAUSE_BAND1_DM_BY_SCAN;
2798 rtlpriv->cfg->ops->set_hw_reg(hw,
2799 HW_VAR_IO_CMD,
2800 (u8 *) & iotype);
2801
2802 break;
2803 case SCAN_OPT_RESTORE:
2804 iotype = IO_CMD_RESUME_DM_BY_SCAN;
2805 rtlpriv->cfg->ops->set_hw_reg(hw,
2806 HW_VAR_IO_CMD,
2807 (u8 *) & iotype);
2808 break;
2809 default:
2810 RT_TRACE(COMP_ERR, DBG_EMERG,
2811 ("Unknown Scan Backup operation.\n"));
2812 break;
2813 }
2814 }
2815}
2816
2817static void _rtl8821ae_phy_set_reg_bw(struct rtl_priv * rtlpriv, u8 bw)
2818{
2819 u16 reg_rf_mode_bw, tmp = 0;
2820 reg_rf_mode_bw = rtl_read_word(rtlpriv, REG_TRXPTCL_CTL);
2821 switch (bw) {
2822 case HT_CHANNEL_WIDTH_20:
2823 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, reg_rf_mode_bw & 0xFE7F);
2824 break;
2825 case HT_CHANNEL_WIDTH_20_40:
2826 tmp = reg_rf_mode_bw | BIT(7);
2827 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFEFF);
2828 break;
2829 case HT_CHANNEL_WIDTH_80:
2830 tmp = reg_rf_mode_bw | BIT(8);
2831 rtl_write_word(rtlpriv, REG_TRXPTCL_CTL, tmp & 0xFF7F);
2832 break;
2833 default:
2834 RT_TRACE(COMP_ERR, DBG_WARNING,("unknown Bandwidth: 0x%x\n",bw));
2835 break;
2836 }
2837}
2838
2839static u8 _rtl8821ae_phy_get_secondary_chnl(struct rtl_priv * rtlpriv)
2840{
2841 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2842 struct rtl_mac *mac = rtl_mac(rtlpriv);
2843 u8 sc_set_40 = 0, sc_set_20 =0;
2844
2845 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
2846 if(mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_LOWER)
2847 sc_set_40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
2848 else if(mac->cur_80_prime_sc == PRIME_CHNL_OFFSET_UPPER)
2849 sc_set_40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
2850 else
2851 RT_TRACE(COMP_ERR, DBG_EMERG,
2852 ("SCMapping: Not Correct Primary40MHz Setting \n"));
2853
2854 if((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
2855 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
2856 sc_set_20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
2857 else if((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
2858 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_LOWER))
2859 sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
2860 else if((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER) &&
2861 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
2862 sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
2863 else if((mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER) &&
2864 (mac->cur_80_prime_sc == HAL_PRIME_CHNL_OFFSET_UPPER))
2865 sc_set_20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
2866 else
2867 RT_TRACE(COMP_ERR, DBG_EMERG,
2868 ("SCMapping: Not Correct Primary40MHz Setting \n"));
2869 } else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
2870 if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_UPPER)
2871 sc_set_20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
2872 else if (mac->cur_40_prime_sc == PRIME_CHNL_OFFSET_LOWER)
2873 sc_set_20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
2874 else
2875 RT_TRACE(COMP_ERR, DBG_EMERG,
2876 ("SCMapping: Not Correct Primary40MHz Setting \n"));
2877 }
2878 return ((sc_set_40 << 4) | sc_set_20);
2879}
2880
2881void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
2882{
2883 struct rtl_priv *rtlpriv = rtl_priv(hw);
2884 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2885 u8 sub_chnl = 0;
2886 u8 l1pk_val = 0;
2887
2888 RT_TRACE(COMP_SCAN, DBG_TRACE,
2889 ("Switch to %s bandwidth\n",
2890 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
2891 "20MHz" :
2892 (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 ?
2893 "40MHz" : "80MHz"))))
2894
2895
2896
2897 _rtl8821ae_phy_set_reg_bw(rtlpriv, rtlphy->current_chan_bw);
2898 sub_chnl = _rtl8821ae_phy_get_secondary_chnl(rtlpriv);
2899 rtl_write_byte(rtlpriv, 0x0483, sub_chnl);
2900
2901 switch (rtlphy->current_chan_bw) {
2902 case HT_CHANNEL_WIDTH_20:
2903 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300200);
2904 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
2905
2906 if(rtlphy->rf_type == RF_2T2R)
2907 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 7);
2908 else
2909 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, 8);
2910 break;
2911 case HT_CHANNEL_WIDTH_20_40:
2912 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300201);
2913 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 0);
2914 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
2915 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
2916
2917 if(rtlphy->reg_837 & BIT(2))
2918 l1pk_val = 6;
2919 else
2920 {
2921 if(rtlphy->rf_type == RF_2T2R)
2922 l1pk_val = 7;
2923 else
2924 l1pk_val = 8;
2925 }
2926 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val); // 0x848[25:22] = 0x6
2927
2928 if(sub_chnl == VHT_DATA_SC_20_UPPER_OF_80MHZ)
2929 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 1);
2930 else
2931 rtl_set_bbreg(hw, RCCK_SYSTEM, BCCK_SYSTEM, 0);
2932 break;
2933
2934 case HT_CHANNEL_WIDTH_80:
2935 rtl_set_bbreg(hw, RRFMOD, 0x003003C3, 0x00300202); // 0x8ac[21,20,9:6,1,0]=8'b11100010
2936 rtl_set_bbreg(hw, RADC_BUF_CLK, BIT(30), 1); // 0x8c4[30] = 1
2937 rtl_set_bbreg(hw, RRFMOD, 0x3C, sub_chnl);
2938 rtl_set_bbreg(hw, RCCAONSEC, 0xf0000000, sub_chnl);
2939
2940 if(rtlphy->reg_837 & BIT(2))
2941 l1pk_val = 5;
2942 else
2943 {
2944 if(rtlphy->rf_type == RF_2T2R)
2945 l1pk_val = 6;
2946 else
2947 l1pk_val = 7;
2948 }
2949 rtl_set_bbreg(hw, RL1PEAKTH, 0x03C00000, l1pk_val);
2950
2951 break;
2952 default:
2953 RT_TRACE(COMP_ERR, DBG_EMERG,
2954 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
2955 break;
2956 }
2957
2958 rtl8812ae_fixspur(hw, rtlphy->current_chan_bw, rtlphy->current_channel);
2959
2960 rtl8821ae_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
2961 rtlphy->set_bwmode_inprogress = false;
2962
2963 RT_TRACE(COMP_SCAN, DBG_LOUD, (" \n"));
2964}
2965
2966void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
2967 enum nl80211_channel_type ch_type)
2968{
2969 struct rtl_priv *rtlpriv = rtl_priv(hw);
2970 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2971 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2972 u8 tmp_bw = rtlphy->current_chan_bw;
2973
2974 if (rtlphy->set_bwmode_inprogress)
2975 return;
2976 rtlphy->set_bwmode_inprogress = true;
2977 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
2978 rtl8821ae_phy_set_bw_mode_callback(hw);
2979 } else {
2980 RT_TRACE(COMP_ERR, DBG_WARNING,
2981 ("FALSE driver sleep or unload\n"));
2982 rtlphy->set_bwmode_inprogress = false;
2983 rtlphy->current_chan_bw = tmp_bw;
2984 }
2985}
2986
2987void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw)
2988{
2989 struct rtl_priv *rtlpriv = rtl_priv(hw);
2990 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2991 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2992 u8 channel = rtlphy->current_channel;
2993 u8 path;
2994 u32 data;
2995
2996 RT_TRACE(COMP_SCAN, DBG_TRACE,
2997 ("switch to channel%d\n", rtlphy->current_channel));
2998 if (is_hal_stop(rtlhal))
2999 return;
3000
3001 if (36 <= channel && channel <= 48)
3002 data = 0x494;
3003 else if (50 <= channel && channel <= 64)
3004 data = 0x453;
3005 else if (100 <= channel && channel <= 116)
3006 data = 0x452;
3007 else if (118 <= channel)
3008 data = 0x412;
3009 else
3010 data = 0x96a;
3011 rtl_set_bbreg(hw, RFC_AREA, 0x1ffe0000, data);
3012
3013
3014 for(path = RF90_PATH_A; path < rtlphy->num_total_rfpath; path++)
3015 {
3016 if (36 <= channel && channel <= 64)
3017 data = 0x101;
3018 else if (100 <= channel && channel <= 140)
3019 data = 0x301;
3020 else if (140 < channel)
3021 data = 0x501;
3022 else
3023 data = 0x000;
3024 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3025 BIT(18)|BIT(17)|BIT(16)|BIT(9)|BIT(8), data);
3026
3027 rtl8821ae_phy_set_rf_reg(hw, path, RF_CHNLBW,
3028 BMASKBYTE0, channel);
3029
3030 if (channel > 14) {
3031 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
3032 if (36 <= channel && channel <= 64)
3033 data = 0x114E9;
3034 else if (100 <= channel && channel <= 140)
3035 data = 0x110E9;
3036 else
3037 data = 0x110E9;
3038 rtl8821ae_phy_set_rf_reg(hw, path, RF_APK,
3039 BRFREGOFFSETMASK, data);
3040 }
3041 }
3042 }
3043 RT_TRACE(COMP_SCAN, DBG_TRACE, ("\n"));
3044}
3045
3046u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw)
3047{
3048 struct rtl_priv *rtlpriv = rtl_priv(hw);
3049 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3050 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3051 u32 timeout = 1000, timecount = 0;
3052 u8 channel = rtlphy->current_channel;
3053
3054 if (rtlphy->sw_chnl_inprogress)
3055 return 0;
3056 if (rtlphy->set_bwmode_inprogress)
3057 return 0;
3058
3059 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
3060 RT_TRACE(COMP_CHAN, DBG_LOUD,
3061 ("sw_chnl_inprogress false driver sleep or unload\n"));
3062 return 0;
3063 }
3064 while (rtlphy->lck_inprogress && timecount < timeout) {
3065 mdelay(50);
3066 timecount += 50;
3067 }
3068
3069 if (rtlphy->current_channel > 14 && rtlhal->current_bandtype != BAND_ON_5G)
3070 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_5G);
3071 else if (rtlphy->current_channel <= 14 && rtlhal->current_bandtype != BAND_ON_2_4G)
3072 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
3073
3074 rtlphy->sw_chnl_inprogress = true;
3075 if (channel == 0)
3076 channel = 1;
3077
3078 RT_TRACE(COMP_SCAN, DBG_TRACE,
3079 ("switch to channel%d, band type is %d\n", rtlphy->current_channel, rtlhal->current_bandtype));
3080
3081 rtl8821ae_phy_sw_chnl_callback(hw);
3082
3083 rtl8821ae_dm_clear_txpower_tracking_state(hw);
3084 rtl8821ae_phy_set_txpower_level(hw, rtlphy->current_channel);
3085
3086 RT_TRACE(COMP_SCAN, DBG_TRACE, ("\n"));
3087 rtlphy->sw_chnl_inprogress = false;
3088 return 1;
3089}
3090
3091#if 0
3092static u8 _rtl8821ae_phy_path_b_iqk(struct ieee80211_hw *hw)
3093{
3094 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3095 u8 result = 0x00;
3096
3097 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
3098 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
3099 mdelay(IQK_DELAY_TIME);
3100 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
3101 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
3102 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
3103 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
3104 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
3105
3106 if (!(reg_eac & BIT(31)) &&
3107 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
3108 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
3109 result |= 0x01;
3110 else
3111 return result;
3112 if (!(reg_eac & BIT(30)) &&
3113 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
3114 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
3115 result |= 0x02;
3116 return result;
3117}
3118
3119static u8 _rtl8821ae_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
3120{
3121 u32 reg_eac, reg_e94, reg_e9c, reg_ea4,u32temp;
3122 u8 result = 0x00;
3123
3124 /*Get TXIMR Setting*/
3125 /*Modify RX IQK mode table*/
3126 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
3127 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
3128 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
3129 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
3130 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
3131 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
3132
3133 /*IQK Setting*/
3134 rtl_set_bbreg(hw, RTx_IQK, MASKDWORD, 0x01007c00);
3135 rtl_set_bbreg(hw, RRx_IQK, MASKDWORD, 0x81004800);
3136
3137 /*path a IQK setting*/
3138 rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x10008c1c);
3139 rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x30008c1c);
3140 rtl_set_bbreg(hw, RTx_IQK_PI_A, MASKDWORD, 0x82160804);
3141 rtl_set_bbreg(hw, RRx_IQK_PI_A, MASKDWORD, 0x28160000);
3142
3143 /*LO calibration Setting*/
3144 rtl_set_bbreg(hw, RIQK_AGC_Rsp, MASKDWORD, 0x0046a911);
3145 /*one shot,path A LOK & iqk*/
3146 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf9000000);
3147 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf8000000);
3148
3149 mdelay(IQK_DELAY_TIME);
3150
3151 reg_eac = rtl_get_bbreg(hw, RRx_Power_After_IQK_A_2, MASKDWORD);
3152 reg_e94 = rtl_get_bbreg(hw, RTx_Power_Before_IQK_A, MASKDWORD);
3153 reg_e9c = rtl_get_bbreg(hw, RTx_Power_After_IQK_A, MASKDWORD);
3154
3155
3156 if (!(reg_eac & BIT(28)) &&
3157 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
3158 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
3159 result |= 0x01;
3160 else
3161 return result;
3162
3163 u32temp = 0x80007C00 | (reg_e94&0x3FF0000) | ((reg_e9c&0x3FF0000) >> 16);
3164 rtl_set_bbreg(hw, RTx_IQK, MASKDWORD, u32temp);
3165 /*RX IQK*/
3166 /*Modify RX IQK mode table*/
3167 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
3168 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
3169 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
3170 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
3171 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
3172 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
3173
3174 /*IQK Setting*/
3175 rtl_set_bbreg(hw, RRx_IQK, MASKDWORD, 0x01004800);
3176
3177 /*path a IQK setting*/
3178 rtl_set_bbreg(hw, RTx_IQK_Tone_A, MASKDWORD, 0x30008c1c);
3179 rtl_set_bbreg(hw, RRx_IQK_Tone_A, MASKDWORD, 0x10008c1c);
3180 rtl_set_bbreg(hw, RTx_IQK_PI_A, MASKDWORD, 0x82160c05);
3181 rtl_set_bbreg(hw, RRx_IQK_PI_A, MASKDWORD, 0x28160c05);
3182
3183 /*LO calibration Setting*/
3184 rtl_set_bbreg(hw, RIQK_AGC_Rsp, MASKDWORD, 0x0046a911);
3185 /*one shot,path A LOK & iqk*/
3186 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf9000000);
3187 rtl_set_bbreg(hw, RIQK_AGC_Pts, MASKDWORD, 0xf8000000);
3188
3189 mdelay(IQK_DELAY_TIME);
3190
3191 reg_eac = rtl_get_bbreg(hw, RRx_Power_After_IQK_A_2, MASKDWORD);
3192 reg_e94 = rtl_get_bbreg(hw, RTx_Power_Before_IQK_A, MASKDWORD);
3193 reg_e9c = rtl_get_bbreg(hw, RTx_Power_After_IQK_A, MASKDWORD);
3194 reg_ea4 = rtl_get_bbreg(hw, RRx_Power_Before_IQK_A_2, MASKDWORD);
3195
3196 if (!(reg_eac & BIT(27)) &&
3197 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
3198 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
3199 result |= 0x02;
3200 return result;
3201}
3202#endif
3203
3204u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl)
3205{
3206 u8 channel_all[TARGET_CHNL_NUM_2G_5G_8812] =
3207 {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,\
3208 44,46,48,50,52,54,56,58,60,62,64,100,\
3209 102,104,106,108,110,112,114,116,118,\
3210 120,122,124,126,128,130,132,134,136,\
3211 138,140,149,151,153,155,157,159,161,\
3212 163,165};
3213 u8 place = chnl;
3214
3215 if(chnl > 14)
3216 {
3217 for(place = 14; place<sizeof(channel_all); place++)
3218 {
3219 if(channel_all[place] == chnl)
3220 {
3221 return place-13;
3222 }
3223 }
3224 }
3225
3226 return 0;
3227}
3228
3229void _rtl8812ae_iqk_rx_fill_iqc(
3230 struct ieee80211_hw *hw,
3231 enum radio_path path,
3232 u32 rx_x,
3233 u32 rx_y
3234 )
3235{
3236 struct rtl_priv *rtlpriv = rtl_priv(hw);
3237
3238 switch (path) {
3239 case RF90_PATH_A:
3240 {
3241 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3242 if (rx_x >> 1 ==0x112 || rx_y >> 1 == 0x3ee){
3243 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x100);
3244 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0);
3245 RT_TRACE(COMP_IQK, DBG_LOUD,
3246 ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n",
3247 rx_x >> 1 & 0x000003ff, rx_y >> 1 & 0x000003ff));
3248 }
3249 else{
3250 rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x >> 1);
3251 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y >> 1);
3252 RT_TRACE(COMP_IQK, DBG_LOUD,
3253 ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n",
3254 rx_x >> 1 & 0x000003ff, rx_y >> 1 & 0x000003ff));
3255 RT_TRACE(COMP_IQK, DBG_LOUD,
3256 ("0xc10 = %x ====>fill to IQC\n",
3257 rtl_read_dword(rtlpriv, 0xc10)));
3258 }
3259 }
3260 break;
3261 case RF90_PATH_B:
3262 {
3263 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3264 if (rx_x >> 1 ==0x112 || rx_y >> 1 == 0x3ee){
3265 rtl_set_bbreg(hw, 0xe10, 0x000003ff, 0x100);
3266 rtl_set_bbreg(hw, 0xe10, 0x03ff0000, 0);
3267 RT_TRACE(COMP_IQK, DBG_LOUD,
3268 ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n",
3269 rx_x >> 1 & 0x000003ff, rx_y >> 1 & 0x000003ff));
3270 }
3271 else{
3272 rtl_set_bbreg(hw, 0xe10, 0x000003ff, rx_x >> 1);
3273 rtl_set_bbreg(hw, 0xe10, 0x03ff0000, rx_y >> 1);
3274 RT_TRACE(COMP_IQK, DBG_LOUD,
3275 ("RX_X = %x;;RX_Y = %x====>fill to IQC\n ",
3276 rx_x >> 1 & 0x000003ff, rx_y >> 1 & 0x000003ff));
3277 RT_TRACE(COMP_IQK, DBG_LOUD,
3278 ("0xe10 = %x====>fill to IQC\n",
3279 rtl_read_dword(rtlpriv, 0xe10)));
3280 }
3281 }
3282 break;
3283 default:
3284 break;
3285 };
3286}
3287
3288void _rtl8812ae_iqk_tx_fill_iqc(
3289 struct ieee80211_hw *hw,
3290 enum radio_path path,
3291 u32 tx_x,
3292 u32 tx_y
3293 )
3294{
3295 struct rtl_priv *rtlpriv = rtl_priv(hw);
3296
3297 switch (path) {
3298 case RF90_PATH_A:
3299 {
3300 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 1 --> Page C1*/
3301 rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
3302 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
3303 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
3304 rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y);
3305 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x);
3306 RT_TRACE(COMP_IQK, DBG_LOUD,
3307 ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n",
3308 tx_x & 0x000007ff, tx_y & 0x000007ff));
3309 RT_TRACE(COMP_IQK, DBG_LOUD,
3310 ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n",
3311 rtl_get_bbreg(hw, 0xcd4, 0x000007ff),
3312 rtl_get_bbreg(hw, 0xccc, 0x000007ff)));
3313 }
3314 break;
3315 case RF90_PATH_B:
3316 {
3317 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 1 --> Page C1*/
3318 rtl_write_dword(rtlpriv, 0xe90, 0x00000080);
3319 rtl_write_dword(rtlpriv, 0xec4, 0x20040000);
3320 rtl_write_dword(rtlpriv, 0xec8, 0x20000000);
3321 rtl_set_bbreg(hw, 0xecc, 0x000007ff, tx_y);
3322 rtl_set_bbreg(hw, 0xed4, 0x000007ff, tx_x);
3323 RT_TRACE(COMP_IQK, DBG_LOUD,
3324 ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n",
3325 tx_x&0x000007ff, tx_y&0x000007ff));
3326 RT_TRACE(COMP_IQK, DBG_LOUD,
3327 ("0xed4 = %x;;0xecc = %x ====>fill to IQC\n",
3328 rtl_get_bbreg(hw, 0xed4, 0x000007ff),
3329 rtl_get_bbreg(hw, 0xecc, 0x000007ff)));
3330 }
3331 break;
3332 default:
3333 break;
3334 };
3335}
3336
3337void _rtl8812ae_iqk_backup_macbb(
3338 struct ieee80211_hw *hw,
3339 u32 *macbb_backup,
3340 u32 *backup_macbb_reg,
3341 u32 mac_bb_num
3342 )
3343{
3344 struct rtl_priv *rtlpriv = rtl_priv(hw);
3345 u32 i;
3346
3347 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3348 /*save MACBB default value*/
3349 for (i = 0; i < mac_bb_num; i++) {
3350 macbb_backup[i] =rtl_read_dword(rtlpriv,backup_macbb_reg[i]);
3351 }
3352
3353 RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupMacBB Success!!!!\n"));
3354}
3355
3356void _rtl8812ae_iqk_backup_afe(
3357 struct ieee80211_hw *hw,
3358 u32 *afe_backup,
3359 u32 *backup_afe_REG,
3360 u32 afe_num
3361 )
3362{
3363 struct rtl_priv *rtlpriv = rtl_priv(hw);
3364 u32 i;
3365
3366 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3367 /*Save AFE Parameters */
3368 for (i = 0; i < afe_num; i++){
3369 afe_backup[i] = rtl_read_dword(rtlpriv, backup_afe_REG[i]);
3370 }
3371 RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupAFE Success!!!!\n"));
3372}
3373
3374void _rtl8812ae_iqk_backup_rf(
3375 struct ieee80211_hw *hw,
3376 u32 *rfa_backup,
3377 u32 *rfb_backup,
3378 u32 *backup_rf_reg,
3379 u32 rf_num
3380 )
3381{
3382
3383 struct rtl_priv *rtlpriv = rtl_priv(hw);
3384 u32 i;
3385
3386 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3387 /*Save RF Parameters*/
3388 for (i = 0; i < rf_num; i++){
3389 rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i], BMASKDWORD);
3390 rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i], BMASKDWORD);
3391 }
3392 RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupRF Success!!!!\n"));
3393}
3394
3395void _rtl8812ae_iqk_configure_mac(
3396 struct ieee80211_hw *hw
3397 )
3398{
3399 struct rtl_priv *rtlpriv = rtl_priv(hw);
3400 /* ========MAC register setting========*/
3401 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3402 rtl_write_byte(rtlpriv, 0x522, 0x3f);
3403 rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0);
3404 rtl_write_byte(rtlpriv, 0x808, 0x00); /*RX ante off*/
3405 rtl_set_bbreg(hw, 0x838, 0xf, 0xc); /*CCA off*/
3406}
3407
3408#define cal_num 10
3409
3410void _rtl8812ae_iqk_tx(
3411 struct ieee80211_hw *hw,
3412 u8 chnl_idx
3413 )
3414{
3415 struct rtl_priv *rtlpriv = rtl_priv(hw);
3416 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3417 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3418
3419 u8 delay_count;
3420 u8 cal0_retry, cal1_retry;
3421 u8 tx0_average = 0, tx1_average = 0, rx0_average = 0, rx1_average = 0;
3422 int tx0_x = 0, tx0_y = 0, rx0_x = 0, rx0_y = 0;
3423 int tx_x0[cal_num], tx_y0[cal_num], rx_x0[cal_num], rx_y0[cal_num];
3424 int tx1_x = 0, tx1_y = 0, rx1_x = 0, rx1_y = 0;
3425 int tx_x1[cal_num], tx_y1[cal_num], rx_x1[cal_num], rx_y1[cal_num];
3426 bool tx0iqkok= false, rx0iqkok = false, tx0_fail = true, rx0_fail;
3427 bool iqk0_ready = false, tx0_finish = false, rx0_finish = false;
3428 bool tx1iqkok = false, rx1iqkok = false, tx1_fail = true, rx1_fail;
3429 bool iqk1_ready = false, tx1_finish = false, rx1_finish = false, vdf_enable = false;
3430 int i, tx_dt[3] = {0}, rx_dt[3] = {0}, ii, dx = 0, dy = 0;
3431
3432 RT_TRACE(COMP_IQK, DBG_LOUD,
3433 ("BandWidth = %d.\n",
3434 rtlphy->current_chan_bw));
3435 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80){
3436 vdf_enable = true;
3437 }
3438 vdf_enable = false;
3439
3440
3441 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3442 /*========Path-A AFE all on========*/
3443 /*Port 0 DAC/ADC on*/
3444 rtl_write_dword(rtlpriv, 0xc60, 0x77777777);
3445 rtl_write_dword(rtlpriv, 0xc64, 0x77777777);
3446
3447 /* Port 1 DAC/ADC off*/
3448 rtl_write_dword(rtlpriv, 0xe60, 0x77777777);
3449 rtl_write_dword(rtlpriv, 0xe64, 0x77777777);
3450
3451 rtl_write_dword(rtlpriv, 0xc68, 0x19791979);
3452 rtl_write_dword(rtlpriv, 0xe68, 0x19791979);
3453 rtl_set_bbreg(hw,0xc00, 0xf, 0x4);/*hardware 3-wire off*/
3454 rtl_set_bbreg(hw,0xe00, 0xf, 0x4);/*hardware 3-wire off*/
3455
3456 /*DAC/ADC sampling rate (160 MHz)*/
3457 rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
3458 rtl_set_bbreg(hw, 0xe5c, BIT(26) | BIT(25) | BIT(24), 0x7);
3459 rtl_set_bbreg(hw, 0x8c4, BIT(30), 0x1);
3460
3461 /*====== Path A TX IQK RF Setting ======*/
3462 rtl_set_bbreg(hw,0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
3463 rtl_set_rfreg(hw,RF90_PATH_A, 0xef, BRFREGOFFSETMASK, 0x80002);
3464 rtl_set_rfreg(hw,RF90_PATH_A, 0x30, BRFREGOFFSETMASK, 0x20000);
3465 rtl_set_rfreg(hw,RF90_PATH_A, 0x31, BRFREGOFFSETMASK, 0x3fffd);
3466 rtl_set_rfreg(hw,RF90_PATH_A, 0x32, BRFREGOFFSETMASK, 0xfe83f);
3467 rtl_set_rfreg(hw,RF90_PATH_A, 0x65, BRFREGOFFSETMASK, 0x931d5);
3468 rtl_set_rfreg(hw,RF90_PATH_A, 0x8f, BRFREGOFFSETMASK, 0x8a001);
3469 /*====== Path A TX IQK RF Setting ======*/
3470 rtl_set_rfreg(hw,RF90_PATH_B, 0xef, BRFREGOFFSETMASK, 0x80002);
3471 rtl_set_rfreg(hw,RF90_PATH_B, 0x30, BRFREGOFFSETMASK, 0x20000);
3472 rtl_set_rfreg(hw,RF90_PATH_B, 0x31, BRFREGOFFSETMASK, 0x3fffd);
3473 rtl_set_rfreg(hw,RF90_PATH_B, 0x32, BRFREGOFFSETMASK, 0xfe83f);
3474 rtl_set_rfreg(hw,RF90_PATH_B, 0x65, BRFREGOFFSETMASK, 0x931d5);
3475 rtl_set_rfreg(hw,RF90_PATH_B, 0x8f, BRFREGOFFSETMASK, 0x8a001);
3476 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3477 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
3478 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
3479 rtl_set_bbreg(hw, 0xe94, BIT(0), 0x1);
3480 rtl_write_dword(rtlpriv, 0x978, 0x29002000);/* TX (X,Y)*/
3481 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);/* RX (X,Y)*/
3482 rtl_write_dword(rtlpriv, 0x984, 0x00462910);/*[0]:AGC_en, [15]:idac_K_Mask*/
3483 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1*/
3484
3485 /*ExternalPA_5G == 0*/
3486 rtl_write_dword(rtlpriv, 0xc88, 0x821403f1);
3487 rtl_write_dword(rtlpriv, 0xe88, 0x821403f1);
3488
3489 if (rtlhal->current_bandtype){
3490 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
3491 rtl_write_dword(rtlpriv, 0xe8c, 0x68163e96);
3492 }
3493 else{
3494 rtl_write_dword(rtlpriv, 0xc8c, 0x28163e96);
3495 rtl_write_dword(rtlpriv, 0xe8c, 0x28163e96);
3496 }
3497
3498 if (vdf_enable){}
3499 else{
3500 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);/*TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16*/
3501 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);/*RX_Tone_idx[9:0], RxK_Mask[29]*/
3502 rtl_write_dword(rtlpriv, 0xce8, 0x00000000);
3503 rtl_write_dword(rtlpriv, 0xe80, 0x18008c10);/*TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16*/
3504 rtl_write_dword(rtlpriv, 0xe84, 0x38008c10);/*RX_Tone_idx[9:0], RxK_Mask[29]*/
3505 rtl_write_dword(rtlpriv, 0xee8, 0x00000000);
3506
3507 cal0_retry = 0;
3508 cal1_retry = 0;
3509 while(1){
3510 /*one shot*/
3511 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);/* cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module*/
3512 rtl_write_dword(rtlpriv, 0xeb8, 0x00100000);/* cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module*/
3513 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
3514 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
3515
3516 mdelay(10); /*Delay 25ms*/
3517 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3518 rtl_write_dword(rtlpriv, 0xeb8, 0x00000000);
3519 delay_count = 0;
3520 while (1){
3521 if (!tx0_finish)
3522 iqk0_ready = (bool) rtl_get_bbreg(hw, 0xd00, BIT(10));
3523 if (!tx1_finish)
3524 iqk1_ready = (bool) rtl_get_bbreg(hw, 0xd40, BIT(10));
3525 if ((iqk0_ready && iqk1_ready) || (delay_count>20))
3526 break;
3527 else{
3528 mdelay(1);
3529 delay_count++;
3530 }
3531 }
3532 RT_TRACE(COMP_IQK, DBG_LOUD, ("TX delay_count = %d\n", delay_count));
3533 if (delay_count < 20){ // If 20ms No Result, then cal_retry++
3534 /* ============TXIQK Check==============*/
3535 tx0_fail = (bool) rtl_get_bbreg(hw, 0xd00, BIT(12));
3536 tx1_fail = (bool) rtl_get_bbreg(hw, 0xd40, BIT(12));
3537 if (!(tx0_fail || tx0_finish)){
3538 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
3539 tx_x0[tx0_average] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000) << 21;
3540 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
3541 tx_y0[tx0_average] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000) << 21;
3542 tx0iqkok = true;
3543 RT_TRACE(COMP_IQK, DBG_LOUD,
3544 ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n",
3545 tx0_average, (tx_x0[tx0_average]) >> 21 & 0x000007ff,
3546 tx0_average, (tx_y0[tx0_average]) >> 21 & 0x000007ff));
3547
3548 tx0_average++;
3549 }
3550 else{
3551 tx0iqkok = false;
3552 cal0_retry++;
3553 if (cal0_retry == 10)
3554 break;
3555 }
3556 if (!(tx1_fail || tx1_finish)){
3557 rtl_write_dword(rtlpriv, 0xeb8, 0x02000000);
3558 tx_x1[tx1_average] = rtl_get_bbreg(hw, 0xd40, 0x07ff0000) << 21;
3559 rtl_write_dword(rtlpriv, 0xeb8, 0x04000000);
3560 tx_y1[tx1_average] = rtl_get_bbreg(hw, 0xd40, 0x07ff0000) << 21;
3561 tx1iqkok= true;
3562 RT_TRACE(COMP_IQK, DBG_LOUD,
3563 ("TX_X1[%d] = %x ;; TX_Y1[%d] = %x\n",
3564 tx1_average, (tx_x1[tx1_average]) >> 21 & 0x000007ff,
3565 tx1_average, (tx_y1[tx1_average]) >> 21 & 0x000007ff));
3566
3567 tx1_average++;
3568 }
3569 else{
3570 tx1iqkok = false;
3571 cal1_retry++;
3572 if (cal1_retry == 10)
3573 break;
3574 }
3575 }
3576 else{
3577 tx0iqkok = false;
3578 tx1iqkok = false;
3579 cal0_retry++;
3580 cal1_retry++;
3581 RT_TRACE(COMP_IQK, DBG_LOUD,
3582 ("Delay 20ms TX IQK Not Ready!!!!!\n"));
3583 if (cal0_retry == 10)
3584 break;
3585 }
3586 if (tx0_average >= 2){
3587 for (i = 0; i < tx0_average; i++){
3588 for (ii = i+1; ii <tx0_average; ii++){
3589 dx = (tx_x0[i] >> 21) - (tx_x0[ii] >> 21);
3590 if (dx < 4 && dx > -4){
3591 dy = (tx_y0[i]>>21) - (tx_y0[ii]>>21);
3592 if (dy < 4 && dy > -4){
3593 tx0_x = ((tx_x0[i] >> 21) + (tx_x0[ii] >> 21)) / 2;
3594 tx0_y = ((tx_y0[i] >> 21) + (tx_y0[ii] >> 21)) / 2;
3595 tx_x0[0] = tx_x0[i];
3596 tx_y0[1] = tx_y0[ii];
3597 RT_TRACE(COMP_IQK, DBG_LOUD,
3598 ("TX0_X = %x;;TX0_Y = %x\n",
3599 tx0_x & 0x000007ff, tx0_y & 0x000007ff));
3600 if ((rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3601 && vdf_enable) {
3602 tx_dt[0] = (tx_dt[i] + tx_dt[ii]) / 2;
3603 }
3604 tx0_finish = true;
3605 }
3606 }
3607 }
3608 }
3609 }
3610 if (tx1_average >= 2){
3611 for (i = 0; i < tx1_average; i++){
3612 for (ii = i+1; ii < tx1_average; ii++){
3613 dx = (tx_x1[i] >> 21) - (tx_x1[ii] >> 21);
3614 if (dx < 4 && dx > -4){
3615 dy = (tx_y1[i] >> 21) - (tx_y1[ii] >> 21);
3616 if (dy < 4 && dy > -4){
3617 tx1_x = ((tx_x1[i] >> 21) + (tx_x1[ii] >> 21)) / 2;
3618 tx1_y = ((tx_y1[i] >> 21) + (tx_y1[ii] >> 21)) / 2;
3619 tx_x1[0] = tx_x1[i];
3620 tx_y1[1] = tx_y1[ii];
3621 RT_TRACE(COMP_IQK, DBG_LOUD,
3622 ("TX1_X = %x;;TX1_Y = %x\n",
3623 tx1_x & 0x000007ff, tx1_y & 0x000007ff));
3624 if ((rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3625 && vdf_enable) {
3626 tx_dt[0] = (tx_dt[i] + tx_dt[ii]) / 2;
3627 }
3628 tx1_finish = true;
3629 }
3630 }
3631 }
3632 }
3633 }
3634 RT_TRACE(COMP_IQK, DBG_LOUD,
3635 ("TX0_Average = %d, TX1_Average = %d\n",
3636 tx0_average, tx1_average));
3637 RT_TRACE(COMP_IQK, DBG_LOUD,
3638 ("TX0_finish = %d, TX1_finish = %d\n",
3639 tx0_finish, tx1_finish));
3640 if (tx0_finish && tx1_finish)
3641 break;
3642 if ((cal0_retry + tx0_average) >= 10
3643 || (cal1_retry + tx1_average) >= 10 )
3644 break;
3645 }
3646 RT_TRACE(COMP_IQK, DBG_LOUD,
3647 ("TXA_cal_retry = %d\n", cal0_retry));
3648 RT_TRACE(COMP_IQK, DBG_LOUD,
3649 ("TXB_cal_retry = %d\n", cal1_retry));
3650
3651 }
3652
3653 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
3654 rtl_set_rfreg(hw, RF90_PATH_A, 0x58, 0x7fe00,
3655 rtl_get_rfreg(hw, RF90_PATH_A, 0x8, 0xffc00)); /*Load LOK*/
3656 rtl_set_rfreg(hw, RF90_PATH_B, 0x58, 0x7fe00,
3657 rtl_get_rfreg(hw, RF90_PATH_B, 0x8, 0xffc00)); /* Load LOK*/
3658 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 1 --> Page C1*/
3659
3660
3661 if (vdf_enable) {}
3662 else{
3663 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3664 if (tx0_finish) {
3665 /*====== Path A RX IQK RF Setting======*/
3666 rtl_set_rfreg(hw, RF90_PATH_A, 0xef, BRFREGOFFSETMASK, 0x80000);
3667 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, 0x00c00, 0x3); /* BW 20M*/
3668 rtl_set_rfreg(hw, RF90_PATH_A, 0x30, BRFREGOFFSETMASK, 0x30000);
3669 rtl_set_rfreg(hw, RF90_PATH_A, 0x31, BRFREGOFFSETMASK, 0x3f7ff);
3670 rtl_set_rfreg(hw, RF90_PATH_A, 0x32, BRFREGOFFSETMASK, 0xfe7bf);
3671 rtl_set_rfreg(hw, RF90_PATH_A, 0x8f, BRFREGOFFSETMASK, 0x88001);
3672 rtl_set_rfreg(hw, RF90_PATH_A, 0x65, BRFREGOFFSETMASK, 0x931d6);
3673 rtl_set_rfreg(hw, RF90_PATH_A, 0xef, BRFREGOFFSETMASK, 0x00000);
3674 }
3675 if (tx1_finish){
3676 /*====== Path B RX IQK RF Setting======*/
3677 rtl_set_rfreg(hw, RF90_PATH_B, 0xef, BRFREGOFFSETMASK, 0x80000);
3678 rtl_set_rfreg(hw, RF90_PATH_B, 0x30, BRFREGOFFSETMASK, 0x30000);
3679 rtl_set_rfreg(hw, RF90_PATH_B, 0x31, BRFREGOFFSETMASK, 0x3f7ff);
3680 rtl_set_rfreg(hw, RF90_PATH_B, 0x32, BRFREGOFFSETMASK, 0xfe7bf);
3681 rtl_set_rfreg(hw, RF90_PATH_B, 0x8f, BRFREGOFFSETMASK, 0x88001);
3682 rtl_set_rfreg(hw, RF90_PATH_B, 0x65, BRFREGOFFSETMASK, 0x931d1);
3683 rtl_set_rfreg(hw, RF90_PATH_B, 0xef, BRFREGOFFSETMASK, 0x00000);
3684 }
3685 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
3686 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
3687 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
3688 rtl_write_dword(rtlpriv, 0x984, 0x0046a890);
3689
3690 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 1 --> Page C1*/
3691 if (tx0_finish) {
3692 rtl_write_dword(rtlpriv, 0xc80, 0x38008c10);/*TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16*/
3693 rtl_write_dword(rtlpriv, 0xc84, 0x18008c10);/*RX_Tone_idx[9:0], RxK_Mask[29]*/
3694 rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
3695 rtl_write_dword(rtlpriv, 0xc8c, 0x28160cc0);
3696 }
3697 if (tx1_finish){
3698 rtl_write_dword(rtlpriv, 0xe80, 0x38008c10);/*TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16*/
3699 rtl_write_dword(rtlpriv, 0xe84, 0x18008c10);/*RX_Tone_idx[9:0], RxK_Mask[29]*/
3700 rtl_write_dword(rtlpriv, 0xe88, 0x02140119);
3701 rtl_write_dword(rtlpriv, 0xe8c, 0x28160ca0);
3702 }
3703 cal0_retry = 0;
3704 cal1_retry = 0;
3705 while(1){
3706 /* one shot*/
3707 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3708 if (tx0_finish){
3709 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0[rx0_average % 2]) >> 21 & 0x000007ff);
3710 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0[rx0_average % 2]) >> 21 & 0x000007ff);
3711 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1*/
3712 rtl_write_dword(rtlpriv, 0xcb8, 0x00300000);/*cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module*/
3713 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);
3714 mdelay(5); /*Delay 10ms*/
3715 }
3716 if (tx1_finish){
3717 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3718 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x1[rx1_average % 2]) >> 21 & 0x000007ff);
3719 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y1[rx1_average % 2]) >> 21 & 0x000007ff);
3720 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 1 --> Page C1*/
3721 rtl_write_dword(rtlpriv, 0xeb8, 0x00300000);/*cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module*/
3722 rtl_write_dword(rtlpriv, 0xeb8, 0x00100000);/* cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module*/
3723 }
3724 mdelay(10); /*Delay 10ms*/
3725 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
3726 rtl_write_dword(rtlpriv, 0xeb8, 0x00000000);
3727 delay_count = 0;
3728 while (1){
3729 if (!rx0_finish && tx0_finish)
3730 iqk0_ready = (bool) rtl_get_bbreg(hw, 0xd00, BIT(10));
3731 if (!rx1_finish && tx1_finish)
3732 iqk1_ready = (bool) rtl_get_bbreg(hw, 0xd40, BIT(10));
3733 if ((iqk0_ready && iqk1_ready)||(delay_count>20))
3734 break;
3735 else{
3736 mdelay(1);
3737 delay_count++;
3738 }
3739 }
3740 RT_TRACE(COMP_IQK, DBG_LOUD,
3741 ("RX delay_count = %d\n", delay_count));
3742 if (delay_count < 20){ // If 20ms No Result, then cal_retry++
3743 // ============RXIQK Check==============
3744 rx0_fail = (bool) rtl_get_bbreg(hw, 0xd00, BIT(11));
3745 rx1_fail = (bool) rtl_get_bbreg(hw, 0xd40, BIT(11));
3746 if (!(rx0_fail || rx0_finish) && tx0_finish){
3747 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
3748 rx_x0[rx0_average] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000) << 21;
3749 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
3750 rx_y0[rx0_average] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000) << 21;
3751 rx0iqkok= true;
3752 RT_TRACE(COMP_IQK, DBG_LOUD,
3753 ("RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n",
3754 rx0_average, (rx_x0[rx0_average]) >> 21 & 0x000007ff,
3755 rx0_average, (rx_y0[rx0_average]) >> 21 & 0x000007ff));
3756
3757 rx0_average++;
3758 }
3759 else{
3760 RT_TRACE(COMP_IQK, DBG_LOUD,
3761 ("1. RXA_cal_retry = %d\n", cal0_retry));
3762 rx0iqkok = false;
3763 cal0_retry++;
3764 if (cal0_retry == 10)
3765 break;
3766 }
3767 if (!(rx1_fail || rx1_finish) && tx1_finish){
3768 rtl_write_dword(rtlpriv, 0xeb8, 0x06000000);
3769 rx_x1[rx1_average] = rtl_get_bbreg(hw, 0xd40, 0x07ff0000) << 21;
3770 rtl_write_dword(rtlpriv, 0xeb8, 0x08000000);
3771 rx_y1[rx1_average] = rtl_get_bbreg(hw, 0xd40, 0x07ff0000) << 21;
3772 rx1iqkok = true;
3773 RT_TRACE(COMP_IQK, DBG_LOUD,
3774 ("RX_X1[%d] = %x ;; RX_Y1[%d] = %x\n",
3775 rx1_average, (rx_x1[rx1_average]) >> 21 & 0x000007ff,
3776 rx1_average, (rx_y1[rx1_average]) >> 21 & 0x000007ff));
3777
3778 rx1_average++;
3779 }
3780 else{
3781 rx1iqkok= false;
3782 cal1_retry++;
3783 if (cal1_retry == 10)
3784 break;
3785 }
3786
3787 }
3788 else{
3789 RT_TRACE(COMP_IQK, DBG_LOUD,
3790 ("2. RXA_cal_retry = %d\n", cal0_retry));
3791 rx0iqkok = false;
3792 rx1iqkok = false;
3793 cal0_retry++;
3794 cal1_retry++;
3795 RT_TRACE(COMP_IQK, DBG_LOUD,
3796 ("Delay 20ms RX IQK Not Ready!!!!!\n"));
3797 if (cal0_retry == 10)
3798 break;
3799 }
3800 RT_TRACE(COMP_IQK, DBG_LOUD,
3801 ("3. RXA_cal_retry = %d\n", cal0_retry));
3802 if (rx0_average >= 2){
3803 for (i = 0; i < rx0_average; i++){
3804 for (ii = i+1; ii < rx0_average; ii++){
3805 dx = (rx_x0[i] >> 21) - (rx_x0[ii] >> 21);
3806 if (dx < 4 && dx > -4){
3807 dy = (rx_y0[i] >> 21) - (rx_y0[ii] >> 21);
3808 if (dy < 4 && dy > -4){
3809 rx0_x = ((rx_x0[i]>>21) + (rx_x0[ii] >> 21)) / 2;
3810 rx0_y = ((rx_y0[i]>>21) + (rx_y0[ii] >> 21)) / 2;
3811 if ((rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3812 && vdf_enable) {
3813 rx_dt[0] = (rx_dt[i] + rx_dt[ii]) / 2;
3814 }
3815 rx0_finish = true;
3816 break;
3817 }
3818 }
3819 }
3820 }
3821 }
3822 if (rx1_average >= 2){
3823 for (i = 0; i < rx1_average; i++){
3824 for (ii = i+1; ii < rx1_average; ii++){
3825 dx = (rx_x1[i] >> 21) - (rx_x1[ii] >> 21);
3826 if (dx < 4 && dx > -4){
3827 dy = (rx_y1[i] >> 21) - (rx_y1[ii] >> 21);
3828 if (dy < 4 && dy > -4){
3829 rx1_x = ((rx_x1[i] >> 21) + (rx_x1[ii] >> 21)) / 2;
3830 rx1_y = ((rx_y1[i] >> 21) + (rx_y1[ii] >> 21)) / 2;
3831 if ((rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3832 && vdf_enable) {
3833 rx_dt[0] = (rx_dt[i] + rx_dt[ii]) / 2;
3834 }
3835 rx1_finish = true;
3836 break;
3837 }
3838 }
3839 }
3840 }
3841 }
3842 RT_TRACE(COMP_IQK, DBG_LOUD,
3843 ("RX0_Average = %d, RX1_Average = %d\n",
3844 rx0_average, rx1_average));
3845 RT_TRACE(COMP_IQK, DBG_LOUD,
3846 ("RX0_finish = %d, RX1_finish = %d\n",
3847 rx0_finish, rx1_finish));
3848 if ((rx0_finish|| !tx0_finish) && (rx1_finish || !tx1_finish) )
3849 break;
3850 if ((cal0_retry + rx0_average) >= 10
3851 || (cal1_retry + rx1_average) >= 10
3852 || rx0_average == 3
3853 || rx1_average == 3)
3854 break;
3855 }
3856 RT_TRACE(COMP_IQK, DBG_LOUD,
3857 ("RXA_cal_retry = %d\n", cal0_retry));
3858 RT_TRACE(COMP_IQK, DBG_LOUD,
3859 ("RXB_cal_retry = %d\n", cal1_retry));
3860 }
3861 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
3862 switch (rtlphy->current_chan_bw)
3863 {
3864 case HT_CHANNEL_WIDTH_20_40:
3865 {
3866 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, 0x00c00, 0x1);
3867 }
3868 break;
3869 case HT_CHANNEL_WIDTH_80:
3870 {
3871 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, 0x00c00, 0x0);
3872 }
3873 break;
3874 default:
3875 break;
3876
3877 }
3878
3879 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 0 --> Page C*/
3880 /*FillIQK Result*/
3881 RT_TRACE(COMP_IQK, DBG_LOUD,
3882 ("========Path_A =======\n"));
3883
3884 if (tx0_finish){
3885 _rtl8812ae_iqk_tx_fill_iqc(hw, RF90_PATH_A, tx0_x, tx0_y);
3886 }
3887 else{
3888 _rtl8812ae_iqk_tx_fill_iqc(hw, RF90_PATH_A, 0x200, 0x0);
3889 }
3890
3891 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80
3892 || vdf_enable){
3893 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 0 --> Page C*/
3894 rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[0] & 0x00003fff);
3895 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3896 }
3897
3898 if (rx0_finish == 1){
3899 _rtl8812ae_iqk_rx_fill_iqc(hw, RF90_PATH_A, rx0_x, rx0_y);
3900 }
3901 else{
3902 _rtl8812ae_iqk_rx_fill_iqc(hw, RF90_PATH_A, 0x200, 0x0);
3903 }
3904
3905 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80
3906 || vdf_enable){
3907 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /*[31] = 0 --> Page C*/
3908 rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[0] & 0x00003fff);
3909 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
3910 }
3911
3912 RT_TRACE(COMP_IQK, DBG_LOUD,
3913 ("========Path_B =======\n"));
3914
3915 if (tx1_finish){
3916 _rtl8812ae_iqk_tx_fill_iqc(hw, RF90_PATH_B, tx1_x, tx1_y);
3917 }
3918 else{
3919 _rtl8812ae_iqk_tx_fill_iqc(hw, RF90_PATH_B, 0x200, 0x0);
3920 }
3921
3922 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80
3923 || vdf_enable){
3924 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 0 --> Page C*/
3925 rtl_set_bbreg(hw, 0xee8, 0x3fff0000, tx_dt[0] & 0x00003fff);
3926 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
3927 }
3928
3929 if (rx1_finish == 1){
3930 _rtl8812ae_iqk_rx_fill_iqc(hw, RF90_PATH_B, rx1_x, rx1_y);
3931 }
3932 else{
3933 _rtl8812ae_iqk_rx_fill_iqc(hw, RF90_PATH_B, 0x200, 0x0);
3934 }
3935
3936 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80
3937 || vdf_enable){
3938 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 0 --> Page C*/
3939 rtl_set_bbreg(hw, 0xee8, 0x00003fff, rx_dt[0] & 0x00003fff);
3940 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
3941 }
3942}
3943
3944void _rtl8812ae_iqk_restore_rf(
3945 struct ieee80211_hw *hw,
3946 enum radio_path path,
3947 u32 *backup_rf_reg,
3948 u32 *rf_backup,
3949 u32 rf_reg_num
3950 )
3951{
3952 struct rtl_priv *rtlpriv = rtl_priv(hw);
3953 u32 i;
3954
3955 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3956 for (i = 0; i < rf_reg_num; i++)
3957 rtl_set_rfreg(hw, path, backup_rf_reg[i], BRFREGOFFSETMASK, rf_backup[i]);
3958
3959 rtl_set_rfreg(hw, path, 0xef, BRFREGOFFSETMASK, 0x0);
3960
3961 switch(path){
3962 case RF90_PATH_A:
3963 {
3964 RT_TRACE(COMP_IQK, DBG_LOUD,
3965 ("RestoreRF Path A Success!!!!\n"));
3966 }
3967 break;
3968 case RF90_PATH_B:
3969 {
3970 RT_TRACE(COMP_IQK, DBG_LOUD,
3971 ("RestoreRF Path B Success!!!!\n"));
3972 }
3973 break;
3974 default:
3975 break;
3976 }
3977}
3978
3979void _rtl8812ae_iqk_restore_afe(
3980 struct ieee80211_hw *hw,
3981 u32 *afe_backup,
3982 u32 *backup_afe_reg,
3983 u32 afe_num
3984 )
3985{
3986 struct rtl_priv *rtlpriv = rtl_priv(hw);
3987 u32 i;
3988 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
3989 /*Reload AFE Parameters */
3990 for (i = 0; i < afe_num; i++){
3991 rtl_write_dword(rtlpriv, backup_afe_reg[i], afe_backup[i]);
3992 }
3993 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1*/
3994 rtl_write_dword(rtlpriv, 0xc80, 0x0);
3995 rtl_write_dword(rtlpriv, 0xc84, 0x0);
3996 rtl_write_dword(rtlpriv, 0xc88, 0x0);
3997 rtl_write_dword(rtlpriv, 0xc8c, 0x3c000000);
3998 rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
3999 rtl_write_dword(rtlpriv, 0xc94, 0x00000000);
4000 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
4001 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
4002 rtl_write_dword(rtlpriv, 0xcb8, 0x0);
4003 rtl_write_dword(rtlpriv, 0xe80, 0x0);
4004 rtl_write_dword(rtlpriv, 0xe84, 0x0);
4005 rtl_write_dword(rtlpriv, 0xe88, 0x0);
4006 rtl_write_dword(rtlpriv, 0xe8c, 0x3c000000);
4007 rtl_write_dword(rtlpriv, 0xe90, 0x00000080);
4008 rtl_write_dword(rtlpriv, 0xe94, 0x00000000);
4009 rtl_write_dword(rtlpriv, 0xec4, 0x20040000);
4010 rtl_write_dword(rtlpriv, 0xec8, 0x20000000);
4011 rtl_write_dword(rtlpriv, 0xeb8, 0x0);
4012 RT_TRACE(COMP_IQK, DBG_LOUD,
4013 ("RestoreAFE Success!!!!\n"));
4014}
4015
4016void _rtl8812ae_iqk_restore_macbb(
4017 struct ieee80211_hw *hw,
4018 u32 *macbb_backup,
4019 u32 *backup_macbb_reg,
4020 u32 macbb_num
4021 )
4022{
4023 struct rtl_priv *rtlpriv = rtl_priv(hw);
4024 u32 i;
4025 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C*/
4026 //Reload MacBB Parameters
4027 for (i = 0; i < macbb_num; i++){
4028 rtl_write_dword(rtlpriv, backup_macbb_reg[i], macbb_backup[i]);
4029 }
4030 RT_TRACE(COMP_IQK, DBG_LOUD,
4031 ("RestoreMacBB Success!!!!\n"));
4032}
4033
4034#define MACBB_REG_NUM 10
4035#define AFE_REG_NUM 14
4036#define RF_REG_NUM 3
4037
4038static void _rtl8812ae_phy_iq_calibrate(
4039 struct ieee80211_hw *hw,
4040 u8 channel)
4041{
4042 u32 macbb_backup[MACBB_REG_NUM];
4043 u32 afe_backup[AFE_REG_NUM];
4044 u32 rfa_backup[RF_REG_NUM];
4045 u32 rfb_backup[RF_REG_NUM];
4046 u32 backup_macbb_reg[MACBB_REG_NUM] = {0xb00, 0x520, 0x550,
4047 0x808, 0x90c, 0xc00, 0xe00,
4048 0x8c4,0x838, 0x82c};
4049 u32 backup_afe_reg[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68,
4050 0xcb8, 0xcb0, 0xcb4,0xe5c,
4051 0xe60, 0xe64, 0xe68, 0xeb8,
4052 0xeb0, 0xeb4};
4053 u32 backup_rf_reg[RF_REG_NUM] = {0x65, 0x8f, 0x0};
4054 u8 chnl_idx = _rtl8812ae_get_right_chnl_place_for_iqk(channel);
4055
4056 _rtl8812ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg, MACBB_REG_NUM);
4057 _rtl8812ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4058 _rtl8812ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg, RF_REG_NUM);
4059
4060 _rtl8812ae_iqk_configure_mac(hw);
4061 _rtl8812ae_iqk_tx(hw, chnl_idx);
4062 _rtl8812ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup, RF_REG_NUM);
4063 _rtl8812ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfb_backup, RF_REG_NUM); // PATH_A ?
4064
4065 _rtl8812ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
4066 _rtl8812ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg, MACBB_REG_NUM);
4067}
4068
4069
4070void _rtl8821ae_iqk_backup_macbb(
4071 struct ieee80211_hw *hw,
4072 u32 *macbb_backup,
4073 u32 *backup_macbb_reg,
4074 u32 mac_bb_num
4075 )
4076{
4077 struct rtl_priv *rtlpriv = rtl_priv(hw);
4078 u32 i;
4079
4080 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
4081 /*save MACBB default value*/
4082 for (i = 0; i < mac_bb_num; i++) {
4083 macbb_backup[i] =rtl_read_dword(rtlpriv,backup_macbb_reg[i]);
4084 }
4085
4086 RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupMacBB Success!!!!\n"));
4087}
4088
4089void _rtl8821ae_iqk_backup_afe(
4090 struct ieee80211_hw *hw,
4091 u32 *afe_backup,
4092 u32 *backup_afe_REG,
4093 u32 afe_num
4094 )
4095{
4096 struct rtl_priv *rtlpriv = rtl_priv(hw);
4097 u32 i;
4098
4099 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
4100 /*Save AFE Parameters */
4101 for (i = 0; i < afe_num; i++){
4102 afe_backup[i] = rtl_read_dword(rtlpriv, backup_afe_REG[i]);
4103 }
4104 RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupAFE Success!!!!\n"));
4105}
4106
4107void _rtl8821ae_iqk_backup_rf(
4108 struct ieee80211_hw *hw,
4109 u32 *rfa_backup,
4110 u32 *rfb_backup,
4111 u32 *backup_rf_reg,
4112 u32 rf_num
4113 )
4114{
4115
4116 struct rtl_priv *rtlpriv = rtl_priv(hw);
4117 u32 i;
4118
4119 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
4120 /*Save RF Parameters*/
4121 for (i = 0; i < rf_num; i++){
4122 rfa_backup[i] = rtl_get_rfreg(hw, RF90_PATH_A, backup_rf_reg[i], BMASKDWORD);
4123 rfb_backup[i] = rtl_get_rfreg(hw, RF90_PATH_B, backup_rf_reg[i], BMASKDWORD);
4124 }
4125 RT_TRACE(COMP_IQK, DBG_LOUD, ("BackupRF Success!!!!\n"));
4126}
4127
4128void _rtl8821ae_iqk_configure_mac(
4129 struct ieee80211_hw *hw
4130 )
4131{
4132 struct rtl_priv *rtlpriv = rtl_priv(hw);
4133 /* ========MAC register setting========*/
4134 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
4135 rtl_write_byte(rtlpriv, 0x522, 0x3f);
4136 rtl_set_bbreg(hw, 0x550, BIT(11) | BIT(3), 0x0);
4137 rtl_write_byte(rtlpriv, 0x808, 0x00); /*RX ante off*/
4138 rtl_set_bbreg(hw, 0x838, 0xf, 0xc); /*CCA off*/
4139}
4140
4141
4142void _rtl8821ae_iqk_tx_fill_iqc(
4143 struct ieee80211_hw *hw,
4144 enum radio_path path,
4145 u32 tx_x,
4146 u32 tx_y
4147 )
4148{
4149 struct rtl_priv *rtlpriv = rtl_priv(hw);
4150 switch (path) {
4151 case RF90_PATH_A:
4152 {
4153 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4154 rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
4155 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
4156 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
4157 rtl_set_bbreg(hw, 0xccc, 0x000007ff, tx_y);
4158 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, tx_x);
4159 RT_TRACE(COMP_IQK, DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", tx_x, tx_y));
4160 RT_TRACE(COMP_IQK, DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", rtl_get_bbreg(hw, 0xcd4, 0x000007ff), rtl_get_bbreg(hw, 0xccc, 0x000007ff)));
4161 }
4162 break;
4163 default:
4164 break;
4165 };
4166}
4167
4168
4169void _rtl8821ae_iqk_rx_fill_iqc(
4170 struct ieee80211_hw *hw,
4171 enum radio_path path,
4172 u32 rx_x,
4173 u32 rx_y
4174 )
4175{
4176 struct rtl_priv *rtlpriv = rtl_priv(hw);
4177 switch (path) {
4178 case RF90_PATH_A:
4179 {
4180 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4181 rtl_set_bbreg(hw, 0xc10, 0x000003ff, rx_x>>1);
4182 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, rx_y>>1);
4183 RT_TRACE(COMP_IQK, DBG_LOUD, ("rx_x = %x;;rx_y = %x ====>fill to IQC\n", rx_x>>1, rx_y>>1));
4184 RT_TRACE(COMP_IQK, DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", rtl_read_dword(rtlpriv, 0xc10)));
4185 }
4186 break;
4187 default:
4188 break;
4189 };
4190}
4191
4192
4193
4194#define cal_num 10
4195
4196void _rtl8821ae_iqk_tx(
4197 struct ieee80211_hw *hw,
4198 enum radio_path path
4199 )
4200{
4201 struct rtl_priv *rtlpriv = rtl_priv(hw);
4202 struct rtl_phy *rtlphy = &(rtlpriv->phy);
4203 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
4204
4205 u32 tx_fail, rx_fail, delay_count, iqk_ready, cal_retry, cal = 0, temp_reg65;
4206 int tx_x = 0, tx_y = 0, rx_x = 0, rx_y = 0, tx_average = 0, rx_average = 0;
4207 int tx_x0[cal_num], tx_y0[cal_num], tx_x0_rxk[cal_num], tx_y0_rxk[cal_num], rx_x0[cal_num], rx_y0[cal_num];
4208 bool tx0iqkok = false, rx0iqkok = false;
4209 bool vdf_enable = false;
4210 int i, k, vdf_y[3], vdf_x[3], tx_dt[3], rx_dt[3], ii, dx = 0, dy = 0, tx_finish = 0, rx_finish = 0;
4211
4212
4213 RT_TRACE(COMP_IQK, DBG_LOUD,
4214 ("BandWidth = %d.\n",
4215 rtlphy->current_chan_bw));
4216 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80){
4217 vdf_enable = true;
4218 }
4219
4220 while (cal < cal_num) {
4221 switch (path) {
4222 case RF90_PATH_A:
4223 {
4224 temp_reg65 = rtl_get_rfreg(hw, path, 0x65, 0xffffffff);
4225 //Path-A LOK
4226 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); /*[31] = 0 --> Page C*/
4227 /*========Path-A AFE all on========*/
4228 /*Port 0 DAC/ADC on*/
4229 rtl_write_dword(rtlpriv, 0xc60, 0x77777777);
4230 rtl_write_dword(rtlpriv, 0xc64, 0x77777777);
4231 rtl_write_dword(rtlpriv, 0xc68, 0x19791979);
4232 rtl_write_dword(rtlpriv, 0xc6c, 0x19791979);
4233 rtl_write_dword(rtlpriv, 0xc70, 0x19791979);
4234 rtl_write_dword(rtlpriv, 0xc74, 0x19791979);
4235 rtl_write_dword(rtlpriv, 0xc78, 0x19791979);
4236 rtl_write_dword(rtlpriv, 0xc7c, 0x19791979);
4237 rtl_write_dword(rtlpriv, 0xc80, 0x19791979);
4238 rtl_write_dword(rtlpriv, 0xc84, 0x19791979);
4239
4240 rtl_set_bbreg(hw, 0xc00, 0xf, 0x4); /*hardware 3-wire off*/
4241
4242 // LOK Setting
4243 //====== LOK ======
4244 /*DAC/ADC sampling rate (160 MHz)*/
4245 rtl_set_bbreg(hw, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
4246
4247 // 2. LoK RF Setting (at BW = 20M)
4248 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80002);
4249 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x3); // BW 20M
4250 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
4251 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
4252 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
4253 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
4254 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4255 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
4256 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4257 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4258 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
4259 rtl_write_dword(rtlpriv, 0x978, 0x29002000);// TX (X,Y)
4260 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);// RX (X,Y)
4261 rtl_write_dword(rtlpriv, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask
4262
4263 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4264 rtl_write_dword(rtlpriv, 0xc88, 0x821403f4);
4265
4266 if (rtlhal->current_bandtype)
4267 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
4268 else
4269 rtl_write_dword(rtlpriv, 0xc8c, 0x28163e96);
4270
4271 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4272 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
4273 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module
4274 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4275 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4276
4277 mdelay(10); //Delay 10ms
4278 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4279
4280 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4281 rtl_set_rfreg(hw, path, 0x58, 0x7fe00, rtl_get_rfreg(hw, path, 0x8, 0xffc00)); // Load LOK
4282
4283 switch (rtlphy->current_chan_bw)
4284 {
4285 case 1:
4286 {
4287 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x1);
4288 }
4289 break;
4290 case 2:
4291 {
4292 rtl_set_rfreg(hw, path, 0x18, 0x00c00, 0x0);
4293 }
4294 break;
4295 default:
4296 break;
4297
4298 }
4299
4300 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4301
4302 // 3. TX RF Setting
4303 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4304 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4305 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x20000);
4306 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0003f);
4307 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xf3fc3);
4308 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d5);
4309 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4310 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4311 //ODM_SetBBReg(pDM_Odm, 0xcb8, 0xf, 0xd);
4312 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4313 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4314 rtl_set_bbreg(hw, 0xc94, BIT(0), 0x1);
4315 rtl_write_dword(rtlpriv, 0x978, 0x29002000);// TX (X,Y)
4316 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);// RX (X,Y)
4317 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask
4318
4319 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4320 rtl_write_dword(rtlpriv, 0xc88, 0x821403f1);
4321 if (rtlhal->current_bandtype)
4322 rtl_write_dword(rtlpriv, 0xc8c, 0x40163e96);
4323 else
4324 rtl_write_dword(rtlpriv, 0xc8c, 0x00163e96);
4325
4326 if (vdf_enable == 1){
4327 RT_TRACE(COMP_IQK, DBG_LOUD, ("VDF_enable\n"));
4328 for (k = 0;k <= 2; k++){
4329 switch (k){
4330 case 0:
4331 {
4332 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4333 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29]
4334 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
4335 }
4336 break;
4337 case 1:
4338 {
4339 rtl_set_bbreg(hw, 0xc80, BIT(28), 0x0);
4340 rtl_set_bbreg(hw, 0xc84, BIT(28), 0x0);
4341 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0);
4342 }
4343 break;
4344 case 2:
4345 {
4346 RT_TRACE(COMP_IQK, DBG_LOUD, ("vdf_y[1] = %x;;;vdf_y[0] = %x\n", vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff));
4347 RT_TRACE(COMP_IQK, DBG_LOUD, ("vdf_x[1] = %x;;;vdf_x[0] = %x\n", vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff));
4348 tx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
4349 tx_dt[cal] = ((16*tx_dt[cal])*10000/15708);
4350 tx_dt[cal] = (tx_dt[cal] >> 1 )+(tx_dt[cal] & BIT(0));
4351 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4352 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29]
4353 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1);
4354 rtl_set_bbreg(hw, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff);
4355 }
4356 break;
4357 default:
4358 break;
4359 }
4360 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module
4361 cal_retry = 0;
4362 while(1){
4363 // one shot
4364 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4365 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4366
4367 mdelay(10); //Delay 10ms
4368 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4369 delay_count = 0;
4370 while (1){
4371 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4372 if ((~iqk_ready) || (delay_count>20)){
4373 break;
4374 }
4375 else{
4376 mdelay(1);
4377 delay_count++;
4378 }
4379 }
4380
4381 if (delay_count < 20){ // If 20ms No Result, then cal_retry++
4382 // ============TXIQK Check==============
4383 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4384
4385 if (~tx_fail){
4386 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4387 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4388 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4389 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4390 tx0iqkok = true;
4391 break;
4392 }
4393 else{
4394 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
4395 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
4396 tx0iqkok = false;
4397 cal_retry++;
4398 if (cal_retry == 10) {
4399 break;
4400 }
4401 }
4402 }
4403 else{
4404 tx0iqkok = false;
4405 cal_retry++;
4406 if (cal_retry == 10){
4407 break;
4408 }
4409 }
4410 }
4411 }
4412 if (k == 3){
4413 tx_x0[cal] = vdf_x[k-1] ;
4414 tx_y0[cal] = vdf_y[k-1];
4415 }
4416 }
4417
4418 else {
4419 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4420 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
4421 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module
4422 cal_retry = 0;
4423 while(1){
4424 // one shot
4425 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4426 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4427
4428 mdelay(10); //Delay 10ms
4429 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4430 delay_count = 0;
4431 while (1){
4432 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4433 if ((~iqk_ready) || (delay_count>20)) {
4434 break;
4435 }
4436 else{
4437 mdelay(1);
4438 delay_count++;
4439 }
4440 }
4441
4442 if (delay_count < 20){ // If 20ms No Result, then cal_retry++
4443 // ============TXIQK Check==============
4444 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4445
4446 if (~tx_fail){
4447 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4448 tx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4449 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4450 tx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4451 tx0iqkok = true;
4452 break;
4453 }
4454 else{
4455 rtl_set_bbreg(hw, 0xccc, 0x000007ff, 0x0);
4456 rtl_set_bbreg(hw, 0xcd4, 0x000007ff, 0x200);
4457 tx0iqkok = false;
4458 cal_retry++;
4459 if (cal_retry == 10) {
4460 break;
4461 }
4462 }
4463 }
4464 else{
4465 tx0iqkok = false;
4466 cal_retry++;
4467 if (cal_retry == 10)
4468 break;
4469 }
4470 }
4471 }
4472
4473
4474 if (tx0iqkok == false)
4475 break; // TXK fail, Don't do RXK
4476
4477 if (vdf_enable == 1){
4478 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x0); // TX VDF Disable
4479 RT_TRACE(COMP_IQK, DBG_LOUD, ("RXVDF Start\n"));
4480 for (k = 0;k <= 2; k++){
4481 //====== RX mode TXK (RXK Step 1) ======
4482 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4483 // 1. TX RF Setting
4484 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4485 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4486 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
4487 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
4488 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4489 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4490 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4491
4492 rtl_set_bbreg(hw, 0xcb8, 0xf, 0xd);
4493 rtl_write_dword(rtlpriv, 0x978, 0x29002000);// TX (X,Y)
4494 rtl_write_dword(rtlpriv, 0x97c, 0xa9002000);// RX (X,Y)
4495 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask
4496 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4497 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4498 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4499 switch (k){
4500 case 0:
4501 {
4502 rtl_write_dword(rtlpriv, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4503 rtl_write_dword(rtlpriv, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29]
4504 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4505 }
4506 break;
4507 case 1:
4508 {
4509 rtl_write_dword(rtlpriv, 0xc80, 0x08008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4510 rtl_write_dword(rtlpriv, 0xc84, 0x28008c38);// RX_Tone_idx[9:0], RxK_Mask[29]
4511 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x0);
4512 }
4513 break;
4514 case 2:
4515 {
4516 RT_TRACE(COMP_IQK, DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", vdf_y[1]>>21 & 0x00007ff, vdf_y[0]>>21 & 0x00007ff));
4517 RT_TRACE(COMP_IQK, DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", vdf_x[1]>>21 & 0x00007ff, vdf_x[0]>>21 & 0x00007ff));
4518 rx_dt[cal] = (vdf_y[1]>>20)-(vdf_y[0]>>20);
4519 RT_TRACE(COMP_IQK, DBG_LOUD, ("Rx_dt = %d\n", rx_dt[cal]));
4520 rx_dt[cal] = ((16*rx_dt[cal])*10000/13823);
4521 rx_dt[cal] = (rx_dt[cal] >> 1 )+(rx_dt[cal] & BIT(0));
4522 rtl_write_dword(rtlpriv, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4523 rtl_write_dword(rtlpriv, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29]
4524 rtl_set_bbreg(hw, 0xce8, 0x00003fff, rx_dt[cal] & 0x00003fff);
4525 }
4526 break;
4527 default:
4528 break;
4529 }
4530 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4531 rtl_write_dword(rtlpriv, 0xc8c, 0x68163e96);
4532 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module
4533 cal_retry = 0;
4534 while(1){
4535 // one shot
4536 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4537 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4538
4539 mdelay(10); //Delay 10ms
4540 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4541 delay_count = 0;
4542 while (1){
4543 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4544 if ((~iqk_ready)||(delay_count>20)){
4545 break;
4546 }
4547 else{
4548 mdelay(1);
4549 delay_count++;
4550 }
4551 }
4552
4553 if (delay_count < 20){ // If 20ms No Result, then cal_retry++
4554 // ============TXIQK Check==============
4555 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4556
4557 if (~tx_fail){
4558 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4559 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4560 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4561 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4562 tx0iqkok = true;
4563 break;
4564 }
4565 else{
4566 tx0iqkok = false;
4567 cal_retry++;
4568 if (cal_retry == 10)
4569 break;
4570 }
4571 }
4572 else{
4573 tx0iqkok = false;
4574 cal_retry++;
4575 if (cal_retry == 10)
4576 break;
4577 }
4578 }
4579
4580 if (tx0iqkok == false){ //If RX mode TXK fail, then take TXK Result
4581 tx_x0_rxk[cal] = tx_x0[cal];
4582 tx_y0_rxk[cal] = tx_y0[cal];
4583 tx0iqkok = true;
4584 RT_TRACE(COMP_IQK, DBG_LOUD, ("RXK Step 1 fail\n"));
4585 }
4586
4587
4588 //====== RX IQK ======
4589 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4590 // 1. RX RF Setting
4591 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4592 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4593 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4594 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4595 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4596 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4597 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4598
4599 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4600 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4601 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4602 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4603 rtl_set_bbreg(hw, 0xcb8, 0xF, 0xe);
4604 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4605 rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4606
4607 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4608 rtl_set_bbreg(hw, 0xc80, BIT(29), 0x1);
4609 rtl_set_bbreg(hw, 0xc84, BIT(29), 0x0);
4610 rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4611
4612 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /* pDM_Odm->SupportInterface == 1 */
4613
4614 if (k==2){
4615 rtl_set_bbreg(hw, 0xce8, BIT(30), 0x1); //RX VDF Enable
4616 }
4617 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module
4618
4619 cal_retry = 0;
4620 while(1){
4621 // one shot
4622 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4623 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4624
4625 mdelay(10); //Delay 10ms
4626 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4627 delay_count = 0;
4628 while (1){
4629 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4630 if ((~iqk_ready)||(delay_count>20)){
4631 break;
4632 }
4633 else{
4634 mdelay(1);
4635 delay_count++;
4636 }
4637 }
4638
4639 if (delay_count < 20){ // If 20ms No Result, then cal_retry++
4640 // ============RXIQK Check==============
4641 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4642 if (rx_fail == 0){
4643 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4644 vdf_x[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4645 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4646 vdf_y[k] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4647 rx0iqkok = true;
4648 break;
4649 }
4650 else{
4651 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4652 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4653 rx0iqkok = false;
4654 cal_retry++;
4655 if (cal_retry == 10)
4656 break;
4657
4658 }
4659 }
4660 else{
4661 rx0iqkok = false;
4662 cal_retry++;
4663 if (cal_retry == 10)
4664 break;
4665 }
4666 }
4667
4668 }
4669 if (k == 3){
4670 rx_x0[cal] = vdf_x[k-1] ;
4671 rx_y0[cal] = vdf_y[k-1];
4672 }
4673 rtl_set_bbreg(hw, 0xce8, BIT(31), 0x1); // TX VDF Enable
4674 }
4675
4676 else{
4677 //====== RX mode TXK (RXK Step 1) ======
4678 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4679 // 1. TX RF Setting
4680 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4681 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4682 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x00029);
4683 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xd7ffb);
4684 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4685 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x8a001);
4686 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4687 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4688 rtl_write_dword(rtlpriv, 0xb00, 0x03000100);
4689 rtl_write_dword(rtlpriv, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask
4690
4691 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4692 rtl_write_dword(rtlpriv, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4693 rtl_write_dword(rtlpriv, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
4694 rtl_write_dword(rtlpriv, 0xc88, 0x821603e0);
4695 //ODM_Write4Byte(pDM_Odm, 0xc8c, 0x68163e96);
4696 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module
4697 cal_retry = 0;
4698 while(1){
4699 // one shot
4700 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4701 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4702
4703 mdelay(10); //Delay 10ms
4704 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4705 delay_count = 0;
4706 while (1){
4707 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4708 if ((~iqk_ready)||(delay_count>20)){
4709 break;
4710 }
4711 else{
4712 mdelay(1);
4713 delay_count++;
4714 }
4715 }
4716
4717 if (delay_count < 20){ // If 20ms No Result, then cal_retry++
4718 // ============TXIQK Check==============
4719 tx_fail = rtl_get_bbreg(hw, 0xd00, BIT(12));
4720
4721 if (~tx_fail){
4722 rtl_write_dword(rtlpriv, 0xcb8, 0x02000000);
4723 tx_x0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4724 rtl_write_dword(rtlpriv, 0xcb8, 0x04000000);
4725 tx_y0_rxk[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4726 tx0iqkok = true;
4727 break;
4728 }
4729 else{
4730 tx0iqkok = false;
4731 cal_retry++;
4732 if (cal_retry == 10)
4733 break;
4734 }
4735 }
4736 else{
4737 tx0iqkok = false;
4738 cal_retry++;
4739 if (cal_retry == 10)
4740 break;
4741 }
4742 }
4743
4744
4745 if (tx0iqkok == false){ //If RX mode TXK fail, then take TXK Result
4746 tx_x0_rxk[cal] = tx_x0[cal];
4747 tx_y0_rxk[cal] = tx_y0[cal];
4748 tx0iqkok = true;
4749 RT_TRACE(COMP_IQK, DBG_LOUD, ("1"));
4750 }
4751
4752
4753 //====== RX IQK ======
4754 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4755 // 1. RX RF Setting
4756 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x80000);
4757 rtl_set_rfreg(hw, path, 0x30, RFREG_OFFSET_MASK, 0x30000);
4758 rtl_set_rfreg(hw, path, 0x31, RFREG_OFFSET_MASK, 0x0002f);
4759 rtl_set_rfreg(hw, path, 0x32, RFREG_OFFSET_MASK, 0xfffbb);
4760 rtl_set_rfreg(hw, path, 0x8f, RFREG_OFFSET_MASK, 0x88001);
4761 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, 0x931d8);
4762 rtl_set_rfreg(hw, path, 0xef, RFREG_OFFSET_MASK, 0x00000);
4763
4764 rtl_set_bbreg(hw, 0x978, 0x03FF8000, (tx_x0_rxk[cal])>>21&0x000007ff);
4765 rtl_set_bbreg(hw, 0x978, 0x000007FF, (tx_y0_rxk[cal])>>21&0x000007ff);
4766 rtl_set_bbreg(hw, 0x978, BIT(31), 0x1);
4767 rtl_set_bbreg(hw, 0x97c, BIT(31), 0x0);
4768 //ODM_SetBBReg(pDM_Odm, 0xcb8, 0xF, 0xe);
4769 rtl_write_dword(rtlpriv, 0x90c, 0x00008000);
4770 rtl_write_dword(rtlpriv, 0x984, 0x0046a911);
4771
4772 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4773 rtl_write_dword(rtlpriv, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
4774 rtl_write_dword(rtlpriv, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
4775 rtl_write_dword(rtlpriv, 0xc88, 0x02140119);
4776
4777 rtl_write_dword(rtlpriv, 0xc8c, 0x28160d00); /*pDM_Odm->SupportInterface == 1*/
4778
4779 rtl_write_dword(rtlpriv, 0xcb8, 0x00100000);// cb8[20] ±N SI/PI ¨Ï¥ÎÅv¤Áµ¹ iqk_dpk module
4780
4781 cal_retry = 0;
4782 while(1){
4783 // one shot
4784 rtl_write_dword(rtlpriv, 0x980, 0xfa000000);
4785 rtl_write_dword(rtlpriv, 0x980, 0xf8000000);
4786
4787 mdelay(10); //Delay 10ms
4788 rtl_write_dword(rtlpriv, 0xcb8, 0x00000000);
4789 delay_count = 0;
4790 while (1){
4791 iqk_ready = rtl_get_bbreg(hw, 0xd00, BIT(10));
4792 if ((~iqk_ready)||(delay_count>20)){
4793 break;
4794 }
4795 else{
4796 mdelay(1);
4797 delay_count++;
4798 }
4799 }
4800
4801 if (delay_count < 20){ // If 20ms No Result, then cal_retry++
4802 // ============RXIQK Check==============
4803 rx_fail = rtl_get_bbreg(hw, 0xd00, BIT(11));
4804 if (rx_fail == 0){
4805 /*
4806 ODM_Write4Byte(pDM_Odm, 0xcb8, 0x05000000);
4807 reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff);
4808 ODM_Write4Byte(pDM_Odm, 0xcb8, 0x06000000);
4809 reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f);
4810 DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2);
4811 Image_Power = (reg2<<32)+reg1;
4812 DbgPrint("Before PW = %d\n", Image_Power);
4813 ODM_Write4Byte(pDM_Odm, 0xcb8, 0x07000000);
4814 reg1 = ODM_GetBBReg(pDM_Odm, 0xd00, 0xffffffff);
4815 ODM_Write4Byte(pDM_Odm, 0xcb8, 0x08000000);
4816 reg2 = ODM_GetBBReg(pDM_Odm, 0xd00, 0x0000001f);
4817 Image_Power = (reg2<<32)+reg1;
4818 DbgPrint("After PW = %d\n", Image_Power);
4819 */
4820
4821 rtl_write_dword(rtlpriv, 0xcb8, 0x06000000);
4822 rx_x0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4823 rtl_write_dword(rtlpriv, 0xcb8, 0x08000000);
4824 rx_y0[cal] = rtl_get_bbreg(hw, 0xd00, 0x07ff0000)<<21;
4825 rx0iqkok = true;
4826 break;
4827 }
4828 else{
4829 rtl_set_bbreg(hw, 0xc10, 0x000003ff, 0x200>>1);
4830 rtl_set_bbreg(hw, 0xc10, 0x03ff0000, 0x0>>1);
4831 rx0iqkok = false;
4832 cal_retry++;
4833 if (cal_retry == 10)
4834 break;
4835
4836 }
4837 }
4838 else{
4839 rx0iqkok = false;
4840 cal_retry++;
4841 if (cal_retry == 10)
4842 break;
4843 }
4844 }
4845 }
4846
4847 if (tx0iqkok)
4848 tx_average++;
4849 if (rx0iqkok)
4850 rx_average++;
4851 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4852 rtl_set_rfreg(hw, path, 0x65, RFREG_OFFSET_MASK, temp_reg65);
4853 }
4854 break;
4855 default:
4856 break;
4857 }
4858 cal++;
4859 }
4860
4861 // FillIQK Result
4862 switch (path){
4863 case RF90_PATH_A:
4864 {
4865 RT_TRACE(COMP_IQK, DBG_LOUD, ("========Path_A =======\n"));
4866 if (tx_average == 0)
4867 break;
4868
4869 for (i = 0; i < tx_average; i++){
4870 RT_TRACE(COMP_IQK, DBG_LOUD, (" TX_X0_RXK[%d] = %x ;; TX_Y0_RXK[%d] = %x\n", i, (tx_x0_rxk[i])>>21&0x000007ff, i, (tx_y0_rxk[i])>>21&0x000007ff));
4871 RT_TRACE(COMP_IQK, DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (tx_x0[i])>>21&0x000007ff, i, (tx_y0[i])>>21&0x000007ff));
4872 }
4873 for (i = 0; i < tx_average; i++){
4874 for (ii = i+1; ii <tx_average; ii++){
4875 dx = (tx_x0[i]>>21) - (tx_x0[ii]>>21);
4876 if (dx < 3 && dx > -3){
4877 dy = (tx_y0[i]>>21) - (tx_y0[ii]>>21);
4878 if (dy < 3 && dy > -3){
4879 tx_x = ((tx_x0[i]>>21) + (tx_x0[ii]>>21))/2;
4880 tx_y = ((tx_y0[i]>>21) + (tx_y0[ii]>>21))/2;
4881 tx_finish = 1;
4882 break;
4883 }
4884 }
4885 }
4886 if (tx_finish == 1)
4887 break;
4888 }
4889
4890 if (tx_finish == 1){
4891 _rtl8821ae_iqk_tx_fill_iqc(hw, path, tx_x, tx_y); // ?
4892 }
4893 else{
4894 _rtl8821ae_iqk_tx_fill_iqc(hw, path, 0x200, 0x0);
4895 }
4896
4897 if (rx_average == 0)
4898 break;
4899
4900 for (i = 0; i < rx_average; i++){
4901 RT_TRACE(COMP_IQK, DBG_LOUD, ("RX_X0[%d] = %x ;; RX_Y0[%d] = %x\n", i, (rx_x0[i])>>21&0x000007ff, i, (rx_y0[i])>>21&0x000007ff));
4902 }
4903 for (i = 0; i < rx_average; i++){
4904 for (ii = i+1; ii <rx_average; ii++){
4905 dx = (rx_x0[i]>>21) - (rx_x0[ii]>>21);
4906 if (dx < 4 && dx > -4){
4907 dy = (rx_y0[i]>>21) - (rx_y0[ii]>>21);
4908 if (dy < 4 && dy > -4){
4909 rx_x = ((rx_x0[i]>>21) + (rx_x0[ii]>>21))/2;
4910 rx_y = ((rx_y0[i]>>21) + (rx_y0[ii]>>21))/2;
4911 rx_finish = 1;
4912 break;
4913 }
4914 }
4915 }
4916 if (rx_finish == 1)
4917 break;
4918 }
4919
4920 if (rx_finish == 1){
4921 _rtl8821ae_iqk_rx_fill_iqc(hw, path, rx_x, rx_y);
4922 }
4923 else{
4924 _rtl8821ae_iqk_rx_fill_iqc(hw, path, 0x200, 0x0);
4925 }
4926 }
4927 break;
4928 default:
4929 break;
4930 }
4931}
4932
4933void _rtl8821ae_iqk_restore_rf(
4934 struct ieee80211_hw *hw,
4935 enum radio_path path,
4936 u32* backup_rf_reg,
4937 u32* rf_backup,
4938 u32 rf_reg_num
4939 )
4940{
4941 u32 i;
4942 struct rtl_priv* rtlpriv = rtl_priv(hw);
4943
4944 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4945 for (i = 0; i < RF_REG_NUM; i++)
4946 rtl_set_rfreg(hw, path, backup_rf_reg[i], RFREG_OFFSET_MASK, rf_backup[i]);
4947
4948 switch(path){
4949 case RF90_PATH_A:
4950 {
4951 RT_TRACE(COMP_IQK, DBG_LOUD, ("RestoreRF Path A Success!!!!\n"));
4952 }
4953 break;
4954 default:
4955 break;
4956 }
4957}
4958
4959void _rtl8821ae_iqk_restore_afe(
4960 struct ieee80211_hw *hw,
4961 u32* afe_backup,
4962 u32* backup_afe_reg,
4963 u32 afe_num
4964 )
4965{
4966 u32 i;
4967 struct rtl_priv* rtlpriv = rtl_priv(hw);
4968
4969 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4970 //Reload AFE Parameters
4971 for (i = 0; i < afe_num; i++){
4972 rtl_write_dword(rtlpriv, backup_afe_reg[i], afe_backup[i]);
4973 }
4974 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
4975 rtl_write_dword(rtlpriv, 0xc80, 0x0);
4976 rtl_write_dword(rtlpriv, 0xc84, 0x0);
4977 rtl_write_dword(rtlpriv, 0xc88, 0x0);
4978 rtl_write_dword(rtlpriv, 0xc8c, 0x3c000000);
4979 rtl_write_dword(rtlpriv, 0xc90, 0x00000080);
4980 rtl_write_dword(rtlpriv, 0xc94, 0x00000000);
4981 rtl_write_dword(rtlpriv, 0xcc4, 0x20040000);
4982 rtl_write_dword(rtlpriv, 0xcc8, 0x20000000);
4983 rtl_write_dword(rtlpriv, 0xcb8, 0x0);
4984 RT_TRACE(COMP_IQK, DBG_LOUD, ("RestoreAFE Success!!!!\n"));
4985}
4986
4987void _rtl8821ae_iqk_restore_macbb(
4988 struct ieee80211_hw *hw,
4989 u32* macbb_backup,
4990 u32* backup_macbb_reg,
4991 u32 macbb_num
4992 )
4993{
4994 u32 i;
4995 struct rtl_priv* rtlpriv = rtl_priv(hw);
4996
4997 rtl_set_bbreg(hw, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
4998 //Reload MacBB Parameters
4999 for (i = 0; i < macbb_num; i++){
5000 rtl_write_dword(rtlpriv, backup_macbb_reg[i], macbb_backup[i]);
5001 }
5002 RT_TRACE(COMP_IQK, DBG_LOUD, ("RestoreMacBB Success!!!!\n"));
5003}
5004
5005
5006#undef MACBB_REG_NUM
5007#undef AFE_REG_NUM
5008#undef RF_REG_NUM
5009
5010#define MACBB_REG_NUM 11
5011#define AFE_REG_NUM 12
5012#define RF_REG_NUM 3
5013
5014static void _rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw)
5015{
5016 u32 macbb_backup[MACBB_REG_NUM];
5017 u32 afe_backup[AFE_REG_NUM];
5018 u32 rfa_backup[RF_REG_NUM];
5019 u32 rfb_backup[RF_REG_NUM];
5020 u32 backup_macbb_reg[MACBB_REG_NUM] = {0xb00, 0x520, 0x550, 0x808, 0x90c, 0xc00, 0xc50,
5021 0xe00, 0xe50, 0x838, 0x82c};
5022 u32 backup_afe_reg[AFE_REG_NUM] = {0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74,
5023 0xc78, 0xc7c, 0xc80, 0xc84, 0xcb8};
5024 u32 backup_rf_reg[RF_REG_NUM] = {0x65, 0x8f, 0x0};
5025
5026 _rtl8821ae_iqk_backup_macbb(hw, macbb_backup, backup_macbb_reg, MACBB_REG_NUM);
5027 _rtl8821ae_iqk_backup_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
5028 _rtl8821ae_iqk_backup_rf(hw, rfa_backup, rfb_backup, backup_rf_reg, RF_REG_NUM);
5029
5030 _rtl8821ae_iqk_configure_mac(hw);
5031 _rtl8821ae_iqk_tx(hw, RF90_PATH_A);
5032 _rtl8821ae_iqk_restore_rf(hw, RF90_PATH_A, backup_rf_reg, rfa_backup, RF_REG_NUM);
5033
5034 _rtl8821ae_iqk_restore_afe(hw, afe_backup, backup_afe_reg, AFE_REG_NUM);
5035 _rtl8821ae_iqk_restore_macbb(hw, macbb_backup, backup_macbb_reg, MACBB_REG_NUM);
5036}
5037
5038static void _rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
5039{
5040 u8 tmpreg;
5041 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
5042 struct rtl_priv *rtlpriv = rtl_priv(hw);
5043
5044 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
5045
5046 if ((tmpreg & 0x70) != 0)
5047 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
5048 else
5049 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
5050
5051 if ((tmpreg & 0x70) != 0) {
5052 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
5053
5054 if (is2t)
5055 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
5056 MASK12BITS);
5057
5058 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
5059 (rf_a_mode & 0x8FFFF) | 0x10000);
5060
5061 if (is2t)
5062 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
5063 (rf_b_mode & 0x8FFFF) | 0x10000);
5064 }
5065 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
5066
5067 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdfbe0);
5068 /* rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); */
5069 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, 0x8c0a);
5070
5071 mdelay(100);
5072
5073 rtl_set_rfreg(hw, RF90_PATH_A, 0xb0, RFREG_OFFSET_MASK, 0xdffe0);
5074
5075 if ((tmpreg & 0x70) != 0) {
5076 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
5077 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
5078
5079 if (is2t)
5080 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, rf_b_mode);
5081 } else {
5082 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
5083 }
5084RT_TRACE(COMP_INIT,DBG_LOUD,("\n"));
5085
5086}
5087
5088static void _rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool main)
5089{
5090 struct rtl_priv *rtlpriv = rtl_priv(hw);
5091 //struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
5092 //struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
5093 RT_TRACE(COMP_INIT,DBG_LOUD,("\n"));
5094
5095 if (main)
5096 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x1);
5097 else
5098 rtl_set_bbreg(hw, RA_RFE_PINMUX + 4, BIT(29) | BIT(28), 0x2);
5099}
5100
5101#undef IQK_ADDA_REG_NUM
5102#undef IQK_DELAY_TIME
5103
5104void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
5105{
5106 struct rtl_priv *rtlpriv = rtl_priv(hw);
5107 struct rtl_phy *rtlphy = &(rtlpriv->phy);
5108
5109 if (!rtlphy->b_iqk_in_progress)
5110 {
5111 spin_lock(&rtlpriv->locks.iqk_lock);
5112 rtlphy->b_iqk_in_progress = true;
5113 spin_unlock(&rtlpriv->locks.iqk_lock);
5114
5115 _rtl8812ae_phy_iq_calibrate(hw, rtlphy->current_channel);
5116
5117 spin_lock(&rtlpriv->locks.iqk_lock);
5118 rtlphy->b_iqk_in_progress = false;
5119 spin_unlock(&rtlpriv->locks.iqk_lock);
5120 }
5121}
5122
5123void rtl8812ae_reset_iqk_result(struct ieee80211_hw *hw)
5124{
5125 struct rtl_priv *rtlpriv = rtl_priv(hw);
5126 struct rtl_phy *rtlphy = &(rtlpriv->phy);
5127 u8 i;
5128
5129 RT_TRACE(COMP_IQK, DBG_LOUD,
5130 ("rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n",
5131 (int)(sizeof(rtlphy->iqk_matrix_regsetting) /
5132 sizeof(struct iqk_matrix_regs)),
5133 IQK_MATRIX_SETTINGS_NUM));
5134
5135 for(i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
5136 {
5137 rtlphy->iqk_matrix_regsetting[i].value[0][0] =
5138 rtlphy->iqk_matrix_regsetting[i].value[0][2] =
5139 rtlphy->iqk_matrix_regsetting[i].value[0][4] =
5140 rtlphy->iqk_matrix_regsetting[i].value[0][6] = 0x100;
5141
5142 rtlphy->iqk_matrix_regsetting[i].value[0][1] =
5143 rtlphy->iqk_matrix_regsetting[i].value[0][3] =
5144 rtlphy->iqk_matrix_regsetting[i].value[0][5] =
5145 rtlphy->iqk_matrix_regsetting[i].value[0][7] = 0x0;
5146
5147 rtlphy->iqk_matrix_regsetting[i].b_iqk_done = false;
5148
5149 }
5150 }
5151}
5152
5153void rtl8812ae_do_iqk(struct ieee80211_hw *hw,u8 delta_thermal_index,
5154 u8 thermal_value, u8 threshold)
5155{
5156 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
5157
5158 rtl8812ae_reset_iqk_result(hw);
5159
5160 rtldm->thermalvalue_iqk= thermal_value;
5161 rtl8812ae_phy_iq_calibrate(hw, false);
5162}
5163
5164void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
5165{
5166 struct rtl_priv *rtlpriv = rtl_priv(hw);
5167 struct rtl_phy *rtlphy = &(rtlpriv->phy);
5168
5169 if (!rtlphy->b_iqk_in_progress)
5170 {
5171 spin_lock(&rtlpriv->locks.iqk_lock);
5172 rtlphy->b_iqk_in_progress = true;
5173 spin_unlock(&rtlpriv->locks.iqk_lock);
5174
5175 _rtl8821ae_phy_iq_calibrate(hw);
5176
5177 spin_lock(&rtlpriv->locks.iqk_lock);
5178 rtlphy->b_iqk_in_progress = false;
5179 spin_unlock(&rtlpriv->locks.iqk_lock);
5180 }
5181}
5182
5183void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw)
5184{
5185 struct rtl_priv *rtlpriv = rtl_priv(hw);
5186 struct rtl_phy *rtlphy = &(rtlpriv->phy);
5187 u8 i;
5188
5189 RT_TRACE(COMP_IQK, DBG_LOUD,
5190 ("rtl8812ae_dm_reset_iqk_result:: settings regs %d default regs %d\n",
5191 (int)(sizeof(rtlphy->iqk_matrix_regsetting) /
5192 sizeof(struct iqk_matrix_regs)),
5193 IQK_MATRIX_SETTINGS_NUM));
5194
5195 for(i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
5196 {
5197 rtlphy->iqk_matrix_regsetting[i].value[0][0] =
5198 rtlphy->iqk_matrix_regsetting[i].value[0][2] =
5199 rtlphy->iqk_matrix_regsetting[i].value[0][4] =
5200 rtlphy->iqk_matrix_regsetting[i].value[0][6] = 0x100;
5201
5202 rtlphy->iqk_matrix_regsetting[i].value[0][1] =
5203 rtlphy->iqk_matrix_regsetting[i].value[0][3] =
5204 rtlphy->iqk_matrix_regsetting[i].value[0][5] =
5205 rtlphy->iqk_matrix_regsetting[i].value[0][7] = 0x0;
5206
5207 rtlphy->iqk_matrix_regsetting[i].b_iqk_done = false;
5208
5209 }
5210 }
5211}
5212
5213void rtl8821ae_do_iqk(struct ieee80211_hw *hw,u8 delta_thermal_index,
5214 u8 thermal_value, u8 threshold)
5215{
5216 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
5217
5218 rtl8821ae_reset_iqk_result(hw);
5219
5220 rtldm->thermalvalue_iqk= thermal_value;
5221 rtl8821ae_phy_iq_calibrate(hw, false);
5222}
5223
5224void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw)
5225{
5226 struct rtl_priv *rtlpriv = rtl_priv(hw);
5227 struct rtl_phy *rtlphy = &(rtlpriv->phy);
5228 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
5229 u32 timeout = 2000, timecount = 0;
5230
5231
5232 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
5233 udelay(50);
5234 timecount += 50;
5235 }
5236
5237 rtlphy->lck_inprogress = true;
5238 RTPRINT(rtlpriv, FINIT, INIT_IQK,
5239 ("LCK:Start!!! currentband %x delay %d ms\n",
5240 rtlhal->current_bandtype, timecount));
5241
5242 _rtl8821ae_phy_lc_calibrate(hw, false);
5243
5244 rtlphy->lck_inprogress = false;
5245}
5246
5247void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
5248{
5249 struct rtl_priv *rtlpriv = rtl_priv(hw);
5250 struct rtl_phy *rtlphy = &(rtlpriv->phy);
5251
5252 if (rtlphy->b_apk_done)
5253 return;
5254
5255 return;
5256}
5257
5258void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
5259{
5260 _rtl8821ae_phy_set_rfpath_switch(hw, bmain);
5261}
5262
5263bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
5264{
5265 struct rtl_priv *rtlpriv = rtl_priv(hw);
5266 struct rtl_phy *rtlphy = &(rtlpriv->phy);
5267 bool b_postprocessing = false;
5268
5269 RT_TRACE(COMP_CMD, DBG_TRACE,
5270 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
5271 iotype, rtlphy->set_io_inprogress));
5272 do {
5273 switch (iotype) {
5274 case IO_CMD_RESUME_DM_BY_SCAN:
5275 RT_TRACE(COMP_CMD, DBG_TRACE,
5276 ("[IO CMD] Resume DM after scan.\n"));
5277 b_postprocessing = true;
5278 break;
5279 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
5280 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
5281 RT_TRACE(COMP_CMD, DBG_TRACE,
5282 ("[IO CMD] Pause DM before scan.\n"));
5283 b_postprocessing = true;
5284 break;
5285 default:
5286 RT_TRACE(COMP_ERR, DBG_EMERG,
5287 ("switch case not process \n"));
5288 break;
5289 }
5290 } while (false);
5291 if (b_postprocessing && !rtlphy->set_io_inprogress) {
5292 rtlphy->set_io_inprogress = true;
5293 rtlphy->current_io_type = iotype;
5294 } else {
5295 return false;
5296 }
5297 rtl8821ae_phy_set_io(hw);
5298 RT_TRACE(COMP_CMD, DBG_TRACE, ("IO Type(%#x)\n", iotype));
5299 return true;
5300}
5301
5302static void rtl8821ae_phy_set_io(struct ieee80211_hw *hw)
5303{
5304 struct rtl_priv *rtlpriv = rtl_priv(hw);
5305 struct rtl_phy *rtlphy = &(rtlpriv->phy);
5306
5307 RT_TRACE(COMP_CMD, DBG_TRACE,
5308 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
5309 rtlphy->current_io_type, rtlphy->set_io_inprogress));
5310 switch (rtlphy->current_io_type) {
5311 case IO_CMD_RESUME_DM_BY_SCAN:
5312 if (rtlpriv->mac80211.opmode== NL80211_IFTYPE_ADHOC)
5313 _rtl8821ae_resume_tx_beacon(hw);
5314 rtl8821ae_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1);
5315 rtl8821ae_dm_write_cck_cca_thres(hw, rtlphy->initgain_backup.cca);
5316 break;
5317 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
5318 if (rtlpriv->mac80211.opmode== NL80211_IFTYPE_ADHOC)
5319 _rtl8821ae_stop_tx_beacon(hw);
5320 rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue;
5321 rtl8821ae_dm_write_dig(hw, 0x17);
5322 rtlphy->initgain_backup.cca = dm_digtable.cur_cck_cca_thres;
5323 rtl8821ae_dm_write_cck_cca_thres(hw, 0x40);
5324 break;
5325 case IO_CMD_PAUSE_BAND1_DM_BY_SCAN:
5326 break;
5327 default:
5328 RT_TRACE(COMP_ERR, DBG_EMERG,
5329 ("switch case not process \n"));
5330 break;
5331 }
5332 rtlphy->set_io_inprogress = false;
5333 RT_TRACE(COMP_CMD, DBG_TRACE,
5334 ("(%#x)\n", rtlphy->current_io_type));
5335}
5336
5337static void rtl8821ae_phy_set_rf_on(struct ieee80211_hw *hw)
5338{
5339 struct rtl_priv *rtlpriv = rtl_priv(hw);
5340
5341 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
5342 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
5343 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
5344 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
5345 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
5346}
5347
5348#if 0
5349static void _rtl8821ae_phy_set_rf_sleep(struct ieee80211_hw *hw)
5350{
5351 struct rtl_priv *rtlpriv = rtl_priv(hw);
5352
5353 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
5354 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
5355 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
5356 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
5357 while (u4b_tmp != 0 && delay > 0) {
5358 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
5359 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
5360 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
5361 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
5362 delay--;
5363 }
5364 if (delay == 0) {
5365 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
5366 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
5367 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
5368 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
5369 RT_TRACE(COMP_POWER, DBG_TRACE,
5370 ("Switch RF timeout !!!.\n"));
5371 return;
5372 }*/
5373 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
5374 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
5375}
5376#endif
5377
5378static bool _rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
5379 enum rf_pwrstate rfpwr_state)
5380{
5381 struct rtl_priv *rtlpriv = rtl_priv(hw);
5382 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
5383 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
5384 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
5385 bool bresult = true;
5386 u8 i, queue_id;
5387 struct rtl8192_tx_ring *ring = NULL;
5388
5389 switch (rfpwr_state) {
5390 case ERFON:{
5391 if ((ppsc->rfpwr_state == ERFOFF) &&
5392 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
5393 bool rtstatus = false;
5394 u32 InitializeCount = 0;
5395 do {
5396 InitializeCount++;
5397 RT_TRACE(COMP_RF, DBG_DMESG,
5398 ("IPS Set eRf nic enable\n"));
5399 rtstatus = rtl_ps_enable_nic(hw);
5400 } while ((rtstatus != true)
5401 && (InitializeCount < 10));
5402 RT_CLEAR_PS_LEVEL(ppsc,
5403 RT_RF_OFF_LEVL_HALT_NIC);
5404 } else {
5405 RT_TRACE(COMP_RF, DBG_DMESG,
5406 ("Set ERFON sleeped:%d ms\n",
5407 jiffies_to_msecs(jiffies -
5408 ppsc->
5409 last_sleep_jiffies)));
5410 ppsc->last_awake_jiffies = jiffies;
5411 rtl8821ae_phy_set_rf_on(hw);
5412 }
5413 if (mac->link_state == MAC80211_LINKED) {
5414 rtlpriv->cfg->ops->led_control(hw,
5415 LED_CTL_LINK);
5416 } else {
5417 rtlpriv->cfg->ops->led_control(hw,
5418 LED_CTL_NO_LINK);
5419 }
5420 break;
5421 }
5422 case ERFOFF:{
5423 for (queue_id = 0, i = 0;
5424 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
5425 ring = &pcipriv->dev.tx_ring[queue_id];
5426 if (skb_queue_len(&ring->queue) == 0) {
5427 queue_id++;
5428 continue;
5429 } else {
5430 RT_TRACE(COMP_ERR, DBG_WARNING,
5431 ("eRf Off/Sleep: %d times "
5432 "TcbBusyQueue[%d] =%d before "
5433 "doze!\n", (i + 1), queue_id,
5434 skb_queue_len(&ring->queue)));
5435
5436 udelay(10);
5437 i++;
5438 }
5439 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
5440 RT_TRACE(COMP_ERR, DBG_WARNING,
5441 ("\n ERFSLEEP: %d times "
5442 "TcbBusyQueue[%d] = %d !\n",
5443 MAX_DOZE_WAITING_TIMES_9x,
5444 queue_id,
5445 skb_queue_len(&ring->queue)));
5446 break;
5447 }
5448 }
5449
5450 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
5451 RT_TRACE(COMP_RF, DBG_DMESG,
5452 ("IPS Set eRf nic disable\n"));
5453 rtl_ps_disable_nic(hw);
5454 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
5455 } else {
5456 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
5457 rtlpriv->cfg->ops->led_control(hw,
5458 LED_CTL_NO_LINK);
5459 } else {
5460 rtlpriv->cfg->ops->led_control(hw,
5461 LED_CTL_POWER_OFF);
5462 }
5463 }
5464 break;
5465 }
5466 /*case ERFSLEEP:{
5467 if (ppsc->rfpwr_state == ERFOFF)
5468 break;
5469 for (queue_id = 0, i = 0;
5470 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
5471 ring = &pcipriv->dev.tx_ring[queue_id];
5472 if (skb_queue_len(&ring->queue) == 0) {
5473 queue_id++;
5474 continue;
5475 } else {
5476 RT_TRACE(COMP_ERR, DBG_WARNING,
5477 ("eRf Off/Sleep: %d times "
5478 "TcbBusyQueue[%d] =%d before "
5479 "doze!\n", (i + 1), queue_id,
5480 skb_queue_len(&ring->queue)));
5481
5482 udelay(10);
5483 i++;
5484 }
5485 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
5486 RT_TRACE(COMP_ERR, DBG_WARNING,
5487 ("\n ERFSLEEP: %d times "
5488 "TcbBusyQueue[%d] = %d !\n",
5489 MAX_DOZE_WAITING_TIMES_9x,
5490 queue_id,
5491 skb_queue_len(&ring->queue)));
5492 break;
5493 }
5494 }
5495 RT_TRACE(COMP_RF, DBG_DMESG,
5496 ("Set ERFSLEEP awaked:%d ms\n",
5497 jiffies_to_msecs(jiffies -
5498 ppsc->last_awake_jiffies)));
5499 ppsc->last_sleep_jiffies = jiffies;
5500 _rtl8821ae_phy_set_rf_sleep(hw);
5501 break;
5502 }*/
5503 default:
5504 RT_TRACE(COMP_ERR, DBG_EMERG,
5505 ("switch case not process \n"));
5506 bresult = false;
5507 break;
5508 }
5509 if (bresult)
5510 ppsc->rfpwr_state = rfpwr_state;
5511 return bresult;
5512}
5513
5514bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
5515 enum rf_pwrstate rfpwr_state)
5516{
5517 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
5518
5519 bool bresult = false;
5520
5521 if (rfpwr_state == ppsc->rfpwr_state)
5522 return bresult;
5523 bresult = _rtl8821ae_phy_set_rf_power_state(hw, rfpwr_state);
5524 return bresult;
5525}
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/phy.h b/drivers/staging/rtl8821ae/rtl8821ae/phy.h
new file mode 100644
index 000000000000..a932d8c9d45d
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/phy.h
@@ -0,0 +1,258 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8821AE_PHY_H__
31#define __RTL8821AE_PHY_H__
32
33/*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
34#define MAX_TX_COUNT 4
35#define TX_1S 0
36#define TX_2S 1
37#define TX_3S 2
38#define TX_4S 3
39
40#define MAX_POWER_INDEX 0x3F
41
42#define MAX_PRECMD_CNT 16
43#define MAX_RFDEPENDCMD_CNT 16
44#define MAX_POSTCMD_CNT 16
45
46#define MAX_DOZE_WAITING_TIMES_9x 64
47
48#define RT_CANNOT_IO(hw) false
49#define HIGHPOWER_RADIOA_ARRAYLEN 22
50
51#define IQK_ADDA_REG_NUM 16
52#define IQK_BB_REG_NUM 9
53#define MAX_TOLERANCE 5
54#define IQK_DELAY_TIME 10
55#define index_mapping_NUM 15
56
57#define APK_BB_REG_NUM 5
58#define APK_AFE_REG_NUM 16
59#define APK_CURVE_REG_NUM 4
60#define PATH_NUM 2
61
62#define LOOP_LIMIT 5
63#define MAX_STALL_TIME 50
64#define AntennaDiversityValue 0x80
65#define MAX_TXPWR_IDX_NMODE_92S 63
66#define Reset_Cnt_Limit 3
67
68#define IQK_ADDA_REG_NUM 16
69#define IQK_MAC_REG_NUM 4
70
71#define RF6052_MAX_PATH 2
72
73#define CT_OFFSET_MAC_ADDR 0X16
74
75#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
76#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
77#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
78#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
79#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
80
81#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
82#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
83
84#define CT_OFFSET_CHANNEL_PLAH 0x75
85#define CT_OFFSET_THERMAL_METER 0x78
86#define CT_OFFSET_RF_OPTION 0x79
87#define CT_OFFSET_VERSION 0x7E
88#define CT_OFFSET_CUSTOMER_ID 0x7F
89
90#define RTL8821AE_MAX_PATH_NUM 2
91
92#define TARGET_CHNL_NUM_2G_5G_8812 59
93
94enum swchnlcmd_id {
95 CMDID_END,
96 CMDID_SET_TXPOWEROWER_LEVEL,
97 CMDID_BBREGWRITE10,
98 CMDID_WRITEPORT_ULONG,
99 CMDID_WRITEPORT_USHORT,
100 CMDID_WRITEPORT_UCHAR,
101 CMDID_RF_WRITEREG,
102};
103
104struct swchnlcmd {
105 enum swchnlcmd_id cmdid;
106 u32 para1;
107 u32 para2;
108 u32 msdelay;
109};
110
111enum hw90_block_e {
112 HW90_BLOCK_MAC = 0,
113 HW90_BLOCK_PHY0 = 1,
114 HW90_BLOCK_PHY1 = 2,
115 HW90_BLOCK_RF = 3,
116 HW90_BLOCK_MAXIMUM = 4,
117};
118
119enum baseband_config_type {
120 BASEBAND_CONFIG_PHY_REG = 0,
121 BASEBAND_CONFIG_AGC_TAB = 1,
122};
123
124enum ra_offset_area {
125 RA_OFFSET_LEGACY_OFDM1,
126 RA_OFFSET_LEGACY_OFDM2,
127 RA_OFFSET_HT_OFDM1,
128 RA_OFFSET_HT_OFDM2,
129 RA_OFFSET_HT_OFDM3,
130 RA_OFFSET_HT_OFDM4,
131 RA_OFFSET_HT_CCK,
132};
133
134enum antenna_path {
135 ANTENNA_NONE,
136 ANTENNA_D,
137 ANTENNA_C,
138 ANTENNA_CD,
139 ANTENNA_B,
140 ANTENNA_BD,
141 ANTENNA_BC,
142 ANTENNA_BCD,
143 ANTENNA_A,
144 ANTENNA_AD,
145 ANTENNA_AC,
146 ANTENNA_ACD,
147 ANTENNA_AB,
148 ANTENNA_ABD,
149 ANTENNA_ABC,
150 ANTENNA_ABCD
151};
152
153struct r_antenna_select_ofdm {
154 u32 r_tx_antenna:4;
155 u32 r_ant_l:4;
156 u32 r_ant_non_ht:4;
157 u32 r_ant_ht1:4;
158 u32 r_ant_ht2:4;
159 u32 r_ant_ht_s1:4;
160 u32 r_ant_non_ht_s1:4;
161 u32 ofdm_txsc:2;
162 u32 reserved:2;
163};
164
165struct r_antenna_select_cck {
166 u8 r_cckrx_enable_2:2;
167 u8 r_cckrx_enable:2;
168 u8 r_ccktx_enable:4;
169};
170
171
172struct efuse_contents {
173 u8 mac_addr[ETH_ALEN];
174 u8 cck_tx_power_idx[6];
175 u8 ht40_1s_tx_power_idx[6];
176 u8 ht40_2s_tx_power_idx_diff[3];
177 u8 ht20_tx_power_idx_diff[3];
178 u8 ofdm_tx_power_idx_diff[3];
179 u8 ht40_max_power_offset[3];
180 u8 ht20_max_power_offset[3];
181 u8 channel_plan;
182 u8 thermal_meter;
183 u8 rf_option[5];
184 u8 version;
185 u8 oem_id;
186 u8 regulatory;
187};
188
189struct tx_power_struct {
190 u8 cck[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
191 u8 ht40_1s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
192 u8 ht40_2s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
193 u8 ht20_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
194 u8 legacy_ht_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
195 u8 legacy_ht_txpowerdiff;
196 u8 groupht20[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
197 u8 groupht40[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
198 u8 pwrgroup_cnt;
199 u32 mcs_original_offset[4][16];
200};
201enum _ANT_DIV_TYPE
202{
203 NO_ANTDIV = 0xFF,
204 CG_TRX_HW_ANTDIV = 0x01,
205 CGCS_RX_HW_ANTDIV = 0x02,
206 FIXED_HW_ANTDIV = 0x03,
207 CG_TRX_SMART_ANTDIV = 0x04,
208 CGCS_RX_SW_ANTDIV = 0x05,
209
210};
211
212extern u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw,
213 u32 regaddr, u32 bitmask);
214extern void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
215 u32 regaddr, u32 bitmask, u32 data);
216extern u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
217 enum radio_path rfpath, u32 regaddr,
218 u32 bitmask);
219extern void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
220 enum radio_path rfpath, u32 regaddr,
221 u32 bitmask, u32 data);
222extern bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw);
223extern bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw);
224extern bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw);
225extern void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band);
226extern void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
227extern void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw,
228 long *powerlevel);
229extern void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
230extern void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw,
231 u8 operation);
232extern void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
233extern void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
234 enum nl80211_channel_type ch_type);
235extern void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw);
236extern u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw);
237extern void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
238extern void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
239void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
240void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw);
241void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
242bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
243 enum radio_path rfpath);
244bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
245 enum radio_path rfpath);
246bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
247extern bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
248 enum rf_pwrstate rfpwr_state);
249u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl);
250void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, u8 channel, u8 path);
251void rtl8812ae_do_iqk(struct ieee80211_hw *hw,u8 delta_thermal_index,
252 u8 thermal_value, u8 threshold);
253void rtl8821ae_do_iqk(struct ieee80211_hw *hw,u8 delta_thermal_index,
254 u8 thermal_value, u8 threshold);
255void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw);
256
257
258#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/pwrseq.c b/drivers/staging/rtl8821ae/rtl8821ae/pwrseq.c
new file mode 100644
index 000000000000..a2e4a01b712b
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/pwrseq.c
@@ -0,0 +1,199 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "pwrseqcmd.h"
31#include "pwrseq.h"
32
33/*
34 drivers should parse below arrays and do the corresponding actions
35*/
36//3 Power on Array
37struct wlan_pwr_cfg rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]=
38{
39 RTL8812_TRANS_CARDEMU_TO_ACT
40 RTL8812_TRANS_END
41};
42
43//3Radio off GPIO Array
44struct wlan_pwr_cfg rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_END_STEPS]=
45{
46 RTL8812_TRANS_ACT_TO_CARDEMU
47 RTL8812_TRANS_END
48};
49
50//3Card Disable Array
51struct wlan_pwr_cfg rtl8812_card_disable_flow[ RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
52 + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
53 + RTL8812_TRANS_END_STEPS ] =
54{
55 RTL8812_TRANS_ACT_TO_CARDEMU
56 RTL8812_TRANS_CARDEMU_TO_CARDDIS
57 RTL8812_TRANS_END
58};
59
60//3 Card Enable Array
61struct wlan_pwr_cfg rtl8812_card_enable_flow[ RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
62 + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
63 + RTL8812_TRANS_END_STEPS ] =
64{
65 RTL8812_TRANS_CARDDIS_TO_CARDEMU
66 RTL8812_TRANS_CARDEMU_TO_ACT
67 RTL8812_TRANS_END
68};
69
70//3Suspend Array
71struct wlan_pwr_cfg rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]=
72{
73 RTL8812_TRANS_ACT_TO_CARDEMU
74 RTL8812_TRANS_CARDEMU_TO_SUS
75 RTL8812_TRANS_END
76};
77
78//3 Resume Array
79struct wlan_pwr_cfg rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]=
80{
81 RTL8812_TRANS_SUS_TO_CARDEMU
82 RTL8812_TRANS_CARDEMU_TO_ACT
83 RTL8812_TRANS_END
84};
85
86
87
88//3HWPDN Array
89struct wlan_pwr_cfg rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]=
90{
91 RTL8812_TRANS_ACT_TO_CARDEMU
92 RTL8812_TRANS_CARDEMU_TO_PDN
93 RTL8812_TRANS_END
94};
95
96//3 Enter LPS
97struct wlan_pwr_cfg rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS+RTL8812_TRANS_END_STEPS]=
98{
99 //FW behavior
100 RTL8812_TRANS_ACT_TO_LPS
101 RTL8812_TRANS_END
102};
103
104//3 Leave LPS
105struct wlan_pwr_cfg rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]=
106{
107 //FW behavior
108 RTL8812_TRANS_LPS_TO_ACT
109 RTL8812_TRANS_END
110};
111
112
113/*
114 drivers should parse below arrays and do the corresponding actions
115*/
116/*3 Power on Array*/
117struct wlan_pwr_cfg rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
118 + RTL8821A_TRANS_END_STEPS] =
119{
120 RTL8821A_TRANS_CARDEMU_TO_ACT
121 RTL8821A_TRANS_END
122};
123
124/*3Radio off GPIO Array */
125struct wlan_pwr_cfg rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
126 + RTL8821A_TRANS_END_STEPS] =
127{
128 RTL8821A_TRANS_ACT_TO_CARDEMU
129 RTL8821A_TRANS_END
130};
131
132/*3Card Disable Array*/
133struct wlan_pwr_cfg rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
134 + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
135 + RTL8821A_TRANS_END_STEPS] =
136{
137 RTL8821A_TRANS_ACT_TO_CARDEMU
138 RTL8821A_TRANS_CARDEMU_TO_CARDDIS
139 RTL8821A_TRANS_END
140};
141
142/*3 Card Enable Array*/
143struct wlan_pwr_cfg rtl8821A_card_enable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
144 + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS /*RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS*/
145 + RTL8821A_TRANS_END_STEPS] =
146{
147 RTL8821A_TRANS_CARDDIS_TO_CARDEMU
148 RTL8821A_TRANS_CARDEMU_TO_ACT
149 RTL8821A_TRANS_END
150};
151
152/*3Suspend Array*/
153struct wlan_pwr_cfg rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
154 + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
155 + RTL8821A_TRANS_END_STEPS] =
156{
157 RTL8821A_TRANS_ACT_TO_CARDEMU
158 RTL8821A_TRANS_CARDEMU_TO_SUS
159 RTL8821A_TRANS_END
160};
161
162/*3 Resume Array*/
163struct wlan_pwr_cfg rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
164 + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
165 + RTL8821A_TRANS_END_STEPS] =
166{
167 RTL8821A_TRANS_SUS_TO_CARDEMU
168 RTL8821A_TRANS_CARDEMU_TO_ACT
169 RTL8821A_TRANS_END
170};
171
172/*3HWPDN Array*/
173struct wlan_pwr_cfg rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
174 + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
175 + RTL8821A_TRANS_END_STEPS] =
176{
177 RTL8821A_TRANS_ACT_TO_CARDEMU
178 RTL8821A_TRANS_CARDEMU_TO_PDN
179 RTL8821A_TRANS_END
180};
181
182/*3 Enter LPS */
183struct wlan_pwr_cfg rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS
184 + RTL8821A_TRANS_END_STEPS] =
185{
186 /*FW behavior*/
187 RTL8821A_TRANS_ACT_TO_LPS
188 RTL8821A_TRANS_END
189};
190
191/*3 Leave LPS */
192struct wlan_pwr_cfg rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS
193 + RTL8821A_TRANS_END_STEPS] =
194{
195 /*FW behavior*/
196 RTL8821A_TRANS_LPS_TO_ACT
197 RTL8821A_TRANS_END
198};
199
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/pwrseq.h b/drivers/staging/rtl8821ae/rtl8821ae/pwrseq.h
new file mode 100644
index 000000000000..8b39c042fa93
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/pwrseq.h
@@ -0,0 +1,413 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8821AE_PWRSEQ_H__
31#define __RTL8821AE_PWRSEQ_H__
32
33#include "pwrseqcmd.h"
34#include "../btcoexist/halbt_precomp.h"
35
36#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15
37#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15
38#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15
39#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15
40#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 25
41#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15
42#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15
43#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15
44#define RTL8812_TRANS_END_STEPS 1
45
46
47#define RTL8812_TRANS_CARDEMU_TO_ACT \
48 /* format */ \
49 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
50 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
51 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
52 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
53 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
54 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
55 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/
56
57#define RTL8812_TRANS_ACT_TO_CARDEMU \
58 /* format */ \
59 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
60 {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
61 {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
62 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
63 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
64 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
65 /*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/ \
66 /*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
67 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
68 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \
69 /*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, // 0x02[1:0] = 0 reset BB */ \
70 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
71 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
72
73#define RTL8812_TRANS_CARDEMU_TO_SUS \
74 /* format */ \
75 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
76 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},\
77 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},\
78 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
79 {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
80 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
81 {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
82 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
83 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
84 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
85 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
86 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \
87 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/
88
89#define RTL8812_TRANS_SUS_TO_CARDEMU \
90 /* format */ \
91 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
92 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
93 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
94 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
95 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
96 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
97 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
98
99#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \
100 /* format */ \
101 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
102 /**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
103 /**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x94}, //0x93=0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
104 {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/ \
105 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/ \
106 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},\
107 {0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},\
108 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
109 {0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
110 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
111 {0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
112 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
113 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
114 {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */ \
115 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
116 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \
117 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
118 {0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */ \
119 {0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */ \
120 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/
121
122#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \
123 /* format */ \
124 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
125 {0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */ \
126 {0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
127 {0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
128 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
129 {0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
130 {0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \
131 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
132 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
133 {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/ \
134 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
135
136
137#define RTL8812_TRANS_CARDEMU_TO_PDN \
138 /* format */ \
139 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
140 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
141
142#define RTL8812_TRANS_PDN_TO_CARDEMU \
143 /* format */ \
144 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
145 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
146
147#define RTL8812_TRANS_ACT_TO_LPS \
148 /* format */ \
149 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
150 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
151 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
152 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
153 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
154 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
155 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
156 {0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
157 {0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
158 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \
159 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
160 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
161 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
162 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
163 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
164
165
166#define RTL8812_TRANS_LPS_TO_ACT \
167 /* format */ \
168 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
169 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
170 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
171 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
172 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
173 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
174 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/ \
175 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
176 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
177 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
178 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
179 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
180
181#define RTL8812_TRANS_END \
182 /* format */ \
183 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
184 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
185
186
187extern struct wlan_pwr_cfg rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS];
188extern struct wlan_pwr_cfg rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_END_STEPS];
189extern struct wlan_pwr_cfg rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS];
190extern struct wlan_pwr_cfg rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS];
191extern struct wlan_pwr_cfg rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS];
192extern struct wlan_pwr_cfg rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS];
193extern struct wlan_pwr_cfg rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS];
194extern struct wlan_pwr_cfg rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS+RTL8812_TRANS_END_STEPS];
195extern struct wlan_pwr_cfg rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS];
196
197/*
198 Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
199 There are 6 HW Power States:
200 0: POFF--Power Off
201 1: PDN--Power Down
202 2: CARDEMU--Card Emulation
203 3: ACT--Active Mode
204 4: LPS--Low Power State
205 5: SUS--Suspend
206
207 The transision from different states are defined below
208 TRANS_CARDEMU_TO_ACT
209 TRANS_ACT_TO_CARDEMU
210 TRANS_CARDEMU_TO_SUS
211 TRANS_SUS_TO_CARDEMU
212 TRANS_CARDEMU_TO_PDN
213 TRANS_ACT_TO_LPS
214 TRANS_LPS_TO_ACT
215
216 TRANS_END
217*/
218#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25
219#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15
220#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15
221#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15
222#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15
223#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15
224#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15
225#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15
226#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15
227#define RTL8821A_TRANS_END_STEPS 1
228
229
230#define RTL8821A_TRANS_CARDEMU_TO_ACT \
231 /* format */ \
232 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
233 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
234 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
235 {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
236 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
237 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \
238 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
239 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
240 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
241 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
242 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
243 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
244 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
245 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
246 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\
247 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\
248 {0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\
249 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
250 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
251 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
252 {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
253 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
254 {0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\
255 {0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \
256 {0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MP·s¼W¹ï©ó0x2Cªº±±¨îÅv¡A¶·§â0x10[6]³]¬°1¤~¯àÅýWLAN±±¨î */ \
257
258
259#define RTL8821A_TRANS_ACT_TO_CARDEMU \
260 /* format */ \
261 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
262 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
263 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
264 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
265 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
266 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
267 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
268 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
269
270
271#define RTL8821A_TRANS_CARDEMU_TO_SUS \
272 /* format */ \
273 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
274 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
275 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
276 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
277 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
278 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
279 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
280 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
281
282#define RTL8821A_TRANS_SUS_TO_CARDEMU \
283 /* format */ \
284 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
285 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
286 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
287 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
288 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
289 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
290
291#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \
292 /* format */ \
293 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
294 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
295 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
296 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
297 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
298 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
299 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
300 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
301
302#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \
303 /* format */ \
304 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
305 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
306 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
307 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
308 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
309 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
310 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
311 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
312
313
314#define RTL8821A_TRANS_CARDEMU_TO_PDN \
315 /* format */ \
316 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
317 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
318 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
319 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
320 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
321
322#define RTL8821A_TRANS_PDN_TO_CARDEMU \
323 /* format */ \
324 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
325 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
326
327#define RTL8821A_TRANS_ACT_TO_LPS \
328 /* format */ \
329 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
330 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
331 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
332 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
333 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
334 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
335 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
336 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
337 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
338 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
339 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
340 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
341 {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
342 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
343
344
345#define RTL8821A_TRANS_LPS_TO_ACT \
346 /* format */ \
347 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
348 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
349 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
350 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
351 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
352 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
353 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
354 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
355 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
356 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
357 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
358 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
359
360#define RTL8821A_TRANS_END \
361 /* format */ \
362 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
363 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
364
365extern struct wlan_pwr_cfg rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
366 + RTL8821A_TRANS_END_STEPS];
367extern struct wlan_pwr_cfg rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
368 + RTL8821A_TRANS_END_STEPS];
369extern struct wlan_pwr_cfg rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
370 + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
371 + RTL8821A_TRANS_END_STEPS];
372extern struct wlan_pwr_cfg rtl8821A_card_enable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
373 + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS/*RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS*/
374 + RTL8821A_TRANS_END_STEPS];
375extern struct wlan_pwr_cfg rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
376 + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
377 + RTL8821A_TRANS_END_STEPS];
378extern struct wlan_pwr_cfg rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
379 + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
380 + RTL8821A_TRANS_END_STEPS];
381extern struct wlan_pwr_cfg rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
382 + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
383 + RTL8821A_TRANS_END_STEPS];
384extern struct wlan_pwr_cfg rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS
385 + RTL8821A_TRANS_END_STEPS];
386extern struct wlan_pwr_cfg rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS
387 + RTL8821A_TRANS_END_STEPS];
388
389/*RTL8812 Power Configuration CMDs for PCIe interface*/
390#define RTL8812_NIC_PWR_ON_FLOW rtl8812_power_on_flow
391#define RTL8812_NIC_RF_OFF_FLOW rtl8812_radio_off_flow
392#define RTL8812_NIC_DISABLE_FLOW rtl8812_card_disable_flow
393#define RTL8812_NIC_ENABLE_FLOW rtl8812_card_enable_flow
394#define RTL8812_NIC_SUSPEND_FLOW rtl8812_suspend_flow
395#define RTL8812_NIC_RESUME_FLOW rtl8812_resume_flow
396#define RTL8812_NIC_PDN_FLOW rtl8812_hwpdn_flow
397#define RTL8812_NIC_LPS_ENTER_FLOW rtl8812_enter_lps_flow
398#define RTL8812_NIC_LPS_LEAVE_FLOW rtl8812_leave_lps_flow
399
400/* RTL8821 Power Configuration CMDs for PCIe interface */
401#define RTL8821A_NIC_PWR_ON_FLOW rtl8821A_power_on_flow
402#define RTL8821A_NIC_RF_OFF_FLOW rtl8821A_radio_off_flow
403#define RTL8821A_NIC_DISABLE_FLOW rtl8821A_card_disable_flow
404#define RTL8821A_NIC_ENABLE_FLOW rtl8821A_card_enable_flow
405#define RTL8821A_NIC_SUSPEND_FLOW rtl8821A_suspend_flow
406#define RTL8821A_NIC_RESUME_FLOW rtl8821A_resume_flow
407#define RTL8821A_NIC_PDN_FLOW rtl8821A_hwpdn_flow
408#define RTL8821A_NIC_LPS_ENTER_FLOW rtl8821A_enter_lps_flow
409#define RTL8821A_NIC_LPS_LEAVE_FLOW rtl8821A_leave_lps_flow
410
411
412#endif
413
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/pwrseqcmd.c b/drivers/staging/rtl8821ae/rtl8821ae/pwrseqcmd.c
new file mode 100644
index 000000000000..710bc015251c
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/pwrseqcmd.c
@@ -0,0 +1,140 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "pwrseq.h"
31
32
33/*
34* Description:
35* This routine deal with the Power Configuration CMDs
36* parsing for RTL8723/RTL8188E Series IC.
37* Assumption:
38* We should follow specific format which was released from HW SD.
39*
40* 2011.07.07, added by Roger.
41*/
42bool rtl_hal_pwrseqcmdparsing (struct rtl_priv* rtlpriv, u8 cut_version,
43 u8 fab_version, u8 interface_type,
44 struct wlan_pwr_cfg pwrcfgcmd[])
45
46{
47 struct wlan_pwr_cfg pwr_cfg_cmd = {0};
48 bool polling_bit = false;
49 u32 ary_idx=0;
50 u8 value = 0;
51 u32 offset = 0;
52 u32 polling_count = 0;
53 u32 max_polling_cnt = 5000;
54
55 do {
56 pwr_cfg_cmd = pwrcfgcmd[ary_idx];
57 RT_TRACE(COMP_INIT, DBG_TRACE,
58 ("rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), fab_msk(%#x),"
59 "interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
60 GET_PWR_CFG_OFFSET(pwr_cfg_cmd), GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd),
61 GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd), GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd),
62 GET_PWR_CFG_BASE(pwr_cfg_cmd), GET_PWR_CFG_CMD(pwr_cfg_cmd),
63 GET_PWR_CFG_MASK(pwr_cfg_cmd), GET_PWR_CFG_VALUE(pwr_cfg_cmd)));
64
65 if ((GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd)&fab_version) &&
66 (GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd)&cut_version) &&
67 (GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd)&interface_type)) {
68 switch (GET_PWR_CFG_CMD(pwr_cfg_cmd)) {
69 case PWR_CMD_READ:
70 RT_TRACE(COMP_INIT, DBG_TRACE,
71 ("rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n"));
72 break;
73
74 case PWR_CMD_WRITE: {
75 RT_TRACE(COMP_INIT, DBG_TRACE,
76 ("rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n"));
77 offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
78
79 /*Read the value from system register*/
80 value = rtl_read_byte(rtlpriv, offset);
81 value = value & (~(GET_PWR_CFG_MASK(pwr_cfg_cmd)));
82 value = value | (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
83 & GET_PWR_CFG_MASK(pwr_cfg_cmd));
84
85 /*Write the value back to sytem register*/
86 rtl_write_byte(rtlpriv, offset, value);
87 }
88 break;
89
90 case PWR_CMD_POLLING:
91 RT_TRACE(COMP_INIT, DBG_TRACE,
92 ("rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n"));
93 polling_bit = false;
94 offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
95
96 do {
97 value = rtl_read_byte(rtlpriv, offset);
98
99 value = value & GET_PWR_CFG_MASK(pwr_cfg_cmd);
100 if (value == (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
101 & GET_PWR_CFG_MASK(pwr_cfg_cmd)))
102 polling_bit=true;
103 else
104 udelay(10);
105
106 if (polling_count++ > max_polling_cnt) {
107 return false;
108 }
109 } while (!polling_bit);
110
111 break;
112
113 case PWR_CMD_DELAY:
114 RT_TRACE(COMP_INIT, DBG_TRACE,
115 ("rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n"));
116 if (GET_PWR_CFG_VALUE(pwr_cfg_cmd) == PWRSEQ_DELAY_US)
117 udelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
118 else
119 mdelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
120 break;
121
122 case PWR_CMD_END:
123 RT_TRACE(COMP_INIT, DBG_TRACE,
124 ("rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n"));
125 return true;
126 break;
127
128 default:
129 RT_ASSERT(false,
130 ("rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n"));
131 break;
132 }
133
134 }
135
136 ary_idx++;
137 } while (1);
138
139 return true;
140}
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/pwrseqcmd.h b/drivers/staging/rtl8821ae/rtl8821ae/pwrseqcmd.h
new file mode 100644
index 000000000000..571e7e50d5b5
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/pwrseqcmd.h
@@ -0,0 +1,71 @@
1#ifndef __RTL8821AE_PWRSEQCMD_H__
2#define __RTL8821AE_PWRSEQCMD_H__
3
4#include "../wifi.h"
5/*---------------------------------------------*/
6/*The value of cmd: 4 bits */
7/*---------------------------------------------*/
8#define PWR_CMD_READ 0x00
9#define PWR_CMD_WRITE 0x01
10#define PWR_CMD_POLLING 0x02
11#define PWR_CMD_DELAY 0x03
12#define PWR_CMD_END 0x04
13
14/* define the base address of each block */
15#define PWR_BASEADDR_MAC 0x00
16#define PWR_BASEADDR_USB 0x01
17#define PWR_BASEADDR_PCIE 0x02
18#define PWR_BASEADDR_SDIO 0x03
19
20#define PWR_INTF_SDIO_MSK BIT(0)
21#define PWR_INTF_USB_MSK BIT(1)
22#define PWR_INTF_PCI_MSK BIT(2)
23#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
24
25#define PWR_FAB_TSMC_MSK BIT(0)
26#define PWR_FAB_UMC_MSK BIT(1)
27#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
28
29#define PWR_CUT_TESTCHIP_MSK BIT(0)
30#define PWR_CUT_A_MSK BIT(1)
31#define PWR_CUT_B_MSK BIT(2)
32#define PWR_CUT_C_MSK BIT(3)
33#define PWR_CUT_D_MSK BIT(4)
34#define PWR_CUT_E_MSK BIT(5)
35#define PWR_CUT_F_MSK BIT(6)
36#define PWR_CUT_G_MSK BIT(7)
37#define PWR_CUT_ALL_MSK 0xFF
38
39
40enum pwrseq_delay_unit {
41 PWRSEQ_DELAY_US,
42 PWRSEQ_DELAY_MS,
43};
44
45struct wlan_pwr_cfg {
46 u16 offset;
47 u8 cut_msk;
48 u8 fab_msk:4;
49 u8 interface_msk:4;
50 u8 base:4;
51 u8 cmd:4;
52 u8 msk;
53 u8 value;
54
55};
56
57#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
58#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
59#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
60#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
61#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
62#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
63#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
64#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
65
66bool rtl_hal_pwrseqcmdparsing(struct rtl_priv * rtlpriv, u8 cut_version,
67 u8 fab_version, u8 interface_type,
68 struct wlan_pwr_cfg pwrcfgcmd[]);
69
70#endif
71
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/reg.h b/drivers/staging/rtl8821ae/rtl8821ae/reg.h
new file mode 100644
index 000000000000..09c5f00d2603
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/reg.h
@@ -0,0 +1,2427 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8821AE_REG_H__
31#define __RTL8821AE_REG_H__
32
33#define TXPKT_BUF_SELECT 0x69
34#define RXPKT_BUF_SELECT 0xA5
35#define DISABLE_TRXPKT_BUF_ACCESS 0x0
36
37#define REG_SYS_ISO_CTRL 0x0000
38#define REG_SYS_FUNC_EN 0x0002
39#define REG_APS_FSMCO 0x0004
40#define REG_SYS_CLKR 0x0008
41#define REG_9346CR 0x000A
42#define REG_EE_VPD 0x000C
43#define REG_AFE_MISC 0x0010
44#define REG_SPS0_CTRL 0x0011
45#define REG_SPS_OCP_CFG 0x0018
46#define REG_RSV_CTRL 0x001C
47#define REG_RF_CTRL 0x001F
48#define REG_LDOA15_CTRL 0x0020
49#define REG_LDOV12D_CTRL 0x0021
50#define REG_LDOHCI12_CTRL 0x0022
51#define REG_LPLDO_CTRL 0x0023
52#define REG_AFE_XTAL_CTRL 0x0024
53#define REG_AFE_LDO_CTRL 0x0027 /* 1.5v for 8188EE test chip, 1.4v for MP chip */
54#define REG_AFE_PLL_CTRL 0x0028
55#define REG_MAC_PHY_CTRL 0x002c
56#define REG_EFUSE_CTRL 0x0030
57#define REG_EFUSE_TEST 0x0034
58#define REG_PWR_DATA 0x0038
59#define REG_CAL_TIMER 0x003C
60#define REG_ACLK_MON 0x003E
61#define REG_GPIO_MUXCFG 0x0040
62#define REG_GPIO_IO_SEL 0x0042
63#define REG_MAC_PINMUX_CFG 0x0043
64#define REG_GPIO_PIN_CTRL 0x0044
65#define REG_GPIO_INTM 0x0048
66#define REG_LEDCFG0 0x004C
67#define REG_LEDCFG1 0x004D
68#define REG_LEDCFG2 0x004E
69#define REG_LEDCFG3 0x004F
70#define REG_FSIMR 0x0050
71#define REG_FSISR 0x0054
72#define REG_HSIMR 0x0058
73#define REG_HSISR 0x005c
74#define REG_GPIO_PIN_CTRL_2 0x0060
75#define REG_GPIO_IO_SEL_2 0x0062
76#define REG_MULTI_FUNC_CTRL 0x0068
77#define REG_GPIO_OUTPUT 0x006c
78#define REG_OPT_CTRL 0x0074
79#define REG_AFE_XTAL_CTRL_EXT 0x0078
80#define REG_XCK_OUT_CTRL 0x007c
81#define REG_MCUFWDL 0x0080
82#define REG_WOL_EVENT 0x0081
83#define REG_MCUTSTCFG 0x0084
84
85
86#define REG_HIMR 0x00B0
87#define REG_HISR 0x00B4
88#define REG_HIMRE 0x00B8
89#define REG_HISRE 0x00BC
90
91#define REG_PMC_DBG_CTRL2 0x00CC
92
93#define REG_EFUSE_ACCESS 0x00CF
94
95#define REG_BIST_SCAN 0x00D0
96#define REG_BIST_RPT 0x00D4
97#define REG_BIST_ROM_RPT 0x00D8
98#define REG_USB_SIE_INTF 0x00E0
99#define REG_PCIE_MIO_INTF 0x00E4
100#define REG_PCIE_MIO_INTD 0x00E8
101#define REG_HPON_FSM 0x00EC
102#define REG_SYS_CFG 0x00F0
103#define REG_GPIO_OUTSTS 0x00F4
104#define REG_SYS_CFG1 0x00FC
105#define REG_ROM_VERSION 0x00FD
106
107#define REG_CR 0x0100
108#define REG_PBP 0x0104
109#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
110#define REG_TRXDMA_CTRL 0x010C
111#define REG_TRXFF_BNDY 0x0114
112#define REG_TRXFF_STATUS 0x0118
113#define REG_RXFF_PTR 0x011C
114
115#define REG_CPWM 0x012F
116#define REG_FWIMR 0x0130
117#define REG_FWISR 0x0134
118#define REG_PKTBUF_DBG_CTRL 0x0140
119#define REG_PKTBUF_DBG_DATA_L 0x0144
120#define REG_PKTBUF_DBG_DATA_H 0x0148
121#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2)
122
123#define REG_TC0_CTRL 0x0150
124#define REG_TC1_CTRL 0x0154
125#define REG_TC2_CTRL 0x0158
126#define REG_TC3_CTRL 0x015C
127#define REG_TC4_CTRL 0x0160
128#define REG_TCUNIT_BASE 0x0164
129#define REG_MBIST_START 0x0174
130#define REG_MBIST_DONE 0x0178
131#define REG_MBIST_FAIL 0x017C
132#define REG_32K_CTRL 0x0194
133#define REG_C2HEVT_MSG_NORMAL 0x01A0
134#define REG_C2HEVT_CLEAR 0x01AF
135#define REG_C2HEVT_MSG_TEST 0x01B8
136#define REG_MCUTST_1 0x01c0
137#define REG_FMETHR 0x01C8
138#define REG_HMETFR 0x01CC
139#define REG_HMEBOX_0 0x01D0
140#define REG_HMEBOX_1 0x01D4
141#define REG_HMEBOX_2 0x01D8
142#define REG_HMEBOX_3 0x01DC
143
144#define REG_LLT_INIT 0x01E0
145#define REG_BB_ACCEESS_CTRL 0x01E8
146#define REG_BB_ACCESS_DATA 0x01EC
147
148#define REG_HMEBOX_EXT_0 0x01F0
149#define REG_HMEBOX_EXT_1 0x01F4
150#define REG_HMEBOX_EXT_2 0x01F8
151#define REG_HMEBOX_EXT_3 0x01FC
152
153#define REG_RQPN 0x0200
154#define REG_FIFOPAGE 0x0204
155#define REG_TDECTRL 0x0208
156#define REG_TXDMA_OFFSET_CHK 0x020C
157#define REG_TXDMA_STATUS 0x0210
158#define REG_RQPN_NPQ 0x0214
159
160#define REG_RXDMA_AGG_PG_TH 0x0280
161#define REG_FW_UPD_RDPTR 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
162#define REG_RXDMA_CONTROL 0x0286 /* Control the RX DMA.*/
163#define REG_RXPKT_NUM 0x0287 /* The number of packets in RXPKTBUF. */
164
165#define REG_PCIE_CTRL_REG 0x0300
166#define REG_INT_MIG 0x0304
167#define REG_BCNQ_DESA 0x0308
168#define REG_HQ_DESA 0x0310
169#define REG_MGQ_DESA 0x0318
170#define REG_VOQ_DESA 0x0320
171#define REG_VIQ_DESA 0x0328
172#define REG_BEQ_DESA 0x0330
173#define REG_BKQ_DESA 0x0338
174#define REG_RX_DESA 0x0340
175
176#define REG_DBI_WDATA 0x0348
177#define REG_DBI_RDATA 0x034C
178#define REG_DBI_ADDR 0x0350
179#define REG_DBI_FLAG 0x0352
180#define REG_MDIO_WDATA 0x0354
181#define REG_MDIO_RDATA 0x0356
182#define REG_MDIO_CTL 0x0358
183#define REG_DBG_SEL 0x0360
184#define REG_PCIE_HRPWM 0x0361
185#define REG_PCIE_HCPWM 0x0363
186#define REG_UART_CTRL 0x0364
187#define REG_WATCH_DOG 0x0368
188#define REG_UART_TX_DESA 0x0370
189#define REG_UART_RX_DESA 0x0378
190
191
192#define REG_HDAQ_DESA_NODEF 0x0000
193#define REG_CMDQ_DESA_NODEF 0x0000
194
195#define REG_VOQ_INFORMATION 0x0400
196#define REG_VIQ_INFORMATION 0x0404
197#define REG_BEQ_INFORMATION 0x0408
198#define REG_BKQ_INFORMATION 0x040C
199#define REG_MGQ_INFORMATION 0x0410
200#define REG_HGQ_INFORMATION 0x0414
201#define REG_BCNQ_INFORMATION 0x0418
202#define REG_TXPKT_EMPTY 0x041A
203
204
205#define REG_CPU_MGQ_INFORMATION 0x041C
206#define REG_FWHW_TXQ_CTRL 0x0420
207#define REG_HWSEQ_CTRL 0x0423
208#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
209#define REG_TXPKTBUF_MGQ_BDNY 0x0425
210#define REG_MULTI_BCNQ_EN 0x0426
211#define REG_MULTI_BCNQ_OFFSET 0x0427
212#define REG_SPEC_SIFS 0x0428
213#define REG_RL 0x042A
214#define REG_DARFRC 0x0430
215#define REG_RARFRC 0x0438
216#define REG_RRSR 0x0440
217#define REG_ARFR0 0x0444
218#define REG_ARFR1 0x044C
219#define REG_CCK_CHECK 0x0454
220#define REG_AMPDU_MAX_TIME 0x0456
221#define REG_AGGLEN_LMT 0x0458
222#define REG_AMPDU_MIN_SPACE 0x045C
223#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
224#define REG_FAST_EDCA_CTRL 0x0460
225#define REG_RD_RESP_PKT_TH 0x0463
226#define REG_INIRTS_RATE_SEL 0x0480
227#define REG_INIDATA_RATE_SEL 0x0484
228#define REG_ARFR2 0x048C
229#define REG_ARFR3 0x0494
230#define REG_POWER_STATUS 0x04A4
231#define REG_POWER_STAGE1 0x04B4
232#define REG_POWER_STAGE2 0x04B8
233#define REG_PKT_LIFE_TIME 0x04C0
234#define REG_STBC_SETTING 0x04C4
235#define REG_HT_SINGLE_AMPDU 0x04C7
236#define REG_PROT_MODE_CTRL 0x04C8
237#define REG_MAX_AGGR_NUM 0x04CA
238#define REG_BAR_MODE_CTRL 0x04CC
239#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
240#define REG_EARLY_MODE_CONTROL 0x04D0
241#define REG_NQOS_SEQ 0x04DC
242#define REG_QOS_SEQ 0x04DE
243#define REG_NEED_CPU_HANDLE 0x04E0
244#define REG_PKT_LOSE_RPT 0x04E1
245#define REG_PTCL_ERR_STATUS 0x04E2
246#define REG_TX_RPT_CTRL 0x04EC
247#define REG_TX_RPT_TIME 0x04F0
248#define REG_DUMMY 0x04FC
249
250#define REG_EDCA_VO_PARAM 0x0500
251#define REG_EDCA_VI_PARAM 0x0504
252#define REG_EDCA_BE_PARAM 0x0508
253#define REG_EDCA_BK_PARAM 0x050C
254#define REG_BCNTCFG 0x0510
255#define REG_PIFS 0x0512
256#define REG_RDG_PIFS 0x0513
257#define REG_SIFS_CTX 0x0514
258#define REG_SIFS_TRX 0x0516
259#define REG_AGGR_BREAK_TIME 0x051A
260#define REG_SLOT 0x051B
261#define REG_TX_PTCL_CTRL 0x0520
262#define REG_TXPAUSE 0x0522
263#define REG_DIS_TXREQ_CLR 0x0523
264#define REG_RD_CTRL 0x0524
265#define REG_TBTT_PROHIBIT 0x0540
266#define REG_RD_NAV_NXT 0x0544
267#define REG_NAV_PROT_LEN 0x0546
268#define REG_BCN_CTRL 0x0550
269#define REG_USTIME_TSF 0x0551
270#define REG_MBID_NUM 0x0552
271#define REG_DUAL_TSF_RST 0x0553
272#define REG_BCN_INTERVAL 0x0554
273#define REG_MBSSID_BCN_SPACE 0x0554
274#define REG_DRVERLYINT 0x0558
275#define REG_BCNDMATIM 0x0559
276#define REG_ATIMWND 0x055A
277#define REG_BCN_MAX_ERR 0x055D
278#define REG_RXTSF_OFFSET_CCK 0x055E
279#define REG_RXTSF_OFFSET_OFDM 0x055F
280#define REG_TSFTR 0x0560
281#define REG_INIT_TSFTR 0x0564
282#define REG_SECONDARY_CCA_CTRL 0x0577
283#define REG_PSTIMER 0x0580
284#define REG_TIMER0 0x0584
285#define REG_TIMER1 0x0588
286#define REG_ACMHWCTRL 0x05C0
287#define REG_ACMRSTCTRL 0x05C1
288#define REG_ACMAVG 0x05C2
289#define REG_VO_ADMTIME 0x05C4
290#define REG_VI_ADMTIME 0x05C6
291#define REG_BE_ADMTIME 0x05C8
292#define REG_EDCA_RANDOM_GEN 0x05CC
293#define REG_NOA_DESC_SEL 0x05CF
294#define REG_NOA_DESC_DURATION 0x05E0
295#define REG_NOA_DESC_INTERVAL 0x05E4
296#define REG_NOA_DESC_START 0x05E8
297#define REG_NOA_DESC_COUNT 0x05EC
298#define REG_SCH_TX_CMD 0x05F8
299
300#define REG_APSD_CTRL 0x0600
301#define REG_BWOPMODE 0x0603
302#define REG_TCR 0x0604
303#define REG_RCR 0x0608
304#define REG_RX_PKT_LIMIT 0x060C
305#define REG_RX_DLK_TIME 0x060D
306#define REG_RX_DRVINFO_SZ 0x060F
307
308#define REG_MACID 0x0610
309#define REG_BSSID 0x0618
310#define REG_MAR 0x0620
311#define REG_MBIDCAMCFG 0x0628
312
313#define REG_USTIME_EDCA 0x0638
314#define REG_MAC_SPEC_SIFS 0x063A
315#define REG_RESP_SIFS_CCK 0x063C
316#define REG_RESP_SIFS_OFDM 0x063E
317#define REG_ACKTO 0x0640
318#define REG_CTS2TO 0x0641
319#define REG_EIFS 0x0642
320
321#define REG_NAV_CTRL 0x0650
322#define REG_NAV_UPPER 0x0652
323#define REG_BACAMCMD 0x0654
324#define REG_BACAMCONTENT 0x0658
325#define REG_LBDLY 0x0660
326#define REG_FWDLY 0x0661
327#define REG_RXERR_RPT 0x0664
328#define REG_TRXPTCL_CTL 0x0668
329
330#define REG_CAMCMD 0x0670
331#define REG_CAMWRITE 0x0674
332#define REG_CAMREAD 0x0678
333#define REG_CAMDBG 0x067C
334#define REG_SECCFG 0x0680
335
336#define REG_WOW_CTRL 0x0690
337#define REG_PSSTATUS 0x0691
338#define REG_PS_RX_INFO 0x0692
339#define REG_UAPSD_TID 0x0693
340#define REG_LPNAV_CTRL 0x0694
341#define REG_WKFMCAM_NUM 0x0698
342#define REG_WKFMCAM_RWD 0x069C
343#define REG_RXFLTMAP0 0x06A0
344#define REG_RXFLTMAP1 0x06A2
345#define REG_RXFLTMAP2 0x06A4
346#define REG_BCN_PSR_RPT 0x06A8
347#define REG_CALB32K_CTRL 0x06AC
348#define REG_PKT_MON_CTRL 0x06B4
349#define REG_BT_COEX_TABLE 0x06C0
350#define REG_WMAC_RESP_TXINFO 0x06D8
351
352#define REG_USB_INFO 0xFE17
353#define REG_USB_SPECIAL_OPTION 0xFE55
354#define REG_USB_DMA_AGG_TO 0xFE5B
355#define REG_USB_AGG_TO 0xFE5C
356#define REG_USB_AGG_TH 0xFE5D
357
358#define REG_TEST_USB_TXQS 0xFE48
359#define REG_TEST_SIE_VID 0xFE60
360#define REG_TEST_SIE_PID 0xFE62
361#define REG_TEST_SIE_OPTIONAL 0xFE64
362#define REG_TEST_SIE_CHIRP_K 0xFE65
363#define REG_TEST_SIE_PHY 0xFE66
364#define REG_TEST_SIE_MAC_ADDR 0xFE70
365#define REG_TEST_SIE_STRING 0xFE80
366
367#define REG_NORMAL_SIE_VID 0xFE60
368#define REG_NORMAL_SIE_PID 0xFE62
369#define REG_NORMAL_SIE_OPTIONAL 0xFE64
370#define REG_NORMAL_SIE_EP 0xFE65
371#define REG_NORMAL_SIE_PHY 0xFE68
372#define REG_NORMAL_SIE_MAC_ADDR 0xFE70
373#define REG_NORMAL_SIE_STRING 0xFE80
374
375#define CR9346 REG_9346CR
376#define MSR (REG_CR + 2)
377#define ISR REG_HISR
378#define TSFR REG_TSFTR
379
380#define MACIDR0 REG_MACID
381#define MACIDR4 (REG_MACID + 4)
382
383#define PBP REG_PBP
384
385#define IDR0 MACIDR0
386#define IDR4 MACIDR4
387
388#define UNUSED_REGISTER 0x1BF
389#define DCAM UNUSED_REGISTER
390#define PSR UNUSED_REGISTER
391#define BBADDR UNUSED_REGISTER
392#define PHYDATAR UNUSED_REGISTER
393
394#define INVALID_BBRF_VALUE 0x12345678
395
396#define MAX_MSS_DENSITY_2T 0x13
397#define MAX_MSS_DENSITY_1T 0x0A
398
399#define CMDEEPROM_EN BIT(5)
400#define CMDEEPROM_SEL BIT(4)
401#define CMD9346CR_9356SEL BIT(4)
402#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL)
403#define AUTOLOAD_EFUSE CMDEEPROM_EN
404
405#define GPIOSEL_GPIO 0
406#define GPIOSEL_ENBT BIT(5)
407
408#define GPIO_IN REG_GPIO_PIN_CTRL
409#define GPIO_OUT (REG_GPIO_PIN_CTRL+1)
410#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)
411#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
412
413/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
414#define HSIMR_GPIO12_0_INT_EN BIT(0)
415#define HSIMR_SPS_OCP_INT_EN BIT(5)
416#define HSIMR_RON_INT_EN BIT(6)
417#define HSIMR_PDN_INT_EN BIT(7)
418#define HSIMR_GPIO9_INT_EN BIT(25)
419
420
421/*
422* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte)
423*/
424#define HSISR_GPIO12_0_INT BIT(0)
425#define HSISR_SPS_OCP_INT BIT(5)
426#define HSISR_RON_INT_EN BIT(6)
427#define HSISR_PDNINT BIT(7)
428#define HSISR_GPIO9_INT BIT(25)
429
430#define MSR_NOLINK 0x00
431#define MSR_ADHOC 0x01
432#define MSR_INFRA 0x02
433#define MSR_AP 0x03
434
435#define RRSR_RSC_OFFSET 21
436#define RRSR_SHORT_OFFSET 23
437#define RRSR_RSC_BW_40M 0x600000
438#define RRSR_RSC_UPSUBCHNL 0x400000
439#define RRSR_RSC_LOWSUBCHNL 0x200000
440#define RRSR_SHORT 0x800000
441#define RRSR_1M BIT(0)
442#define RRSR_2M BIT(1)
443#define RRSR_5_5M BIT(2)
444#define RRSR_11M BIT(3)
445#define RRSR_6M BIT(4)
446#define RRSR_9M BIT(5)
447#define RRSR_12M BIT(6)
448#define RRSR_18M BIT(7)
449#define RRSR_24M BIT(8)
450#define RRSR_36M BIT(9)
451#define RRSR_48M BIT(10)
452#define RRSR_54M BIT(11)
453#define RRSR_MCS0 BIT(12)
454#define RRSR_MCS1 BIT(13)
455#define RRSR_MCS2 BIT(14)
456#define RRSR_MCS3 BIT(15)
457#define RRSR_MCS4 BIT(16)
458#define RRSR_MCS5 BIT(17)
459#define RRSR_MCS6 BIT(18)
460#define RRSR_MCS7 BIT(19)
461#define BRSR_ACKSHORTPMB BIT(23)
462
463#define RATR_1M 0x00000001
464#define RATR_2M 0x00000002
465#define RATR_55M 0x00000004
466#define RATR_11M 0x00000008
467#define RATR_6M 0x00000010
468#define RATR_9M 0x00000020
469#define RATR_12M 0x00000040
470#define RATR_18M 0x00000080
471#define RATR_24M 0x00000100
472#define RATR_36M 0x00000200
473#define RATR_48M 0x00000400
474#define RATR_54M 0x00000800
475#define RATR_MCS0 0x00001000
476#define RATR_MCS1 0x00002000
477#define RATR_MCS2 0x00004000
478#define RATR_MCS3 0x00008000
479#define RATR_MCS4 0x00010000
480#define RATR_MCS5 0x00020000
481#define RATR_MCS6 0x00040000
482#define RATR_MCS7 0x00080000
483#define RATR_MCS8 0x00100000
484#define RATR_MCS9 0x00200000
485#define RATR_MCS10 0x00400000
486#define RATR_MCS11 0x00800000
487#define RATR_MCS12 0x01000000
488#define RATR_MCS13 0x02000000
489#define RATR_MCS14 0x04000000
490#define RATR_MCS15 0x08000000
491
492#define RATE_1M BIT(0)
493#define RATE_2M BIT(1)
494#define RATE_5_5M BIT(2)
495#define RATE_11M BIT(3)
496#define RATE_6M BIT(4)
497#define RATE_9M BIT(5)
498#define RATE_12M BIT(6)
499#define RATE_18M BIT(7)
500#define RATE_24M BIT(8)
501#define RATE_36M BIT(9)
502#define RATE_48M BIT(10)
503#define RATE_54M BIT(11)
504#define RATE_MCS0 BIT(12)
505#define RATE_MCS1 BIT(13)
506#define RATE_MCS2 BIT(14)
507#define RATE_MCS3 BIT(15)
508#define RATE_MCS4 BIT(16)
509#define RATE_MCS5 BIT(17)
510#define RATE_MCS6 BIT(18)
511#define RATE_MCS7 BIT(19)
512#define RATE_MCS8 BIT(20)
513#define RATE_MCS9 BIT(21)
514#define RATE_MCS10 BIT(22)
515#define RATE_MCS11 BIT(23)
516#define RATE_MCS12 BIT(24)
517#define RATE_MCS13 BIT(25)
518#define RATE_MCS14 BIT(26)
519#define RATE_MCS15 BIT(27)
520
521#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
522#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\
523 RATR_24M| RATR_36M | RATR_48M | RATR_54M)
524#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\
525 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\
526 RATR_MCS6 | RATR_MCS7)
527#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\
528 RATR_MCS11| RATR_MCS12 | RATR_MCS13 |\
529 RATR_MCS14 | RATR_MCS15)
530
531#define BW_OPMODE_20MHZ BIT(2)
532#define BW_OPMODE_5G BIT(1)
533#define BW_OPMODE_11J BIT(0)
534
535#define CAM_VALID BIT(15)
536#define CAM_NOTVALID 0x0000
537#define CAM_USEDK BIT(5)
538
539#define CAM_NONE 0x0
540#define CAM_WEP40 0x01
541#define CAM_TKIP 0x02
542#define CAM_AES 0x04
543#define CAM_WEP104 0x05
544
545#define TOTAL_CAM_ENTRY 32
546#define HALF_CAM_ENTRY 16
547
548#define CAM_WRITE BIT(16)
549#define CAM_READ 0x00000000
550#define CAM_POLLINIG BIT(31)
551
552#define SCR_USEDK 0x01
553#define SCR_TXSEC_ENABLE 0x02
554#define SCR_RXSEC_ENABLE 0x04
555
556#define WOW_PMEN BIT(0)
557#define WOW_WOMEN BIT(1)
558#define WOW_MAGIC BIT(2)
559#define WOW_UWF BIT(3)
560
561/*********************************************
562* 8188 IMR/ISR bits
563**********************************************/
564#define IMR_DISABLED 0x0
565/* IMR DW0(0x0060-0063) Bit 0-31 */
566#define IMR_TXCCK BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */
567#define IMR_PSTIMEOUT BIT(29) /* Power Save Time Out Interrupt */
568#define IMR_GTINT4 BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
569#define IMR_GTINT3 BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
570#define IMR_TBDER BIT(26) /* Transmit Beacon0 Error */
571#define IMR_TBDOK BIT(25) /* Transmit Beacon0 OK */
572#define IMR_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle indication interrupt */
573#define IMR_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
574#define IMR_BCNDOK0 BIT(16) /* Beacon Queue DMA OK0 */
575#define IMR_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
576#define IMR_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
577#define IMR_ATIMEND BIT(12) /* CTWidnow End or ATIM Window End */
578#define IMR_HISR1_IND_INT BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)*/
579#define IMR_C2HCMD BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
580#define IMR_CPWM2 BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
581#define IMR_CPWM BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
582#define IMR_HIGHDOK BIT(7) /* High Queue DMA OK */
583#define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK */
584#define IMR_BKDOK BIT(5) /* AC_BK DMA OK */
585#define IMR_BEDOK BIT(4) /* AC_BE DMA OK */
586#define IMR_VIDOK BIT(3) /* AC_VI DMA OK */
587#define IMR_VODOK BIT(2) /* AC_VO DMA OK */
588#define IMR_RDU BIT(1) /* Rx Descriptor Unavailable */
589#define IMR_ROK BIT(0) /* Receive DMA OK */
590
591/* IMR DW1(0x00B4-00B7) Bit 0-31 */
592#define IMR_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */
593#define IMR_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */
594#define IMR_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */
595#define IMR_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */
596#define IMR_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
597#define IMR_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
598#define IMR_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
599#define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrup 7 */
600#define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrup 6 */
601#define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrup 5 */
602#define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrup 4 */
603#define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrup 3 */
604#define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrup 2 */
605#define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrup 1 */
606#define IMR_ATIMEND_E BIT(13) /* ATIM Window End Extension for Win7 */
607#define IMR_TXERR BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */
608#define IMR_RXERR BIT(10) /* Rx Error Flag INT Status, Write 1 clear */
609#define IMR_TXFOVW BIT(9) /* Transmit FIFO Overflow */
610#define IMR_RXFOVW BIT(8) /* Receive FIFO Overflow */
611
612
613#define HWSET_MAX_SIZE 512
614#define EFUSE_MAX_SECTION 64
615#define EFUSE_REAL_CONTENT_LEN 256
616#define EFUSE_OOB_PROTECT_BYTES 18 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/
617
618
619#define EEPROM_DEFAULT_TSSI 0x0
620#define EEPROM_DEFAULT_TXPOWERDIFF 0x0
621#define EEPROM_DEFAULT_CRYSTALCAP 0x5
622#define EEPROM_DEFAULT_BOARDTYPE 0x02
623#define EEPROM_DEFAULT_TXPOWER 0x1010
624#define EEPROM_DEFAULT_HT2T_TXPWR 0x10
625
626#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
627#define EEPROM_DEFAULT_THERMALMETER 0x18
628#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0
629#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5
630#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22
631#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
632#define EEPROM_DEFAULT_HT20_DIFF 2
633#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
634#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
635#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
636
637#define RF_OPTION1 0x79
638#define RF_OPTION2 0x7A
639#define RF_OPTION3 0x7B
640#define RF_OPTION4 0xC3
641
642#define EEPROM_DEFAULT_PID 0x1234
643#define EEPROM_DEFAULT_VID 0x5678
644#define EEPROM_DEFAULT_CUSTOMERID 0xAB
645#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD
646#define EEPROM_DEFAULT_VERSION 0
647
648#define EEPROM_CHANNEL_PLAN_FCC 0x0
649#define EEPROM_CHANNEL_PLAN_IC 0x1
650#define EEPROM_CHANNEL_PLAN_ETSI 0x2
651#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
652#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
653#define EEPROM_CHANNEL_PLAN_MKK 0x5
654#define EEPROM_CHANNEL_PLAN_MKK1 0x6
655#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
656#define EEPROM_CHANNEL_PLAN_TELEC 0x8
657#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
658#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
659#define EEPROM_CHANNEL_PLAN_NCC 0xB
660#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
661
662#define EEPROM_CID_DEFAULT 0x0
663#define EEPROM_CID_TOSHIBA 0x4
664#define EEPROM_CID_CCX 0x10
665#define EEPROM_CID_QMI 0x0D
666#define EEPROM_CID_WHQL 0xFE
667
668#define RTL_EEPROM_ID 0x8129
669
670#define EEPROM_HPON 0x02
671#define EEPROM_CLK 0x06
672#define EEPROM_TESTR 0x08
673
674
675#define EEPROM_TXPOWERCCK 0x10
676#define EEPROM_TXPOWERHT40_1S 0x16
677#define EEPROM_TXPOWERHT20DIFF 0x1B
678#define EEPROM_TXPOWER_OFDMDIFF 0x1B
679
680
681
682#define EEPROM_TX_PWR_INX 0x10
683
684#define EEPROM_CHANNELPLAN 0xB8
685#define EEPROM_XTAL_8821AE 0xB9
686#define EEPROM_THERMAL_METER 0xBA
687#define EEPROM_IQK_LCK_88E 0xBB
688
689#define EEPROM_RF_BOARD_OPTION 0xC1
690#define EEPROM_RF_FEATURE_OPTION_88E 0xC2
691#define EEPROM_RF_BT_SETTING 0xC3
692#define EEPROM_VERSION 0xC4
693#define EEPROM_CUSTOMER_ID 0xC5
694#define EEPROM_RF_ANTENNA_OPT_88E 0xC9
695
696#define EEPROM_MAC_ADDR 0xD0
697#define EEPROM_VID 0xD6
698#define EEPROM_DID 0xD8
699#define EEPROM_SVID 0xDA
700#define EEPROM_SMID 0xDC
701
702#define STOPBECON BIT(6)
703#define STOPHIGHT BIT(5)
704#define STOPMGT BIT(4)
705#define STOPVO BIT(3)
706#define STOPVI BIT(2)
707#define STOPBE BIT(1)
708#define STOPBK BIT(0)
709
710#define RCR_APPFCS BIT(31)
711#define RCR_APP_MIC BIT(30)
712#define RCR_APP_ICV BIT(29)
713#define RCR_APP_PHYST_RXFF BIT(28)
714#define RCR_APP_BA_SSN BIT(27)
715#define RCR_NONQOS_VHT BIT(26)
716#define RCR_ENMBID BIT(24)
717#define RCR_LSIGEN BIT(23)
718#define RCR_MFBEN BIT(22)
719#define RCR_HTC_LOC_CTRL BIT(14)
720#define RCR_AMF BIT(13)
721#define RCR_ACF BIT(12)
722#define RCR_ADF BIT(11)
723#define RCR_AICV BIT(9)
724#define RCR_ACRC32 BIT(8)
725#define RCR_CBSSID_BCN BIT(7)
726#define RCR_CBSSID_DATA BIT(6)
727#define RCR_CBSSID RCR_CBSSID_DATA
728#define RCR_APWRMGT BIT(5)
729#define RCR_ADD3 BIT(4)
730#define RCR_AB BIT(3)
731#define RCR_AM BIT(2)
732#define RCR_APM BIT(1)
733#define RCR_AAP BIT(0)
734#define RCR_MXDMA_OFFSET 8
735#define RCR_FIFO_OFFSET 13
736
737#define RSV_CTRL 0x001C
738#define RD_CTRL 0x0524
739
740#define REG_USB_INFO 0xFE17
741#define REG_USB_SPECIAL_OPTION 0xFE55
742#define REG_USB_DMA_AGG_TO 0xFE5B
743#define REG_USB_AGG_TO 0xFE5C
744#define REG_USB_AGG_TH 0xFE5D
745
746#define REG_USB_VID 0xFE60
747#define REG_USB_PID 0xFE62
748#define REG_USB_OPTIONAL 0xFE64
749#define REG_USB_CHIRP_K 0xFE65
750#define REG_USB_PHY 0xFE66
751#define REG_USB_MAC_ADDR 0xFE70
752#define REG_USB_HRPWM 0xFE58
753#define REG_USB_HCPWM 0xFE57
754
755#define SW18_FPWM BIT(3)
756
757#define ISO_MD2PP BIT(0)
758#define ISO_UA2USB BIT(1)
759#define ISO_UD2CORE BIT(2)
760#define ISO_PA2PCIE BIT(3)
761#define ISO_PD2CORE BIT(4)
762#define ISO_IP2MAC BIT(5)
763#define ISO_DIOP BIT(6)
764#define ISO_DIOE BIT(7)
765#define ISO_EB2CORE BIT(8)
766#define ISO_DIOR BIT(9)
767
768#define PWC_EV25V BIT(14)
769#define PWC_EV12V BIT(15)
770
771#define FEN_BBRSTB BIT(0)
772#define FEN_BB_GLB_RSTN BIT(1)
773#define FEN_USBA BIT(2)
774#define FEN_UPLL BIT(3)
775#define FEN_USBD BIT(4)
776#define FEN_DIO_PCIE BIT(5)
777#define FEN_PCIEA BIT(6)
778#define FEN_PPLL BIT(7)
779#define FEN_PCIED BIT(8)
780#define FEN_DIOE BIT(9)
781#define FEN_CPUEN BIT(10)
782#define FEN_DCORE BIT(11)
783#define FEN_ELDR BIT(12)
784#define FEN_DIO_RF BIT(13)
785#define FEN_HWPDN BIT(14)
786#define FEN_MREGEN BIT(15)
787
788#define PFM_LDALL BIT(0)
789#define PFM_ALDN BIT(1)
790#define PFM_LDKP BIT(2)
791#define PFM_WOWL BIT(3)
792#define EnPDN BIT(4)
793#define PDN_PL BIT(5)
794#define APFM_ONMAC BIT(8)
795#define APFM_OFF BIT(9)
796#define APFM_RSM BIT(10)
797#define AFSM_HSUS BIT(11)
798#define AFSM_PCIE BIT(12)
799#define APDM_MAC BIT(13)
800#define APDM_HOST BIT(14)
801#define APDM_HPDN BIT(15)
802#define RDY_MACON BIT(16)
803#define SUS_HOST BIT(17)
804#define ROP_ALD BIT(20)
805#define ROP_PWR BIT(21)
806#define ROP_SPS BIT(22)
807#define SOP_MRST BIT(25)
808#define SOP_FUSE BIT(26)
809#define SOP_ABG BIT(27)
810#define SOP_AMB BIT(28)
811#define SOP_RCK BIT(29)
812#define SOP_A8M BIT(30)
813#define XOP_BTCK BIT(31)
814
815#define ANAD16V_EN BIT(0)
816#define ANA8M BIT(1)
817#define MACSLP BIT(4)
818#define LOADER_CLK_EN BIT(5)
819#define _80M_SSC_DIS BIT(7)
820#define _80M_SSC_EN_HO BIT(8)
821#define PHY_SSC_RSTB BIT(9)
822#define SEC_CLK_EN BIT(10)
823#define MAC_CLK_EN BIT(11)
824#define SYS_CLK_EN BIT(12)
825#define RING_CLK_EN BIT(13)
826
827#define BOOT_FROM_EEPROM BIT(4)
828#define EEPROM_EN BIT(5)
829
830#define AFE_BGEN BIT(0)
831#define AFE_MBEN BIT(1)
832#define MAC_ID_EN BIT(7)
833
834#define WLOCK_ALL BIT(0)
835#define WLOCK_00 BIT(1)
836#define WLOCK_04 BIT(2)
837#define WLOCK_08 BIT(3)
838#define WLOCK_40 BIT(4)
839#define R_DIS_PRST_0 BIT(5)
840#define R_DIS_PRST_1 BIT(6)
841#define LOCK_ALL_EN BIT(7)
842
843#define RF_EN BIT(0)
844#define RF_RSTB BIT(1)
845#define RF_SDMRSTB BIT(2)
846
847#define LDA15_EN BIT(0)
848#define LDA15_STBY BIT(1)
849#define LDA15_OBUF BIT(2)
850#define LDA15_REG_VOS BIT(3)
851#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
852
853#define LDV12_EN BIT(0)
854#define LDV12_SDBY BIT(1)
855#define LPLDO_HSM BIT(2)
856#define LPLDO_LSM_DIS BIT(3)
857#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
858
859#define XTAL_EN BIT(0)
860#define XTAL_BSEL BIT(1)
861#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
862#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
863#define XTAL_GATE_USB BIT(8)
864#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
865#define XTAL_GATE_AFE BIT(11)
866#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
867#define XTAL_RF_GATE BIT(14)
868#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
869#define XTAL_GATE_DIG BIT(17)
870#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
871#define XTAL_BT_GATE BIT(20)
872#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
873#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
874
875#define CKDLY_AFE BIT(26)
876#define CKDLY_USB BIT(27)
877#define CKDLY_DIG BIT(28)
878#define CKDLY_BT BIT(29)
879
880#define APLL_EN BIT(0)
881#define APLL_320_EN BIT(1)
882#define APLL_FREF_SEL BIT(2)
883#define APLL_EDGE_SEL BIT(3)
884#define APLL_WDOGB BIT(4)
885#define APLL_LPFEN BIT(5)
886
887#define APLL_REF_CLK_13MHZ 0x1
888#define APLL_REF_CLK_19_2MHZ 0x2
889#define APLL_REF_CLK_20MHZ 0x3
890#define APLL_REF_CLK_25MHZ 0x4
891#define APLL_REF_CLK_26MHZ 0x5
892#define APLL_REF_CLK_38_4MHZ 0x6
893#define APLL_REF_CLK_40MHZ 0x7
894
895#define APLL_320EN BIT(14)
896#define APLL_80EN BIT(15)
897#define APLL_1MEN BIT(24)
898
899#define ALD_EN BIT(18)
900#define EF_PD BIT(19)
901#define EF_FLAG BIT(31)
902
903#define EF_TRPT BIT(7)
904#define LDOE25_EN BIT(31)
905
906#define RSM_EN BIT(0)
907#define Timer_EN BIT(4)
908
909#define TRSW0EN BIT(2)
910#define TRSW1EN BIT(3)
911#define EROM_EN BIT(4)
912#define EnBT BIT(5)
913#define EnUart BIT(8)
914#define Uart_910 BIT(9)
915#define EnPMAC BIT(10)
916#define SIC_SWRST BIT(11)
917#define EnSIC BIT(12)
918#define SIC_23 BIT(13)
919#define EnHDP BIT(14)
920#define SIC_LBK BIT(15)
921
922#define LED0PL BIT(4)
923#define LED1PL BIT(12)
924#define LED0DIS BIT(7)
925
926#define MCUFWDL_EN BIT(0)
927#define MCUFWDL_RDY BIT(1)
928#define FWDL_CHKSUM_RPT BIT(2)
929#define MACINI_RDY BIT(3)
930#define BBINI_RDY BIT(4)
931#define RFINI_RDY BIT(5)
932#define WINTINI_RDY BIT(6)
933#define CPRST BIT(23)
934
935#define XCLK_VLD BIT(0)
936#define ACLK_VLD BIT(1)
937#define UCLK_VLD BIT(2)
938#define PCLK_VLD BIT(3)
939#define PCIRSTB BIT(4)
940#define V15_VLD BIT(5)
941#define TRP_B15V_EN BIT(7)
942#define SIC_IDLE BIT(8)
943#define BD_MAC2 BIT(9)
944#define BD_MAC1 BIT(10)
945#define IC_MACPHY_MODE BIT(11)
946#define VENDOR_ID BIT(19)
947#define PAD_HWPD_IDN BIT(22)
948#define TRP_VAUX_EN BIT(23)
949#define TRP_BT_EN BIT(24)
950#define BD_PKG_SEL BIT(25)
951#define BD_HCI_SEL BIT(26)
952#define TYPE_ID BIT(27)
953
954#define CHIP_VER_RTL_MASK 0xF000
955#define CHIP_VER_RTL_SHIFT 12
956
957#define REG_LBMODE (REG_CR + 3)
958
959#define HCI_TXDMA_EN BIT(0)
960#define HCI_RXDMA_EN BIT(1)
961#define TXDMA_EN BIT(2)
962#define RXDMA_EN BIT(3)
963#define PROTOCOL_EN BIT(4)
964#define SCHEDULE_EN BIT(5)
965#define MACTXEN BIT(6)
966#define MACRXEN BIT(7)
967#define ENSWBCN BIT(8)
968#define ENSEC BIT(9)
969
970#define _NETTYPE(x) (((x) & 0x3) << 16)
971#define MASK_NETTYPE 0x30000
972#define NT_NO_LINK 0x0
973#define NT_LINK_AD_HOC 0x1
974#define NT_LINK_AP 0x2
975#define NT_AS_AP 0x3
976
977#define _LBMODE(x) (((x) & 0xF) << 24)
978#define MASK_LBMODE 0xF000000
979#define LOOPBACK_NORMAL 0x0
980#define LOOPBACK_IMMEDIATELY 0xB
981#define LOOPBACK_MAC_DELAY 0x3
982#define LOOPBACK_PHY 0x1
983#define LOOPBACK_DMA 0x7
984
985#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
986#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
987#define _PSRX_MASK 0xF
988#define _PSTX_MASK 0xF0
989#define _PSRX(x) (x)
990#define _PSTX(x) ((x) << 4)
991
992#define PBP_64 0x0
993#define PBP_128 0x1
994#define PBP_256 0x2
995#define PBP_512 0x3
996#define PBP_1024 0x4
997
998#define RXDMA_ARBBW_EN BIT(0)
999#define RXSHFT_EN BIT(1)
1000#define RXDMA_AGG_EN BIT(2)
1001#define QS_VO_QUEUE BIT(8)
1002#define QS_VI_QUEUE BIT(9)
1003#define QS_BE_QUEUE BIT(10)
1004#define QS_BK_QUEUE BIT(11)
1005#define QS_MANAGER_QUEUE BIT(12)
1006#define QS_HIGH_QUEUE BIT(13)
1007
1008#define HQSEL_VOQ BIT(0)
1009#define HQSEL_VIQ BIT(1)
1010#define HQSEL_BEQ BIT(2)
1011#define HQSEL_BKQ BIT(3)
1012#define HQSEL_MGTQ BIT(4)
1013#define HQSEL_HIQ BIT(5)
1014
1015#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)
1016#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)
1017#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)
1018#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 )
1019#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 )
1020#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 )
1021
1022#define QUEUE_LOW 1
1023#define QUEUE_NORMAL 2
1024#define QUEUE_HIGH 3
1025
1026#define _LLT_NO_ACTIVE 0x0
1027#define _LLT_WRITE_ACCESS 0x1
1028#define _LLT_READ_ACCESS 0x2
1029
1030#define _LLT_INIT_DATA(x) ((x) & 0xFF)
1031#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
1032#define _LLT_OP(x) (((x) & 0x3) << 30)
1033#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
1034
1035#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
1036#define BB_WRITE_EN BIT(30)
1037#define BB_READ_EN BIT(31)
1038
1039#define _HPQ(x) ((x) & 0xFF)
1040#define _LPQ(x) (((x) & 0xFF) << 8)
1041#define _PUBQ(x) (((x) & 0xFF) << 16)
1042#define _NPQ(x) ((x) & 0xFF)
1043
1044#define HPQ_PUBLIC_DIS BIT(24)
1045#define LPQ_PUBLIC_DIS BIT(25)
1046#define LD_RQPN BIT(31)
1047
1048#define BCN_VALID BIT(16)
1049#define BCN_HEAD(x) (((x) & 0xFF) << 8)
1050#define BCN_HEAD_MASK 0xFF00
1051
1052#define BLK_DESC_NUM_SHIFT 4
1053#define BLK_DESC_NUM_MASK 0xF
1054
1055#define DROP_DATA_EN BIT(9)
1056
1057#define EN_AMPDU_RTY_NEW BIT(7)
1058
1059#define _INIRTSMCS_SEL(x) ((x) & 0x3F)
1060
1061#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
1062#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
1063
1064#define RATE_REG_BITMAP_ALL 0xFFFFF
1065
1066#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
1067
1068#define _RRSR_RSC(x) (((x) & 0x3) << 21)
1069#define RRSR_RSC_RESERVED 0x0
1070#define RRSR_RSC_UPPER_SUBCHANNEL 0x1
1071#define RRSR_RSC_LOWER_SUBCHANNEL 0x2
1072#define RRSR_RSC_DUPLICATE_MODE 0x3
1073
1074#define USE_SHORT_G1 BIT(20)
1075
1076#define _AGGLMT_MCS0(x) ((x) & 0xF)
1077#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
1078#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
1079#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
1080#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
1081#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
1082#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
1083#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
1084
1085#define RETRY_LIMIT_SHORT_SHIFT 8
1086#define RETRY_LIMIT_LONG_SHIFT 0
1087
1088#define _DARF_RC1(x) ((x) & 0x1F)
1089#define _DARF_RC2(x) (((x) & 0x1F) << 8)
1090#define _DARF_RC3(x) (((x) & 0x1F) << 16)
1091#define _DARF_RC4(x) (((x) & 0x1F) << 24)
1092#define _DARF_RC5(x) ((x) & 0x1F)
1093#define _DARF_RC6(x) (((x) & 0x1F) << 8)
1094#define _DARF_RC7(x) (((x) & 0x1F) << 16)
1095#define _DARF_RC8(x) (((x) & 0x1F) << 24)
1096
1097#define _RARF_RC1(x) ((x) & 0x1F)
1098#define _RARF_RC2(x) (((x) & 0x1F) << 8)
1099#define _RARF_RC3(x) (((x) & 0x1F) << 16)
1100#define _RARF_RC4(x) (((x) & 0x1F) << 24)
1101#define _RARF_RC5(x) ((x) & 0x1F)
1102#define _RARF_RC6(x) (((x) & 0x1F) << 8)
1103#define _RARF_RC7(x) (((x) & 0x1F) << 16)
1104#define _RARF_RC8(x) (((x) & 0x1F) << 24)
1105
1106#define AC_PARAM_TXOP_LIMIT_OFFSET 16
1107#define AC_PARAM_ECW_MAX_OFFSET 12
1108#define AC_PARAM_ECW_MIN_OFFSET 8
1109#define AC_PARAM_AIFS_OFFSET 0
1110
1111#define _AIFS(x) (x)
1112#define _ECW_MAX_MIN(x) ((x) << 8)
1113#define _TXOP_LIMIT(x) ((x) << 16)
1114
1115#define _BCNIFS(x) ((x) & 0xFF)
1116#define _BCNECW(x) ((((x) & 0xF))<< 8)
1117
1118#define _LRL(x) ((x) & 0x3F)
1119#define _SRL(x) (((x) & 0x3F) << 8)
1120
1121#define _SIFS_CCK_CTX(x) ((x) & 0xFF)
1122#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8);
1123
1124#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
1125#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8);
1126
1127#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
1128
1129#define DIS_EDCA_CNT_DWN BIT(11)
1130
1131#define EN_MBSSID BIT(1)
1132#define EN_TXBCN_RPT BIT(2)
1133#define EN_BCN_FUNCTION BIT(3)
1134
1135#define TSFTR_RST BIT(0)
1136#define TSFTR1_RST BIT(1)
1137
1138#define STOP_BCNQ BIT(6)
1139
1140#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
1141#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
1142
1143#define AcmHw_HwEn BIT(0)
1144#define AcmHw_BeqEn BIT(1)
1145#define AcmHw_ViqEn BIT(2)
1146#define AcmHw_VoqEn BIT(3)
1147#define AcmHw_BeqStatus BIT(4)
1148#define AcmHw_ViqStatus BIT(5)
1149#define AcmHw_VoqStatus BIT(6)
1150
1151#define APSDOFF BIT(6)
1152#define APSDOFF_STATUS BIT(7)
1153
1154#define BW_20MHZ BIT(2)
1155
1156#define RATE_BITMAP_ALL 0xFFFFF
1157
1158#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
1159
1160#define TSFRST BIT(0)
1161#define DIS_GCLK BIT(1)
1162#define PAD_SEL BIT(2)
1163#define PWR_ST BIT(6)
1164#define PWRBIT_OW_EN BIT(7)
1165#define ACRC BIT(8)
1166#define CFENDFORM BIT(9)
1167#define ICV BIT(10)
1168
1169#define AAP BIT(0)
1170#define APM BIT(1)
1171#define AM BIT(2)
1172#define AB BIT(3)
1173#define ADD3 BIT(4)
1174#define APWRMGT BIT(5)
1175#define CBSSID BIT(6)
1176#define CBSSID_DATA BIT(6)
1177#define CBSSID_BCN BIT(7)
1178#define ACRC32 BIT(8)
1179#define AICV BIT(9)
1180#define ADF BIT(11)
1181#define ACF BIT(12)
1182#define AMF BIT(13)
1183#define HTC_LOC_CTRL BIT(14)
1184#define UC_DATA_EN BIT(16)
1185#define BM_DATA_EN BIT(17)
1186#define MFBEN BIT(22)
1187#define LSIGEN BIT(23)
1188#define EnMBID BIT(24)
1189#define APP_BASSN BIT(27)
1190#define APP_PHYSTS BIT(28)
1191#define APP_ICV BIT(29)
1192#define APP_MIC BIT(30)
1193#define APP_FCS BIT(31)
1194
1195#define _MIN_SPACE(x) ((x) & 0x7)
1196#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
1197
1198#define RXERR_TYPE_OFDM_PPDU 0
1199#define RXERR_TYPE_OFDM_FALSE_ALARM 1
1200#define RXERR_TYPE_OFDM_MPDU_OK 2
1201#define RXERR_TYPE_OFDM_MPDU_FAIL 3
1202#define RXERR_TYPE_CCK_PPDU 4
1203#define RXERR_TYPE_CCK_FALSE_ALARM 5
1204#define RXERR_TYPE_CCK_MPDU_OK 6
1205#define RXERR_TYPE_CCK_MPDU_FAIL 7
1206#define RXERR_TYPE_HT_PPDU 8
1207#define RXERR_TYPE_HT_FALSE_ALARM 9
1208#define RXERR_TYPE_HT_MPDU_TOTAL 10
1209#define RXERR_TYPE_HT_MPDU_OK 11
1210#define RXERR_TYPE_HT_MPDU_FAIL 12
1211#define RXERR_TYPE_RX_FULL_DROP 15
1212
1213#define RXERR_COUNTER_MASK 0xFFFFF
1214#define RXERR_RPT_RST BIT(27)
1215#define _RXERR_RPT_SEL(type) ((type) << 28)
1216
1217#define SCR_TxUseDK BIT(0)
1218#define SCR_RxUseDK BIT(1)
1219#define SCR_TxEncEnable BIT(2)
1220#define SCR_RxDecEnable BIT(3)
1221#define SCR_SKByA2 BIT(4)
1222#define SCR_NoSKMC BIT(5)
1223#define SCR_TXBCUSEDK BIT(6)
1224#define SCR_RXBCUSEDK BIT(7)
1225
1226#define XCLK_VLD BIT(0)
1227#define ACLK_VLD BIT(1)
1228#define UCLK_VLD BIT(2)
1229#define PCLK_VLD BIT(3)
1230#define PCIRSTB BIT(4)
1231#define V15_VLD BIT(5)
1232#define TRP_B15V_EN BIT(7)
1233#define SIC_IDLE BIT(8)
1234#define BD_MAC2 BIT(9)
1235#define BD_MAC1 BIT(10)
1236#define IC_MACPHY_MODE BIT(11)
1237#define BT_FUNC BIT(16)
1238#define VENDOR_ID BIT(19)
1239#define PAD_HWPD_IDN BIT(22)
1240#define TRP_VAUX_EN BIT(23)
1241#define TRP_BT_EN BIT(24)
1242#define BD_PKG_SEL BIT(25)
1243#define BD_HCI_SEL BIT(26)
1244#define TYPE_ID BIT(27)
1245
1246#define USB_IS_HIGH_SPEED 0
1247#define USB_IS_FULL_SPEED 1
1248#define USB_SPEED_MASK BIT(5)
1249
1250#define USB_NORMAL_SIE_EP_MASK 0xF
1251#define USB_NORMAL_SIE_EP_SHIFT 4
1252
1253#define USB_TEST_EP_MASK 0x30
1254#define USB_TEST_EP_SHIFT 4
1255
1256#define USB_AGG_EN BIT(3)
1257
1258#define MAC_ADDR_LEN 6
1259#define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/
1260
1261#define POLLING_LLT_THRESHOLD 20
1262#define POLLING_READY_TIMEOUT_COUNT 3000
1263
1264#define MAX_MSS_DENSITY_2T 0x13
1265#define MAX_MSS_DENSITY_1T 0x0A
1266
1267#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
1268#define EPROM_CMD_CONFIG 0x3
1269#define EPROM_CMD_LOAD 1
1270
1271#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1272
1273#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1274
1275#define RA_LSSIWRITE_8821A 0xc90
1276#define RB_LSSIWRITE_8821A 0xe90
1277
1278#define RA_PIREAD_8821A 0xd04
1279#define RB_PIREAD_8821A 0xd44
1280#define RA_SIREAD_8821A 0xd08
1281#define RB_SIREAD_8821A 0xd48
1282
1283#define RPMAC_RESET 0x100
1284#define RPMAC_TXSTART 0x104
1285#define RPMAC_TXLEGACYSIG 0x108
1286#define RPMAC_TXHTSIG1 0x10c
1287#define RPMAC_TXHTSIG2 0x110
1288#define RPMAC_PHYDEBUG 0x114
1289#define RPMAC_TXPACKETNUM 0x118
1290#define RPMAC_TXIDLE 0x11c
1291#define RPMAC_TXMACHEADER0 0x120
1292#define RPMAC_TXMACHEADER1 0x124
1293#define RPMAC_TXMACHEADER2 0x128
1294#define RPMAC_TXMACHEADER3 0x12c
1295#define RPMAC_TXMACHEADER4 0x130
1296#define RPMAC_TXMACHEADER5 0x134
1297#define RPMAC_TXDADATYPE 0x138
1298#define RPMAC_TXRANDOMSEED 0x13c
1299#define RPMAC_CCKPLCPPREAMBLE 0x140
1300#define RPMAC_CCKPLCPHEADER 0x144
1301#define RPMAC_CCKCRC16 0x148
1302#define RPMAC_OFDMRXCRC32OK 0x170
1303#define RPMAC_OFDMRXCRC32Er 0x174
1304#define RPMAC_OFDMRXPARITYER 0x178
1305#define RPMAC_OFDMRXCRC8ER 0x17c
1306#define RPMAC_CCKCRXRC16ER 0x180
1307#define RPMAC_CCKCRXRC32ER 0x184
1308#define RPMAC_CCKCRXRC32OK 0x188
1309#define RPMAC_TXSTATUS 0x18c
1310
1311#define RFPGA0_RFMOD 0x800
1312
1313#define RFPGA0_TXINFO 0x804
1314#define RFPGA0_PSDFUNCTION 0x808
1315
1316#define RFPGA0_TXGAINSTAGE 0x80c
1317
1318#define RFPGA0_RFTIMING1 0x810
1319#define RFPGA0_RFTIMING2 0x814
1320
1321#define RFPGA0_XA_HSSIPARAMETER1 0x820
1322#define RFPGA0_XA_HSSIPARAMETER2 0x824
1323#define RFPGA0_XB_HSSIPARAMETER1 0x828
1324#define RFPGA0_XB_HSSIPARAMETER2 0x82c
1325#define RCCAONSEC 0x838
1326
1327#define RFPGA0_XA_LSSIPARAMETER 0x840
1328#define RFPGA0_XB_LSSIPARAMETER 0x844
1329#define RL1PEAKTH 0x848
1330
1331#define RFPGA0_RFWAKEUPPARAMETER 0x850
1332#define RFPGA0_RFSLEEPUPPARAMETER 0x854
1333
1334#define RFPGA0_XAB_SWITCHCONTROL 0x858
1335#define RFPGA0_XCD_SWITCHCONTROL 0x85c
1336
1337#define RFPGA0_XA_RFINTERFACEOE 0x860
1338#define RFC_AREA 0x860
1339#define RFPGA0_XB_RFINTERFACEOE 0x864
1340
1341#define RFPGA0_XAB_RFINTERFACESW 0x870
1342#define RFPGA0_XCD_RFINTERFACESW 0x874
1343
1344#define rFPGA0_XAB_RFPARAMETER 0x878
1345#define rFPGA0_XCD_RFPARAMETER 0x87c
1346
1347#define RFPGA0_ANALOGPARAMETER1 0x880
1348#define RFPGA0_ANALOGPARAMETER2 0x884
1349#define RFPGA0_ANALOGPARAMETER3 0x888
1350#define RFPGA0_ANALOGPARAMETER4 0x88c
1351
1352#define RFPGA0_XA_LSSIREADBACK 0x8a0
1353#define RFPGA0_XB_LSSIREADBACK 0x8a4
1354#define RFPGA0_XC_LSSIREADBACK 0x8a8
1355//#define RFPGA0_XD_LSSIREADBACK 0x8ac
1356#define RRFMOD 0x8ac
1357#define RHSSIREAD_8821AE 0x8b0
1358
1359#define RFPGA0_PSDREPORT 0x8b4
1360#define TRANSCEIVEA_HSPI_READBACK 0x8b8
1361#define TRANSCEIVEB_HSPI_READBACK 0x8bc
1362//#define REG_SC_CNT 0x8c4
1363#define RADC_BUF_CLK 0x8c4
1364#define RFPGA0_XAB_RFINTERFACERB 0x8e0
1365#define RFPGA0_XCD_RFINTERFACERB 0x8e4
1366
1367#define RFPGA1_RFMOD 0x900
1368
1369#define RFPGA1_TXBLOCK 0x904
1370#define RFPGA1_DEBUGSELECT 0x908
1371#define RFPGA1_TXINFO 0x90c
1372
1373#define RCCK_SYSTEM 0xa00
1374#define BCCK_SYSTEM 0x10
1375
1376
1377#define RCCK0_AFESETTING 0xa04
1378#define RCCK0_CCA 0xa08
1379
1380#define RCCK0_RXAGC1 0xa0c
1381#define RCCK0_RXAGC2 0xa10
1382
1383#define RCCK0_RXHP 0xa14
1384
1385#define RCCK0_DSPPARAMETER1 0xa18
1386#define RCCK0_DSPPARAMETER2 0xa1c
1387
1388#define RCCK0_TXFILTER1 0xa20
1389#define RCCK0_TXFILTER2 0xa24
1390#define RCCK0_DEBUGPORT 0xa28
1391#define RCCK0_FALSEALARMREPORT 0xa2c
1392#define RCCK0_TRSSIREPORT 0xa50
1393#define RCCK0_RXREPORT 0xa54
1394#define RCCK0_FACOUNTERLOWER 0xa5c
1395#define RCCK0_FACOUNTERUPPER 0xa58
1396#define RCCK0_CCA_CNT 0xa60
1397
1398
1399/* PageB(0xB00) */
1400#define rPdp_AntA 0xb00
1401#define rPdp_AntA_4 0xb04
1402#define rPdp_AntA_8 0xb08
1403#define rPdp_AntA_C 0xb0c
1404#define rPdp_AntA_10 0xb10
1405#define rPdp_AntA_14 0xb14
1406#define rPdp_AntA_18 0xb18
1407#define rPdp_AntA_1C 0xb1c
1408#define rPdp_AntA_20 0xb20
1409#define rPdp_AntA_24 0xb24
1410
1411#define rConfig_Pmpd_AntA 0xb28
1412#define rConfig_ram64x16 0xb2c
1413
1414#define rBndA 0xb30
1415#define rHssiPar 0xb34
1416
1417#define rConfig_AntA 0xb68
1418#define rConfig_AntB 0xb6c
1419
1420#define rPdp_AntB 0xb70
1421#define rPdp_AntB_4 0xb74
1422#define rPdp_AntB_8 0xb78
1423#define rPdp_AntB_C 0xb7c
1424#define rPdp_AntB_10 0xb80
1425#define rPdp_AntB_14 0xb84
1426#define rPdp_AntB_18 0xb88
1427#define rPdp_AntB_1C 0xb8c
1428#define rPdp_AntB_20 0xb90
1429#define rPdp_AntB_24 0xb94
1430
1431#define rConfig_Pmpd_AntB 0xb98
1432
1433#define rBndB 0xba0
1434
1435#define rAPK 0xbd8
1436#define rPm_Rx0_AntA 0xbdc
1437#define rPm_Rx1_AntA 0xbe0
1438#define rPm_Rx2_AntA 0xbe4
1439#define rPm_Rx3_AntA 0xbe8
1440#define rPm_Rx0_AntB 0xbec
1441#define rPm_Rx1_AntB 0xbf0
1442#define rPm_Rx2_AntB 0xbf4
1443#define rPm_Rx3_AntB 0xbf8
1444
1445/*RSSI Dump*/
1446#define RA_RSSI_DUMP 0xBF0
1447#define RB_RSSI_DUMP 0xBF1
1448#define RS1_RX_EVM_DUMP 0xBF4
1449#define RS2_RX_EVM_DUMP 0xBF5
1450#define RA_RX_SNR_DUMP 0xBF6
1451#define RB_RX_SNR_DUMP 0xBF7
1452#define RA_CFO_SHORT_DUMP 0xBF8
1453#define RB_CFO_SHORT_DUMP 0xBFA
1454#define RA_CFO_LONG_DUMP 0xBEC
1455#define RB_CFO_LONG_DUMP 0xBEE
1456
1457/*Page C*/
1458#define ROFDM0_LSTF 0xc00
1459
1460#define ROFDM0_TRXPATHENABLE 0xc04
1461#define ROFDM0_TRMUXPAR 0xc08
1462#define ROFDM0_TRSWISOLATION 0xc0c
1463
1464#define ROFDM0_XARXAFE 0xc10
1465#define ROFDM0_XARXIQIMBALANCE 0xc14
1466#define ROFDM0_XBRXAFE 0xc18
1467#define ROFDM0_XBRXIQIMBALANCE 0xc1c
1468#define ROFDM0_XCRXAFE 0xc20
1469#define ROFDM0_XCRXIQIMBANLANCE 0xc24
1470#define ROFDM0_XDRXAFE 0xc28
1471#define ROFDM0_XDRXIQIMBALANCE 0xc2c
1472
1473#define ROFDM0_RXDETECTOR1 0xc30
1474#define ROFDM0_RXDETECTOR2 0xc34
1475#define ROFDM0_RXDETECTOR3 0xc38
1476#define ROFDM0_RXDETECTOR4 0xc3c
1477
1478#define ROFDM0_RXDSP 0xc40
1479#define ROFDM0_CFOANDDAGC 0xc44
1480#define ROFDM0_CCADROPTHRESHOLD 0xc48
1481#define ROFDM0_ECCATHRESHOLD 0xc4c
1482
1483#define ROFDM0_XAAGCCORE1 0xc50
1484#define ROFDM0_XAAGCCORE2 0xc54
1485#define ROFDM0_XBAGCCORE1 0xc58
1486#define ROFDM0_XBAGCCORE2 0xc5c
1487#define ROFDM0_XCAGCCORE1 0xc60
1488#define ROFDM0_XCAGCCORE2 0xc64
1489#define ROFDM0_XDAGCCORE1 0xc68
1490#define ROFDM0_XDAGCCORE2 0xc6c
1491
1492#define ROFDM0_AGCPARAMETER1 0xc70
1493#define ROFDM0_AGCPARAMETER2 0xc74
1494#define ROFDM0_AGCRSSITABLE 0xc78
1495#define ROFDM0_HTSTFAGC 0xc7c
1496
1497#define ROFDM0_XATXIQIMBALANCE 0xc80
1498#define ROFDM0_XATXAFE 0xc84
1499#define ROFDM0_XBTXIQIMBALANCE 0xc88
1500#define ROFDM0_XBTXAFE 0xc8c
1501#define ROFDM0_XCTXIQIMBALANCE 0xc90
1502#define ROFDM0_XCTXAFE 0xc94
1503#define ROFDM0_XDTXIQIMBALANCE 0xc98
1504#define ROFDM0_XDTXAFE 0xc9c
1505
1506#define ROFDM0_RXIQEXTANTA 0xca0
1507#define ROFDM0_TXCOEFF1 0xca4
1508#define ROFDM0_TXCOEFF2 0xca8
1509#define ROFDM0_TXCOEFF3 0xcac
1510#define ROFDM0_TXCOEFF4 0xcb0
1511#define ROFDM0_TXCOEFF5 0xcb4
1512#define ROFDM0_TXCOEFF6 0xcb8
1513
1514/*Path_A RFE cotrol */
1515#define RA_RFE_CTRL_8812 0xcb8
1516/*Path_B RFE control*/
1517#define RB_RFE_CTRL_8812 0xeb8
1518
1519#define ROFDM0_RXHPPARAMETER 0xce0
1520#define ROFDM0_TXPSEUDONOISEWGT 0xce4
1521#define ROFDM0_FRAMESYNC 0xcf0
1522#define ROFDM0_DFSREPORT 0xcf4
1523
1524
1525#define ROFDM1_LSTF 0xd00
1526#define ROFDM1_TRXPATHENABLE 0xd04
1527
1528#define ROFDM1_CF0 0xd08
1529#define ROFDM1_CSI1 0xd10
1530#define ROFDM1_SBD 0xd14
1531#define ROFDM1_CSI2 0xd18
1532#define ROFDM1_CFOTRACKING 0xd2c
1533#define ROFDM1_TRXMESAURE1 0xd34
1534#define ROFDM1_INTFDET 0xd3c
1535#define ROFDM1_PSEUDONOISESTATEAB 0xd50
1536#define ROFDM1_PSEUDONOISESTATECD 0xd54
1537#define ROFDM1_RXPSEUDONOISEWGT 0xd58
1538
1539#define ROFDM_PHYCOUNTER1 0xda0
1540#define ROFDM_PHYCOUNTER2 0xda4
1541#define ROFDM_PHYCOUNTER3 0xda8
1542
1543#define ROFDM_SHORTCFOAB 0xdac
1544#define ROFDM_SHORTCFOCD 0xdb0
1545#define ROFDM_LONGCFOAB 0xdb4
1546#define ROFDM_LONGCFOCD 0xdb8
1547#define ROFDM_TAILCF0AB 0xdbc
1548#define ROFDM_TAILCF0CD 0xdc0
1549#define ROFDM_PWMEASURE1 0xdc4
1550#define ROFDM_PWMEASURE2 0xdc8
1551#define ROFDM_BWREPORT 0xdcc
1552#define ROFDM_AGCREPORT 0xdd0
1553#define ROFDM_RXSNR 0xdd4
1554#define ROFDM_RXEVMCSI 0xdd8
1555#define ROFDM_SIGREPORT 0xddc
1556
1557#define RTXAGC_A_CCK11_CCK1 0xc20
1558#define RTXAGC_A_OFDM18_OFDM6 0xc24
1559#define RTXAGC_A_OFDM54_OFDM24 0xc28
1560#define RTXAGC_A_MCS03_MCS00 0xc2c
1561#define RTXAGC_A_MCS07_MCS04 0xc30
1562#define RTXAGC_A_MCS11_MCS08 0xc34
1563#define RTXAGC_A_MCS15_MCS12 0xc38
1564#define RTXAGC_A_NSS1INDEX3_NSS1INDEX0 0xc3c
1565#define RTXAGC_A_NSS1INDEX7_NSS1INDEX4 0xc40
1566#define RTXAGC_A_NSS2INDEX1_NSS1INDEX8 0xc44
1567#define RTXAGC_A_NSS2INDEX5_NSS2INDEX2 0xc48
1568#define RTXAGC_A_NSS2INDEX9_NSS2INDEX6 0xc4c
1569#define RTXAGC_B_CCK11_CCK1 0xe20
1570#define RTXAGC_B_OFDM18_OFDM6 0xe24
1571#define RTXAGC_B_OFDM54_OFDM24 0xe28
1572#define RTXAGC_B_MCS03_MCS00 0xe2c
1573#define RTXAGC_B_MCS07_MCS04 0xe30
1574#define RTXAGC_B_MCS11_MCS08 0xe34
1575#define RTXAGC_B_MCS15_MCS12 0xe38
1576#define RTXAGC_B_NSS1INDEX3_NSS1INDEX0 0xe3c
1577#define RTXAGC_B_NSS1INDEX7_NSS1INDEX4 0xe40
1578#define RTXAGC_B_NSS2INDEX1_NSS1INDEX8 0xe44
1579#define RTXAGC_B_NSS2INDEX5_NSS2INDEX2 0xe48
1580#define RTXAGC_B_NSS2INDEX9_NSS2INDEX6 0xe4c
1581
1582#define RA_TXPWRTRAING 0xc54
1583#define RB_TXPWRTRAING 0xe54
1584
1585
1586#define RFPGA0_IQK 0xe28
1587#define RTx_IQK_Tone_A 0xe30
1588#define RRx_IQK_Tone_A 0xe34
1589#define RTx_IQK_PI_A 0xe38
1590#define RRx_IQK_PI_A 0xe3c
1591
1592#define RTx_IQK 0xe40
1593#define RRx_IQK 0xe44
1594#define RIQK_AGC_Pts 0xe48
1595#define RIQK_AGC_Rsp 0xe4c
1596#define RTx_IQK_Tone_B 0xe50
1597#define RRx_IQK_Tone_B 0xe54
1598#define RTx_IQK_PI_B 0xe58
1599#define RRx_IQK_PI_B 0xe5c
1600#define RIQK_AGC_Cont 0xe60
1601
1602#define RBlue_Tooth 0xe6c
1603#define RRx_Wait_CCA 0xe70
1604#define RTx_CCK_RFON 0xe74
1605#define RTx_CCK_BBON 0xe78
1606#define RTx_OFDM_RFON 0xe7c
1607#define RTx_OFDM_BBON 0xe80
1608#define RTx_To_Rx 0xe84
1609#define RTx_To_Tx 0xe88
1610#define RRx_CCK 0xe8c
1611
1612#define RTx_Power_Before_IQK_A 0xe94
1613#define RTx_Power_After_IQK_A 0xe9c
1614
1615#define RRx_Power_Before_IQK_A 0xea0
1616#define RRx_Power_Before_IQK_A_2 0xea4
1617#define RRx_Power_After_IQK_A 0xea8
1618#define RRx_Power_After_IQK_A_2 0xeac
1619
1620#define RTx_Power_Before_IQK_B 0xeb4
1621#define RTx_Power_After_IQK_B 0xebc
1622
1623#define RRx_Power_Before_IQK_B 0xec0
1624#define RRx_Power_Before_IQK_B_2 0xec4
1625#define RRx_Power_After_IQK_B 0xec8
1626#define RRx_Power_After_IQK_B_2 0xecc
1627
1628#define RRx_OFDM 0xed0
1629#define RRx_Wait_RIFS 0xed4
1630#define RRx_TO_Rx 0xed8
1631#define RStandby 0xedc
1632#define RSleep 0xee0
1633#define RPMPD_ANAEN 0xeec
1634
1635#define RZEBRA1_HSSIENABLE 0x0
1636#define RZEBRA1_TRXENABLE1 0x1
1637#define RZEBRA1_TRXENABLE2 0x2
1638#define RZEBRA1_AGC 0x4
1639#define RZEBRA1_CHARGEPUMP 0x5
1640#define RZEBRA1_CHANNEL 0x7
1641
1642#define RZEBRA1_TXGAIN 0x8
1643#define RZEBRA1_TXLPF 0x9
1644#define RZEBRA1_RXLPF 0xb
1645#define RZEBRA1_RXHPFCORNER 0xc
1646
1647#define RGLOBALCTRL 0
1648#define RRTL8256_TXLPF 19
1649#define RRTL8256_RXLPF 11
1650#define RRTL8258_TXLPF 0x11
1651#define RRTL8258_RXLPF 0x13
1652#define RRTL8258_RSSILPF 0xa
1653
1654#define RF_AC 0x00
1655
1656#define RF_IQADJ_G1 0x01
1657#define RF_IQADJ_G2 0x02
1658#define RF_POW_TRSW 0x05
1659
1660#define RF_GAIN_RX 0x06
1661#define RF_GAIN_TX 0x07
1662
1663#define RF_TXM_IDAC 0x08
1664#define RF_BS_IQGEN 0x0F
1665
1666#define RF_MODE1 0x10
1667#define RF_MODE2 0x11
1668
1669#define RF_RX_AGC_HP 0x12
1670#define RF_TX_AGC 0x13
1671#define RF_BIAS 0x14
1672#define RF_IPA 0x15
1673#define RF_POW_ABILITY 0x17
1674#define RF_MODE_AG 0x18
1675#define RRFCHANNEL 0x18
1676#define RF_CHNLBW 0x18
1677#define RF_TOP 0x19
1678
1679#define RF_RX_G1 0x1A
1680#define RF_RX_G2 0x1B
1681
1682#define RF_RX_BB2 0x1C
1683#define RF_RX_BB1 0x1D
1684
1685#define RF_RCK1 0x1E
1686#define RF_RCK2 0x1F
1687
1688#define RF_TX_G1 0x20
1689#define RF_TX_G2 0x21
1690#define RF_TX_G3 0x22
1691
1692#define RF_TX_BB1 0x23
1693#define RF_T_METER 0x24
1694#define RF_T_METER_88E 0x42
1695#define RF_T_METER_8812A 0x42
1696
1697#define RF_SYN_G1 0x25
1698#define RF_SYN_G2 0x26
1699#define RF_SYN_G3 0x27
1700#define RF_SYN_G4 0x28
1701#define RF_SYN_G5 0x29
1702#define RF_SYN_G6 0x2A
1703#define RF_SYN_G7 0x2B
1704#define RF_SYN_G8 0x2C
1705
1706#define RF_RCK_OS 0x30
1707#define RF_TXPA_G1 0x31
1708#define RF_TXPA_G2 0x32
1709#define RF_TXPA_G3 0x33
1710
1711#define RF_TX_BIAS_A 0x35
1712#define RF_TX_BIAS_D 0x36
1713#define RF_LOBF_9 0x38
1714#define RF_RXRF_A3 0x3C
1715#define RF_TRSW 0x3F
1716
1717#define RF_TXRF_A2 0x41
1718#define RF_TXPA_G4 0x46
1719#define RF_TXPA_A4 0x4B
1720
1721#define RF_APK 0x63
1722
1723#define RF_WE_LUT 0xEF
1724
1725#define BBBRESETB 0x100
1726#define BGLOBALRESETB 0x200
1727#define BOFDMTXSTART 0x4
1728#define BCCKTXSTART 0x8
1729#define BCRC32DEBUG 0x100
1730#define BPMACLOOPBACK 0x10
1731#define BTXLSIG 0xffffff
1732#define BOFDMTXRATE 0xf
1733#define BOFDMTXRESERVED 0x10
1734#define BOFDMTXLENGTH 0x1ffe0
1735#define BOFDMTXPARITY 0x20000
1736#define BTXHTSIG1 0xffffff
1737#define BTXHTMCSRATE 0x7f
1738#define BTXHTBW 0x80
1739#define BTXHTLENGTH 0xffff00
1740#define BTXHTSIG2 0xffffff
1741#define BTXHTSMOOTHING 0x1
1742#define BTXHTSOUNDING 0x2
1743#define BTXHTRESERVED 0x4
1744#define BTXHTAGGREATION 0x8
1745#define BTXHTSTBC 0x30
1746#define BTXHTADVANCECODING 0x40
1747#define BTXHTSHORTGI 0x80
1748#define BTXHTNUMBERHT_LTF 0x300
1749#define BTXHTCRC8 0x3fc00
1750#define BCOUNTERRESET 0x10000
1751#define BNUMOFOFDMTX 0xffff
1752#define BNUMOFCCKTX 0xffff0000
1753#define BTXIDLEINTERVAL 0xffff
1754#define BOFDMSERVICE 0xffff0000
1755#define BTXMACHEADER 0xffffffff
1756#define BTXDATAINIT 0xff
1757#define BTXHTMODE 0x100
1758#define BTXDATATYPE 0x30000
1759#define BTXRANDOMSEED 0xffffffff
1760#define BCCKTXPREAMBLE 0x1
1761#define BCCKTXSFD 0xffff0000
1762#define BCCKTXSIG 0xff
1763#define BCCKTXSERVICE 0xff00
1764#define BCCKLENGTHEXT 0x8000
1765#define BCCKTXLENGHT 0xffff0000
1766#define BCCKTXCRC16 0xffff
1767#define BCCKTXSTATUS 0x1
1768#define BOFDMTXSTATUS 0x2
1769#define IS_BB_REG_OFFSET_92S(_Offset) \
1770 ((_Offset >= 0x800) && (_Offset <= 0xfff))
1771
1772#define BRFMOD 0x1
1773#define BJAPANMODE 0x2
1774#define BCCKTXSC 0x30
1775/* Block & Path enable*/
1776#define ROFDMCCKEN 0x808
1777#define BCCKEN 0x10000000
1778#define BOFDMEN 0x20000000
1779#define RRXPATH 0x808 /* Rx antenna*/
1780#define BRXPATH 0xff
1781#define RTXPATH 0x80c /* Tx antenna*/
1782#define BTXPATH 0x0fffffff
1783#define RCCK_RX 0xa04 /* for cck rx path selection*/
1784#define BCCK_RX 0x0c000000
1785#define RVHTLEN_USE_LSIG 0x8c3 /* Use LSIG for VHT length*/
1786
1787
1788#define BOFDMRXADCPHASE 0x10000
1789#define BOFDMTXDACPHASE 0x40000
1790#define BXATXAGC 0x3f
1791
1792#define BXBTXAGC 0xf00
1793#define BXCTXAGC 0xf000
1794#define BXDTXAGC 0xf0000
1795
1796#define BPASTART 0xf0000000
1797#define BTRSTART 0x00f00000
1798#define BRFSTART 0x0000f000
1799#define BBBSTART 0x000000f0
1800#define BBBCCKSTART 0x0000000f
1801#define BPAEND 0xf
1802#define BTREND 0x0f000000
1803#define BRFEND 0x000f0000
1804#define BCCAMASK 0x000000f0
1805#define BR2RCCAMASK 0x00000f00
1806#define BHSSI_R2TDELAY 0xf8000000
1807#define BHSSI_T2RDELAY 0xf80000
1808#define BCONTXHSSI 0x400
1809#define BIGFROMCCK 0x200
1810#define BAGCADDRESS 0x3f
1811#define BRXHPTX 0x7000
1812#define BRXHP2RX 0x38000
1813#define BRXHPCCKINI 0xc0000
1814#define BAGCTXCODE 0xc00000
1815#define BAGCRXCODE 0x300000
1816
1817#define B3WIREDATALENGTH 0x800
1818#define B3WIREADDREAALENGTH 0x400
1819
1820#define B3WIRERFPOWERDOWN 0x1
1821#define B5GPAPEPOLARITY 0x40000000
1822#define B2GPAPEPOLARITY 0x80000000
1823#define BRFSW_TXDEFAULTANT 0x3
1824#define BRFSW_TXOPTIONANT 0x30
1825#define BRFSW_RXDEFAULTANT 0x300
1826#define BRFSW_RXOPTIONANT 0x3000
1827#define BRFSI_3WIREDATA 0x1
1828#define BRFSI_3WIRECLOCK 0x2
1829#define BRFSI_3WIRELOAD 0x4
1830#define BRFSI_3WIRERW 0x8
1831#define BRFSI_3WIRE 0xf
1832
1833#define BRFSI_RFENV 0x10
1834
1835#define BRFSI_TRSW 0x20
1836#define BRFSI_TRSWB 0x40
1837#define BRFSI_ANTSW 0x100
1838#define BRFSI_ANTSWB 0x200
1839#define BRFSI_PAPE 0x400
1840#define BRFSI_PAPE5G 0x800
1841#define BBANDSELECT 0x1
1842#define BHTSIG2_GI 0x80
1843#define BHTSIG2_SMOOTHING 0x01
1844#define BHTSIG2_SOUNDING 0x02
1845#define BHTSIG2_AGGREATON 0x08
1846#define BHTSIG2_STBC 0x30
1847#define BHTSIG2_ADVCODING 0x40
1848#define BHTSIG2_NUMOFHTLTF 0x300
1849#define BHTSIG2_CRC8 0x3fc
1850#define BHTSIG1_MCS 0x7f
1851#define BHTSIG1_BANDWIDTH 0x80
1852#define BHTSIG1_HTLENGTH 0xffff
1853#define BLSIG_RATE 0xf
1854#define BLSIG_RESERVED 0x10
1855#define BLSIG_LENGTH 0x1fffe
1856#define BLSIG_PARITY 0x20
1857#define BCCKRXPHASE 0x4
1858
1859#define BLSSIREADADDRESS 0x7f800000
1860#define BLSSIREADEDGE 0x80000000
1861
1862#define BLSSIREADBACKDATA 0xfffff
1863
1864#define BLSSIREADOKFLAG 0x1000
1865#define BCCKSAMPLERATE 0x8
1866#define BREGULATOR0STANDBY 0x1
1867#define BREGULATORPLLSTANDBY 0x2
1868#define BREGULATOR1STANDBY 0x4
1869#define BPLLPOWERUP 0x8
1870#define BDPLLPOWERUP 0x10
1871#define BDA10POWERUP 0x20
1872#define BAD7POWERUP 0x200
1873#define BDA6POWERUP 0x2000
1874#define BXTALPOWERUP 0x4000
1875#define B40MDCLKPOWERUP 0x8000
1876#define BDA6DEBUGMODE 0x20000
1877#define BDA6SWING 0x380000
1878
1879#define BADCLKPHASE 0x4000000
1880#define B80MCLKDELAY 0x18000000
1881#define BAFEWATCHDOGENABLE 0x20000000
1882
1883#define BXTALCAP01 0xc0000000
1884#define BXTALCAP23 0x3
1885#define BXTALCAP92X 0x0f000000
1886#define BXTALCAP 0x0f000000
1887
1888#define BINTDIFCLKENABLE 0x400
1889#define BEXTSIGCLKENABLE 0x800
1890#define BBANDGAP_MBIAS_POWERUP 0x10000
1891#define BAD11SH_GAIN 0xc0000
1892#define BAD11NPUT_RANGE 0x700000
1893#define BAD110P_CURRENT 0x3800000
1894#define BLPATH_LOOPBACK 0x4000000
1895#define BQPATH_LOOPBACK 0x8000000
1896#define BAFE_LOOPBACK 0x10000000
1897#define BDA10_SWING 0x7e0
1898#define BDA10_REVERSE 0x800
1899#define BDA_CLK_SOURCE 0x1000
1900#define BDA7INPUT_RANGE 0x6000
1901#define BDA7_GAIN 0x38000
1902#define BDA7OUTPUT_CM_MODE 0x40000
1903#define BDA7INPUT_CM_MODE 0x380000
1904#define BDA7CURRENT 0xc00000
1905#define BREGULATOR_ADJUST 0x7000000
1906#define BAD11POWERUP_ATTX 0x1
1907#define BDA10PS_ATTX 0x10
1908#define BAD11POWERUP_ATRX 0x100
1909#define BDA10PS_ATRX 0x1000
1910#define BCCKRX_AGC_FORMAT 0x200
1911#define BPSDFFT_SAMPLE_POINT 0xc000
1912#define BPSD_AVERAGE_NUM 0x3000
1913#define BIQPATH_CONTROL 0xc00
1914#define BPSD_FREQ 0x3ff
1915#define BPSD_ANTENNA_PATH 0x30
1916#define BPSD_IQ_SWITCH 0x40
1917#define BPSD_RX_TRIGGER 0x400000
1918#define BPSD_TX_TRIGGER 0x80000000
1919#define BPSD_SINE_TONE_SCALE 0x7f000000
1920#define BPSD_REPORT 0xffff
1921
1922#define BOFDM_TXSC 0x30000000
1923#define BCCK_TXON 0x1
1924#define BOFDM_TXON 0x2
1925#define BDEBUG_PAGE 0xfff
1926#define BDEBUG_ITEM 0xff
1927#define BANTL 0x10
1928#define BANT_NONHT 0x100
1929#define BANT_HT1 0x1000
1930#define BANT_HT2 0x10000
1931#define BANT_HT1S1 0x100000
1932#define BANT_NONHTS1 0x1000000
1933
1934#define BCCK_BBMODE 0x3
1935#define BCCK_TXPOWERSAVING 0x80
1936#define BCCK_RXPOWERSAVING 0x40
1937
1938#define BCCK_SIDEBAND 0x10
1939
1940#define BCCK_SCRAMBLE 0x8
1941#define BCCK_ANTDIVERSITY 0x8000
1942#define BCCK_CARRIER_RECOVERY 0x4000
1943#define BCCK_TXRATE 0x3000
1944#define BCCK_DCCANCEL 0x0800
1945#define BCCK_ISICANCEL 0x0400
1946#define BCCK_MATCH_FILTER 0x0200
1947#define BCCK_EQUALIZER 0x0100
1948#define BCCK_PREAMBLE_DETECT 0x800000
1949#define BCCK_FAST_FALSECCA 0x400000
1950#define BCCK_CH_ESTSTART 0x300000
1951#define BCCK_CCA_COUNT 0x080000
1952#define BCCK_CS_LIM 0x070000
1953#define BCCK_BIST_MODE 0x80000000
1954#define BCCK_CCAMASK 0x40000000
1955#define BCCK_TX_DAC_PHASE 0x4
1956#define BCCK_RX_ADC_PHASE 0x20000000
1957#define BCCKR_CP_MODE 0x0100
1958#define BCCK_TXDC_OFFSET 0xf0
1959#define BCCK_RXDC_OFFSET 0xf
1960#define BCCK_CCA_MODE 0xc000
1961#define BCCK_FALSECS_LIM 0x3f00
1962#define BCCK_CS_RATIO 0xc00000
1963#define BCCK_CORGBIT_SEL 0x300000
1964#define BCCK_PD_LIM 0x0f0000
1965#define BCCK_NEWCCA 0x80000000
1966#define BCCK_RXHP_OF_IG 0x8000
1967#define BCCK_RXIG 0x7f00
1968#define BCCK_LNA_POLARITY 0x800000
1969#define BCCK_RX1ST_BAIN 0x7f0000
1970#define BCCK_RF_EXTEND 0x20000000
1971#define BCCK_RXAGC_SATLEVEL 0x1f000000
1972#define BCCK_RXAGC_SATCOUNT 0xe0
1973#define bCCKRxRFSettle 0x1f
1974#define BCCK_FIXED_RXAGC 0x8000
1975#define BCCK_ANTENNA_POLARITY 0x2000
1976#define BCCK_TXFILTER_TYPE 0x0c00
1977#define BCCK_RXAGC_REPORTTYPE 0x0300
1978#define BCCK_RXDAGC_EN 0x80000000
1979#define BCCK_RXDAGC_PERIOD 0x20000000
1980#define BCCK_RXDAGC_SATLEVEL 0x1f000000
1981#define BCCK_TIMING_RECOVERY 0x800000
1982#define BCCK_TXC0 0x3f0000
1983#define BCCK_TXC1 0x3f000000
1984#define BCCK_TXC2 0x3f
1985#define BCCK_TXC3 0x3f00
1986#define BCCK_TXC4 0x3f0000
1987#define BCCK_TXC5 0x3f000000
1988#define BCCK_TXC6 0x3f
1989#define BCCK_TXC7 0x3f00
1990#define BCCK_DEBUGPORT 0xff0000
1991#define BCCK_DAC_DEBUG 0x0f000000
1992#define BCCK_FALSEALARM_ENABLE 0x8000
1993#define BCCK_FALSEALARM_READ 0x4000
1994#define BCCK_TRSSI 0x7f
1995#define BCCK_RXAGC_REPORT 0xfe
1996#define BCCK_RXREPORT_ANTSEL 0x80000000
1997#define BCCK_RXREPORT_MFOFF 0x40000000
1998#define BCCK_RXREPORT_SQLOSS 0x20000000
1999#define BCCK_RXREPORT_PKTLOSS 0x10000000
2000#define BCCK_RXREPORT_LOCKEDBIT 0x08000000
2001#define BCCK_RXREPORT_RATEERROR 0x04000000
2002#define BCCK_RXREPORT_RXRATE 0x03000000
2003#define BCCK_RXFA_COUNTER_LOWER 0xff
2004#define BCCK_RXFA_COUNTER_UPPER 0xff000000
2005#define BCCK_RXHPAGC_START 0xe000
2006#define BCCK_RXHPAGC_FINAL 0x1c00
2007#define BCCK_RXFALSEALARM_ENABLE 0x8000
2008#define BCCK_FACOUNTER_FREEZE 0x4000
2009#define BCCK_TXPATH_SEL 0x10000000
2010#define BCCK_DEFAULT_RXPATH 0xc000000
2011#define BCCK_OPTION_RXPATH 0x3000000
2012
2013#define BNUM_OFSTF 0x3
2014#define BSHIFT_L 0xc0
2015#define BGI_TH 0xc
2016#define BRXPATH_A 0x1
2017#define BRXPATH_B 0x2
2018#define BRXPATH_C 0x4
2019#define BRXPATH_D 0x8
2020#define BTXPATH_A 0x1
2021#define BTXPATH_B 0x2
2022#define BTXPATH_C 0x4
2023#define BTXPATH_D 0x8
2024#define BTRSSI_FREQ 0x200
2025#define BADC_BACKOFF 0x3000
2026#define BDFIR_BACKOFF 0xc000
2027#define BTRSSI_LATCH_PHASE 0x10000
2028#define BRX_LDC_OFFSET 0xff
2029#define BRX_QDC_OFFSET 0xff00
2030#define BRX_DFIR_MODE 0x1800000
2031#define BRX_DCNF_TYPE 0xe000000
2032#define BRXIQIMB_A 0x3ff
2033#define BRXIQIMB_B 0xfc00
2034#define BRXIQIMB_C 0x3f0000
2035#define BRXIQIMB_D 0xffc00000
2036#define BDC_DC_NOTCH 0x60000
2037#define BRXNB_NOTCH 0x1f000000
2038#define BPD_TH 0xf
2039#define BPD_TH_OPT2 0xc000
2040#define BPWED_TH 0x700
2041#define BIFMF_WIN_L 0x800
2042#define BPD_OPTION 0x1000
2043#define BMF_WIN_L 0xe000
2044#define BBW_SEARCH_L 0x30000
2045#define BWIN_ENH_L 0xc0000
2046#define BBW_TH 0x700000
2047#define BED_TH2 0x3800000
2048#define BBW_OPTION 0x4000000
2049#define BRADIO_TH 0x18000000
2050#define BWINDOW_L 0xe0000000
2051#define BSBD_OPTION 0x1
2052#define BFRAME_TH 0x1c
2053#define BFS_OPTION 0x60
2054#define BDC_SLOPE_CHECK 0x80
2055#define BFGUARD_COUNTER_DC_L 0xe00
2056#define BFRAME_WEIGHT_SHORT 0x7000
2057#define BSUB_TUNE 0xe00000
2058#define BFRAME_DC_LENGTH 0xe000000
2059#define BSBD_START_OFFSET 0x30000000
2060#define BFRAME_TH_2 0x7
2061#define BFRAME_GI2_TH 0x38
2062#define BGI2_SYNC_EN 0x40
2063#define BSARCH_SHORT_EARLY 0x300
2064#define BSARCH_SHORT_LATE 0xc00
2065#define BSARCH_GI2_LATE 0x70000
2066#define BCFOANTSUM 0x1
2067#define BCFOACC 0x2
2068#define BCFOSTARTOFFSET 0xc
2069#define BCFOLOOPBACK 0x70
2070#define BCFOSUMWEIGHT 0x80
2071#define BDAGCENABLE 0x10000
2072#define BTXIQIMB_A 0x3ff
2073#define BTXIQIMB_b 0xfc00
2074#define BTXIQIMB_C 0x3f0000
2075#define BTXIQIMB_D 0xffc00000
2076#define BTXIDCOFFSET 0xff
2077#define BTXIQDCOFFSET 0xff00
2078#define BTXDFIRMODE 0x10000
2079#define BTXPESUDO_NOISEON 0x4000000
2080#define BTXPESUDO_NOISE_A 0xff
2081#define BTXPESUDO_NOISE_B 0xff00
2082#define BTXPESUDO_NOISE_C 0xff0000
2083#define BTXPESUDO_NOISE_D 0xff000000
2084#define BCCA_DROPOPTION 0x20000
2085#define BCCA_DROPTHRES 0xfff00000
2086#define BEDCCA_H 0xf
2087#define BEDCCA_L 0xf0
2088#define BLAMBDA_ED 0x300
2089#define BRX_INITIALGAIN 0x7f
2090#define BRX_ANTDIV_EN 0x80
2091#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
2092#define BRX_HIGHPOWER_FLOW 0x8000
2093#define BRX_AGC_FREEZE_THRES 0xc0000
2094#define BRX_FREEZESTEP_AGC1 0x300000
2095#define BRX_FREEZESTEP_AGC2 0xc00000
2096#define BRX_FREEZESTEP_AGC3 0x3000000
2097#define BRX_FREEZESTEP_AGC0 0xc000000
2098#define BRXRSSI_CMP_EN 0x10000000
2099#define BRXQUICK_AGCEN 0x20000000
2100#define BRXAGC_FREEZE_THRES_MODE 0x40000000
2101#define BRX_OVERFLOW_CHECKTYPE 0x80000000
2102#define BRX_AGCSHIFT 0x7f
2103#define BTRSW_TRI_ONLY 0x80
2104#define BPOWER_THRES 0x300
2105#define BRXAGC_EN 0x1
2106#define BRXAGC_TOGETHER_EN 0x2
2107#define BRXAGC_MIN 0x4
2108#define BRXHP_INI 0x7
2109#define BRXHP_TRLNA 0x70
2110#define BRXHP_RSSI 0x700
2111#define BRXHP_BBP1 0x7000
2112#define BRXHP_BBP2 0x70000
2113#define BRXHP_BBP3 0x700000
2114#define BRSSI_H 0x7f0000
2115#define BRSSI_GEN 0x7f000000
2116#define BRXSETTLE_TRSW 0x7
2117#define BRXSETTLE_LNA 0x38
2118#define BRXSETTLE_RSSI 0x1c0
2119#define BRXSETTLE_BBP 0xe00
2120#define BRXSETTLE_RXHP 0x7000
2121#define BRXSETTLE_ANTSW_RSSI 0x38000
2122#define BRXSETTLE_ANTSW 0xc0000
2123#define BRXPROCESS_TIME_DAGC 0x300000
2124#define BRXSETTLE_HSSI 0x400000
2125#define BRXPROCESS_TIME_BBPPW 0x800000
2126#define BRXANTENNA_POWER_SHIFT 0x3000000
2127#define BRSSI_TABLE_SELECT 0xc000000
2128#define BRXHP_FINAL 0x7000000
2129#define BRXHPSETTLE_BBP 0x7
2130#define BRXHTSETTLE_HSSI 0x8
2131#define BRXHTSETTLE_RXHP 0x70
2132#define BRXHTSETTLE_BBPPW 0x80
2133#define BRXHTSETTLE_IDLE 0x300
2134#define BRXHTSETTLE_RESERVED 0x1c00
2135#define BRXHT_RXHP_EN 0x8000
2136#define BRXAGC_FREEZE_THRES 0x30000
2137#define BRXAGC_TOGETHEREN 0x40000
2138#define BRXHTAGC_MIN 0x80000
2139#define BRXHTAGC_EN 0x100000
2140#define BRXHTDAGC_EN 0x200000
2141#define BRXHT_RXHP_BBP 0x1c00000
2142#define BRXHT_RXHP_FINAL 0xe0000000
2143#define BRXPW_RADIO_TH 0x3
2144#define BRXPW_RADIO_EN 0x4
2145#define BRXMF_HOLD 0x3800
2146#define BRXPD_DELAY_TH1 0x38
2147#define BRXPD_DELAY_TH2 0x1c0
2148#define BRXPD_DC_COUNT_MAX 0x600
2149#define BRXPD_DELAY_TH 0x8000
2150#define BRXPROCESS_DELAY 0xf0000
2151#define BRXSEARCHRANGE_GI2_EARLY 0x700000
2152#define BRXFRAME_FUARD_COUNTER_L 0x3800000
2153#define BRXSGI_GUARD_L 0xc000000
2154#define BRXSGI_SEARCH_L 0x30000000
2155#define BRXSGI_TH 0xc0000000
2156#define BDFSCNT0 0xff
2157#define BDFSCNT1 0xff00
2158#define BDFSFLAG 0xf0000
2159#define BMF_WEIGHT_SUM 0x300000
2160#define BMINIDX_TH 0x7f000000
2161#define BDAFORMAT 0x40000
2162#define BTXCH_EMU_ENABLE 0x01000000
2163#define BTRSW_ISOLATION_A 0x7f
2164#define BTRSW_ISOLATION_B 0x7f00
2165#define BTRSW_ISOLATION_C 0x7f0000
2166#define BTRSW_ISOLATION_D 0x7f000000
2167#define BEXT_LNA_GAIN 0x7c00
2168
2169#define BSTBC_EN 0x4
2170#define BANTENNA_MAPPING 0x10
2171#define BNSS 0x20
2172#define BCFO_ANTSUM_ID 0x200
2173#define BPHY_COUNTER_RESET 0x8000000
2174#define BCFO_REPORT_GET 0x4000000
2175#define BOFDM_CONTINUE_TX 0x10000000
2176#define BOFDM_SINGLE_CARRIER 0x20000000
2177#define BOFDM_SINGLE_TONE 0x40000000
2178#define BHT_DETECT 0x100
2179#define BCFOEN 0x10000
2180#define BCFOVALUE 0xfff00000
2181#define BSIGTONE_RE 0x3f
2182#define BSIGTONE_IM 0x7f00
2183#define BCOUNTER_CCA 0xffff
2184#define BCOUNTER_PARITYFAIL 0xffff0000
2185#define BCOUNTER_RATEILLEGAL 0xffff
2186#define BCOUNTER_CRC8FAIL 0xffff0000
2187#define BCOUNTER_MCSNOSUPPORT 0xffff
2188#define BCOUNTER_FASTSYNC 0xffff
2189#define BSHORTCFO 0xfff
2190#define BSHORTCFOT_LENGTH 12
2191#define BSHORTCFOF_LENGTH 11
2192#define BLONGCFO 0x7ff
2193#define BLONGCFOT_LENGTH 11
2194#define BLONGCFOF_LENGTH 11
2195#define BTAILCFO 0x1fff
2196#define BTAILCFOT_LENGTH 13
2197#define BTAILCFOF_LENGTH 12
2198#define BNOISE_EN_PWDB 0xffff
2199#define BCC_POWER_DB 0xffff0000
2200#define BMOISE_PWDB 0xffff
2201#define BPOWERMEAST_LENGTH 10
2202#define BPOWERMEASF_LENGTH 3
2203#define BRX_HT_BW 0x1
2204#define BRXSC 0x6
2205#define BRX_HT 0x8
2206#define BNB_INTF_DET_ON 0x1
2207#define BINTF_WIN_LEN_CFG 0x30
2208#define BNB_INTF_TH_CFG 0x1c0
2209#define BRFGAIN 0x3f
2210#define BTABLESEL 0x40
2211#define BTRSW 0x80
2212#define BRXSNR_A 0xff
2213#define BRXSNR_B 0xff00
2214#define BRXSNR_C 0xff0000
2215#define BRXSNR_D 0xff000000
2216#define BSNR_EVMT_LENGTH 8
2217#define BSNR_EVMF_LENGTH 1
2218#define BCSI1ST 0xff
2219#define BCSI2ND 0xff00
2220#define BRXEVM1ST 0xff0000
2221#define BRXEVM2ND 0xff000000
2222#define BSIGEVM 0xff
2223#define BPWDB 0xff00
2224#define BSGIEN 0x10000
2225
2226#define BSFACTOR_QMA1 0xf
2227#define BSFACTOR_QMA2 0xf0
2228#define BSFACTOR_QMA3 0xf00
2229#define BSFACTOR_QMA4 0xf000
2230#define BSFACTOR_QMA5 0xf0000
2231#define BSFACTOR_QMA6 0xf0000
2232#define BSFACTOR_QMA7 0xf00000
2233#define BSFACTOR_QMA8 0xf000000
2234#define BSFACTOR_QMA9 0xf0000000
2235#define BCSI_SCHEME 0x100000
2236
2237#define BNOISE_LVL_TOP_SET 0x3
2238#define BCHSMOOTH 0x4
2239#define BCHSMOOTH_CFG1 0x38
2240#define BCHSMOOTH_CFG2 0x1c0
2241#define BCHSMOOTH_CFG3 0xe00
2242#define BCHSMOOTH_CFG4 0x7000
2243#define BMRCMODE 0x800000
2244#define BTHEVMCFG 0x7000000
2245
2246#define BLOOP_FIT_TYPE 0x1
2247#define BUPD_CFO 0x40
2248#define BUPD_CFO_OFFDATA 0x80
2249#define BADV_UPD_CFO 0x100
2250#define BADV_TIME_CTRL 0x800
2251#define BUPD_CLKO 0x1000
2252#define BFC 0x6000
2253#define BTRACKING_MODE 0x8000
2254#define BPHCMP_ENABLE 0x10000
2255#define BUPD_CLKO_LTF 0x20000
2256#define BCOM_CH_CFO 0x40000
2257#define BCSI_ESTI_MODE 0x80000
2258#define BADV_UPD_EQZ 0x100000
2259#define BUCHCFG 0x7000000
2260#define BUPDEQZ 0x8000000
2261
2262#define BRX_PESUDO_NOISE_ON 0x20000000
2263#define BRX_PESUDO_NOISE_A 0xff
2264#define BRX_PESUDO_NOISE_B 0xff00
2265#define BRX_PESUDO_NOISE_C 0xff0000
2266#define BRX_PESUDO_NOISE_D 0xff000000
2267#define BRX_PESUDO_NOISESTATE_A 0xffff
2268#define BRX_PESUDO_NOISESTATE_B 0xffff0000
2269#define BRX_PESUDO_NOISESTATE_C 0xffff
2270#define BRX_PESUDO_NOISESTATE_D 0xffff0000
2271
2272#define BZEBRA1_HSSIENABLE 0x8
2273#define BZEBRA1_TRXCONTROL 0xc00
2274#define BZEBRA1_TRXGAINSETTING 0x07f
2275#define BZEBRA1_RXCOUNTER 0xc00
2276#define BZEBRA1_TXCHANGEPUMP 0x38
2277#define BZEBRA1_RXCHANGEPUMP 0x7
2278#define BZEBRA1_CHANNEL_NUM 0xf80
2279#define BZEBRA1_TXLPFBW 0x400
2280#define BZEBRA1_RXLPFBW 0x600
2281
2282#define BRTL8256REG_MODE_CTRL1 0x100
2283#define BRTL8256REG_MODE_CTRL0 0x40
2284#define BRTL8256REG_TXLPFBW 0x18
2285#define BRTL8256REG_RXLPFBW 0x600
2286
2287#define BRTL8258_TXLPFBW 0xc
2288#define BRTL8258_RXLPFBW 0xc00
2289#define BRTL8258_RSSILPFBW 0xc0
2290
2291#define BBYTE0 0x1
2292#define BBYTE1 0x2
2293#define BBYTE2 0x4
2294#define BBYTE3 0x8
2295#define BWORD0 0x3
2296#define BWORD1 0xc
2297#define BWORD 0xf
2298
2299#define MASKBYTE0 0xff
2300#define MASKBYTE1 0xff00
2301#define MASKBYTE2 0xff0000
2302#define MASKBYTE3 0xff000000
2303#define MASKHWORD 0xffff0000
2304#define MASKLWORD 0x0000ffff
2305#define MASKDWORD 0xffffffff
2306#define MASK12BITS 0xfff
2307#define MASKH4BITS 0xf0000000
2308#define MASKOFDM_D 0xffc00000
2309#define MASKCCK 0x3f3f3f3f
2310
2311#define MASK4BITS 0x0f
2312#define MASK20BITS 0xfffff
2313#define RFREG_OFFSET_MASK 0xfffff
2314
2315#define BENABLE 0x1
2316#define BDISABLE 0x0
2317
2318#define LEFT_ANTENNA 0x0
2319#define RIGHT_ANTENNA 0x1
2320
2321#define TCHECK_TXSTATUS 500
2322#define TUPDATE_RXCOUNTER 100
2323
2324#define REG_UN_used_register 0x01bf
2325
2326/* WOL bit information */
2327#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
2328#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
2329#define HAL92C_WOL_DISASSOC_EVENT BIT(2)
2330#define HAL92C_WOL_DEAUTH_EVENT BIT(3)
2331#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4)
2332
2333#define WOL_REASON_PTK_UPDATE BIT(0)
2334#define WOL_REASON_GTK_UPDATE BIT(1)
2335#define WOL_REASON_DISASSOC BIT(2)
2336#define WOL_REASON_DEAUTH BIT(3)
2337#define WOL_REASON_FW_DISCONNECT BIT(4)
2338
2339#define RA_RFE_PINMUX 0xcb0 /* Path_A RFE cotrol pinmux*/
2340#define RB_RFE_PINMUX 0xeb0 /* Path_B RFE control pinmux*/
2341
2342#define RA_RFE_INV 0xcb4
2343#define RB_RFE_INV 0xeb4
2344
2345/* RXIQC */
2346#define RA_RXIQC_AB 0xc10 /*RxIQ imblance matrix coeff. A & B*/
2347#define RA_RXIQC_CD 0xc14 /*RxIQ imblance matrix coeff. C & D*/
2348#define RA_TXSCALE 0xc1c /* Pah_A TX scaling factor*/
2349#define RB_TXSCALE 0xe1c /* Path_B TX scaling factor*/
2350#define RB_RXIQC_AB 0xe10 /*RxIQ imblance matrix coeff. A & B*/
2351#define RB_RXIQC_CD 0xe14 /*RxIQ imblance matrix coeff. C & D*/
2352#define RXIQC_AC 0x02ff /*bit mask for IQC matrix element A & C*/
2353#define RXIQC_BD 0x02ff0000 /*bit mask for IQC matrix element A & C*/
2354
2355/* 2 EFUSE_TEST (For RTL8723 partially) */
2356#define EFUSE_SEL(x) (((x) & 0x3) << 8)
2357#define EFUSE_SEL_MASK 0x300
2358#define EFUSE_WIFI_SEL_0 0x0
2359
2360/*REG_MULTI_FUNC_CTRL(For RTL8723 Only)*/
2361#define WL_HWPDN_EN BIT(0) /* Enable GPIO[9] as WiFi HW PDn source*/
2362#define WL_HWPDN_SL BIT(1) /* WiFi HW PDn polarity control*/
2363#define WL_FUNC_EN BIT(2) // WiFi function enable
2364#define WL_HWROF_EN BIT(3) // Enable GPIO[9] as WiFi RF HW PDn source
2365#define BT_HWPDN_EN BIT(16) // Enable GPIO[11] as BT HW PDn source
2366#define BT_HWPDN_SL BIT(17) // BT HW PDn polarity control
2367#define BT_FUNC_EN BIT(18) // BT function enable
2368#define BT_HWROF_EN BIT(19) // Enable GPIO[11] as BT/GPS RF HW PDn source
2369#define GPS_HWPDN_EN BIT(20) // Enable GPIO[10] as GPS HW PDn source
2370#define GPS_HWPDN_SL BIT(21) // GPS HW PDn polarity control
2371#define GPS_FUNC_EN BIT(22) // GPS function enable
2372
2373
2374#define BMASKBYTE0 0xff
2375#define BMASKBYTE1 0xff00
2376#define BMASKBYTE2 0xff0000
2377#define BMASKBYTE3 0xff000000
2378#define BMASKHWORD 0xffff0000
2379#define BMASKLWORD 0x0000ffff
2380#define BMASKDWORD 0xffffffff
2381#define BMASK12BITS 0xfff
2382#define BMASKH4BITS 0xf0000000
2383#define BMASKOFDM_D 0xffc00000
2384#define BMASKCCK 0x3f3f3f3f
2385
2386#define BRFREGOFFSETMASK 0xfffff
2387
2388#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
2389#define ODM_REG_BB_RX_PATH_11AC 0x808
2390/*PAGE 9*/
2391#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
2392/*PAGE A*/
2393#define ODM_REG_CCK_CCA_11AC 0xA0A
2394#define ODM_REG_CCK_FA_RST_11AC 0xA2C
2395#define ODM_REG_CCK_FA_11AC 0xA5C
2396/*PAGE C*/
2397#define ODM_REG_IGI_A_11AC 0xC50
2398/*PAGE E*/
2399#define ODM_REG_IGI_B_11AC 0xE50
2400/*PAGE F*/
2401#define ODM_REG_OFDM_FA_11AC 0xF48
2402
2403
2404//2 MAC REG LIST
2405
2406
2407
2408
2409//DIG Related
2410#define ODM_BIT_IGI_11AC 0xFFFFFFFF
2411#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16
2412#define ODM_BIT_BB_RX_PATH_11AC 0xF
2413
2414typedef enum AGGRE_SIZE{
2415 HT_AGG_SIZE_8K = 0,
2416 HT_AGG_SIZE_16K = 1,
2417 HT_AGG_SIZE_32K = 2,
2418 HT_AGG_SIZE_64K = 3,
2419 VHT_AGG_SIZE_128K = 4,
2420 VHT_AGG_SIZE_256K = 5,
2421 VHT_AGG_SIZE_512K = 6,
2422 VHT_AGG_SIZE_1024K = 7,
2423}AGGRE_SIZE_E, *PAGGRE_SIZE_E;
2424
2425#define REG_AMPDU_MAX_LENGTH_8812 0x0458
2426
2427#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/rf.c b/drivers/staging/rtl8821ae/rtl8821ae/rf.c
new file mode 100644
index 000000000000..87c1c9746c43
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/rf.c
@@ -0,0 +1,464 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "reg.h"
32#include "def.h"
33#include "phy.h"
34#include "rf.h"
35#include "dm.h"
36
37static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
38
39void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
40{
41 struct rtl_priv *rtlpriv = rtl_priv(hw);
42
43 switch (bandwidth) {
44 case HT_CHANNEL_WIDTH_20:
45 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3);
46 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3);
47 break;
48 case HT_CHANNEL_WIDTH_20_40:
49 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1);
50 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1);
51 break;
52 case HT_CHANNEL_WIDTH_80:
53 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0);
54 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0);
55 break;
56 default:
57 RT_TRACE(COMP_ERR, DBG_EMERG,
58 ("unknown bandwidth: %#X\n", bandwidth));
59 break;
60 }
61}
62
63void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
64 u8 *ppowerlevel)
65{
66 struct rtl_priv *rtlpriv = rtl_priv(hw);
67 struct rtl_phy *rtlphy = &(rtlpriv->phy);
68 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
69 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
70 u32 tx_agc[2] = {0, 0}, tmpval;
71 bool turbo_scanoff = false;
72 u8 idx1, idx2;
73 u8 *ptr;
74 u8 direction;
75 u32 pwrtrac_value;
76
77 if (rtlefuse->eeprom_regulatory != 0)
78 turbo_scanoff = true;
79
80 if (mac->act_scanning == true) {
81 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
82 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
83
84 if (turbo_scanoff) {
85 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
86 tx_agc[idx1] = ppowerlevel[idx1] |
87 (ppowerlevel[idx1] << 8) |
88 (ppowerlevel[idx1] << 16) |
89 (ppowerlevel[idx1] << 24);
90 }
91 }
92 } else {
93 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
94 tx_agc[idx1] = ppowerlevel[idx1] |
95 (ppowerlevel[idx1] << 8) |
96 (ppowerlevel[idx1] << 16) |
97 (ppowerlevel[idx1] << 24);
98 }
99
100 if (rtlefuse->eeprom_regulatory == 0) {
101 tmpval =
102 (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
103 (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
104 8);
105 tx_agc[RF90_PATH_A] += tmpval;
106
107 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
108 (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
109 24);
110 tx_agc[RF90_PATH_B] += tmpval;
111 }
112 }
113
114 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
115 ptr = (u8 *) (&(tx_agc[idx1]));
116 for (idx2 = 0; idx2 < 4; idx2++) {
117 if (*ptr > RF6052_MAX_TX_PWR)
118 *ptr = RF6052_MAX_TX_PWR;
119 ptr++;
120 }
121 }
122 rtl8821ae_dm_txpower_track_adjust(hw,1,&direction,&pwrtrac_value);
123 if (direction ==1){
124 tx_agc[0] += pwrtrac_value;
125 tx_agc[1] += pwrtrac_value;
126 } else if (direction == 2){
127 tx_agc[0] -= pwrtrac_value;
128 tx_agc[1] -= pwrtrac_value;
129 }
130 tmpval = tx_agc[RF90_PATH_A] ;
131 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKDWORD, tmpval);
132
133 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
134 ("CCK PWR 1~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
135 RTXAGC_A_CCK11_CCK1));
136
137 tmpval = tx_agc[RF90_PATH_B] ;
138 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKDWORD, tmpval);
139
140 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
141 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
142 RTXAGC_B_CCK11_CCK1));
143}
144
145static void rtl8821ae_phy_get_power_base(struct ieee80211_hw *hw,
146 u8 *ppowerlevel_ofdm, u8 *ppowerlevel_bw20, u8 *ppowerlevel_bw40, u8 channel,
147 u32 *ofdmbase, u32 *mcsbase)
148{
149 struct rtl_priv *rtlpriv = rtl_priv(hw);
150 struct rtl_phy *rtlphy = &(rtlpriv->phy);
151 u32 powerBase0, powerBase1;
152 u8 i, powerlevel[2];
153
154 for (i = 0; i < 2; i++) {
155 powerBase0 = ppowerlevel_ofdm[i];
156
157 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
158 (powerBase0 << 8) | powerBase0;
159 *(ofdmbase + i) = powerBase0;
160 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
161 (" [OFDM power base index rf(%c) = 0x%x]\n",
162 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
163 }
164
165 for (i = 0; i < 2; i++) {
166 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
167 powerlevel[i] = ppowerlevel_bw20[i];
168 }else{
169 powerlevel[i] = ppowerlevel_bw40[i];
170 }
171 powerBase1 = powerlevel[i];
172 powerBase1 = (powerBase1 << 24) |
173 (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
174
175 *(mcsbase + i) = powerBase1;
176
177 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
178 (" [MCS power base index rf(%c) = 0x%x]\n",
179 ((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
180 }
181}
182
183static void _rtl8821ae_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
184 u8 channel, u8 index,
185 u32 *powerBase0,
186 u32 *powerBase1,
187 u32 *p_outwriteval)
188{
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 struct rtl_phy *rtlphy = &(rtlpriv->phy);
191 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
192 u8 i, chnlgroup = 0, pwr_diff_limit[4],pwr_diff = 0,customer_pwr_diff;
193 u32 writeVal, customer_limit, rf;
194
195 for (rf = 0; rf < 2; rf++) {
196 switch (rtlefuse->eeprom_regulatory) {
197 case 0:
198 chnlgroup = 0;
199
200 writeVal =
201 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
202 (rf ? 8 : 0)]
203 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
204
205 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
206 ("RTK better performance, "
207 "writeVal(%c) = 0x%x\n",
208 ((rf == 0) ? 'A' : 'B'), writeVal));
209 break;
210 case 1:
211 if (rtlphy->pwrgroup_cnt == 1)
212 chnlgroup = 0;
213 else {
214 if(channel<3)
215 chnlgroup = 0;
216 else if (channel <6)
217 chnlgroup = 1;
218 else if (channel <9)
219 chnlgroup = 2;
220 else if (channel <12)
221 chnlgroup = 3;
222 else if (channel < 14)
223 chnlgroup = 4;
224 else if (channel == 14)
225 chnlgroup = 5;
226 }
227
228 writeVal =
229 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
230 [index + (rf ? 8 : 0)] + ((index < 2) ?
231 powerBase0[rf] :
232 powerBase1[rf]);
233
234 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
235 ("Realtek regulatory, 20MHz, "
236 "writeVal(%c) = 0x%x\n",
237 ((rf == 0) ? 'A' : 'B'), writeVal));
238
239 break;
240 case 2:
241 writeVal =
242 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
243
244 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
245 ("Better regulatory, "
246 "writeVal(%c) = 0x%x\n",
247 ((rf == 0) ? 'A' : 'B'), writeVal));
248 break;
249 case 3:
250 chnlgroup = 0;
251
252 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
253 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
254 ("customer's limit, 40MHz "
255 "rf(%c) = 0x%x\n",
256 ((rf == 0) ? 'A' : 'B'),
257 rtlefuse->pwrgroup_ht40[rf][channel -
258 1]));
259 } else {
260 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
261 ("customer's limit, 20MHz "
262 "rf(%c) = 0x%x\n",
263 ((rf == 0) ? 'A' : 'B'),
264 rtlefuse->pwrgroup_ht20[rf][channel -
265 1]));
266 }
267
268 if (index < 2)
269 pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
270 else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
271 pwr_diff = rtlefuse->txpwr_ht20diff[rf][channel-1];
272
273 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
274 customer_pwr_diff = rtlefuse->pwrgroup_ht40[rf][channel-1];
275 else
276 customer_pwr_diff = rtlefuse->pwrgroup_ht20[rf][channel-1];
277
278 if (pwr_diff > customer_pwr_diff)
279 pwr_diff = 0;
280 else
281 pwr_diff = customer_pwr_diff - pwr_diff;
282
283 for (i = 0; i < 4; i++) {
284 pwr_diff_limit[i] =
285 (u8) ((rtlphy->mcs_txpwrlevel_origoffset
286 [chnlgroup][index + (rf ? 8 : 0)] & (0x7f <<
287 (i * 8))) >> (i * 8));
288
289 if(pwr_diff_limit[i] > pwr_diff)
290 pwr_diff_limit[i] = pwr_diff;
291 }
292
293 customer_limit = (pwr_diff_limit[3] << 24) |
294 (pwr_diff_limit[2] << 16) |
295 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
296
297 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
298 ("Customer's limit rf(%c) = 0x%x\n",
299 ((rf == 0) ? 'A' : 'B'), customer_limit));
300
301 writeVal = customer_limit +
302 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
303
304 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
305 ("Customer, writeVal rf(%c)= 0x%x\n",
306 ((rf == 0) ? 'A' : 'B'), writeVal));
307 break;
308 default:
309 chnlgroup = 0;
310 writeVal =
311 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
312 [index + (rf ? 8 : 0)]
313 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
314
315 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
316 ("RTK better performance, writeVal "
317 "rf(%c) = 0x%x\n",
318 ((rf == 0) ? 'A' : 'B'), writeVal));
319 break;
320 }
321
322 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
323 writeVal = writeVal - 0x06060606;
324 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
325 TXHIGHPWRLEVEL_BT2)
326 writeVal = writeVal - 0x0c0c0c0c;
327 *(p_outwriteval + rf) = writeVal;
328 }
329}
330
331static void _rtl8821ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
332 u8 index, u32 *pValue)
333{
334 struct rtl_priv *rtlpriv = rtl_priv(hw);
335 u16 regoffset_a[6] = {
336 RTXAGC_A_OFDM18_OFDM6, RTXAGC_A_OFDM54_OFDM24,
337 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
338 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
339 };
340 u16 regoffset_b[6] = {
341 RTXAGC_B_OFDM18_OFDM6, RTXAGC_B_OFDM54_OFDM24,
342 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
343 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
344 };
345 u8 i, rf, pwr_val[4];
346 u32 writeVal;
347 u16 regoffset;
348
349 for (rf = 0; rf < 2; rf++) {
350 writeVal = pValue[rf];
351 for (i = 0; i < 4; i++) {
352 pwr_val[i] = (u8) ((writeVal & (0x7f <<
353 (i * 8))) >> (i * 8));
354
355 if (pwr_val[i] > RF6052_MAX_TX_PWR)
356 pwr_val[i] = RF6052_MAX_TX_PWR;
357 }
358 writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
359 (pwr_val[1] << 8) | pwr_val[0];
360
361 if (rf == 0)
362 regoffset = regoffset_a[index];
363 else
364 regoffset = regoffset_b[index];
365 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
366
367 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
368 ("Set 0x%x = %08x\n", regoffset, writeVal));
369 }
370}
371
372void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
373 u8 *ppowerlevel_ofdm, u8 *ppowerlevel_bw20, u8 *ppowerlevel_bw40, u8 channel)
374{
375 u32 writeVal[2], powerBase0[2], powerBase1[2];
376 u8 index;
377 u8 direction;
378 u32 pwrtrac_value;
379
380 rtl8821ae_phy_get_power_base(hw, ppowerlevel_ofdm, ppowerlevel_bw20, ppowerlevel_bw40,
381 channel, &powerBase0[0], &powerBase1[0]);
382
383 rtl8821ae_dm_txpower_track_adjust(hw,1,&direction,&pwrtrac_value);
384
385 for (index = 0; index < 6; index++) {
386 _rtl8821ae_get_txpower_writeval_by_regulatory(hw,
387 channel, index,
388 &powerBase0[0],
389 &powerBase1[0],
390 &writeVal[0]);
391 if (direction ==1){
392 writeVal[0] += pwrtrac_value;
393 writeVal[1] += pwrtrac_value;
394 } else if (direction == 2){
395 writeVal[0] -= pwrtrac_value;
396 writeVal[1] -= pwrtrac_value;
397 }
398 _rtl8821ae_write_ofdm_power_reg(hw, index, &writeVal[0]);
399 }
400}
401
402bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw)
403{
404 struct rtl_priv *rtlpriv = rtl_priv(hw);
405 struct rtl_phy *rtlphy = &(rtlpriv->phy);
406
407 if (rtlphy->rf_type == RF_1T1R)
408 rtlphy->num_total_rfpath = 1;
409 else
410 rtlphy->num_total_rfpath = 2;
411
412 return _rtl8821ae_phy_rf6052_config_parafile(hw);
413
414}
415
416static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
417{
418 struct rtl_priv *rtlpriv = rtl_priv(hw);
419 struct rtl_phy *rtlphy = &(rtlpriv->phy);
420 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
421 //u32 u4_regvalue = 0;
422 u8 rfpath;
423 bool rtstatus = true;
424 //struct bb_reg_def *pphyreg;
425
426 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
427 switch (rfpath) {
428 case RF90_PATH_A: {
429 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
430 rtstatus = rtl8812ae_phy_config_rf_with_headerfile(hw,
431 (enum radio_path)rfpath);
432 else
433 rtstatus = rtl8821ae_phy_config_rf_with_headerfile(hw,
434 (enum radio_path)rfpath);
435 break;
436 }
437 case RF90_PATH_B: {
438 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
439 rtstatus = rtl8812ae_phy_config_rf_with_headerfile(hw,
440 (enum radio_path)rfpath);
441 else
442 rtstatus = rtl8821ae_phy_config_rf_with_headerfile(hw,
443 (enum radio_path)rfpath);
444 break;
445 }
446 case RF90_PATH_C:
447 break;
448 case RF90_PATH_D:
449 break;
450 }
451
452 if (rtstatus != true) {
453 RT_TRACE(COMP_INIT, DBG_TRACE,
454 ("Radio[%d] Fail!!", rfpath));
455 return false;
456 }
457
458 }
459
460 /*put arrays in dm.c*/
461 /*_rtl8821ae_config_rf_txpwr_track_headerfile(hw);*/
462 RT_TRACE(COMP_INIT, DBG_TRACE, ("\n"));
463 return rtstatus;
464}
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/rf.h b/drivers/staging/rtl8821ae/rtl8821ae/rf.h
new file mode 100644
index 000000000000..b665c0ff1b7d
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/rf.h
@@ -0,0 +1,46 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8821AE_RF_H__
31#define __RTL8821AE_RF_H__
32
33#define RF6052_MAX_TX_PWR 0x3F
34#define RF6052_MAX_REG 0x3F
35
36extern void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
37 u8 bandwidth);
38extern void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
39 u8 *ppowerlevel);
40extern void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
41 u8 *ppowerlevel_ofdm,
42 u8 *ppowerlevel_bw20,
43 u8 *ppowerlevel_bw40,
44 u8 channel);
45extern bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw);
46#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/sw.c b/drivers/staging/rtl8821ae/rtl8821ae/sw.c
new file mode 100644
index 000000000000..85a3474fc099
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/sw.c
@@ -0,0 +1,499 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include <linux/vmalloc.h>
31#include <linux/module.h>
32
33#include "../wifi.h"
34#include "../core.h"
35#include "../pci.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "dm.h"
40#include "hw.h"
41#include "sw.h"
42#include "trx.h"
43#include "led.h"
44#include "table.h"
45#include "hal_btc.h"
46#include "../btcoexist/rtl_btc.h"
47
48void rtl8821ae_init_aspm_vars(struct ieee80211_hw *hw)
49{
50 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
51
52 /*close ASPM for AMD defaultly */
53 rtlpci->const_amdpci_aspm = 0;
54
55 /*
56 * ASPM PS mode.
57 * 0 - Disable ASPM,
58 * 1 - Enable ASPM without Clock Req,
59 * 2 - Enable ASPM with Clock Req,
60 * 3 - Alwyas Enable ASPM with Clock Req,
61 * 4 - Always Enable ASPM without Clock Req.
62 * set defult to RTL8192CE:3 RTL8192E:2
63 * */
64 rtlpci->const_pci_aspm = 3;
65
66 /*Setting for PCI-E device */
67 rtlpci->const_devicepci_aspm_setting = 0x03;
68
69 /*Setting for PCI-E bridge */
70 rtlpci->const_hostpci_aspm_setting = 0x02;
71
72 /*
73 * In Hw/Sw Radio Off situation.
74 * 0 - Default,
75 * 1 - From ASPM setting without low Mac Pwr,
76 * 2 - From ASPM setting with low Mac Pwr,
77 * 3 - Bus D3
78 * set default to RTL8192CE:0 RTL8192SE:2
79 */
80 rtlpci->const_hwsw_rfoff_d3 = 0;
81
82 /*
83 * This setting works for those device with
84 * backdoor ASPM setting such as EPHY setting.
85 * 0 - Not support ASPM,
86 * 1 - Support ASPM,
87 * 2 - According to chipset.
88 */
89 rtlpci->const_support_pciaspm = 1;
90}
91
92/*InitializeVariables8812E*/
93int rtl8821ae_init_sw_vars(struct ieee80211_hw *hw)
94{
95 int err = 0;
96 struct rtl_priv *rtlpriv = rtl_priv(hw);
97 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
98 const struct firmware *firmware;
99 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
100 char *fw_name = NULL;
101
102 rtl8821ae_bt_reg_init(hw);
103 rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
104
105 rtlpriv->dm.b_dm_initialgain_enable = 1;
106 rtlpriv->dm.dm_flag = 0;
107 rtlpriv->dm.b_disable_framebursting = 0;;
108 rtlpriv->dm.thermalvalue = 0;
109 rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25);
110
111 mac->ht_enable = true;
112
113 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
114 /*following 2 is for register 5G band, refer to _rtl_init_mac80211()*/
115 rtlpriv->rtlhal.bandset = BAND_ON_BOTH;
116 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
117
118 rtlpci->receive_config = (RCR_APPFCS |
119 RCR_APP_MIC |
120 RCR_APP_ICV |
121 RCR_APP_PHYST_RXFF |
122 RCR_NONQOS_VHT |
123 RCR_HTC_LOC_CTRL |
124 RCR_AMF |
125 RCR_ACF |
126 RCR_ADF | /*This bit controls the PS-Poll packet filter.*/
127 RCR_AICV |
128 RCR_ACRC32 |
129 RCR_AB |
130 RCR_AM |
131 RCR_APM |
132 0);
133
134
135 rtlpci->irq_mask[0] =
136 (u32) (IMR_PSTIMEOUT |
137 IMR_GTINT3 |
138 /*IMR_TBDER |
139 IMR_TBDOK |
140 IMR_BCNDMAINT0 |*/
141 IMR_HSISR_IND_ON_INT |
142 IMR_C2HCMD |
143 IMR_HIGHDOK |
144 IMR_MGNTDOK |
145 IMR_BKDOK |
146 IMR_BEDOK |
147 IMR_VIDOK |
148 IMR_VODOK |
149 IMR_RDU |
150 IMR_ROK |
151 0);
152
153 rtlpci->irq_mask[1] =
154 (u32)( IMR_RXFOVW |
155 IMR_TXFOVW |
156 0);
157
158 /* for LPS & IPS */
159 rtlpriv->psc.b_inactiveps = rtlpriv->cfg->mod_params->b_inactiveps;
160 rtlpriv->psc.b_swctrl_lps = rtlpriv->cfg->mod_params->b_swctrl_lps;
161 rtlpriv->psc.b_fwctrl_lps = rtlpriv->cfg->mod_params->b_fwctrl_lps;
162 rtlpriv->psc.b_reg_fwctrl_lps = 3;
163 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
164 /* for ASPM, you can close aspm through
165 * set const_support_pciaspm = 0 */
166 rtl8821ae_init_aspm_vars(hw);
167
168 if (rtlpriv->psc.b_reg_fwctrl_lps == 1)
169 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
170 else if (rtlpriv->psc.b_reg_fwctrl_lps == 2)
171 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
172 else if (rtlpriv->psc.b_reg_fwctrl_lps == 3)
173 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
174
175 /* for firmware buf */
176 rtlpriv->rtlhal.pfirmware = (u8 *) vmalloc(0x8000);
177 if (!rtlpriv->rtlhal.pfirmware) {
178 RT_TRACE(COMP_ERR, DBG_EMERG,
179 ("Can't alloc buffer for fw.\n"));
180 return 1;
181 }
182
183 fw_name = "rtlwifi/rtl8821aefw.bin";
184 err = request_firmware(&firmware, fw_name, rtlpriv->io.dev);
185 if (err) {
186 RT_TRACE(COMP_ERR, DBG_EMERG,
187 ("Failed to request firmware!\n"));
188 return 1;
189 }
190
191 if (firmware->size > 0x8000) {
192 RT_TRACE(COMP_ERR, DBG_EMERG,
193 ("Firmware is too big!\n"));
194 release_firmware(firmware);
195 return 1;
196 }
197
198 memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
199 rtlpriv->rtlhal.fwsize = firmware->size;
200 release_firmware(firmware);
201
202 if (rtlpriv->cfg->ops->get_btc_status()){
203 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
204 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
205 }
206
207 RT_TRACE(COMP_INIT, DBG_LOUD, (" FirmwareDownload OK\n"));
208 return err;
209}
210
211void rtl8821ae_deinit_sw_vars(struct ieee80211_hw *hw)
212{
213 struct rtl_priv *rtlpriv = rtl_priv(hw);
214
215 //printk("=========>rtl8821ae_deinit_sw_vars().\n");
216 if (rtlpriv->cfg->ops->get_btc_status()){
217 //printk("=========>rtl8821ae_deinit_sw_vars().get_btc_status\n");
218 rtlpriv->btcoexist.btc_ops->btc_halt_notify();
219 }
220 if (rtlpriv->rtlhal.pfirmware) {
221 //printk("=========>rtl8821ae_deinit_sw_vars().rtlpriv->rtlhal.pfirmware\n");
222 vfree(rtlpriv->rtlhal.pfirmware);
223 rtlpriv->rtlhal.pfirmware = NULL;
224 }
225 //printk("<=========rtl8821ae_deinit_sw_vars().\n");
226}
227
228u32 rtl8812ae_rx_command_packet_handler(
229 struct ieee80211_hw *hw,
230 struct rtl_stats status,
231 struct sk_buff *skb
232 )
233{
234 u32 result = 0;
235 struct rtl_priv *rtlpriv = rtl_priv(hw);
236
237 switch (status.packet_report_type) {
238 case NORMAL_RX:
239 result = 0;
240 break;
241 case C2H_PACKET:
242 rtl8812ae_c2h_packet_handler(hw, skb->data, (u8) skb->len);
243 result = 1;
244 RT_TRACE(COMP_RECV, DBG_LOUD,
245 ("===>rtl8821ae_rx_command_packet_handler(): (u8) skb->len=%d\n\n", skb->len));
246 break;
247 default:
248 RT_TRACE(COMP_RECV, DBG_LOUD,
249 ("===>rtl8821ae_rx_command_packet_handler(): No this packet type!!\n"));
250 break;
251 }
252
253 return result;
254}
255
256
257/* get bt coexist status */
258bool rtl8821ae_get_btc_status(void)
259{
260 return true;
261}
262
263struct rtl_hal_ops rtl8821ae_hal_ops = {
264 .init_sw_vars = rtl8821ae_init_sw_vars,
265 .deinit_sw_vars = rtl8821ae_deinit_sw_vars,
266 .read_eeprom_info = rtl8821ae_read_eeprom_info,
267 .interrupt_recognized = rtl8821ae_interrupt_recognized,
268 .hw_init = rtl8821ae_hw_init,
269 .hw_disable = rtl8821ae_card_disable,
270 .hw_suspend = rtl8821ae_suspend,
271 .hw_resume = rtl8821ae_resume,
272 .enable_interrupt = rtl8821ae_enable_interrupt,
273 .disable_interrupt = rtl8821ae_disable_interrupt,
274 .set_network_type = rtl8821ae_set_network_type,
275 .set_chk_bssid = rtl8821ae_set_check_bssid,
276 .set_qos = rtl8821ae_set_qos,
277 .set_bcn_reg = rtl8821ae_set_beacon_related_registers,
278 .set_bcn_intv = rtl8821ae_set_beacon_interval,
279 .update_interrupt_mask = rtl8821ae_update_interrupt_mask,
280 .get_hw_reg = rtl8821ae_get_hw_reg,
281 .set_hw_reg = rtl8821ae_set_hw_reg,
282 .update_rate_tbl = rtl8821ae_update_hal_rate_tbl,
283 .fill_tx_desc = rtl8821ae_tx_fill_desc,
284 .fill_tx_cmddesc = rtl8821ae_tx_fill_cmddesc,
285 .query_rx_desc = rtl8821ae_rx_query_desc,
286 .set_channel_access = rtl8821ae_update_channel_access_setting,
287 .radio_onoff_checking = rtl8821ae_gpio_radio_on_off_checking,
288 .set_bw_mode = rtl8821ae_phy_set_bw_mode,
289 .switch_channel = rtl8821ae_phy_sw_chnl,
290 .dm_watchdog = rtl8821ae_dm_watchdog,
291 .scan_operation_backup = rtl8821ae_phy_scan_operation_backup,
292 .set_rf_power_state = rtl8821ae_phy_set_rf_power_state,
293 .led_control = rtl8821ae_led_control,
294 .set_desc = rtl8821ae_set_desc,
295 .get_desc = rtl8821ae_get_desc,
296 .is_tx_desc_closed = rtl8821ae_is_tx_desc_closed,
297 .tx_polling = rtl8821ae_tx_polling,
298 .enable_hw_sec = rtl8821ae_enable_hw_security_config,
299 .set_key = rtl8821ae_set_key,
300 .init_sw_leds = rtl8821ae_init_sw_leds,
301 .allow_all_destaddr = rtl8821ae_allow_all_destaddr,
302 .get_bbreg = rtl8821ae_phy_query_bb_reg,
303 .set_bbreg = rtl8821ae_phy_set_bb_reg,
304 .get_rfreg = rtl8821ae_phy_query_rf_reg,
305 .set_rfreg = rtl8821ae_phy_set_rf_reg,
306 .c2h_command_handle = rtl_8821ae_c2h_command_handle,
307 .bt_wifi_media_status_notify = rtl_8821ae_bt_wifi_media_status_notify,
308 .bt_turn_off_bt_coexist_before_enter_lps = rtl8821ae_dm_bt_turn_off_bt_coexist_before_enter_lps,
309 .fill_h2c_cmd = rtl8821ae_fill_h2c_cmd,
310 .get_btc_status = rtl8821ae_get_btc_status,
311 .rx_command_packet_handler = rtl8812ae_rx_command_packet_handler,
312};
313
314struct rtl_mod_params rtl8821ae_mod_params = {
315 .sw_crypto = false,
316 .b_inactiveps = false,//true,
317 .b_swctrl_lps = false,
318 .b_fwctrl_lps = false, //true,
319};
320
321struct rtl_hal_cfg rtl8821ae_hal_cfg = {
322 .bar_id = 2,
323 .write_readback = true,
324 .name = "rtl8821ae_pci",
325 .fw_name = "rtlwifi/rtl8821aefw.bin",
326 .ops = &rtl8821ae_hal_ops,
327 .mod_params = &rtl8821ae_mod_params,
328 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
329 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
330 .maps[SYS_CLK] = REG_SYS_CLKR,
331 .maps[MAC_RCR_AM] = AM,
332 .maps[MAC_RCR_AB] = AB,
333 .maps[MAC_RCR_ACRC32] = ACRC32,
334 .maps[MAC_RCR_ACF] = ACF,
335 .maps[MAC_RCR_AAP] = AAP,
336 .maps[MAC_HIMR] = REG_HIMR,
337 .maps[MAC_HIMRE] = REG_HIMRE,
338
339
340 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
341
342 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
343 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
344 .maps[EFUSE_CLK] = 0,
345 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
346 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
347 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
348 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
349 .maps[EFUSE_ANA8M] = ANA8M,
350 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
351 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
352 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
353 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
354
355 .maps[RWCAM] = REG_CAMCMD,
356 .maps[WCAMI] = REG_CAMWRITE,
357 .maps[RCAMO] = REG_CAMREAD,
358 .maps[CAMDBG] = REG_CAMDBG,
359 .maps[SECR] = REG_SECCFG,
360 .maps[SEC_CAM_NONE] = CAM_NONE,
361 .maps[SEC_CAM_WEP40] = CAM_WEP40,
362 .maps[SEC_CAM_TKIP] = CAM_TKIP,
363 .maps[SEC_CAM_AES] = CAM_AES,
364 .maps[SEC_CAM_WEP104] = CAM_WEP104,
365
366 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
367 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
368 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
369 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
370 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
371 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
372/* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
373 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
374 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
375 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
376 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
377 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
378 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
379 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
380/* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
381/* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
382
383 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
384 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
385 .maps[RTL_IMR_BcnInt] = IMR_BCNDMAINT0,
386 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
387 .maps[RTL_IMR_RDU] = IMR_RDU,
388 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
389 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
390 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
391 .maps[RTL_IMR_TBDER] = IMR_TBDER,
392 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
393 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
394 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
395 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
396 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
397 .maps[RTL_IMR_VODOK] = IMR_VODOK,
398 .maps[RTL_IMR_ROK] = IMR_ROK,
399 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
400
401 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
402 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
403 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
404 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
405 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
406 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
407 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
408 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
409 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
410 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
411 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
412 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
413
414 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
415 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
416};
417
418#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0))
419static struct pci_device_id rtl8821ae_pci_ids[] = {
420 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8812, rtl8821ae_hal_cfg)},
421 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8821, rtl8821ae_hal_cfg)},
422 {},
423};
424#else
425static struct pci_device_id rtl8821ae_pci_ids[] __devinitdata = {
426 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8812, rtl8821ae_hal_cfg)},
427 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8821, rtl8821ae_hal_cfg)},
428 {},
429};
430#endif
431
432MODULE_DEVICE_TABLE(pci, rtl8821ae_pci_ids);
433
434MODULE_AUTHOR("Ping Yan<ping_yan@realsil.com.cn>");
435MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
436MODULE_LICENSE("GPL");
437MODULE_DESCRIPTION("Realtek 8821ae 802.11ac PCI wireless");
438MODULE_FIRMWARE("rtlwifi/rtl8821aefw.bin");
439
440module_param_named(swenc, rtl8821ae_mod_params.sw_crypto, bool, 0444);
441module_param_named(ips, rtl8821ae_mod_params.b_inactiveps, bool, 0444);
442module_param_named(swlps, rtl8821ae_mod_params.b_swctrl_lps, bool, 0444);
443module_param_named(fwlps, rtl8821ae_mod_params.b_fwctrl_lps, bool, 0444);
444MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
445MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n");
446MODULE_PARM_DESC(fwlps, "using linked fw control power save (default 1 is open)\n");
447
448#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29))
449static const SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
450#endif
451
452#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29))
453compat_pci_suspend(rtl_pci_suspend)
454compat_pci_resume(rtl_pci_resume)
455#endif
456
457static struct pci_driver rtl8821ae_driver = {
458 .name = KBUILD_MODNAME,
459 .id_table = rtl8821ae_pci_ids,
460 .probe = rtl_pci_probe,
461 .remove = rtl_pci_disconnect,
462
463#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29))
464 .driver.pm = &rtlwifi_pm_ops,
465#elif defined(CONFIG_PM)
466 .suspend = rtl_pci_suspend_compat,
467 .resume = rtl_pci_resume_compat,
468#endif
469
470};
471
472
473extern int rtl_core_module_init(void);
474extern void rtl_core_module_exit(void);
475
476static int __init rtl8821ae_module_init(void)
477{
478 int ret;
479
480 ret = rtl_core_module_init();
481 if (ret)
482 return ret;
483
484 //printk("==========>rtl8821ae_module_init().\n");
485 ret = pci_register_driver(&rtl8821ae_driver);
486 if (ret)
487 RT_ASSERT(false, (": No device found\n"));
488
489 return ret;
490}
491
492static void __exit rtl8821ae_module_exit(void)
493{
494 pci_unregister_driver(&rtl8821ae_driver);
495 rtl_core_module_exit();
496}
497
498module_init(rtl8821ae_module_init);
499module_exit(rtl8821ae_module_exit);
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/sw.h b/drivers/staging/rtl8821ae/rtl8821ae/sw.h
new file mode 100644
index 000000000000..3d49b2f043da
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/sw.h
@@ -0,0 +1,39 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8821AE_SW_H__
31#define __RTL8821AE_SW_H__
32
33int rtl8821ae_init_sw_vars(struct ieee80211_hw *hw);
34void rtl8821ae_deinit_sw_vars(struct ieee80211_hw *hw);
35void rtl8821ae_init_var_map(struct ieee80211_hw *hw);
36bool rtl8821ae_get_btc_status(void);
37
38
39#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/table.c b/drivers/staging/rtl8821ae/rtl8821ae/table.c
new file mode 100644
index 000000000000..a6c4ca4fd9b2
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/table.c
@@ -0,0 +1,4002 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Created on 2010/ 5/18, 1:41
27 *
28 * Larry Finger <Larry.Finger@lwfinger.net>
29 *
30 *****************************************************************************/
31
32#include "table.h"
33u32 RTL8812AE_PHY_REG_ARRAY[] = {
34 0x800, 0x8020D010,
35 0x804, 0x080112E0,
36 0x808, 0x0E028233,
37 0x80C, 0x12131113,
38 0x810, 0x20101263,
39 0x814, 0x020C3D10,
40 0x818, 0x03A00385,
41 0x820, 0x00000000,
42 0x824, 0x00030FE0,
43 0x828, 0x00000000,
44 0x82C, 0x002083DD,
45 0x830, 0x2AAA6C86,
46 0x834, 0x0037A706,
47 0x838, 0x06C89B44,
48 0x83C, 0x0000095B,
49 0x840, 0xC0000001,
50 0x844, 0x40003CDE,
51 0x848, 0x6210FF8B,
52 0x84C, 0x6CFDFFB8,
53 0x850, 0x28874706,
54 0x854, 0x0001520C,
55 0x858, 0x8060E000,
56 0x85C, 0x74210168,
57 0x860, 0x6929C321,
58 0x864, 0x79727432,
59 0x868, 0x8CA7A314,
60 0x86C, 0x338C2878,
61 0x870, 0x03333333,
62 0x874, 0x31602C2E,
63 0x878, 0x00003152,
64 0x87C, 0x000FC000,
65 0x8A0, 0x00000013,
66 0x8A4, 0x7F7F7F7F,
67 0x8A8, 0xA202033E,
68 0x8AC, 0x0FF0FA0A,
69 0x8B0, 0x00000600,
70 0x8B4, 0x000FC080,
71 0x8B8, 0x6C0057FF,
72 0x8BC, 0x4CA520A3,
73 0x8C0, 0x27F00020,
74 0x8C4, 0x00000000,
75 0x8C8, 0x00013169,
76 0x8CC, 0x08248492,
77 0x8D0, 0x0000B800,
78 0x8DC, 0x00000000,
79 0x8D4, 0x940008A0,
80 0x8D8, 0x290B5612,
81 0x8F8, 0x400002C0,
82 0x8FC, 0x00000000,
83 0xFF0F07D8, 0xABCD,
84 0x900, 0x00000700,
85 0xFF0F07D0, 0xCDEF,
86 0x900, 0x00000700,
87 0xCDCDCDCD, 0xCDCD,
88 0x900, 0x00000700,
89 0xFF0F07D8, 0xDEAD,
90 0x90C, 0x00000000,
91 0x910, 0x0000FC00,
92 0x914, 0x00000404,
93 0x918, 0x1C1028C0,
94 0x91C, 0x64B11A1C,
95 0x920, 0xE0767233,
96 0x924, 0x055AA500,
97 0x928, 0x00000004,
98 0x92C, 0xFFFE0000,
99 0x930, 0xFFFFFFFE,
100 0x934, 0x001FFFFF,
101 0x960, 0x00000000,
102 0x964, 0x00000000,
103 0x968, 0x00000000,
104 0x96C, 0x00000000,
105 0x970, 0x801FFFFF,
106 0x978, 0x00000000,
107 0x97C, 0x00000000,
108 0x980, 0x00000000,
109 0x984, 0x00000000,
110 0x988, 0x00000000,
111 0x990, 0x27100000,
112 0x994, 0xFFFF0100,
113 0x998, 0xFFFFFF5C,
114 0x99C, 0xFFFFFFFF,
115 0x9A0, 0x000000FF,
116 0x9A4, 0x00080080,
117 0x9A8, 0x00000000,
118 0x9AC, 0x00000000,
119 0x9B0, 0x81081008,
120 0x9B4, 0x00000000,
121 0x9B8, 0x01081008,
122 0x9BC, 0x01081008,
123 0x9D0, 0x00000000,
124 0x9D4, 0x00000000,
125 0x9D8, 0x00000000,
126 0x9DC, 0x00000000,
127 0x9E4, 0x00000002,
128 0x9E8, 0x000002D5,
129 0xA00, 0x00D047C8,
130 0xA04, 0x01FF000C,
131 0xA08, 0x8C838300,
132 0xA0C, 0x2E7F000F,
133 0xA10, 0x9500BB78,
134 0xA14, 0x11144028,
135 0xA18, 0x00881117,
136 0xA1C, 0x89140F00,
137 0xA20, 0x1A1B0000,
138 0xA24, 0x090E1317,
139 0xA28, 0x00000204,
140 0xA2C, 0x00900000,
141 0xA70, 0x101FFF00,
142 0xA74, 0x00000008,
143 0xA78, 0x00000900,
144 0xA7C, 0x225B0606,
145 0xA80, 0x218075B2,
146 0xA84, 0x001F8C80,
147 0xB00, 0x03100000,
148 0xB04, 0x0000B000,
149 0xB08, 0xAE0201EB,
150 0xB0C, 0x01003207,
151 0xB10, 0x00009807,
152 0xB14, 0x01000000,
153 0xB18, 0x00000002,
154 0xB1C, 0x00000002,
155 0xB20, 0x0000001F,
156 0xB24, 0x03020100,
157 0xB28, 0x07060504,
158 0xB2C, 0x0B0A0908,
159 0xB30, 0x0F0E0D0C,
160 0xB34, 0x13121110,
161 0xB38, 0x17161514,
162 0xB3C, 0x0000003A,
163 0xB40, 0x00000000,
164 0xB44, 0x00000000,
165 0xB48, 0x13000032,
166 0xB4C, 0x48080000,
167 0xB50, 0x00000000,
168 0xB54, 0x00000000,
169 0xB58, 0x00000000,
170 0xB5C, 0x00000000,
171 0xC00, 0x00000007,
172 0xC04, 0x00042020,
173 0xC08, 0x80410231,
174 0xC0C, 0x00000000,
175 0xC10, 0x00000100,
176 0xC14, 0x01000000,
177 0xC1C, 0x40000003,
178 0xC20, 0x12121212,
179 0xC24, 0x12121212,
180 0xC28, 0x12121212,
181 0xC2C, 0x12121212,
182 0xC30, 0x12121212,
183 0xC34, 0x12121212,
184 0xC38, 0x12121212,
185 0xC3C, 0x12121212,
186 0xC40, 0x12121212,
187 0xC44, 0x12121212,
188 0xC48, 0x12121212,
189 0xC4C, 0x12121212,
190 0xC50, 0x00000020,
191 0xC54, 0x0008121C,
192 0xC58, 0x30000C1C,
193 0xC5C, 0x00000058,
194 0xC60, 0x34344443,
195 0xC64, 0x07003333,
196 0xC68, 0x59791979,
197 0xC6C, 0x59795979,
198 0xC70, 0x19795979,
199 0xC74, 0x19795979,
200 0xC78, 0x19791979,
201 0xC7C, 0x19791979,
202 0xC80, 0x19791979,
203 0xC84, 0x19791979,
204 0xC94, 0x0100005C,
205 0xC98, 0x00000000,
206 0xC9C, 0x00000000,
207 0xCA0, 0x00000029,
208 0xCA4, 0x08040201,
209 0xCA8, 0x80402010,
210 0xFF0F0740, 0xABCD,
211 0xCB0, 0x77547717,
212 0xFF0F01C0, 0xCDEF,
213 0xCB0, 0x77547717,
214 0xFF0F02C0, 0xCDEF,
215 0xCB0, 0x77547717,
216 0xFF0F07D8, 0xCDEF,
217 0xCB0, 0x54547710,
218 0xFF0F07D0, 0xCDEF,
219 0xCB0, 0x54547710,
220 0xCDCDCDCD, 0xCDCD,
221 0xCB0, 0x77547777,
222 0xFF0F0740, 0xDEAD,
223 0xCB4, 0x00000077,
224 0xCB8, 0x00508242,
225 0xE00, 0x00000007,
226 0xE04, 0x00042020,
227 0xE08, 0x80410231,
228 0xE0C, 0x00000000,
229 0xE10, 0x00000100,
230 0xE14, 0x01000000,
231 0xE1C, 0x40000003,
232 0xE20, 0x12121212,
233 0xE24, 0x12121212,
234 0xE28, 0x12121212,
235 0xE2C, 0x12121212,
236 0xE30, 0x12121212,
237 0xE34, 0x12121212,
238 0xE38, 0x12121212,
239 0xE3C, 0x12121212,
240 0xE40, 0x12121212,
241 0xE44, 0x12121212,
242 0xE48, 0x12121212,
243 0xE4C, 0x12121212,
244 0xE50, 0x00000020,
245 0xE54, 0x0008121C,
246 0xE58, 0x30000C1C,
247 0xE5C, 0x00000058,
248 0xE60, 0x34344443,
249 0xE64, 0x07003333,
250 0xE68, 0x59791979,
251 0xE6C, 0x59795979,
252 0xE70, 0x19795979,
253 0xE74, 0x19795979,
254 0xE78, 0x19791979,
255 0xE7C, 0x19791979,
256 0xE80, 0x19791979,
257 0xE84, 0x19791979,
258 0xE94, 0x0100005C,
259 0xE98, 0x00000000,
260 0xE9C, 0x00000000,
261 0xEA0, 0x00000029,
262 0xEA4, 0x08040201,
263 0xEA8, 0x80402010,
264 0xFF0F0740, 0xABCD,
265 0xEB0, 0x77547717,
266 0xFF0F01C0, 0xCDEF,
267 0xEB0, 0x77547717,
268 0xFF0F02C0, 0xCDEF,
269 0xEB0, 0x77547717,
270 0xFF0F07D8, 0xCDEF,
271 0xEB0, 0x54547710,
272 0xFF0F07D0, 0xCDEF,
273 0xEB0, 0x54547710,
274 0xCDCDCDCD, 0xCDCD,
275 0xEB0, 0x77547777,
276 0xFF0F0740, 0xDEAD,
277 0xEB4, 0x00000077,
278 0xEB8, 0x00508242,
279};
280
281u32 RTL8821AE_PHY_REG_ARRAY[] = {
282 0x800, 0x0020D090,
283 0x804, 0x080112E0,
284 0x808, 0x0E028211,
285 0x80C, 0x92131111,
286 0x810, 0x20101261,
287 0x814, 0x020C3D10,
288 0x818, 0x03A00385,
289 0x820, 0x00000000,
290 0x824, 0x00030FE0,
291 0x828, 0x00000000,
292 0x82C, 0x002081DD,
293 0x830, 0x2AAA8E24,
294 0x834, 0x0037A706,
295 0x838, 0x06489B44,
296 0x83C, 0x0000095B,
297 0x840, 0xC0000001,
298 0x844, 0x40003CDE,
299 0x848, 0x62103F8B,
300 0x84C, 0x6CFDFFB8,
301 0x850, 0x28874706,
302 0x854, 0x0001520C,
303 0x858, 0x8060E000,
304 0x85C, 0x74210168,
305 0x860, 0x6929C321,
306 0x864, 0x79727432,
307 0x868, 0x8CA7A314,
308 0x86C, 0x888C2878,
309 0x870, 0x08888888,
310 0x874, 0x31612C2E,
311 0x878, 0x00000152,
312 0x87C, 0x000FD000,
313 0x8A0, 0x00000013,
314 0x8A4, 0x7F7F7F7F,
315 0x8A8, 0xA2000338,
316 0x8AC, 0x0FF0FA0A,
317 0x8B4, 0x000FC080,
318 0x8B8, 0x6C10D7FF,
319 0x8BC, 0x0CA52090,
320 0x8C0, 0x1BF00020,
321 0x8C4, 0x00000000,
322 0x8C8, 0x00013169,
323 0x8CC, 0x08248492,
324 0x8D4, 0x940008A0,
325 0x8D8, 0x290B5612,
326 0x8F8, 0x400002C0,
327 0x8FC, 0x00000000,
328 0x900, 0x00000700,
329 0x90C, 0x00000000,
330 0x910, 0x0000FC00,
331 0x914, 0x00000404,
332 0x918, 0x1C1028C0,
333 0x91C, 0x64B11A1C,
334 0x920, 0xE0767233,
335 0x924, 0x055AA500,
336 0x928, 0x00000004,
337 0x92C, 0xFFFE0000,
338 0x930, 0xFFFFFFFE,
339 0x934, 0x001FFFFF,
340 0x960, 0x00000000,
341 0x964, 0x00000000,
342 0x968, 0x00000000,
343 0x96C, 0x00000000,
344 0x970, 0x801FFFFF,
345 0x974, 0x000003FF,
346 0x978, 0x00000000,
347 0x97C, 0x00000000,
348 0x980, 0x00000000,
349 0x984, 0x00000000,
350 0x988, 0x00000000,
351 0x990, 0x27100000,
352 0x994, 0xFFFF0100,
353 0x998, 0xFFFFFF5C,
354 0x99C, 0xFFFFFFFF,
355 0x9A0, 0x000000FF,
356 0x9A4, 0x00480080,
357 0x9A8, 0x00000000,
358 0x9AC, 0x00000000,
359 0x9B0, 0x81081008,
360 0x9B4, 0x01081008,
361 0x9B8, 0x01081008,
362 0x9BC, 0x01081008,
363 0x9D0, 0x00000000,
364 0x9D4, 0x00000000,
365 0x9D8, 0x00000000,
366 0x9DC, 0x00000000,
367 0x9E0, 0x00005D00,
368 0x9E4, 0x00000002,
369 0x9E8, 0x00000001,
370 0xA00, 0x00D047C8,
371 0xA04, 0x01FF000C,
372 0xA08, 0x8C8A8300,
373 0xA0C, 0x2E68000F,
374 0xA10, 0x9500BB78,
375 0xA14, 0x11144028,
376 0xA18, 0x00881117,
377 0xA1C, 0x89140F00,
378 0xA20, 0x1A1B0000,
379 0xA24, 0x090E1317,
380 0xA28, 0x00000204,
381 0xA2C, 0x00900000,
382 0xA70, 0x101FFF00,
383 0xA74, 0x00000008,
384 0xA78, 0x00000900,
385 0xA7C, 0x225B0606,
386 0xA80, 0x21805490,
387 0xA84, 0x001F0000,
388 0xB00, 0x03100040,
389 0xB04, 0x0000B000,
390 0xB08, 0xAE0201EB,
391 0xB0C, 0x01003207,
392 0xB10, 0x00009807,
393 0xB14, 0x01000000,
394 0xB18, 0x00000002,
395 0xB1C, 0x00000002,
396 0xB20, 0x0000001F,
397 0xB24, 0x03020100,
398 0xB28, 0x07060504,
399 0xB2C, 0x0B0A0908,
400 0xB30, 0x0F0E0D0C,
401 0xB34, 0x13121110,
402 0xB38, 0x17161514,
403 0xB3C, 0x0000003A,
404 0xB40, 0x00000000,
405 0xB44, 0x00000000,
406 0xB48, 0x13000032,
407 0xB4C, 0x48080000,
408 0xB50, 0x00000000,
409 0xB54, 0x00000000,
410 0xB58, 0x00000000,
411 0xB5C, 0x00000000,
412 0xC00, 0x00000007,
413 0xC04, 0x00042020,
414 0xC08, 0x80410231,
415 0xC0C, 0x00000000,
416 0xC10, 0x00000100,
417 0xC14, 0x01000000,
418 0xC1C, 0x40000003,
419 0xC20, 0x2C2C2C2C,
420 0xC24, 0x30303030,
421 0xC28, 0x30303030,
422 0xC2C, 0x2C2C2C2C,
423 0xC30, 0x2C2C2C2C,
424 0xC34, 0x2C2C2C2C,
425 0xC38, 0x2C2C2C2C,
426 0xC3C, 0x2A2A2A2A,
427 0xC40, 0x2A2A2A2A,
428 0xC44, 0x2A2A2A2A,
429 0xC48, 0x2A2A2A2A,
430 0xC4C, 0x2A2A2A2A,
431 0xC50, 0x00000020,
432 0xC54, 0x001C1208,
433 0xC58, 0x30000C1C,
434 0xC5C, 0x00000058,
435 0xC60, 0x34344443,
436 0xC64, 0x07003333,
437 0xC68, 0x19791979,
438 0xC6C, 0x19791979,
439 0xC70, 0x19791979,
440 0xC74, 0x19791979,
441 0xC78, 0x19791979,
442 0xC7C, 0x19791979,
443 0xC80, 0x19791979,
444 0xC84, 0x19791979,
445 0xC94, 0x0100005C,
446 0xC98, 0x00000000,
447 0xC9C, 0x00000000,
448 0xCA0, 0x00000029,
449 0xCA4, 0x08040201,
450 0xCA8, 0x80402010,
451 0xCB0, 0x77775747,
452 0xCB4, 0x10000077,
453 0xCB8, 0x00508240,
454};
455
456u32 RTL8812AE_PHY_REG_ARRAY_PG[] = {
457 0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840,
458 0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
459 0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638,
460 0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444,
461 0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236,
462 0, 0, 1, 0x00000c34, 0xffffffff, 0x38404242,
463 0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034,
464 0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444,
465 0, 0, 0, 0x00000c40, 0xffffffff, 0x28303236,
466 0, 0, 0, 0x00000c44, 0xffffffff, 0x42422426,
467 0, 0, 1, 0x00000c48, 0xffffffff, 0x30343840,
468 0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
469 0, 1, 0, 0x00000e20, 0xffffffff, 0x34363840,
470 0, 1, 0, 0x00000e24, 0xffffffff, 0x42424444,
471 0, 1, 0, 0x00000e28, 0xffffffff, 0x30323638,
472 0, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444,
473 0, 1, 0, 0x00000e30, 0xffffffff, 0x28303236,
474 0, 1, 1, 0x00000e34, 0xffffffff, 0x38404242,
475 0, 1, 1, 0x00000e38, 0xffffffff, 0x26283034,
476 0, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444,
477 0, 1, 0, 0x00000e40, 0xffffffff, 0x28303236,
478 0, 1, 0, 0x00000e44, 0xffffffff, 0x42422426,
479 0, 1, 1, 0x00000e48, 0xffffffff, 0x30343840,
480 0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628,
481 1, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
482 1, 0, 0, 0x00000c28, 0xffffffff, 0x30323640,
483 1, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444,
484 1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236,
485 1, 0, 1, 0x00000c34, 0xffffffff, 0x38404242,
486 1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034,
487 1, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444,
488 1, 0, 0, 0x00000c40, 0xffffffff, 0x28303236,
489 1, 0, 0, 0x00000c44, 0xffffffff, 0x42422426,
490 1, 0, 1, 0x00000c48, 0xffffffff, 0x30343840,
491 1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
492 1, 1, 0, 0x00000e24, 0xffffffff, 0x42424444,
493 1, 1, 0, 0x00000e28, 0xffffffff, 0x30323640,
494 1, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444,
495 1, 1, 0, 0x00000e30, 0xffffffff, 0x28303236,
496 1, 1, 1, 0x00000e34, 0xffffffff, 0x38404242,
497 1, 1, 1, 0x00000e38, 0xffffffff, 0x26283034,
498 1, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444,
499 1, 1, 0, 0x00000e40, 0xffffffff, 0x28303236,
500 1, 1, 0, 0x00000e44, 0xffffffff, 0x42422426,
501 1, 1, 1, 0x00000e48, 0xffffffff, 0x30343840,
502 1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628
503};
504
505u32 RTL8821AE_PHY_REG_ARRAY_PG[] = {
506 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638,
507 0, 0, 0, 0x00000c24, 0xffffffff, 0x36363838,
508 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234,
509 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363838,
510 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032,
511 0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636,
512 0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
513 0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022,
514 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343636,
515 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032,
516 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343636,
517 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830,
518 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636,
519 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
520 1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022
521};
522
523/* it seems not used
524u8 *RTL8821AE_TXPWR_LMT_ARRAY[] = {
525 "FCC", "2.4G", "20M", "CCK", "1T", "01", "32",
526 "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
527 "MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
528 "FCC", "2.4G", "20M", "CCK", "1T", "02", "32",
529 "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32",
530 "MKK", "2.4G", "20M", "CCK", "1T", "02", "32",
531 "FCC", "2.4G", "20M", "CCK", "1T", "03", "32",
532 "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32",
533 "MKK", "2.4G", "20M", "CCK", "1T", "03", "32",
534 "FCC", "2.4G", "20M", "CCK", "1T", "04", "34",
535 "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32",
536 "MKK", "2.4G", "20M", "CCK", "1T", "04", "32",
537 "FCC", "2.4G", "20M", "CCK", "1T", "05", "34",
538 "ETSI", "2.4G", "20M", "CCK", "1T", "05", "32",
539 "MKK", "2.4G", "20M", "CCK", "1T", "05", "32",
540 "FCC", "2.4G", "20M", "CCK", "1T", "06", "34",
541 "ETSI", "2.4G", "20M", "CCK", "1T", "06", "32",
542 "MKK", "2.4G", "20M", "CCK", "1T", "06", "32",
543 "FCC", "2.4G", "20M", "CCK", "1T", "07", "34",
544 "ETSI", "2.4G", "20M", "CCK", "1T", "07", "32",
545 "MKK", "2.4G", "20M", "CCK", "1T", "07", "32",
546 "FCC", "2.4G", "20M", "CCK", "1T", "08", "34",
547 "ETSI", "2.4G", "20M", "CCK", "1T", "08", "32",
548 "MKK", "2.4G", "20M", "CCK", "1T", "08", "32",
549 "FCC", "2.4G", "20M", "CCK", "1T", "09", "34",
550 "ETSI", "2.4G", "20M", "CCK", "1T", "09", "32",
551 "MKK", "2.4G", "20M", "CCK", "1T", "09", "32",
552 "FCC", "2.4G", "20M", "CCK", "1T", "10", "32",
553 "ETSI", "2.4G", "20M", "CCK", "1T", "10", "32",
554 "MKK", "2.4G", "20M", "CCK", "1T", "10", "32",
555 "FCC", "2.4G", "20M", "CCK", "1T", "11", "32",
556 "ETSI", "2.4G", "20M", "CCK", "1T", "11", "32",
557 "MKK", "2.4G", "20M", "CCK", "1T", "11", "32",
558 "FCC", "2.4G", "20M", "CCK", "1T", "12", "63",
559 "ETSI", "2.4G", "20M", "CCK", "1T", "12", "32",
560 "MKK", "2.4G", "20M", "CCK", "1T", "12", "32",
561 "FCC", "2.4G", "20M", "CCK", "1T", "13", "63",
562 "ETSI", "2.4G", "20M", "CCK", "1T", "13", "32",
563 "MKK", "2.4G", "20M", "CCK", "1T", "13", "32",
564 "FCC", "2.4G", "20M", "CCK", "1T", "14", "63",
565 "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63",
566 "MKK", "2.4G", "20M", "CCK", "1T", "14", "32",
567 "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30",
568 "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "32",
569 "MKK", "2.4G", "20M", "OFDM", "1T", "01", "32",
570 "FCC", "2.4G", "20M", "OFDM", "1T", "02", "30",
571 "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "32",
572 "MKK", "2.4G", "20M", "OFDM", "1T", "02", "32",
573 "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30",
574 "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "32",
575 "MKK", "2.4G", "20M", "OFDM", "1T", "03", "32",
576 "FCC", "2.4G", "20M", "OFDM", "1T", "04", "32",
577 "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "32",
578 "MKK", "2.4G", "20M", "OFDM", "1T", "04", "32",
579 "FCC", "2.4G", "20M", "OFDM", "1T", "05", "32",
580 "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "32",
581 "MKK", "2.4G", "20M", "OFDM", "1T", "05", "32",
582 "FCC", "2.4G", "20M", "OFDM", "1T", "06", "32",
583 "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "32",
584 "MKK", "2.4G", "20M", "OFDM", "1T", "06", "32",
585 "FCC", "2.4G", "20M", "OFDM", "1T", "07", "32",
586 "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "32",
587 "MKK", "2.4G", "20M", "OFDM", "1T", "07", "32",
588 "FCC", "2.4G", "20M", "OFDM", "1T", "08", "32",
589 "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "32",
590 "MKK", "2.4G", "20M", "OFDM", "1T", "08", "32",
591 "FCC", "2.4G", "20M", "OFDM", "1T", "09", "32",
592 "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "32",
593 "MKK", "2.4G", "20M", "OFDM", "1T", "09", "32",
594 "FCC", "2.4G", "20M", "OFDM", "1T", "10", "30",
595 "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "32",
596 "MKK", "2.4G", "20M", "OFDM", "1T", "10", "32",
597 "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30",
598 "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "32",
599 "MKK", "2.4G", "20M", "OFDM", "1T", "11", "32",
600 "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63",
601 "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "32",
602 "MKK", "2.4G", "20M", "OFDM", "1T", "12", "32",
603 "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63",
604 "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "32",
605 "MKK", "2.4G", "20M", "OFDM", "1T", "13", "32",
606 "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63",
607 "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63",
608 "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63",
609 "FCC", "2.4G", "20M", "HT", "1T", "01", "26",
610 "ETSI", "2.4G", "20M", "HT", "1T", "01", "32",
611 "MKK", "2.4G", "20M", "HT", "1T", "01", "32",
612 "FCC", "2.4G", "20M", "HT", "1T", "02", "26",
613 "ETSI", "2.4G", "20M", "HT", "1T", "02", "32",
614 "MKK", "2.4G", "20M", "HT", "1T", "02", "32",
615 "FCC", "2.4G", "20M", "HT", "1T", "03", "26",
616 "ETSI", "2.4G", "20M", "HT", "1T", "03", "32",
617 "MKK", "2.4G", "20M", "HT", "1T", "03", "32",
618 "FCC", "2.4G", "20M", "HT", "1T", "04", "32",
619 "ETSI", "2.4G", "20M", "HT", "1T", "04", "32",
620 "MKK", "2.4G", "20M", "HT", "1T", "04", "32",
621 "FCC", "2.4G", "20M", "HT", "1T", "05", "32",
622 "ETSI", "2.4G", "20M", "HT", "1T", "05", "32",
623 "MKK", "2.4G", "20M", "HT", "1T", "05", "32",
624 "FCC", "2.4G", "20M", "HT", "1T", "06", "32",
625 "ETSI", "2.4G", "20M", "HT", "1T", "06", "32",
626 "MKK", "2.4G", "20M", "HT", "1T", "06", "32",
627 "FCC", "2.4G", "20M", "HT", "1T", "07", "32",
628 "ETSI", "2.4G", "20M", "HT", "1T", "07", "32",
629 "MKK", "2.4G", "20M", "HT", "1T", "07", "32",
630 "FCC", "2.4G", "20M", "HT", "1T", "08", "32",
631 "ETSI", "2.4G", "20M", "HT", "1T", "08", "32",
632 "MKK", "2.4G", "20M", "HT", "1T", "08", "32",
633 "FCC", "2.4G", "20M", "HT", "1T", "09", "32",
634 "ETSI", "2.4G", "20M", "HT", "1T", "09", "32",
635 "MKK", "2.4G", "20M", "HT", "1T", "09", "32",
636 "FCC", "2.4G", "20M", "HT", "1T", "10", "26",
637 "ETSI", "2.4G", "20M", "HT", "1T", "10", "32",
638 "MKK", "2.4G", "20M", "HT", "1T", "10", "32",
639 "FCC", "2.4G", "20M", "HT", "1T", "11", "26",
640 "ETSI", "2.4G", "20M", "HT", "1T", "11", "32",
641 "MKK", "2.4G", "20M", "HT", "1T", "11", "32",
642 "FCC", "2.4G", "20M", "HT", "1T", "12", "63",
643 "ETSI", "2.4G", "20M", "HT", "1T", "12", "32",
644 "MKK", "2.4G", "20M", "HT", "1T", "12", "32",
645 "FCC", "2.4G", "20M", "HT", "1T", "13", "63",
646 "ETSI", "2.4G", "20M", "HT", "1T", "13", "32",
647 "MKK", "2.4G", "20M", "HT", "1T", "13", "32",
648 "FCC", "2.4G", "20M", "HT", "1T", "14", "63",
649 "ETSI", "2.4G", "20M", "HT", "1T", "14", "63",
650 "MKK", "2.4G", "20M", "HT", "1T", "14", "63",
651 "FCC", "2.4G", "20M", "HT", "2T", "01", "30",
652 "ETSI", "2.4G", "20M", "HT", "2T", "01", "32",
653 "MKK", "2.4G", "20M", "HT", "2T", "01", "32",
654 "FCC", "2.4G", "20M", "HT", "2T", "02", "32",
655 "ETSI", "2.4G", "20M", "HT", "2T", "02", "32",
656 "MKK", "2.4G", "20M", "HT", "2T", "02", "32",
657 "FCC", "2.4G", "20M", "HT", "2T", "03", "32",
658 "ETSI", "2.4G", "20M", "HT", "2T", "03", "32",
659 "MKK", "2.4G", "20M", "HT", "2T", "03", "32",
660 "FCC", "2.4G", "20M", "HT", "2T", "04", "32",
661 "ETSI", "2.4G", "20M", "HT", "2T", "04", "32",
662 "MKK", "2.4G", "20M", "HT", "2T", "04", "32",
663 "FCC", "2.4G", "20M", "HT", "2T", "05", "32",
664 "ETSI", "2.4G", "20M", "HT", "2T", "05", "32",
665 "MKK", "2.4G", "20M", "HT", "2T", "05", "32",
666 "FCC", "2.4G", "20M", "HT", "2T", "06", "32",
667 "ETSI", "2.4G", "20M", "HT", "2T", "06", "32",
668 "MKK", "2.4G", "20M", "HT", "2T", "06", "32",
669 "FCC", "2.4G", "20M", "HT", "2T", "07", "32",
670 "ETSI", "2.4G", "20M", "HT", "2T", "07", "32",
671 "MKK", "2.4G", "20M", "HT", "2T", "07", "32",
672 "FCC", "2.4G", "20M", "HT", "2T", "08", "32",
673 "ETSI", "2.4G", "20M", "HT", "2T", "08", "32",
674 "MKK", "2.4G", "20M", "HT", "2T", "08", "32",
675 "FCC", "2.4G", "20M", "HT", "2T", "09", "32",
676 "ETSI", "2.4G", "20M", "HT", "2T", "09", "32",
677 "MKK", "2.4G", "20M", "HT", "2T", "09", "32",
678 "FCC", "2.4G", "20M", "HT", "2T", "10", "32",
679 "ETSI", "2.4G", "20M", "HT", "2T", "10", "32",
680 "MKK", "2.4G", "20M", "HT", "2T", "10", "32",
681 "FCC", "2.4G", "20M", "HT", "2T", "11", "30",
682 "ETSI", "2.4G", "20M", "HT", "2T", "11", "32",
683 "MKK", "2.4G", "20M", "HT", "2T", "11", "32",
684 "FCC", "2.4G", "20M", "HT", "2T", "12", "63",
685 "ETSI", "2.4G", "20M", "HT", "2T", "12", "32",
686 "MKK", "2.4G", "20M", "HT", "2T", "12", "32",
687 "FCC", "2.4G", "20M", "HT", "2T", "13", "63",
688 "ETSI", "2.4G", "20M", "HT", "2T", "13", "32",
689 "MKK", "2.4G", "20M", "HT", "2T", "13", "32",
690 "FCC", "2.4G", "20M", "HT", "2T", "14", "63",
691 "ETSI", "2.4G", "20M", "HT", "2T", "14", "63",
692 "MKK", "2.4G", "20M", "HT", "2T", "14", "63",
693 "FCC", "2.4G", "40M", "HT", "1T", "01", "63",
694 "ETSI", "2.4G", "40M", "HT", "1T", "01", "63",
695 "MKK", "2.4G", "40M", "HT", "1T", "01", "63",
696 "FCC", "2.4G", "40M", "HT", "1T", "02", "63",
697 "ETSI", "2.4G", "40M", "HT", "1T", "02", "63",
698 "MKK", "2.4G", "40M", "HT", "1T", "02", "63",
699 "FCC", "2.4G", "40M", "HT", "1T", "03", "26",
700 "ETSI", "2.4G", "40M", "HT", "1T", "03", "32",
701 "MKK", "2.4G", "40M", "HT", "1T", "03", "32",
702 "FCC", "2.4G", "40M", "HT", "1T", "04", "26",
703 "ETSI", "2.4G", "40M", "HT", "1T", "04", "32",
704 "MKK", "2.4G", "40M", "HT", "1T", "04", "32",
705 "FCC", "2.4G", "40M", "HT", "1T", "05", "32",
706 "ETSI", "2.4G", "40M", "HT", "1T", "05", "32",
707 "MKK", "2.4G", "40M", "HT", "1T", "05", "32",
708 "FCC", "2.4G", "40M", "HT", "1T", "06", "32",
709 "ETSI", "2.4G", "40M", "HT", "1T", "06", "32",
710 "MKK", "2.4G", "40M", "HT", "1T", "06", "32",
711 "FCC", "2.4G", "40M", "HT", "1T", "07", "32",
712 "ETSI", "2.4G", "40M", "HT", "1T", "07", "32",
713 "MKK", "2.4G", "40M", "HT", "1T", "07", "32",
714 "FCC", "2.4G", "40M", "HT", "1T", "08", "26",
715 "ETSI", "2.4G", "40M", "HT", "1T", "08", "32",
716 "MKK", "2.4G", "40M", "HT", "1T", "08", "32",
717 "FCC", "2.4G", "40M", "HT", "1T", "09", "26",
718 "ETSI", "2.4G", "40M", "HT", "1T", "09", "32",
719 "MKK", "2.4G", "40M", "HT", "1T", "09", "32",
720 "FCC", "2.4G", "40M", "HT", "1T", "10", "26",
721 "ETSI", "2.4G", "40M", "HT", "1T", "10", "32",
722 "MKK", "2.4G", "40M", "HT", "1T", "10", "32",
723 "FCC", "2.4G", "40M", "HT", "1T", "11", "26",
724 "ETSI", "2.4G", "40M", "HT", "1T", "11", "32",
725 "MKK", "2.4G", "40M", "HT", "1T", "11", "32",
726 "FCC", "2.4G", "40M", "HT", "1T", "12", "63",
727 "ETSI", "2.4G", "40M", "HT", "1T", "12", "32",
728 "MKK", "2.4G", "40M", "HT", "1T", "12", "32",
729 "FCC", "2.4G", "40M", "HT", "1T", "13", "63",
730 "ETSI", "2.4G", "40M", "HT", "1T", "13", "32",
731 "MKK", "2.4G", "40M", "HT", "1T", "13", "32",
732 "FCC", "2.4G", "40M", "HT", "1T", "14", "63",
733 "ETSI", "2.4G", "40M", "HT", "1T", "14", "63",
734 "MKK", "2.4G", "40M", "HT", "1T", "14", "63",
735 "FCC", "2.4G", "40M", "HT", "2T", "01", "63",
736 "ETSI", "2.4G", "40M", "HT", "2T", "01", "63",
737 "MKK", "2.4G", "40M", "HT", "2T", "01", "63",
738 "FCC", "2.4G", "40M", "HT", "2T", "02", "63",
739 "ETSI", "2.4G", "40M", "HT", "2T", "02", "63",
740 "MKK", "2.4G", "40M", "HT", "2T", "02", "63",
741 "FCC", "2.4G", "40M", "HT", "2T", "03", "30",
742 "ETSI", "2.4G", "40M", "HT", "2T", "03", "30",
743 "MKK", "2.4G", "40M", "HT", "2T", "03", "30",
744 "FCC", "2.4G", "40M", "HT", "2T", "04", "32",
745 "ETSI", "2.4G", "40M", "HT", "2T", "04", "30",
746 "MKK", "2.4G", "40M", "HT", "2T", "04", "30",
747 "FCC", "2.4G", "40M", "HT", "2T", "05", "32",
748 "ETSI", "2.4G", "40M", "HT", "2T", "05", "30",
749 "MKK", "2.4G", "40M", "HT", "2T", "05", "30",
750 "FCC", "2.4G", "40M", "HT", "2T", "06", "32",
751 "ETSI", "2.4G", "40M", "HT", "2T", "06", "30",
752 "MKK", "2.4G", "40M", "HT", "2T", "06", "30",
753 "FCC", "2.4G", "40M", "HT", "2T", "07", "32",
754 "ETSI", "2.4G", "40M", "HT", "2T", "07", "30",
755 "MKK", "2.4G", "40M", "HT", "2T", "07", "30",
756 "FCC", "2.4G", "40M", "HT", "2T", "08", "32",
757 "ETSI", "2.4G", "40M", "HT", "2T", "08", "30",
758 "MKK", "2.4G", "40M", "HT", "2T", "08", "30",
759 "FCC", "2.4G", "40M", "HT", "2T", "09", "32",
760 "ETSI", "2.4G", "40M", "HT", "2T", "09", "30",
761 "MKK", "2.4G", "40M", "HT", "2T", "09", "30",
762 "FCC", "2.4G", "40M", "HT", "2T", "10", "32",
763 "ETSI", "2.4G", "40M", "HT", "2T", "10", "30",
764 "MKK", "2.4G", "40M", "HT", "2T", "10", "30",
765 "FCC", "2.4G", "40M", "HT", "2T", "11", "30",
766 "ETSI", "2.4G", "40M", "HT", "2T", "11", "30",
767 "MKK", "2.4G", "40M", "HT", "2T", "11", "30",
768 "FCC", "2.4G", "40M", "HT", "2T", "12", "63",
769 "ETSI", "2.4G", "40M", "HT", "2T", "12", "32",
770 "MKK", "2.4G", "40M", "HT", "2T", "12", "32",
771 "FCC", "2.4G", "40M", "HT", "2T", "13", "63",
772 "ETSI", "2.4G", "40M", "HT", "2T", "13", "32",
773 "MKK", "2.4G", "40M", "HT", "2T", "13", "32",
774 "FCC", "2.4G", "40M", "HT", "2T", "14", "63",
775 "ETSI", "2.4G", "40M", "HT", "2T", "14", "63",
776 "MKK", "2.4G", "40M", "HT", "2T", "14", "63",
777 "FCC", "5G", "20M", "OFDM", "1T", "36", "30",
778 "ETSI", "5G", "20M", "OFDM", "1T", "36", "30",
779 "MKK", "5G", "20M", "OFDM", "1T", "36", "30",
780 "FCC", "5G", "20M", "OFDM", "1T", "40", "30",
781 "ETSI", "5G", "20M", "OFDM", "1T", "40", "30",
782 "MKK", "5G", "20M", "OFDM", "1T", "40", "30",
783 "FCC", "5G", "20M", "OFDM", "1T", "44", "30",
784 "ETSI", "5G", "20M", "OFDM", "1T", "44", "30",
785 "MKK", "5G", "20M", "OFDM", "1T", "44", "30",
786 "FCC", "5G", "20M", "OFDM", "1T", "48", "30",
787 "ETSI", "5G", "20M", "OFDM", "1T", "48", "30",
788 "MKK", "5G", "20M", "OFDM", "1T", "48", "30",
789 "FCC", "5G", "20M", "OFDM", "1T", "52", "30",
790 "ETSI", "5G", "20M", "OFDM", "1T", "52", "30",
791 "MKK", "5G", "20M", "OFDM", "1T", "52", "30",
792 "FCC", "5G", "20M", "OFDM", "1T", "56", "30",
793 "ETSI", "5G", "20M", "OFDM", "1T", "56", "30",
794 "MKK", "5G", "20M", "OFDM", "1T", "56", "30",
795 "FCC", "5G", "20M", "OFDM", "1T", "60", "30",
796 "ETSI", "5G", "20M", "OFDM", "1T", "60", "30",
797 "MKK", "5G", "20M", "OFDM", "1T", "60", "30",
798 "FCC", "5G", "20M", "OFDM", "1T", "64", "30",
799 "ETSI", "5G", "20M", "OFDM", "1T", "64", "30",
800 "MKK", "5G", "20M", "OFDM", "1T", "64", "30",
801 "FCC", "5G", "20M", "OFDM", "1T", "100", "30",
802 "ETSI", "5G", "20M", "OFDM", "1T", "100", "30",
803 "MKK", "5G", "20M", "OFDM", "1T", "100", "30",
804 "FCC", "5G", "20M", "OFDM", "1T", "114", "30",
805 "ETSI", "5G", "20M", "OFDM", "1T", "114", "30",
806 "MKK", "5G", "20M", "OFDM", "1T", "114", "30",
807 "FCC", "5G", "20M", "OFDM", "1T", "108", "30",
808 "ETSI", "5G", "20M", "OFDM", "1T", "108", "30",
809 "MKK", "5G", "20M", "OFDM", "1T", "108", "30",
810 "FCC", "5G", "20M", "OFDM", "1T", "112", "30",
811 "ETSI", "5G", "20M", "OFDM", "1T", "112", "30",
812 "MKK", "5G", "20M", "OFDM", "1T", "112", "30",
813 "FCC", "5G", "20M", "OFDM", "1T", "116", "30",
814 "ETSI", "5G", "20M", "OFDM", "1T", "116", "30",
815 "MKK", "5G", "20M", "OFDM", "1T", "116", "30",
816 "FCC", "5G", "20M", "OFDM", "1T", "120", "30",
817 "ETSI", "5G", "20M", "OFDM", "1T", "120", "30",
818 "MKK", "5G", "20M", "OFDM", "1T", "120", "30",
819 "FCC", "5G", "20M", "OFDM", "1T", "124", "30",
820 "ETSI", "5G", "20M", "OFDM", "1T", "124", "30",
821 "MKK", "5G", "20M", "OFDM", "1T", "124", "30",
822 "FCC", "5G", "20M", "OFDM", "1T", "128", "30",
823 "ETSI", "5G", "20M", "OFDM", "1T", "128", "30",
824 "MKK", "5G", "20M", "OFDM", "1T", "128", "30",
825 "FCC", "5G", "20M", "OFDM", "1T", "132", "30",
826 "ETSI", "5G", "20M", "OFDM", "1T", "132", "30",
827 "MKK", "5G", "20M", "OFDM", "1T", "132", "30",
828 "FCC", "5G", "20M", "OFDM", "1T", "136", "30",
829 "ETSI", "5G", "20M", "OFDM", "1T", "136", "30",
830 "MKK", "5G", "20M", "OFDM", "1T", "136", "30",
831 "FCC", "5G", "20M", "OFDM", "1T", "140", "30",
832 "ETSI", "5G", "20M", "OFDM", "1T", "140", "30",
833 "MKK", "5G", "20M", "OFDM", "1T", "140", "30",
834 "FCC", "5G", "20M", "OFDM", "1T", "149", "30",
835 "ETSI", "5G", "20M", "OFDM", "1T", "149", "30",
836 "MKK", "5G", "20M", "OFDM", "1T", "149", "63",
837 "FCC", "5G", "20M", "OFDM", "1T", "153", "30",
838 "ETSI", "5G", "20M", "OFDM", "1T", "153", "30",
839 "MKK", "5G", "20M", "OFDM", "1T", "153", "63",
840 "FCC", "5G", "20M", "OFDM", "1T", "157", "30",
841 "ETSI", "5G", "20M", "OFDM", "1T", "157", "30",
842 "MKK", "5G", "20M", "OFDM", "1T", "157", "63",
843 "FCC", "5G", "20M", "OFDM", "1T", "161", "30",
844 "ETSI", "5G", "20M", "OFDM", "1T", "161", "30",
845 "MKK", "5G", "20M", "OFDM", "1T", "161", "63",
846 "FCC", "5G", "20M", "OFDM", "1T", "165", "30",
847 "ETSI", "5G", "20M", "OFDM", "1T", "165", "30",
848 "MKK", "5G", "20M", "OFDM", "1T", "165", "63",
849 "FCC", "5G", "20M", "HT", "1T", "36", "30",
850 "ETSI", "5G", "20M", "HT", "1T", "36", "30",
851 "MKK", "5G", "20M", "HT", "1T", "36", "30",
852 "FCC", "5G", "20M", "HT", "1T", "40", "30",
853 "ETSI", "5G", "20M", "HT", "1T", "40", "30",
854 "MKK", "5G", "20M", "HT", "1T", "40", "30",
855 "FCC", "5G", "20M", "HT", "1T", "44", "30",
856 "ETSI", "5G", "20M", "HT", "1T", "44", "30",
857 "MKK", "5G", "20M", "HT", "1T", "44", "30",
858 "FCC", "5G", "20M", "HT", "1T", "48", "30",
859 "ETSI", "5G", "20M", "HT", "1T", "48", "30",
860 "MKK", "5G", "20M", "HT", "1T", "48", "30",
861 "FCC", "5G", "20M", "HT", "1T", "52", "30",
862 "ETSI", "5G", "20M", "HT", "1T", "52", "30",
863 "MKK", "5G", "20M", "HT", "1T", "52", "30",
864 "FCC", "5G", "20M", "HT", "1T", "56", "30",
865 "ETSI", "5G", "20M", "HT", "1T", "56", "30",
866 "MKK", "5G", "20M", "HT", "1T", "56", "30",
867 "FCC", "5G", "20M", "HT", "1T", "60", "30",
868 "ETSI", "5G", "20M", "HT", "1T", "60", "30",
869 "MKK", "5G", "20M", "HT", "1T", "60", "30",
870 "FCC", "5G", "20M", "HT", "1T", "64", "30",
871 "ETSI", "5G", "20M", "HT", "1T", "64", "30",
872 "MKK", "5G", "20M", "HT", "1T", "64", "30",
873 "FCC", "5G", "20M", "HT", "1T", "100", "30",
874 "ETSI", "5G", "20M", "HT", "1T", "100", "30",
875 "MKK", "5G", "20M", "HT", "1T", "100", "30",
876 "FCC", "5G", "20M", "HT", "1T", "114", "30",
877 "ETSI", "5G", "20M", "HT", "1T", "114", "30",
878 "MKK", "5G", "20M", "HT", "1T", "114", "30",
879 "FCC", "5G", "20M", "HT", "1T", "108", "30",
880 "ETSI", "5G", "20M", "HT", "1T", "108", "30",
881 "MKK", "5G", "20M", "HT", "1T", "108", "30",
882 "FCC", "5G", "20M", "HT", "1T", "112", "30",
883 "ETSI", "5G", "20M", "HT", "1T", "112", "30",
884 "MKK", "5G", "20M", "HT", "1T", "112", "30",
885 "FCC", "5G", "20M", "HT", "1T", "116", "30",
886 "ETSI", "5G", "20M", "HT", "1T", "116", "30",
887 "MKK", "5G", "20M", "HT", "1T", "116", "30",
888 "FCC", "5G", "20M", "HT", "1T", "120", "30",
889 "ETSI", "5G", "20M", "HT", "1T", "120", "30",
890 "MKK", "5G", "20M", "HT", "1T", "120", "30",
891 "FCC", "5G", "20M", "HT", "1T", "124", "30",
892 "ETSI", "5G", "20M", "HT", "1T", "124", "30",
893 "MKK", "5G", "20M", "HT", "1T", "124", "30",
894 "FCC", "5G", "20M", "HT", "1T", "128", "30",
895 "ETSI", "5G", "20M", "HT", "1T", "128", "30",
896 "MKK", "5G", "20M", "HT", "1T", "128", "30",
897 "FCC", "5G", "20M", "HT", "1T", "132", "30",
898 "ETSI", "5G", "20M", "HT", "1T", "132", "30",
899 "MKK", "5G", "20M", "HT", "1T", "132", "30",
900 "FCC", "5G", "20M", "HT", "1T", "136", "30",
901 "ETSI", "5G", "20M", "HT", "1T", "136", "30",
902 "MKK", "5G", "20M", "HT", "1T", "136", "30",
903 "FCC", "5G", "20M", "HT", "1T", "140", "30",
904 "ETSI", "5G", "20M", "HT", "1T", "140", "30",
905 "MKK", "5G", "20M", "HT", "1T", "140", "30",
906 "FCC", "5G", "20M", "HT", "1T", "149", "30",
907 "ETSI", "5G", "20M", "HT", "1T", "149", "30",
908 "MKK", "5G", "20M", "HT", "1T", "149", "63",
909 "FCC", "5G", "20M", "HT", "1T", "153", "30",
910 "ETSI", "5G", "20M", "HT", "1T", "153", "30",
911 "MKK", "5G", "20M", "HT", "1T", "153", "63",
912 "FCC", "5G", "20M", "HT", "1T", "157", "30",
913 "ETSI", "5G", "20M", "HT", "1T", "157", "30",
914 "MKK", "5G", "20M", "HT", "1T", "157", "63",
915 "FCC", "5G", "20M", "HT", "1T", "161", "30",
916 "ETSI", "5G", "20M", "HT", "1T", "161", "30",
917 "MKK", "5G", "20M", "HT", "1T", "161", "63",
918 "FCC", "5G", "20M", "HT", "1T", "165", "30",
919 "ETSI", "5G", "20M", "HT", "1T", "165", "30",
920 "MKK", "5G", "20M", "HT", "1T", "165", "63",
921 "FCC", "5G", "20M", "HT", "2T", "36", "28",
922 "ETSI", "5G", "20M", "HT", "2T", "36", "30",
923 "MKK", "5G", "20M", "HT", "2T", "36", "30",
924 "FCC", "5G", "20M", "HT", "2T", "40", "28",
925 "ETSI", "5G", "20M", "HT", "2T", "40", "30",
926 "MKK", "5G", "20M", "HT", "2T", "40", "30",
927 "FCC", "5G", "20M", "HT", "2T", "44", "28",
928 "ETSI", "5G", "20M", "HT", "2T", "44", "30",
929 "MKK", "5G", "20M", "HT", "2T", "44", "30",
930 "FCC", "5G", "20M", "HT", "2T", "48", "28",
931 "ETSI", "5G", "20M", "HT", "2T", "48", "30",
932 "MKK", "5G", "20M", "HT", "2T", "48", "30",
933 "FCC", "5G", "20M", "HT", "2T", "52", "34",
934 "ETSI", "5G", "20M", "HT", "2T", "52", "30",
935 "MKK", "5G", "20M", "HT", "2T", "52", "30",
936 "FCC", "5G", "20M", "HT", "2T", "56", "32",
937 "ETSI", "5G", "20M", "HT", "2T", "56", "30",
938 "MKK", "5G", "20M", "HT", "2T", "56", "30",
939 "FCC", "5G", "20M", "HT", "2T", "60", "30",
940 "ETSI", "5G", "20M", "HT", "2T", "60", "30",
941 "MKK", "5G", "20M", "HT", "2T", "60", "30",
942 "FCC", "5G", "20M", "HT", "2T", "64", "26",
943 "ETSI", "5G", "20M", "HT", "2T", "64", "30",
944 "MKK", "5G", "20M", "HT", "2T", "64", "30",
945 "FCC", "5G", "20M", "HT", "2T", "100", "28",
946 "ETSI", "5G", "20M", "HT", "2T", "100", "30",
947 "MKK", "5G", "20M", "HT", "2T", "100", "30",
948 "FCC", "5G", "20M", "HT", "2T", "114", "28",
949 "ETSI", "5G", "20M", "HT", "2T", "114", "30",
950 "MKK", "5G", "20M", "HT", "2T", "114", "30",
951 "FCC", "5G", "20M", "HT", "2T", "108", "30",
952 "ETSI", "5G", "20M", "HT", "2T", "108", "30",
953 "MKK", "5G", "20M", "HT", "2T", "108", "30",
954 "FCC", "5G", "20M", "HT", "2T", "112", "32",
955 "ETSI", "5G", "20M", "HT", "2T", "112", "30",
956 "MKK", "5G", "20M", "HT", "2T", "112", "30",
957 "FCC", "5G", "20M", "HT", "2T", "116", "32",
958 "ETSI", "5G", "20M", "HT", "2T", "116", "30",
959 "MKK", "5G", "20M", "HT", "2T", "116", "30",
960 "FCC", "5G", "20M", "HT", "2T", "120", "34",
961 "ETSI", "5G", "20M", "HT", "2T", "120", "30",
962 "MKK", "5G", "20M", "HT", "2T", "120", "30",
963 "FCC", "5G", "20M", "HT", "2T", "124", "32",
964 "ETSI", "5G", "20M", "HT", "2T", "124", "30",
965 "MKK", "5G", "20M", "HT", "2T", "124", "30",
966 "FCC", "5G", "20M", "HT", "2T", "128", "30",
967 "ETSI", "5G", "20M", "HT", "2T", "128", "30",
968 "MKK", "5G", "20M", "HT", "2T", "128", "30",
969 "FCC", "5G", "20M", "HT", "2T", "132", "28",
970 "ETSI", "5G", "20M", "HT", "2T", "132", "30",
971 "MKK", "5G", "20M", "HT", "2T", "132", "30",
972 "FCC", "5G", "20M", "HT", "2T", "136", "28",
973 "ETSI", "5G", "20M", "HT", "2T", "136", "30",
974 "MKK", "5G", "20M", "HT", "2T", "136", "30",
975 "FCC", "5G", "20M", "HT", "2T", "140", "26",
976 "ETSI", "5G", "20M", "HT", "2T", "140", "30",
977 "MKK", "5G", "20M", "HT", "2T", "140", "30",
978 "FCC", "5G", "20M", "HT", "2T", "149", "34",
979 "ETSI", "5G", "20M", "HT", "2T", "149", "30",
980 "MKK", "5G", "20M", "HT", "2T", "149", "63",
981 "FCC", "5G", "20M", "HT", "2T", "153", "34",
982 "ETSI", "5G", "20M", "HT", "2T", "153", "30",
983 "MKK", "5G", "20M", "HT", "2T", "153", "63",
984 "FCC", "5G", "20M", "HT", "2T", "157", "34",
985 "ETSI", "5G", "20M", "HT", "2T", "157", "30",
986 "MKK", "5G", "20M", "HT", "2T", "157", "63",
987 "FCC", "5G", "20M", "HT", "2T", "161", "34",
988 "ETSI", "5G", "20M", "HT", "2T", "161", "30",
989 "MKK", "5G", "20M", "HT", "2T", "161", "63",
990 "FCC", "5G", "20M", "HT", "2T", "165", "34",
991 "ETSI", "5G", "20M", "HT", "2T", "165", "30",
992 "MKK", "5G", "20M", "HT", "2T", "165", "63",
993 "FCC", "5G", "40M", "HT", "1T", "38", "26",
994 "ETSI", "5G", "40M", "HT", "1T", "38", "30",
995 "MKK", "5G", "40M", "HT", "1T", "38", "30",
996 "FCC", "5G", "40M", "HT", "1T", "46", "30",
997 "ETSI", "5G", "40M", "HT", "1T", "46", "30",
998 "MKK", "5G", "40M", "HT", "1T", "46", "30",
999 "FCC", "5G", "40M", "HT", "1T", "54", "30",
1000 "ETSI", "5G", "40M", "HT", "1T", "54", "30",
1001 "MKK", "5G", "40M", "HT", "1T", "54", "30",
1002 "FCC", "5G", "40M", "HT", "1T", "62", "26",
1003 "ETSI", "5G", "40M", "HT", "1T", "62", "30",
1004 "MKK", "5G", "40M", "HT", "1T", "62", "30",
1005 "FCC", "5G", "40M", "HT", "1T", "102", "24",
1006 "ETSI", "5G", "40M", "HT", "1T", "102", "30",
1007 "MKK", "5G", "40M", "HT", "1T", "102", "30",
1008 "FCC", "5G", "40M", "HT", "1T", "110", "30",
1009 "ETSI", "5G", "40M", "HT", "1T", "110", "30",
1010 "MKK", "5G", "40M", "HT", "1T", "110", "30",
1011 "FCC", "5G", "40M", "HT", "1T", "118", "30",
1012 "ETSI", "5G", "40M", "HT", "1T", "118", "30",
1013 "MKK", "5G", "40M", "HT", "1T", "118", "30",
1014 "FCC", "5G", "40M", "HT", "1T", "126", "30",
1015 "ETSI", "5G", "40M", "HT", "1T", "126", "30",
1016 "MKK", "5G", "40M", "HT", "1T", "126", "30",
1017 "FCC", "5G", "40M", "HT", "1T", "134", "30",
1018 "ETSI", "5G", "40M", "HT", "1T", "134", "30",
1019 "MKK", "5G", "40M", "HT", "1T", "134", "30",
1020 "FCC", "5G", "40M", "HT", "1T", "151", "30",
1021 "ETSI", "5G", "40M", "HT", "1T", "151", "30",
1022 "MKK", "5G", "40M", "HT", "1T", "151", "63",
1023 "FCC", "5G", "40M", "HT", "1T", "159", "30",
1024 "ETSI", "5G", "40M", "HT", "1T", "159", "30",
1025 "MKK", "5G", "40M", "HT", "1T", "159", "63",
1026 "FCC", "5G", "40M", "HT", "2T", "38", "28",
1027 "ETSI", "5G", "40M", "HT", "2T", "38", "30",
1028 "MKK", "5G", "40M", "HT", "2T", "38", "30",
1029 "FCC", "5G", "40M", "HT", "2T", "46", "28",
1030 "ETSI", "5G", "40M", "HT", "2T", "46", "30",
1031 "MKK", "5G", "40M", "HT", "2T", "46", "30",
1032 "FCC", "5G", "40M", "HT", "2T", "54", "30",
1033 "ETSI", "5G", "40M", "HT", "2T", "54", "30",
1034 "MKK", "5G", "40M", "HT", "2T", "54", "30",
1035 "FCC", "5G", "40M", "HT", "2T", "62", "30",
1036 "ETSI", "5G", "40M", "HT", "2T", "62", "30",
1037 "MKK", "5G", "40M", "HT", "2T", "62", "30",
1038 "FCC", "5G", "40M", "HT", "2T", "102", "26",
1039 "ETSI", "5G", "40M", "HT", "2T", "102", "30",
1040 "MKK", "5G", "40M", "HT", "2T", "102", "30",
1041 "FCC", "5G", "40M", "HT", "2T", "110", "30",
1042 "ETSI", "5G", "40M", "HT", "2T", "110", "30",
1043 "MKK", "5G", "40M", "HT", "2T", "110", "30",
1044 "FCC", "5G", "40M", "HT", "2T", "118", "34",
1045 "ETSI", "5G", "40M", "HT", "2T", "118", "30",
1046 "MKK", "5G", "40M", "HT", "2T", "118", "30",
1047 "FCC", "5G", "40M", "HT", "2T", "126", "32",
1048 "ETSI", "5G", "40M", "HT", "2T", "126", "30",
1049 "MKK", "5G", "40M", "HT", "2T", "126", "30",
1050 "FCC", "5G", "40M", "HT", "2T", "134", "30",
1051 "ETSI", "5G", "40M", "HT", "2T", "134", "30",
1052 "MKK", "5G", "40M", "HT", "2T", "134", "30",
1053 "FCC", "5G", "40M", "HT", "2T", "151", "34",
1054 "ETSI", "5G", "40M", "HT", "2T", "151", "30",
1055 "MKK", "5G", "40M", "HT", "2T", "151", "63",
1056 "FCC", "5G", "40M", "HT", "2T", "159", "34",
1057 "ETSI", "5G", "40M", "HT", "2T", "159", "30",
1058 "MKK", "5G", "40M", "HT", "2T", "159", "63",
1059 "FCC", "5G", "80M", "VHT", "1T", "42", "22",
1060 "ETSI", "5G", "80M", "VHT", "1T", "42", "30",
1061 "MKK", "5G", "80M", "VHT", "1T", "42", "30",
1062 "FCC", "5G", "80M", "VHT", "1T", "58", "20",
1063 "ETSI", "5G", "80M", "VHT", "1T", "58", "30",
1064 "MKK", "5G", "80M", "VHT", "1T", "58", "30",
1065 "FCC", "5G", "80M", "VHT", "1T", "106", "20",
1066 "ETSI", "5G", "80M", "VHT", "1T", "106", "30",
1067 "MKK", "5G", "80M", "VHT", "1T", "106", "30",
1068 "FCC", "5G", "80M", "VHT", "1T", "122", "28",
1069 "ETSI", "5G", "80M", "VHT", "1T", "122", "30",
1070 "MKK", "5G", "80M", "VHT", "1T", "122", "30",
1071 "FCC", "5G", "80M", "VHT", "1T", "155", "30",
1072 "ETSI", "5G", "80M", "VHT", "1T", "155", "30",
1073 "MKK", "5G", "80M", "VHT", "1T", "155", "63",
1074 "FCC", "5G", "80M", "VHT", "2T", "42", "28",
1075 "ETSI", "5G", "80M", "VHT", "2T", "42", "30",
1076 "MKK", "5G", "80M", "VHT", "2T", "42", "30",
1077 "FCC", "5G", "80M", "VHT", "2T", "58", "26",
1078 "ETSI", "5G", "80M", "VHT", "2T", "58", "30",
1079 "MKK", "5G", "80M", "VHT", "2T", "58", "30",
1080 "FCC", "5G", "80M", "VHT", "2T", "106", "28",
1081 "ETSI", "5G", "80M", "VHT", "2T", "106", "30",
1082 "MKK", "5G", "80M", "VHT", "2T", "106", "30",
1083 "FCC", "5G", "80M", "VHT", "2T", "122", "32",
1084 "ETSI", "5G", "80M", "VHT", "2T", "122", "30",
1085 "MKK", "5G", "80M", "VHT", "2T", "122", "30",
1086 "FCC", "5G", "80M", "VHT", "2T", "155", "34",
1087 "ETSI", "5G", "80M", "VHT", "2T", "155", "30",
1088 "MKK", "5G", "80M", "VHT", "2T", "155", "63"
1089};*/
1090
1091u32 RTL8812AE_RADIOA_ARRAY[] = {
1092 0x000, 0x00010000,
1093 0x018, 0x0001712A,
1094 0x056, 0x00051CF2,
1095 0x066, 0x00040000,
1096 0x01E, 0x00080000,
1097 0x089, 0x00000080,
1098 0xFF0F0740, 0xABCD,
1099 0x086, 0x00014B38,
1100 0xFF0F02C0, 0xCDEF,
1101 0x086, 0x00014B38,
1102 0xFF0F01C0, 0xCDEF,
1103 0x086, 0x00014B38,
1104 0xFF0F07D8, 0xCDEF,
1105 0x086, 0x00014B3A,
1106 0xFF0F07D0, 0xCDEF,
1107 0x086, 0x00014B3A,
1108 0xCDCDCDCD, 0xCDCD,
1109 0x086, 0x00014B38,
1110 0xFF0F0740, 0xDEAD,
1111 0x0B1, 0x0001FC1A,
1112 0x0B3, 0x000F0810,
1113 0x0B4, 0x0001A78D,
1114 0x0BA, 0x00086180,
1115 0x018, 0x00000006,
1116 0x0EF, 0x00002000,
1117 0xFF0F07D8, 0xABCD,
1118 0x03B, 0x0003F218,
1119 0x03B, 0x00030A58,
1120 0x03B, 0x0002FA58,
1121 0x03B, 0x00022590,
1122 0x03B, 0x0001FA50,
1123 0x03B, 0x00010248,
1124 0x03B, 0x00008240,
1125 0xFF0F07D0, 0xCDEF,
1126 0x03B, 0x0003F218,
1127 0x03B, 0x00030A58,
1128 0x03B, 0x0002FA58,
1129 0x03B, 0x00022590,
1130 0x03B, 0x0001FA50,
1131 0x03B, 0x00010248,
1132 0x03B, 0x00008240,
1133 0xCDCDCDCD, 0xCDCD,
1134 0x03B, 0x00038A58,
1135 0x03B, 0x00037A58,
1136 0x03B, 0x0002A590,
1137 0x03B, 0x00027A50,
1138 0x03B, 0x00018248,
1139 0x03B, 0x00010240,
1140 0x03B, 0x00008240,
1141 0xFF0F07D8, 0xDEAD,
1142 0x0EF, 0x00000100,
1143 0xFF0F07D8, 0xABCD,
1144 0x034, 0x0000A4EE,
1145 0x034, 0x00009076,
1146 0x034, 0x00008073,
1147 0x034, 0x00007070,
1148 0x034, 0x0000606D,
1149 0x034, 0x0000506A,
1150 0x034, 0x00004049,
1151 0x034, 0x00003046,
1152 0x034, 0x00002028,
1153 0x034, 0x00001025,
1154 0x034, 0x00000022,
1155 0xCDCDCDCD, 0xCDCD,
1156 0x034, 0x0000ADF4,
1157 0x034, 0x00009DF1,
1158 0x034, 0x00008DEE,
1159 0x034, 0x00007DEB,
1160 0x034, 0x00006DE8,
1161 0x034, 0x00005CEC,
1162 0x034, 0x00004CE9,
1163 0x034, 0x000034EA,
1164 0x034, 0x000024E7,
1165 0x034, 0x0000146B,
1166 0x034, 0x0000006D,
1167 0xFF0F07D8, 0xDEAD,
1168 0x0EF, 0x00000000,
1169 0x0EF, 0x000020A2,
1170 0x0DF, 0x00000080,
1171 0x035, 0x00000192,
1172 0x035, 0x00008192,
1173 0x035, 0x00010192,
1174 0x036, 0x00000024,
1175 0x036, 0x00008024,
1176 0x036, 0x00010024,
1177 0x036, 0x00018024,
1178 0x0EF, 0x00000000,
1179 0x051, 0x00000C21,
1180 0x052, 0x000006D9,
1181 0x053, 0x000FC649,
1182 0x054, 0x0000017E,
1183 0x0EF, 0x00000002,
1184 0x008, 0x00008400,
1185 0x018, 0x0001712A,
1186 0x0EF, 0x00001000,
1187 0x03A, 0x00000080,
1188 0x03B, 0x0003A02C,
1189 0x03C, 0x00004000,
1190 0x03A, 0x00000400,
1191 0x03B, 0x0003202C,
1192 0x03C, 0x00010000,
1193 0x03A, 0x000000A0,
1194 0x03B, 0x0002B064,
1195 0x03C, 0x00004000,
1196 0x03A, 0x000000D8,
1197 0x03B, 0x00023070,
1198 0x03C, 0x00004000,
1199 0x03A, 0x00000468,
1200 0x03B, 0x0001B870,
1201 0x03C, 0x00010000,
1202 0x03A, 0x00000098,
1203 0x03B, 0x00012085,
1204 0x03C, 0x000E4000,
1205 0x03A, 0x00000418,
1206 0x03B, 0x0000A080,
1207 0x03C, 0x000F0000,
1208 0x03A, 0x00000418,
1209 0x03B, 0x00002080,
1210 0x03C, 0x00010000,
1211 0x03A, 0x00000080,
1212 0x03B, 0x0007A02C,
1213 0x03C, 0x00004000,
1214 0x03A, 0x00000400,
1215 0x03B, 0x0007202C,
1216 0x03C, 0x00010000,
1217 0x03A, 0x000000A0,
1218 0x03B, 0x0006B064,
1219 0x03C, 0x00004000,
1220 0x03A, 0x000000D8,
1221 0x03B, 0x00023070,
1222 0x03C, 0x00004000,
1223 0x03A, 0x00000468,
1224 0x03B, 0x0005B870,
1225 0x03C, 0x00010000,
1226 0x03A, 0x00000098,
1227 0x03B, 0x00052085,
1228 0x03C, 0x000E4000,
1229 0x03A, 0x00000418,
1230 0x03B, 0x0004A080,
1231 0x03C, 0x000F0000,
1232 0x03A, 0x00000418,
1233 0x03B, 0x00042080,
1234 0x03C, 0x00010000,
1235 0x03A, 0x00000080,
1236 0x03B, 0x000BA02C,
1237 0x03C, 0x00004000,
1238 0x03A, 0x00000400,
1239 0x03B, 0x000B202C,
1240 0x03C, 0x00010000,
1241 0x03A, 0x000000A0,
1242 0x03B, 0x000AB064,
1243 0x03C, 0x00004000,
1244 0x03A, 0x000000D8,
1245 0x03B, 0x000A3070,
1246 0x03C, 0x00004000,
1247 0x03A, 0x00000468,
1248 0x03B, 0x0009B870,
1249 0x03C, 0x00010000,
1250 0x03A, 0x00000098,
1251 0x03B, 0x00092085,
1252 0x03C, 0x000E4000,
1253 0x03A, 0x00000418,
1254 0x03B, 0x0008A080,
1255 0x03C, 0x000F0000,
1256 0x03A, 0x00000418,
1257 0x03B, 0x00082080,
1258 0x03C, 0x00010000,
1259 0x0EF, 0x00001100,
1260 0xFF0F0740, 0xABCD,
1261 0x034, 0x0004A0B2,
1262 0x034, 0x000490AF,
1263 0x034, 0x00048070,
1264 0x034, 0x0004706D,
1265 0x034, 0x00046050,
1266 0x034, 0x0004504D,
1267 0x034, 0x0004404A,
1268 0x034, 0x00043047,
1269 0x034, 0x0004200A,
1270 0x034, 0x00041007,
1271 0x034, 0x00040004,
1272 0xFF0F02C0, 0xCDEF,
1273 0x034, 0x0004A0B2,
1274 0x034, 0x000490AF,
1275 0x034, 0x00048070,
1276 0x034, 0x0004706D,
1277 0x034, 0x00046050,
1278 0x034, 0x0004504D,
1279 0x034, 0x0004404A,
1280 0x034, 0x00043047,
1281 0x034, 0x0004200A,
1282 0x034, 0x00041007,
1283 0x034, 0x00040004,
1284 0xFF0F01C0, 0xCDEF,
1285 0x034, 0x0004A0B2,
1286 0x034, 0x000490AF,
1287 0x034, 0x00048070,
1288 0x034, 0x0004706D,
1289 0x034, 0x00046050,
1290 0x034, 0x0004504D,
1291 0x034, 0x0004404A,
1292 0x034, 0x00043047,
1293 0x034, 0x0004200A,
1294 0x034, 0x00041007,
1295 0x034, 0x00040004,
1296 0xFF0F07D8, 0xCDEF,
1297 0x034, 0x0004A0B2,
1298 0x034, 0x000490AF,
1299 0x034, 0x00048070,
1300 0x034, 0x0004706D,
1301 0x034, 0x00046050,
1302 0x034, 0x0004504D,
1303 0x034, 0x0004404A,
1304 0x034, 0x00043047,
1305 0x034, 0x0004200A,
1306 0x034, 0x00041007,
1307 0x034, 0x00040004,
1308 0xFF0F07D0, 0xCDEF,
1309 0x034, 0x0004A0B2,
1310 0x034, 0x000490AF,
1311 0x034, 0x00048070,
1312 0x034, 0x0004706D,
1313 0x034, 0x00046050,
1314 0x034, 0x0004504D,
1315 0x034, 0x0004404A,
1316 0x034, 0x00043047,
1317 0x034, 0x0004200A,
1318 0x034, 0x00041007,
1319 0x034, 0x00040004,
1320 0xCDCDCDCD, 0xCDCD,
1321 0x034, 0x0004ADF5,
1322 0x034, 0x00049DF2,
1323 0x034, 0x00048DEF,
1324 0x034, 0x00047DEC,
1325 0x034, 0x00046DE9,
1326 0x034, 0x00045DC9,
1327 0x034, 0x00044CE8,
1328 0x034, 0x000438CA,
1329 0x034, 0x00042889,
1330 0x034, 0x0004184A,
1331 0x034, 0x0004044A,
1332 0xFF0F0740, 0xDEAD,
1333 0xFF0F0740, 0xABCD,
1334 0x034, 0x0002A0B2,
1335 0x034, 0x000290AF,
1336 0x034, 0x00028070,
1337 0x034, 0x0002706D,
1338 0x034, 0x00026050,
1339 0x034, 0x0002504D,
1340 0x034, 0x0002404A,
1341 0x034, 0x00023047,
1342 0x034, 0x0002200A,
1343 0x034, 0x00021007,
1344 0x034, 0x00020004,
1345 0xFF0F02C0, 0xCDEF,
1346 0x034, 0x0002A0B2,
1347 0x034, 0x000290AF,
1348 0x034, 0x00028070,
1349 0x034, 0x0002706D,
1350 0x034, 0x00026050,
1351 0x034, 0x0002504D,
1352 0x034, 0x0002404A,
1353 0x034, 0x00023047,
1354 0x034, 0x0002200A,
1355 0x034, 0x00021007,
1356 0x034, 0x00020004,
1357 0xFF0F01C0, 0xCDEF,
1358 0x034, 0x0002A0B2,
1359 0x034, 0x000290AF,
1360 0x034, 0x00028070,
1361 0x034, 0x0002706D,
1362 0x034, 0x00026050,
1363 0x034, 0x0002504D,
1364 0x034, 0x0002404A,
1365 0x034, 0x00023047,
1366 0x034, 0x0002200A,
1367 0x034, 0x00021007,
1368 0x034, 0x00020004,
1369 0xFF0F07D8, 0xCDEF,
1370 0x034, 0x0002A0B2,
1371 0x034, 0x000290AF,
1372 0x034, 0x00028070,
1373 0x034, 0x0002706D,
1374 0x034, 0x00026050,
1375 0x034, 0x0002504D,
1376 0x034, 0x0002404A,
1377 0x034, 0x00023047,
1378 0x034, 0x0002200A,
1379 0x034, 0x00021007,
1380 0x034, 0x00020004,
1381 0xFF0F07D0, 0xCDEF,
1382 0x034, 0x0002A0B2,
1383 0x034, 0x000290AF,
1384 0x034, 0x00028070,
1385 0x034, 0x0002706D,
1386 0x034, 0x00026050,
1387 0x034, 0x0002504D,
1388 0x034, 0x0002404A,
1389 0x034, 0x00023047,
1390 0x034, 0x0002200A,
1391 0x034, 0x00021007,
1392 0x034, 0x00020004,
1393 0xCDCDCDCD, 0xCDCD,
1394 0x034, 0x0002ADF5,
1395 0x034, 0x00029DF2,
1396 0x034, 0x00028DEF,
1397 0x034, 0x00027DEC,
1398 0x034, 0x00026DE9,
1399 0x034, 0x00025DC9,
1400 0x034, 0x00024CE8,
1401 0x034, 0x000238CA,
1402 0x034, 0x00022889,
1403 0x034, 0x0002184A,
1404 0x034, 0x0002044A,
1405 0xFF0F0740, 0xDEAD,
1406 0xFF0F0740, 0xABCD,
1407 0x034, 0x0000A0B2,
1408 0x034, 0x000090AF,
1409 0x034, 0x00008070,
1410 0x034, 0x0000706D,
1411 0x034, 0x00006050,
1412 0x034, 0x0000504D,
1413 0x034, 0x0000404A,
1414 0x034, 0x00003047,
1415 0x034, 0x0000200A,
1416 0x034, 0x00001007,
1417 0x034, 0x00000004,
1418 0xFF0F02C0, 0xCDEF,
1419 0x034, 0x0000A0B2,
1420 0x034, 0x000090AF,
1421 0x034, 0x00008070,
1422 0x034, 0x0000706D,
1423 0x034, 0x00006050,
1424 0x034, 0x0000504D,
1425 0x034, 0x0000404A,
1426 0x034, 0x00003047,
1427 0x034, 0x0000200A,
1428 0x034, 0x00001007,
1429 0x034, 0x00000004,
1430 0xFF0F01C0, 0xCDEF,
1431 0x034, 0x0000A0B2,
1432 0x034, 0x000090AF,
1433 0x034, 0x00008070,
1434 0x034, 0x0000706D,
1435 0x034, 0x00006050,
1436 0x034, 0x0000504D,
1437 0x034, 0x0000404A,
1438 0x034, 0x00003047,
1439 0x034, 0x0000200A,
1440 0x034, 0x00001007,
1441 0x034, 0x00000004,
1442 0xFF0F07D8, 0xCDEF,
1443 0x034, 0x0000A0B2,
1444 0x034, 0x000090AF,
1445 0x034, 0x00008070,
1446 0x034, 0x0000706D,
1447 0x034, 0x00006050,
1448 0x034, 0x0000504D,
1449 0x034, 0x0000404A,
1450 0x034, 0x00003047,
1451 0x034, 0x0000200A,
1452 0x034, 0x00001007,
1453 0x034, 0x00000004,
1454 0xFF0F07D0, 0xCDEF,
1455 0x034, 0x0000A0B2,
1456 0x034, 0x000090AF,
1457 0x034, 0x00008070,
1458 0x034, 0x0000706D,
1459 0x034, 0x00006050,
1460 0x034, 0x0000504D,
1461 0x034, 0x0000404A,
1462 0x034, 0x00003047,
1463 0x034, 0x0000200A,
1464 0x034, 0x00001007,
1465 0x034, 0x00000004,
1466 0xCDCDCDCD, 0xCDCD,
1467 0x034, 0x0000AFF7,
1468 0x034, 0x00009DF7,
1469 0x034, 0x00008DF4,
1470 0x034, 0x00007DF1,
1471 0x034, 0x00006DEE,
1472 0x034, 0x00005DCD,
1473 0x034, 0x00004CEB,
1474 0x034, 0x000038CC,
1475 0x034, 0x0000288B,
1476 0x034, 0x0000184C,
1477 0x034, 0x0000044C,
1478 0xFF0F0740, 0xDEAD,
1479 0x0EF, 0x00000000,
1480 0xFF0F0740, 0xABCD,
1481 0x018, 0x0001712A,
1482 0x0EF, 0x00000040,
1483 0x035, 0x000001D4,
1484 0x035, 0x000081D4,
1485 0x035, 0x000101D4,
1486 0x035, 0x000201B4,
1487 0x035, 0x000281B4,
1488 0x035, 0x000301B4,
1489 0x035, 0x000401B4,
1490 0x035, 0x000481B4,
1491 0x035, 0x000501B4,
1492 0xFF0F02C0, 0xCDEF,
1493 0x018, 0x0001712A,
1494 0x0EF, 0x00000040,
1495 0x035, 0x000001D4,
1496 0x035, 0x000081D4,
1497 0x035, 0x000101D4,
1498 0x035, 0x000201B4,
1499 0x035, 0x000281B4,
1500 0x035, 0x000301B4,
1501 0x035, 0x000401B4,
1502 0x035, 0x000481B4,
1503 0x035, 0x000501B4,
1504 0xFF0F01C0, 0xCDEF,
1505 0x018, 0x0001712A,
1506 0x0EF, 0x00000040,
1507 0x035, 0x000001D4,
1508 0x035, 0x000081D4,
1509 0x035, 0x000101D4,
1510 0x035, 0x000201B4,
1511 0x035, 0x000281B4,
1512 0x035, 0x000301B4,
1513 0x035, 0x000401B4,
1514 0x035, 0x000481B4,
1515 0x035, 0x000501B4,
1516 0xFF0F07D8, 0xCDEF,
1517 0x018, 0x0001712A,
1518 0x0EF, 0x00000040,
1519 0x035, 0x000001D4,
1520 0x035, 0x000081D4,
1521 0x035, 0x000101D4,
1522 0x035, 0x000201B4,
1523 0x035, 0x000281B4,
1524 0x035, 0x000301B4,
1525 0x035, 0x000401B4,
1526 0x035, 0x000481B4,
1527 0x035, 0x000501B4,
1528 0xFF0F07D0, 0xCDEF,
1529 0x018, 0x0001712A,
1530 0x0EF, 0x00000040,
1531 0x035, 0x000001D4,
1532 0x035, 0x000081D4,
1533 0x035, 0x000101D4,
1534 0x035, 0x000201B4,
1535 0x035, 0x000281B4,
1536 0x035, 0x000301B4,
1537 0x035, 0x000401B4,
1538 0x035, 0x000481B4,
1539 0x035, 0x000501B4,
1540 0xCDCDCDCD, 0xCDCD,
1541 0x018, 0x0001712A,
1542 0x0EF, 0x00000040,
1543 0x035, 0x00000188,
1544 0x035, 0x00008147,
1545 0x035, 0x00010147,
1546 0x035, 0x000201D7,
1547 0x035, 0x000281D7,
1548 0x035, 0x000301D7,
1549 0x035, 0x000401D8,
1550 0x035, 0x000481D8,
1551 0x035, 0x000501D8,
1552 0xFF0F0740, 0xDEAD,
1553 0x0EF, 0x00000000,
1554 0xFF0F0740, 0xABCD,
1555 0x018, 0x0001712A,
1556 0x0EF, 0x00000010,
1557 0x036, 0x00004BFB,
1558 0x036, 0x0000CBFB,
1559 0x036, 0x00014BFB,
1560 0x036, 0x0001CBFB,
1561 0x036, 0x00024F4B,
1562 0x036, 0x0002CF4B,
1563 0x036, 0x00034F4B,
1564 0x036, 0x0003CF4B,
1565 0x036, 0x00044F4B,
1566 0x036, 0x0004CF4B,
1567 0x036, 0x00054F4B,
1568 0x036, 0x0005CF4B,
1569 0xFF0F02C0, 0xCDEF,
1570 0x018, 0x0001712A,
1571 0x0EF, 0x00000010,
1572 0x036, 0x00004BFB,
1573 0x036, 0x0000CBFB,
1574 0x036, 0x00014BFB,
1575 0x036, 0x0001CBFB,
1576 0x036, 0x00024F4B,
1577 0x036, 0x0002CF4B,
1578 0x036, 0x00034F4B,
1579 0x036, 0x0003CF4B,
1580 0x036, 0x00044F4B,
1581 0x036, 0x0004CF4B,
1582 0x036, 0x00054F4B,
1583 0x036, 0x0005CF4B,
1584 0xFF0F01C0, 0xCDEF,
1585 0x018, 0x0001712A,
1586 0x0EF, 0x00000010,
1587 0x036, 0x00004BFB,
1588 0x036, 0x0000CBFB,
1589 0x036, 0x00014BFB,
1590 0x036, 0x0001CBFB,
1591 0x036, 0x00024F4B,
1592 0x036, 0x0002CF4B,
1593 0x036, 0x00034F4B,
1594 0x036, 0x0003CF4B,
1595 0x036, 0x00044F4B,
1596 0x036, 0x0004CF4B,
1597 0x036, 0x00054F4B,
1598 0x036, 0x0005CF4B,
1599 0xFF0F07D8, 0xCDEF,
1600 0x018, 0x0001712A,
1601 0x0EF, 0x00000010,
1602 0x036, 0x00004BFB,
1603 0x036, 0x0000CBFB,
1604 0x036, 0x00014BFB,
1605 0x036, 0x0001CBFB,
1606 0x036, 0x00024F4B,
1607 0x036, 0x0002CF4B,
1608 0x036, 0x00034F4B,
1609 0x036, 0x0003CF4B,
1610 0x036, 0x00044F4B,
1611 0x036, 0x0004CF4B,
1612 0x036, 0x00054F4B,
1613 0x036, 0x0005CF4B,
1614 0xFF0F07D0, 0xCDEF,
1615 0x018, 0x0001712A,
1616 0x0EF, 0x00000010,
1617 0x036, 0x00004BFB,
1618 0x036, 0x0000CBFB,
1619 0x036, 0x00014BFB,
1620 0x036, 0x0001CBFB,
1621 0x036, 0x00024F4B,
1622 0x036, 0x0002CF4B,
1623 0x036, 0x00034F4B,
1624 0x036, 0x0003CF4B,
1625 0x036, 0x00044F4B,
1626 0x036, 0x0004CF4B,
1627 0x036, 0x00054F4B,
1628 0x036, 0x0005CF4B,
1629 0xCDCDCDCD, 0xCDCD,
1630 0x018, 0x0001712A,
1631 0x0EF, 0x00000010,
1632 0x036, 0x00084EB4,
1633 0x036, 0x0008CC35,
1634 0x036, 0x00094C35,
1635 0x036, 0x0009CC35,
1636 0x036, 0x000A4935,
1637 0x036, 0x000ACC35,
1638 0x036, 0x000B4C35,
1639 0x036, 0x000BCC35,
1640 0x036, 0x000C4EB4,
1641 0x036, 0x000CCEB5,
1642 0x036, 0x000D4EB5,
1643 0x036, 0x000DCEB5,
1644 0xFF0F0740, 0xDEAD,
1645 0x0EF, 0x00000000,
1646 0x0EF, 0x00000008,
1647 0xFF0F0740, 0xABCD,
1648 0x03C, 0x000002CC,
1649 0x03C, 0x00000522,
1650 0x03C, 0x00000902,
1651 0xFF0F02C0, 0xCDEF,
1652 0x03C, 0x000002CC,
1653 0x03C, 0x00000522,
1654 0x03C, 0x00000902,
1655 0xFF0F01C0, 0xCDEF,
1656 0x03C, 0x000002CC,
1657 0x03C, 0x00000522,
1658 0x03C, 0x00000902,
1659 0xFF0F07D8, 0xCDEF,
1660 0x03C, 0x000002CC,
1661 0x03C, 0x00000522,
1662 0x03C, 0x00000902,
1663 0xFF0F07D0, 0xCDEF,
1664 0x03C, 0x000002CC,
1665 0x03C, 0x00000522,
1666 0x03C, 0x00000902,
1667 0xCDCDCDCD, 0xCDCD,
1668 0x03C, 0x000002A8,
1669 0x03C, 0x000005A2,
1670 0x03C, 0x00000880,
1671 0xFF0F0740, 0xDEAD,
1672 0x0EF, 0x00000000,
1673 0x018, 0x0001712A,
1674 0x0EF, 0x00000002,
1675 0x0DF, 0x00000080,
1676 0x01F, 0x00040064,
1677 0xFF0F0740, 0xABCD,
1678 0x061, 0x000FDD43,
1679 0x062, 0x00038F4B,
1680 0x063, 0x00032117,
1681 0x064, 0x000194AC,
1682 0x065, 0x000931D1,
1683 0xFF0F02C0, 0xCDEF,
1684 0x061, 0x000FDD43,
1685 0x062, 0x00038F4B,
1686 0x063, 0x00032117,
1687 0x064, 0x000194AC,
1688 0x065, 0x000931D1,
1689 0xFF0F01C0, 0xCDEF,
1690 0x061, 0x000FDD43,
1691 0x062, 0x00038F4B,
1692 0x063, 0x00032117,
1693 0x064, 0x000194AC,
1694 0x065, 0x000931D1,
1695 0xFF0F07D8, 0xCDEF,
1696 0x061, 0x000FDD43,
1697 0x062, 0x00038F4B,
1698 0x063, 0x00032117,
1699 0x064, 0x000194AC,
1700 0x065, 0x000931D1,
1701 0xFF0F07D0, 0xCDEF,
1702 0x061, 0x000FDD43,
1703 0x062, 0x00038F4B,
1704 0x063, 0x00032117,
1705 0x064, 0x000194AC,
1706 0x065, 0x000931D1,
1707 0xCDCDCDCD, 0xCDCD,
1708 0x061, 0x000E5D53,
1709 0x062, 0x00038FCD,
1710 0x063, 0x000314EB,
1711 0x064, 0x000196AC,
1712 0x065, 0x000911D7,
1713 0xFF0F0740, 0xDEAD,
1714 0x008, 0x00008400,
1715 0x01C, 0x000739D2,
1716 0x0B4, 0x0001E78D,
1717 0x018, 0x0001F12A,
1718 0x0FE, 0x00000000,
1719 0x0FE, 0x00000000,
1720 0x0FE, 0x00000000,
1721 0x0FE, 0x00000000,
1722 0x0B4, 0x0001A78D,
1723 0x018, 0x0001712A,
1724};
1725
1726u32 RTL8812AE_RADIOB_ARRAY[] = {
1727 0x056, 0x00051CF2,
1728 0x066, 0x00040000,
1729 0x089, 0x00000080,
1730 0xFF0F0740, 0xABCD,
1731 0x086, 0x00014B38,
1732 0xFF0F01C0, 0xCDEF,
1733 0x086, 0x00014B38,
1734 0xFF0F02C0, 0xCDEF,
1735 0x086, 0x00014B38,
1736 0xFF0F07D8, 0xCDEF,
1737 0x086, 0x00014B3A,
1738 0xFF0F07D0, 0xCDEF,
1739 0x086, 0x00014B3A,
1740 0xCDCDCDCD, 0xCDCD,
1741 0x086, 0x00014B38,
1742 0xFF0F0740, 0xDEAD,
1743 0x018, 0x00000006,
1744 0x0EF, 0x00002000,
1745 0xFF0F07D8, 0xABCD,
1746 0x03B, 0x0003F218,
1747 0x03B, 0x00030A58,
1748 0x03B, 0x0002FA58,
1749 0x03B, 0x00022590,
1750 0x03B, 0x0001FA50,
1751 0x03B, 0x00010248,
1752 0x03B, 0x00008240,
1753 0xFF0F07D0, 0xCDEF,
1754 0x03B, 0x0003F218,
1755 0x03B, 0x00030A58,
1756 0x03B, 0x0002FA58,
1757 0x03B, 0x00022590,
1758 0x03B, 0x0001FA50,
1759 0x03B, 0x00010248,
1760 0x03B, 0x00008240,
1761 0xCDCDCDCD, 0xCDCD,
1762 0x03B, 0x00038A58,
1763 0x03B, 0x00037A58,
1764 0x03B, 0x0002A590,
1765 0x03B, 0x00027A50,
1766 0x03B, 0x00018248,
1767 0x03B, 0x00010240,
1768 0x03B, 0x00008240,
1769 0xFF0F07D8, 0xDEAD,
1770 0x0EF, 0x00000100,
1771 0xFF0F07D8, 0xABCD,
1772 0x034, 0x0000A4EE,
1773 0x034, 0x00009076,
1774 0x034, 0x00008073,
1775 0x034, 0x00007070,
1776 0x034, 0x0000606D,
1777 0x034, 0x0000506A,
1778 0x034, 0x00004049,
1779 0x034, 0x00003046,
1780 0x034, 0x00002028,
1781 0x034, 0x00001025,
1782 0x034, 0x00000022,
1783 0xCDCDCDCD, 0xCDCD,
1784 0x034, 0x0000ADF4,
1785 0x034, 0x00009DF1,
1786 0x034, 0x00008DEE,
1787 0x034, 0x00007DEB,
1788 0x034, 0x00006DE8,
1789 0x034, 0x00005CEC,
1790 0x034, 0x00004CE9,
1791 0x034, 0x000034EA,
1792 0x034, 0x000024E7,
1793 0x034, 0x0000146B,
1794 0x034, 0x0000006D,
1795 0xFF0F07D8, 0xDEAD,
1796 0x0EF, 0x00000000,
1797 0x0EF, 0x000020A2,
1798 0x0DF, 0x00000080,
1799 0x035, 0x00000192,
1800 0x035, 0x00008192,
1801 0x035, 0x00010192,
1802 0x036, 0x00000024,
1803 0x036, 0x00008024,
1804 0x036, 0x00010024,
1805 0x036, 0x00018024,
1806 0x0EF, 0x00000000,
1807 0x051, 0x00000C21,
1808 0x052, 0x000006D9,
1809 0x053, 0x000FC649,
1810 0x054, 0x0000017E,
1811 0x0EF, 0x00000002,
1812 0x008, 0x00008400,
1813 0x018, 0x0001712A,
1814 0x0EF, 0x00001000,
1815 0x03A, 0x00000080,
1816 0x03B, 0x0003A02C,
1817 0x03C, 0x00004000,
1818 0x03A, 0x00000400,
1819 0x03B, 0x0003202C,
1820 0x03C, 0x00010000,
1821 0x03A, 0x000000A0,
1822 0x03B, 0x0002B064,
1823 0x03C, 0x00004000,
1824 0x03A, 0x000000D8,
1825 0x03B, 0x00023070,
1826 0x03C, 0x00004000,
1827 0x03A, 0x00000468,
1828 0x03B, 0x0001B870,
1829 0x03C, 0x00010000,
1830 0x03A, 0x00000098,
1831 0x03B, 0x00012085,
1832 0x03C, 0x000E4000,
1833 0x03A, 0x00000418,
1834 0x03B, 0x0000A080,
1835 0x03C, 0x000F0000,
1836 0x03A, 0x00000418,
1837 0x03B, 0x00002080,
1838 0x03C, 0x00010000,
1839 0x03A, 0x00000080,
1840 0x03B, 0x0007A02C,
1841 0x03C, 0x00004000,
1842 0x03A, 0x00000400,
1843 0x03B, 0x0007202C,
1844 0x03C, 0x00010000,
1845 0x03A, 0x000000A0,
1846 0x03B, 0x0006B064,
1847 0x03C, 0x00004000,
1848 0x03A, 0x000000D8,
1849 0x03B, 0x00063070,
1850 0x03C, 0x00004000,
1851 0x03A, 0x00000468,
1852 0x03B, 0x0005B870,
1853 0x03C, 0x00010000,
1854 0x03A, 0x00000098,
1855 0x03B, 0x00052085,
1856 0x03C, 0x000E4000,
1857 0x03A, 0x00000418,
1858 0x03B, 0x0004A080,
1859 0x03C, 0x000F0000,
1860 0x03A, 0x00000418,
1861 0x03B, 0x00042080,
1862 0x03C, 0x00010000,
1863 0x03A, 0x00000080,
1864 0x03B, 0x000BA02C,
1865 0x03C, 0x00004000,
1866 0x03A, 0x00000400,
1867 0x03B, 0x000B202C,
1868 0x03C, 0x00010000,
1869 0x03A, 0x000000A0,
1870 0x03B, 0x000AB064,
1871 0x03C, 0x00004000,
1872 0x03A, 0x000000D8,
1873 0x03B, 0x000A3070,
1874 0x03C, 0x00004000,
1875 0x03A, 0x00000468,
1876 0x03B, 0x0009B870,
1877 0x03C, 0x00010000,
1878 0x03A, 0x00000098,
1879 0x03B, 0x00092085,
1880 0x03C, 0x000E4000,
1881 0x03A, 0x00000418,
1882 0x03B, 0x0008A080,
1883 0x03C, 0x000F0000,
1884 0x03A, 0x00000418,
1885 0x03B, 0x00082080,
1886 0x03C, 0x00010000,
1887 0x0EF, 0x00001100,
1888 0xFF0F0740, 0xABCD,
1889 0x034, 0x0004A0B2,
1890 0x034, 0x000490AF,
1891 0x034, 0x00048070,
1892 0x034, 0x0004706D,
1893 0x034, 0x00046050,
1894 0x034, 0x0004504D,
1895 0x034, 0x0004404A,
1896 0x034, 0x00043047,
1897 0x034, 0x0004200A,
1898 0x034, 0x00041007,
1899 0x034, 0x00040004,
1900 0xFF0F01C0, 0xCDEF,
1901 0x034, 0x0004A0B2,
1902 0x034, 0x000490AF,
1903 0x034, 0x00048070,
1904 0x034, 0x0004706D,
1905 0x034, 0x00046050,
1906 0x034, 0x0004504D,
1907 0x034, 0x0004404A,
1908 0x034, 0x00043047,
1909 0x034, 0x0004200A,
1910 0x034, 0x00041007,
1911 0x034, 0x00040004,
1912 0xFF0F02C0, 0xCDEF,
1913 0x034, 0x0004A0B2,
1914 0x034, 0x000490AF,
1915 0x034, 0x00048070,
1916 0x034, 0x0004706D,
1917 0x034, 0x00046050,
1918 0x034, 0x0004504D,
1919 0x034, 0x0004404A,
1920 0x034, 0x00043047,
1921 0x034, 0x0004200A,
1922 0x034, 0x00041007,
1923 0x034, 0x00040004,
1924 0xFF0F07D8, 0xCDEF,
1925 0x034, 0x0004A0B2,
1926 0x034, 0x000490AF,
1927 0x034, 0x00048070,
1928 0x034, 0x0004706D,
1929 0x034, 0x00046050,
1930 0x034, 0x0004504D,
1931 0x034, 0x0004404A,
1932 0x034, 0x00043047,
1933 0x034, 0x0004200A,
1934 0x034, 0x00041007,
1935 0x034, 0x00040004,
1936 0xFF0F07D0, 0xCDEF,
1937 0x034, 0x0004A0B2,
1938 0x034, 0x000490AF,
1939 0x034, 0x00048070,
1940 0x034, 0x0004706D,
1941 0x034, 0x00046050,
1942 0x034, 0x0004504D,
1943 0x034, 0x0004404A,
1944 0x034, 0x00043047,
1945 0x034, 0x0004200A,
1946 0x034, 0x00041007,
1947 0x034, 0x00040004,
1948 0xCDCDCDCD, 0xCDCD,
1949 0x034, 0x0004ADF5,
1950 0x034, 0x00049DF2,
1951 0x034, 0x00048DEF,
1952 0x034, 0x00047DEC,
1953 0x034, 0x00046DE9,
1954 0x034, 0x00045DC9,
1955 0x034, 0x00044CE8,
1956 0x034, 0x000438CA,
1957 0x034, 0x00042889,
1958 0x034, 0x0004184A,
1959 0x034, 0x0004044A,
1960 0xFF0F0740, 0xDEAD,
1961 0xFF0F0740, 0xABCD,
1962 0x034, 0x0002A0B2,
1963 0x034, 0x000290AF,
1964 0x034, 0x00028070,
1965 0x034, 0x0002706D,
1966 0x034, 0x00026050,
1967 0x034, 0x0002504D,
1968 0x034, 0x0002404A,
1969 0x034, 0x00023047,
1970 0x034, 0x0002200A,
1971 0x034, 0x00021007,
1972 0x034, 0x00020004,
1973 0xFF0F01C0, 0xCDEF,
1974 0x034, 0x0002A0B2,
1975 0x034, 0x000290AF,
1976 0x034, 0x00028070,
1977 0x034, 0x0002706D,
1978 0x034, 0x00026050,
1979 0x034, 0x0002504D,
1980 0x034, 0x0002404A,
1981 0x034, 0x00023047,
1982 0x034, 0x0002200A,
1983 0x034, 0x00021007,
1984 0x034, 0x00020004,
1985 0xFF0F02C0, 0xCDEF,
1986 0x034, 0x0002A0B2,
1987 0x034, 0x000290AF,
1988 0x034, 0x00028070,
1989 0x034, 0x0002706D,
1990 0x034, 0x00026050,
1991 0x034, 0x0002504D,
1992 0x034, 0x0002404A,
1993 0x034, 0x00023047,
1994 0x034, 0x0002200A,
1995 0x034, 0x00021007,
1996 0x034, 0x00020004,
1997 0xFF0F07D8, 0xCDEF,
1998 0x034, 0x0002A0B2,
1999 0x034, 0x000290AF,
2000 0x034, 0x00028070,
2001 0x034, 0x0002706D,
2002 0x034, 0x00026050,
2003 0x034, 0x0002504D,
2004 0x034, 0x0002404A,
2005 0x034, 0x00023047,
2006 0x034, 0x0002200A,
2007 0x034, 0x00021007,
2008 0x034, 0x00020004,
2009 0xFF0F07D0, 0xCDEF,
2010 0x034, 0x0002A0B2,
2011 0x034, 0x000290AF,
2012 0x034, 0x00028070,
2013 0x034, 0x0002706D,
2014 0x034, 0x00026050,
2015 0x034, 0x0002504D,
2016 0x034, 0x0002404A,
2017 0x034, 0x00023047,
2018 0x034, 0x0002200A,
2019 0x034, 0x00021007,
2020 0x034, 0x00020004,
2021 0xCDCDCDCD, 0xCDCD,
2022 0x034, 0x0002ADF5,
2023 0x034, 0x00029DF2,
2024 0x034, 0x00028DEF,
2025 0x034, 0x00027DEC,
2026 0x034, 0x00026DE9,
2027 0x034, 0x00025DC9,
2028 0x034, 0x00024CE8,
2029 0x034, 0x000238CA,
2030 0x034, 0x00022889,
2031 0x034, 0x0002184A,
2032 0x034, 0x0002044A,
2033 0xFF0F0740, 0xDEAD,
2034 0xFF0F0740, 0xABCD,
2035 0x034, 0x0000A0B2,
2036 0x034, 0x000090AF,
2037 0x034, 0x00008070,
2038 0x034, 0x0000706D,
2039 0x034, 0x00006050,
2040 0x034, 0x0000504D,
2041 0x034, 0x0000404A,
2042 0x034, 0x00003047,
2043 0x034, 0x0000200A,
2044 0x034, 0x00001007,
2045 0x034, 0x00000004,
2046 0xFF0F01C0, 0xCDEF,
2047 0x034, 0x0000A0B2,
2048 0x034, 0x000090AF,
2049 0x034, 0x00008070,
2050 0x034, 0x0000706D,
2051 0x034, 0x00006050,
2052 0x034, 0x0000504D,
2053 0x034, 0x0000404A,
2054 0x034, 0x00003047,
2055 0x034, 0x0000200A,
2056 0x034, 0x00001007,
2057 0x034, 0x00000004,
2058 0xFF0F02C0, 0xCDEF,
2059 0x034, 0x0000A0B2,
2060 0x034, 0x000090AF,
2061 0x034, 0x00008070,
2062 0x034, 0x0000706D,
2063 0x034, 0x00006050,
2064 0x034, 0x0000504D,
2065 0x034, 0x0000404A,
2066 0x034, 0x00003047,
2067 0x034, 0x0000200A,
2068 0x034, 0x00001007,
2069 0x034, 0x00000004,
2070 0xFF0F07D8, 0xCDEF,
2071 0x034, 0x0000A0B2,
2072 0x034, 0x000090AF,
2073 0x034, 0x00008070,
2074 0x034, 0x0000706D,
2075 0x034, 0x00006050,
2076 0x034, 0x0000504D,
2077 0x034, 0x0000404A,
2078 0x034, 0x00003047,
2079 0x034, 0x0000200A,
2080 0x034, 0x00001007,
2081 0x034, 0x00000004,
2082 0xFF0F07D0, 0xCDEF,
2083 0x034, 0x0000A0B2,
2084 0x034, 0x000090AF,
2085 0x034, 0x00008070,
2086 0x034, 0x0000706D,
2087 0x034, 0x00006050,
2088 0x034, 0x0000504D,
2089 0x034, 0x0000404A,
2090 0x034, 0x00003047,
2091 0x034, 0x0000200A,
2092 0x034, 0x00001007,
2093 0x034, 0x00000004,
2094 0xCDCDCDCD, 0xCDCD,
2095 0x034, 0x0000AFF7,
2096 0x034, 0x00009DF7,
2097 0x034, 0x00008DF4,
2098 0x034, 0x00007DF1,
2099 0x034, 0x00006DEE,
2100 0x034, 0x00005DCD,
2101 0x034, 0x00004CEB,
2102 0x034, 0x000038CC,
2103 0x034, 0x0000288B,
2104 0x034, 0x0000184C,
2105 0x034, 0x0000044C,
2106 0xFF0F0740, 0xDEAD,
2107 0x0EF, 0x00000000,
2108 0xFF0F0740, 0xABCD,
2109 0x018, 0x0001712A,
2110 0x0EF, 0x00000040,
2111 0x035, 0x000001C5,
2112 0x035, 0x000081C5,
2113 0x035, 0x000101C5,
2114 0x035, 0x00020174,
2115 0x035, 0x00028174,
2116 0x035, 0x00030174,
2117 0x035, 0x00040185,
2118 0x035, 0x00048185,
2119 0x035, 0x00050185,
2120 0x0EF, 0x00000000,
2121 0xFF0F01C0, 0xCDEF,
2122 0x018, 0x0001712A,
2123 0x0EF, 0x00000040,
2124 0x035, 0x000001C5,
2125 0x035, 0x000081C5,
2126 0x035, 0x000101C5,
2127 0x035, 0x00020174,
2128 0x035, 0x00028174,
2129 0x035, 0x00030174,
2130 0x035, 0x00040185,
2131 0x035, 0x00048185,
2132 0x035, 0x00050185,
2133 0x0EF, 0x00000000,
2134 0xFF0F02C0, 0xCDEF,
2135 0x018, 0x0001712A,
2136 0x0EF, 0x00000040,
2137 0x035, 0x000001C5,
2138 0x035, 0x000081C5,
2139 0x035, 0x000101C5,
2140 0x035, 0x00020174,
2141 0x035, 0x00028174,
2142 0x035, 0x00030174,
2143 0x035, 0x00040185,
2144 0x035, 0x00048185,
2145 0x035, 0x00050185,
2146 0x0EF, 0x00000000,
2147 0xFF0F07D8, 0xCDEF,
2148 0x018, 0x0001712A,
2149 0x0EF, 0x00000040,
2150 0x035, 0x000001C5,
2151 0x035, 0x000081C5,
2152 0x035, 0x000101C5,
2153 0x035, 0x00020174,
2154 0x035, 0x00028174,
2155 0x035, 0x00030174,
2156 0x035, 0x00040185,
2157 0x035, 0x00048185,
2158 0x035, 0x00050185,
2159 0x0EF, 0x00000000,
2160 0xFF0F07D0, 0xCDEF,
2161 0x018, 0x0001712A,
2162 0x0EF, 0x00000040,
2163 0x035, 0x000001C5,
2164 0x035, 0x000081C5,
2165 0x035, 0x000101C5,
2166 0x035, 0x00020174,
2167 0x035, 0x00028174,
2168 0x035, 0x00030174,
2169 0x035, 0x00040185,
2170 0x035, 0x00048185,
2171 0x035, 0x00050185,
2172 0x0EF, 0x00000000,
2173 0xCDCDCDCD, 0xCDCD,
2174 0x018, 0x0001712A,
2175 0x0EF, 0x00000040,
2176 0x035, 0x00000186,
2177 0x035, 0x00008186,
2178 0x035, 0x00010185,
2179 0x035, 0x000201D5,
2180 0x035, 0x000281D5,
2181 0x035, 0x000301D5,
2182 0x035, 0x000401D5,
2183 0x035, 0x000481D5,
2184 0x035, 0x000501D5,
2185 0x0EF, 0x00000000,
2186 0xFF0F0740, 0xDEAD,
2187 0xFF0F0740, 0xABCD,
2188 0x018, 0x0001712A,
2189 0x0EF, 0x00000010,
2190 0x036, 0x00005B8B,
2191 0x036, 0x0000DB8B,
2192 0x036, 0x00015B8B,
2193 0x036, 0x0001DB8B,
2194 0x036, 0x000262DB,
2195 0x036, 0x0002E2DB,
2196 0x036, 0x000362DB,
2197 0x036, 0x0003E2DB,
2198 0x036, 0x0004553B,
2199 0x036, 0x0004D53B,
2200 0x036, 0x0005553B,
2201 0x036, 0x0005D53B,
2202 0xFF0F01C0, 0xCDEF,
2203 0x018, 0x0001712A,
2204 0x0EF, 0x00000010,
2205 0x036, 0x00005B8B,
2206 0x036, 0x0000DB8B,
2207 0x036, 0x00015B8B,
2208 0x036, 0x0001DB8B,
2209 0x036, 0x000262DB,
2210 0x036, 0x0002E2DB,
2211 0x036, 0x000362DB,
2212 0x036, 0x0003E2DB,
2213 0x036, 0x0004553B,
2214 0x036, 0x0004D53B,
2215 0x036, 0x0005553B,
2216 0x036, 0x0005D53B,
2217 0xFF0F02C0, 0xCDEF,
2218 0x018, 0x0001712A,
2219 0x0EF, 0x00000010,
2220 0x036, 0x00005B8B,
2221 0x036, 0x0000DB8B,
2222 0x036, 0x00015B8B,
2223 0x036, 0x0001DB8B,
2224 0x036, 0x000262DB,
2225 0x036, 0x0002E2DB,
2226 0x036, 0x000362DB,
2227 0x036, 0x0003E2DB,
2228 0x036, 0x0004553B,
2229 0x036, 0x0004D53B,
2230 0x036, 0x0005553B,
2231 0x036, 0x0005D53B,
2232 0xFF0F07D8, 0xCDEF,
2233 0x018, 0x0001712A,
2234 0x0EF, 0x00000010,
2235 0x036, 0x00005B8B,
2236 0x036, 0x0000DB8B,
2237 0x036, 0x00015B8B,
2238 0x036, 0x0001DB8B,
2239 0x036, 0x000262DB,
2240 0x036, 0x0002E2DB,
2241 0x036, 0x000362DB,
2242 0x036, 0x0003E2DB,
2243 0x036, 0x0004553B,
2244 0x036, 0x0004D53B,
2245 0x036, 0x0005553B,
2246 0x036, 0x0005D53B,
2247 0xFF0F07D0, 0xCDEF,
2248 0x018, 0x0001712A,
2249 0x0EF, 0x00000010,
2250 0x036, 0x00005B8B,
2251 0x036, 0x0000DB8B,
2252 0x036, 0x00015B8B,
2253 0x036, 0x0001DB8B,
2254 0x036, 0x000262DB,
2255 0x036, 0x0002E2DB,
2256 0x036, 0x000362DB,
2257 0x036, 0x0003E2DB,
2258 0x036, 0x0004553B,
2259 0x036, 0x0004D53B,
2260 0x036, 0x0005553B,
2261 0x036, 0x0005D53B,
2262 0xCDCDCDCD, 0xCDCD,
2263 0x018, 0x0001712A,
2264 0x0EF, 0x00000010,
2265 0x036, 0x00084EB4,
2266 0x036, 0x0008C9B4,
2267 0x036, 0x000949B4,
2268 0x036, 0x0009C9B4,
2269 0x036, 0x000A4935,
2270 0x036, 0x000AC935,
2271 0x036, 0x000B4935,
2272 0x036, 0x000BC935,
2273 0x036, 0x000C4EB4,
2274 0x036, 0x000CCEB4,
2275 0x036, 0x000D4EB4,
2276 0x036, 0x000DCEB4,
2277 0xFF0F0740, 0xDEAD,
2278 0x0EF, 0x00000000,
2279 0x0EF, 0x00000008,
2280 0xFF0F0740, 0xABCD,
2281 0x03C, 0x000002DC,
2282 0x03C, 0x00000524,
2283 0x03C, 0x00000902,
2284 0xFF0F01C0, 0xCDEF,
2285 0x03C, 0x000002DC,
2286 0x03C, 0x00000524,
2287 0x03C, 0x00000902,
2288 0xFF0F02C0, 0xCDEF,
2289 0x03C, 0x000002DC,
2290 0x03C, 0x00000524,
2291 0x03C, 0x00000902,
2292 0xFF0F07D8, 0xCDEF,
2293 0x03C, 0x000002DC,
2294 0x03C, 0x00000524,
2295 0x03C, 0x00000902,
2296 0xFF0F07D0, 0xCDEF,
2297 0x03C, 0x000002DC,
2298 0x03C, 0x00000524,
2299 0x03C, 0x00000902,
2300 0xCDCDCDCD, 0xCDCD,
2301 0x03C, 0x000002AA,
2302 0x03C, 0x000005A2,
2303 0x03C, 0x00000880,
2304 0xFF0F0740, 0xDEAD,
2305 0x0EF, 0x00000000,
2306 0x018, 0x0001712A,
2307 0x0EF, 0x00000002,
2308 0x0DF, 0x00000080,
2309 0xFF0F0740, 0xABCD,
2310 0x061, 0x000EAC43,
2311 0x062, 0x00038F47,
2312 0x063, 0x00031157,
2313 0x064, 0x0001C4AC,
2314 0x065, 0x000931D1,
2315 0xFF0F01C0, 0xCDEF,
2316 0x061, 0x000EAC43,
2317 0x062, 0x00038F47,
2318 0x063, 0x00031157,
2319 0x064, 0x0001C4AC,
2320 0x065, 0x000931D1,
2321 0xFF0F02C0, 0xCDEF,
2322 0x061, 0x000EAC43,
2323 0x062, 0x00038F47,
2324 0x063, 0x00031157,
2325 0x064, 0x0001C4AC,
2326 0x065, 0x000931D1,
2327 0xFF0F07D8, 0xCDEF,
2328 0x061, 0x000EAC43,
2329 0x062, 0x00038F47,
2330 0x063, 0x00031157,
2331 0x064, 0x0001C4AC,
2332 0x065, 0x000931D1,
2333 0xFF0F07D0, 0xCDEF,
2334 0x061, 0x000EAC43,
2335 0x062, 0x00038F47,
2336 0x063, 0x00031157,
2337 0x064, 0x0001C4AC,
2338 0x065, 0x000931D1,
2339 0xCDCDCDCD, 0xCDCD,
2340 0x061, 0x000E5D53,
2341 0x062, 0x00038FCD,
2342 0x063, 0x000314EB,
2343 0x064, 0x000196AC,
2344 0x065, 0x000931D7,
2345 0xFF0F0740, 0xDEAD,
2346 0x008, 0x00008400,
2347};
2348
2349u32 RTL8821AE_RADIOA_ARRAY[] = {
2350 0x018, 0x0001712A,
2351 0x056, 0x00051CF2,
2352 0x066, 0x00040000,
2353 0x000, 0x00010000,
2354 0x01E, 0x00080000,
2355 0x082, 0x00000830,
2356 0x083, 0x00021800,
2357 0x084, 0x00028000,
2358 0x085, 0x00048000,
2359 0x086, 0x00094838,
2360 0x087, 0x00044980,
2361 0x088, 0x00048000,
2362 0x089, 0x0000D480,
2363 0x08A, 0x00042240,
2364 0x08B, 0x000F0380,
2365 0x08C, 0x00090000,
2366 0x08D, 0x00022852,
2367 0x08E, 0x00065540,
2368 0x08F, 0x00088001,
2369 0x0EF, 0x00020000,
2370 0x03E, 0x00000380,
2371 0x03F, 0x00090018,
2372 0x03E, 0x00020380,
2373 0x03F, 0x000A0018,
2374 0x03E, 0x00040308,
2375 0x03F, 0x000A0018,
2376 0x03E, 0x00060018,
2377 0x03F, 0x000A0018,
2378 0x0EF, 0x00000000,
2379 0x018, 0x0001712A,
2380 0x089, 0x00000080,
2381 0x08B, 0x00080180,
2382 0x0EF, 0x00001000,
2383 0x03A, 0x00000244,
2384 0x03B, 0x00038027,
2385 0x03C, 0x00082000,
2386 0x03A, 0x00000244,
2387 0x03B, 0x00030113,
2388 0x03C, 0x00082000,
2389 0x03A, 0x0000014C,
2390 0x03B, 0x00028027,
2391 0x03C, 0x00082000,
2392 0x03A, 0x000000CC,
2393 0x03B, 0x00027027,
2394 0x03C, 0x00042000,
2395 0x03A, 0x0000014C,
2396 0x03B, 0x0001F913,
2397 0x03C, 0x00042000,
2398 0x03A, 0x0000010C,
2399 0x03B, 0x00017F10,
2400 0x03C, 0x00012000,
2401 0x03A, 0x000000D0,
2402 0x03B, 0x00008027,
2403 0x03C, 0x000CA000,
2404 0x03A, 0x00000244,
2405 0x03B, 0x00078027,
2406 0x03C, 0x00082000,
2407 0x03A, 0x00000244,
2408 0x03B, 0x00070113,
2409 0x03C, 0x00082000,
2410 0x03A, 0x0000014C,
2411 0x03B, 0x00068027,
2412 0x03C, 0x00082000,
2413 0x03A, 0x000000CC,
2414 0x03B, 0x00067027,
2415 0x03C, 0x00042000,
2416 0x03A, 0x0000014C,
2417 0x03B, 0x0005F913,
2418 0x03C, 0x00042000,
2419 0x03A, 0x0000010C,
2420 0x03B, 0x00057F10,
2421 0x03C, 0x00012000,
2422 0x03A, 0x000000D0,
2423 0x03B, 0x00048027,
2424 0x03C, 0x000CA000,
2425 0x03A, 0x00000244,
2426 0x03B, 0x000B8027,
2427 0x03C, 0x00082000,
2428 0x03A, 0x00000244,
2429 0x03B, 0x000B0113,
2430 0x03C, 0x00082000,
2431 0x03A, 0x0000014C,
2432 0x03B, 0x000A8027,
2433 0x03C, 0x00082000,
2434 0x03A, 0x000000CC,
2435 0x03B, 0x000A7027,
2436 0x03C, 0x00042000,
2437 0x03A, 0x0000014C,
2438 0x03B, 0x0009F913,
2439 0x03C, 0x00042000,
2440 0x03A, 0x0000010C,
2441 0x03B, 0x00097F10,
2442 0x03C, 0x00012000,
2443 0x03A, 0x000000D0,
2444 0x03B, 0x00088027,
2445 0x03C, 0x000CA000,
2446 0x0EF, 0x00000000,
2447 0x0EF, 0x00001100,
2448 0xFF0F0104, 0xABCD,
2449 0x034, 0x0004ADF3,
2450 0x034, 0x00049DF0,
2451 0xFF0F0204, 0xCDEF,
2452 0x034, 0x0004ADF3,
2453 0x034, 0x00049DF0,
2454 0xFF0F0404, 0xCDEF,
2455 0x034, 0x0004ADF3,
2456 0x034, 0x00049DF0,
2457 0xFF0F0200, 0xCDEF,
2458 0x034, 0x0004ADF5,
2459 0x034, 0x00049DF2,
2460 0xFF0F02C0, 0xCDEF,
2461 0x034, 0x0004A0F3,
2462 0x034, 0x000490B1,
2463 0xCDCDCDCD, 0xCDCD,
2464 0x034, 0x0004ADF7,
2465 0x034, 0x00049DF3,
2466 0xFF0F0104, 0xDEAD,
2467 0xFF0F0104, 0xABCD,
2468 0x034, 0x00048DED,
2469 0x034, 0x00047DEA,
2470 0x034, 0x00046DE7,
2471 0x034, 0x00045CE9,
2472 0x034, 0x00044CE6,
2473 0x034, 0x000438C6,
2474 0x034, 0x00042886,
2475 0x034, 0x00041486,
2476 0x034, 0x00040447,
2477 0xFF0F0204, 0xCDEF,
2478 0x034, 0x00048DED,
2479 0x034, 0x00047DEA,
2480 0x034, 0x00046DE7,
2481 0x034, 0x00045CE9,
2482 0x034, 0x00044CE6,
2483 0x034, 0x000438C6,
2484 0x034, 0x00042886,
2485 0x034, 0x00041486,
2486 0x034, 0x00040447,
2487 0xFF0F0404, 0xCDEF,
2488 0x034, 0x00048DED,
2489 0x034, 0x00047DEA,
2490 0x034, 0x00046DE7,
2491 0x034, 0x00045CE9,
2492 0x034, 0x00044CE6,
2493 0x034, 0x000438C6,
2494 0x034, 0x00042886,
2495 0x034, 0x00041486,
2496 0x034, 0x00040447,
2497 0xFF0F02C0, 0xCDEF,
2498 0x034, 0x000480AE,
2499 0x034, 0x000470AB,
2500 0x034, 0x0004608B,
2501 0x034, 0x00045069,
2502 0x034, 0x00044048,
2503 0x034, 0x00043045,
2504 0x034, 0x00042026,
2505 0x034, 0x00041023,
2506 0x034, 0x00040002,
2507 0xCDCDCDCD, 0xCDCD,
2508 0x034, 0x00048DEF,
2509 0x034, 0x00047DEC,
2510 0x034, 0x00046DE9,
2511 0x034, 0x00045CCB,
2512 0x034, 0x0004488D,
2513 0x034, 0x0004348D,
2514 0x034, 0x0004248A,
2515 0x034, 0x0004108D,
2516 0x034, 0x0004008A,
2517 0xFF0F0104, 0xDEAD,
2518 0xFF0F0200, 0xABCD,
2519 0x034, 0x0002ADF4,
2520 0xFF0F02C0, 0xCDEF,
2521 0x034, 0x0002A0F3,
2522 0xCDCDCDCD, 0xCDCD,
2523 0x034, 0x0002ADF7,
2524 0xFF0F0200, 0xDEAD,
2525 0xFF0F0104, 0xABCD,
2526 0x034, 0x00029DF4,
2527 0xFF0F0204, 0xCDEF,
2528 0x034, 0x00029DF4,
2529 0xFF0F0404, 0xCDEF,
2530 0x034, 0x00029DF4,
2531 0xFF0F0200, 0xCDEF,
2532 0x034, 0x00029DF1,
2533 0xFF0F02C0, 0xCDEF,
2534 0x034, 0x000290F0,
2535 0xCDCDCDCD, 0xCDCD,
2536 0x034, 0x00029DF2,
2537 0xFF0F0104, 0xDEAD,
2538 0xFF0F0104, 0xABCD,
2539 0x034, 0x00028DF1,
2540 0x034, 0x00027DEE,
2541 0x034, 0x00026DEB,
2542 0x034, 0x00025CEC,
2543 0x034, 0x00024CE9,
2544 0x034, 0x000238CA,
2545 0x034, 0x00022889,
2546 0x034, 0x00021489,
2547 0x034, 0x0002044A,
2548 0xFF0F0204, 0xCDEF,
2549 0x034, 0x00028DF1,
2550 0x034, 0x00027DEE,
2551 0x034, 0x00026DEB,
2552 0x034, 0x00025CEC,
2553 0x034, 0x00024CE9,
2554 0x034, 0x000238CA,
2555 0x034, 0x00022889,
2556 0x034, 0x00021489,
2557 0x034, 0x0002044A,
2558 0xFF0F0404, 0xCDEF,
2559 0x034, 0x00028DF1,
2560 0x034, 0x00027DEE,
2561 0x034, 0x00026DEB,
2562 0x034, 0x00025CEC,
2563 0x034, 0x00024CE9,
2564 0x034, 0x000238CA,
2565 0x034, 0x00022889,
2566 0x034, 0x00021489,
2567 0x034, 0x0002044A,
2568 0xFF0F02C0, 0xCDEF,
2569 0x034, 0x000280AF,
2570 0x034, 0x000270AC,
2571 0x034, 0x0002608B,
2572 0x034, 0x00025069,
2573 0x034, 0x00024048,
2574 0x034, 0x00023045,
2575 0x034, 0x00022026,
2576 0x034, 0x00021023,
2577 0x034, 0x00020002,
2578 0xCDCDCDCD, 0xCDCD,
2579 0x034, 0x00028DEE,
2580 0x034, 0x00027DEB,
2581 0x034, 0x00026CCD,
2582 0x034, 0x00025CCA,
2583 0x034, 0x0002488C,
2584 0x034, 0x0002384C,
2585 0x034, 0x00022849,
2586 0x034, 0x00021449,
2587 0x034, 0x0002004D,
2588 0xFF0F0104, 0xDEAD,
2589 0xFF0F02C0, 0xABCD,
2590 0x034, 0x0000A0D7,
2591 0x034, 0x000090D3,
2592 0x034, 0x000080B1,
2593 0x034, 0x000070AE,
2594 0xCDCDCDCD, 0xCDCD,
2595 0x034, 0x0000ADF7,
2596 0x034, 0x00009DF4,
2597 0x034, 0x00008DF1,
2598 0x034, 0x00007DEE,
2599 0xFF0F02C0, 0xDEAD,
2600 0xFF0F0104, 0xABCD,
2601 0x034, 0x00006DEB,
2602 0x034, 0x00005CEC,
2603 0x034, 0x00004CE9,
2604 0x034, 0x000038CA,
2605 0x034, 0x00002889,
2606 0x034, 0x00001489,
2607 0x034, 0x0000044A,
2608 0xFF0F0204, 0xCDEF,
2609 0x034, 0x00006DEB,
2610 0x034, 0x00005CEC,
2611 0x034, 0x00004CE9,
2612 0x034, 0x000038CA,
2613 0x034, 0x00002889,
2614 0x034, 0x00001489,
2615 0x034, 0x0000044A,
2616 0xFF0F0404, 0xCDEF,
2617 0x034, 0x00006DEB,
2618 0x034, 0x00005CEC,
2619 0x034, 0x00004CE9,
2620 0x034, 0x000038CA,
2621 0x034, 0x00002889,
2622 0x034, 0x00001489,
2623 0x034, 0x0000044A,
2624 0xFF0F02C0, 0xCDEF,
2625 0x034, 0x0000608D,
2626 0x034, 0x0000506B,
2627 0x034, 0x0000404A,
2628 0x034, 0x00003047,
2629 0x034, 0x00002044,
2630 0x034, 0x00001025,
2631 0x034, 0x00000004,
2632 0xCDCDCDCD, 0xCDCD,
2633 0x034, 0x00006DCD,
2634 0x034, 0x00005CCD,
2635 0x034, 0x00004CCA,
2636 0x034, 0x0000388C,
2637 0x034, 0x00002888,
2638 0x034, 0x00001488,
2639 0x034, 0x00000486,
2640 0xFF0F0104, 0xDEAD,
2641 0x0EF, 0x00000000,
2642 0x018, 0x0001712A,
2643 0x0EF, 0x00000040,
2644 0xFF0F0104, 0xABCD,
2645 0x035, 0x00000187,
2646 0x035, 0x00008187,
2647 0x035, 0x00010187,
2648 0x035, 0x00020188,
2649 0x035, 0x00028188,
2650 0x035, 0x00030188,
2651 0x035, 0x00040188,
2652 0x035, 0x00048188,
2653 0x035, 0x00050188,
2654 0xFF0F0204, 0xCDEF,
2655 0x035, 0x00000187,
2656 0x035, 0x00008187,
2657 0x035, 0x00010187,
2658 0x035, 0x00020188,
2659 0x035, 0x00028188,
2660 0x035, 0x00030188,
2661 0x035, 0x00040188,
2662 0x035, 0x00048188,
2663 0x035, 0x00050188,
2664 0xFF0F0404, 0xCDEF,
2665 0x035, 0x00000187,
2666 0x035, 0x00008187,
2667 0x035, 0x00010187,
2668 0x035, 0x00020188,
2669 0x035, 0x00028188,
2670 0x035, 0x00030188,
2671 0x035, 0x00040188,
2672 0x035, 0x00048188,
2673 0x035, 0x00050188,
2674 0xCDCDCDCD, 0xCDCD,
2675 0x035, 0x00000145,
2676 0x035, 0x00008145,
2677 0x035, 0x00010145,
2678 0x035, 0x00020196,
2679 0x035, 0x00028196,
2680 0x035, 0x00030196,
2681 0x035, 0x000401C7,
2682 0x035, 0x000481C7,
2683 0x035, 0x000501C7,
2684 0xFF0F0104, 0xDEAD,
2685 0x0EF, 0x00000000,
2686 0x018, 0x0001712A,
2687 0x0EF, 0x00000010,
2688 0xFF0F0104, 0xABCD,
2689 0x036, 0x00085733,
2690 0x036, 0x0008D733,
2691 0x036, 0x00095733,
2692 0x036, 0x0009D733,
2693 0x036, 0x000A64B4,
2694 0x036, 0x000AE4B4,
2695 0x036, 0x000B64B4,
2696 0x036, 0x000BE4B4,
2697 0x036, 0x000C64B4,
2698 0x036, 0x000CE4B4,
2699 0x036, 0x000D64B4,
2700 0x036, 0x000DE4B4,
2701 0xFF0F0204, 0xCDEF,
2702 0x036, 0x00085733,
2703 0x036, 0x0008D733,
2704 0x036, 0x00095733,
2705 0x036, 0x0009D733,
2706 0x036, 0x000A64B4,
2707 0x036, 0x000AE4B4,
2708 0x036, 0x000B64B4,
2709 0x036, 0x000BE4B4,
2710 0x036, 0x000C64B4,
2711 0x036, 0x000CE4B4,
2712 0x036, 0x000D64B4,
2713 0x036, 0x000DE4B4,
2714 0xFF0F0404, 0xCDEF,
2715 0x036, 0x00085733,
2716 0x036, 0x0008D733,
2717 0x036, 0x00095733,
2718 0x036, 0x0009D733,
2719 0x036, 0x000A64B4,
2720 0x036, 0x000AE4B4,
2721 0x036, 0x000B64B4,
2722 0x036, 0x000BE4B4,
2723 0x036, 0x000C64B4,
2724 0x036, 0x000CE4B4,
2725 0x036, 0x000D64B4,
2726 0x036, 0x000DE4B4,
2727 0xCDCDCDCD, 0xCDCD,
2728 0x036, 0x000056B3,
2729 0x036, 0x0000D6B3,
2730 0x036, 0x000156B3,
2731 0x036, 0x0001D6B3,
2732 0x036, 0x00026634,
2733 0x036, 0x0002E634,
2734 0x036, 0x00036634,
2735 0x036, 0x0003E634,
2736 0x036, 0x000467B4,
2737 0x036, 0x0004E7B4,
2738 0x036, 0x000567B4,
2739 0x036, 0x0005E7B4,
2740 0xFF0F0104, 0xDEAD,
2741 0x0EF, 0x00000000,
2742 0x0EF, 0x00000008,
2743 0xFF0F0104, 0xABCD,
2744 0x03C, 0x000001C8,
2745 0x03C, 0x00000492,
2746 0xFF0F0204, 0xCDEF,
2747 0x03C, 0x000001C8,
2748 0x03C, 0x00000492,
2749 0xFF0F0404, 0xCDEF,
2750 0x03C, 0x000001C8,
2751 0x03C, 0x00000492,
2752 0xCDCDCDCD, 0xCDCD,
2753 0x03C, 0x0000022A,
2754 0x03C, 0x00000594,
2755 0xFF0F0104, 0xDEAD,
2756 0xFF0F0104, 0xABCD,
2757 0x03C, 0x00000800,
2758 0xFF0F0204, 0xCDEF,
2759 0x03C, 0x00000800,
2760 0xFF0F0404, 0xCDEF,
2761 0x03C, 0x00000800,
2762 0xFF0F02C0, 0xCDEF,
2763 0x03C, 0x00000820,
2764 0xCDCDCDCD, 0xCDCD,
2765 0x03C, 0x00000900,
2766 0xFF0F0104, 0xDEAD,
2767 0x0EF, 0x00000000,
2768 0x018, 0x0001712A,
2769 0x0EF, 0x00000002,
2770 0xFF0F0104, 0xABCD,
2771 0x008, 0x0004E400,
2772 0xFF0F0204, 0xCDEF,
2773 0x008, 0x0004E400,
2774 0xFF0F0404, 0xCDEF,
2775 0x008, 0x0004E400,
2776 0xCDCDCDCD, 0xCDCD,
2777 0x008, 0x00002000,
2778 0xFF0F0104, 0xDEAD,
2779 0x0EF, 0x00000000,
2780 0x0DF, 0x000000C0,
2781 0x01F, 0x00040064,
2782 0xFF0F0104, 0xABCD,
2783 0x058, 0x000A7284,
2784 0x059, 0x000600EC,
2785 0xFF0F0204, 0xCDEF,
2786 0x058, 0x000A7284,
2787 0x059, 0x000600EC,
2788 0xFF0F0404, 0xCDEF,
2789 0x058, 0x000A7284,
2790 0x059, 0x000600EC,
2791 0xCDCDCDCD, 0xCDCD,
2792 0x058, 0x00081184,
2793 0x059, 0x0006016C,
2794 0xFF0F0104, 0xDEAD,
2795 0xFF0F0104, 0xABCD,
2796 0x061, 0x000E8D73,
2797 0x062, 0x00093FC5,
2798 0xFF0F0204, 0xCDEF,
2799 0x061, 0x000E8D73,
2800 0x062, 0x00093FC5,
2801 0xFF0F0404, 0xCDEF,
2802 0x061, 0x000E8D73,
2803 0x062, 0x00093FC5,
2804 0xCDCDCDCD, 0xCDCD,
2805 0x061, 0x000EAD53,
2806 0x062, 0x00093BC4,
2807 0xFF0F0104, 0xDEAD,
2808 0xFF0F0104, 0xABCD,
2809 0x063, 0x000110E9,
2810 0xFF0F0204, 0xCDEF,
2811 0x063, 0x000110E9,
2812 0xFF0F0404, 0xCDEF,
2813 0x063, 0x000110E9,
2814 0xFF0F0200, 0xCDEF,
2815 0x063, 0x000710E9,
2816 0xFF0F02C0, 0xCDEF,
2817 0x063, 0x000110E9,
2818 0xCDCDCDCD, 0xCDCD,
2819 0x063, 0x000714E9,
2820 0xFF0F0104, 0xDEAD,
2821 0xFF0F0104, 0xABCD,
2822 0x064, 0x0001C27C,
2823 0xFF0F0204, 0xCDEF,
2824 0x064, 0x0001C27C,
2825 0xFF0F0404, 0xCDEF,
2826 0x064, 0x0001C27C,
2827 0xCDCDCDCD, 0xCDCD,
2828 0x064, 0x0001C67C,
2829 0xFF0F0104, 0xDEAD,
2830 0xFF0F0200, 0xABCD,
2831 0x065, 0x00093016,
2832 0xFF0F02C0, 0xCDEF,
2833 0x065, 0x00093015,
2834 0xCDCDCDCD, 0xCDCD,
2835 0x065, 0x00091016,
2836 0xFF0F0200, 0xDEAD,
2837 0x018, 0x00000006,
2838 0x0EF, 0x00002000,
2839 0x03B, 0x0003824B,
2840 0x03B, 0x0003024B,
2841 0x03B, 0x0002844B,
2842 0x03B, 0x00020F4B,
2843 0x03B, 0x00018F4B,
2844 0x03B, 0x000104B2,
2845 0x03B, 0x00008049,
2846 0x03B, 0x00000148,
2847 0x03B, 0x0007824B,
2848 0x03B, 0x0007024B,
2849 0x03B, 0x0006824B,
2850 0x03B, 0x00060F4B,
2851 0x03B, 0x00058F4B,
2852 0x03B, 0x000504B2,
2853 0x03B, 0x00048049,
2854 0x03B, 0x00040148,
2855 0x0EF, 0x00000000,
2856 0x0EF, 0x00000100,
2857 0x034, 0x0000ADF3,
2858 0x034, 0x00009DEF,
2859 0x034, 0x00008DEC,
2860 0x034, 0x00007DE9,
2861 0x034, 0x00006CED,
2862 0x034, 0x00005CE9,
2863 0x034, 0x000044E9,
2864 0x034, 0x000034E6,
2865 0x034, 0x0000246A,
2866 0x034, 0x00001467,
2867 0x034, 0x00000068,
2868 0x0EF, 0x00000000,
2869 0x0ED, 0x00000010,
2870 0x044, 0x0000ADF2,
2871 0x044, 0x00009DEF,
2872 0x044, 0x00008DEC,
2873 0x044, 0x00007DE9,
2874 0x044, 0x00006CEC,
2875 0x044, 0x00005CE9,
2876 0x044, 0x000044EC,
2877 0x044, 0x000034E9,
2878 0x044, 0x0000246C,
2879 0x044, 0x00001469,
2880 0x044, 0x0000006C,
2881 0x0ED, 0x00000000,
2882 0x0ED, 0x00000001,
2883 0x040, 0x00038DA7,
2884 0x040, 0x000300C2,
2885 0x040, 0x000288E2,
2886 0x040, 0x000200B8,
2887 0x040, 0x000188A5,
2888 0x040, 0x00010FBC,
2889 0x040, 0x00008F71,
2890 0x040, 0x00000240,
2891 0x0ED, 0x00000000,
2892 0x0EF, 0x000020A2,
2893 0x0DF, 0x00000080,
2894 0x035, 0x00000120,
2895 0x035, 0x00008120,
2896 0x035, 0x00010120,
2897 0x036, 0x00000085,
2898 0x036, 0x00008085,
2899 0x036, 0x00010085,
2900 0x036, 0x00018085,
2901 0x0EF, 0x00000000,
2902 0x051, 0x00000C31,
2903 0x052, 0x00000622,
2904 0x053, 0x000FC70B,
2905 0x054, 0x0000017E,
2906 0x056, 0x00051DF3,
2907 0x051, 0x00000C01,
2908 0x052, 0x000006D6,
2909 0x053, 0x000FC649,
2910 0x070, 0x00049661,
2911 0x071, 0x0007843E,
2912 0x072, 0x00000382,
2913 0x074, 0x00051400,
2914 0x035, 0x00000160,
2915 0x035, 0x00008160,
2916 0x035, 0x00010160,
2917 0x036, 0x00000124,
2918 0x036, 0x00008124,
2919 0x036, 0x00010124,
2920 0x036, 0x00018124,
2921 0x0ED, 0x0000000C,
2922 0x045, 0x00000140,
2923 0x045, 0x00008140,
2924 0x045, 0x00010140,
2925 0x046, 0x00000124,
2926 0x046, 0x00008124,
2927 0x046, 0x00010124,
2928 0x046, 0x00018124,
2929 0x0DF, 0x00000088,
2930 0x0B3, 0x000F0E18,
2931 0x0B4, 0x0001214C,
2932 0x0B7, 0x0003000C,
2933 0x01C, 0x000539D2,
2934 0x018, 0x0001F12A,
2935 0x0FE, 0x00000000,
2936 0x0FE, 0x00000000,
2937 0x018, 0x0001712A,
2938};
2939
2940u32 RTL8812AE_MAC_REG_ARRAY[] = {
2941 0x010, 0x0000000C,
2942 0xFF0F0180, 0xABCD,
2943 0x025, 0x0000000F,
2944 0xFF0F01C0, 0xCDEF,
2945 0x025, 0x0000000F,
2946 0xCDCDCDCD, 0xCDCD,
2947 0x025, 0x0000006F,
2948 0xFF0F0180, 0xDEAD,
2949 0x072, 0x00000000,
2950 0x428, 0x0000000A,
2951 0x429, 0x00000010,
2952 0x430, 0x00000000,
2953 0x431, 0x00000000,
2954 0x432, 0x00000000,
2955 0x433, 0x00000001,
2956 0x434, 0x00000004,
2957 0x435, 0x00000005,
2958 0x436, 0x00000007,
2959 0x437, 0x00000008,
2960 0x43C, 0x00000004,
2961 0x43D, 0x00000005,
2962 0x43E, 0x00000007,
2963 0x43F, 0x00000008,
2964 0x440, 0x0000005D,
2965 0x441, 0x00000001,
2966 0x442, 0x00000000,
2967 0x444, 0x00000010,
2968 0x445, 0x00000000,
2969 0x446, 0x00000000,
2970 0x447, 0x00000000,
2971 0x448, 0x00000000,
2972 0x449, 0x000000F0,
2973 0x44A, 0x0000000F,
2974 0x44B, 0x0000003E,
2975 0x44C, 0x00000010,
2976 0x44D, 0x00000000,
2977 0x44E, 0x00000000,
2978 0x44F, 0x00000000,
2979 0x450, 0x00000000,
2980 0x451, 0x000000F0,
2981 0x452, 0x0000000F,
2982 0x453, 0x00000000,
2983 0x45B, 0x00000080,
2984 0x460, 0x00000066,
2985 0x461, 0x00000066,
2986 0x4C8, 0x000000FF,
2987 0x4C9, 0x00000008,
2988 0x4CC, 0x000000FF,
2989 0x4CD, 0x000000FF,
2990 0x4CE, 0x00000001,
2991 0x500, 0x00000026,
2992 0x501, 0x000000A2,
2993 0x502, 0x0000002F,
2994 0x503, 0x00000000,
2995 0x504, 0x00000028,
2996 0x505, 0x000000A3,
2997 0x506, 0x0000005E,
2998 0x507, 0x00000000,
2999 0x508, 0x0000002B,
3000 0x509, 0x000000A4,
3001 0x50A, 0x0000005E,
3002 0x50B, 0x00000000,
3003 0x50C, 0x0000004F,
3004 0x50D, 0x000000A4,
3005 0x50E, 0x00000000,
3006 0x50F, 0x00000000,
3007 0x512, 0x0000001C,
3008 0x514, 0x0000000A,
3009 0x516, 0x0000000A,
3010 0x525, 0x0000004F,
3011 0x550, 0x00000010,
3012 0x551, 0x00000010,
3013 0x559, 0x00000002,
3014 0x55C, 0x00000050,
3015 0x55D, 0x000000FF,
3016 0x604, 0x00000001,
3017 0x605, 0x00000030,
3018 0x607, 0x00000003,
3019 0x608, 0x0000000E,
3020 0x609, 0x0000002A,
3021 0x620, 0x000000FF,
3022 0x621, 0x000000FF,
3023 0x622, 0x000000FF,
3024 0x623, 0x000000FF,
3025 0x624, 0x000000FF,
3026 0x625, 0x000000FF,
3027 0x626, 0x000000FF,
3028 0x627, 0x000000FF,
3029 0x638, 0x00000050,
3030 0x63C, 0x0000000A,
3031 0x63D, 0x0000000A,
3032 0x63E, 0x0000000E,
3033 0x63F, 0x0000000E,
3034 0x640, 0x00000080,
3035 0x642, 0x00000040,
3036 0x643, 0x00000000,
3037 0x652, 0x000000C8,
3038 0x66E, 0x00000005,
3039 0x700, 0x00000021,
3040 0x701, 0x00000043,
3041 0x702, 0x00000065,
3042 0x703, 0x00000087,
3043 0x708, 0x00000021,
3044 0x709, 0x00000043,
3045 0x70A, 0x00000065,
3046 0x70B, 0x00000087,
3047 0x718, 0x00000040,
3048};
3049
3050u32 RTL8821AE_MAC_REG_ARRAY[] = {
3051 0x428, 0x0000000A,
3052 0x429, 0x00000010,
3053 0x430, 0x00000000,
3054 0x431, 0x00000000,
3055 0x432, 0x00000000,
3056 0x433, 0x00000001,
3057 0x434, 0x00000004,
3058 0x435, 0x00000005,
3059 0x436, 0x00000007,
3060 0x437, 0x00000008,
3061 0x43C, 0x00000004,
3062 0x43D, 0x00000005,
3063 0x43E, 0x00000007,
3064 0x43F, 0x00000008,
3065 0x440, 0x0000005D,
3066 0x441, 0x00000001,
3067 0x442, 0x00000000,
3068 0x444, 0x00000010,
3069 0x445, 0x00000000,
3070 0x446, 0x00000000,
3071 0x447, 0x00000000,
3072 0x448, 0x00000000,
3073 0x449, 0x000000F0,
3074 0x44A, 0x0000000F,
3075 0x44B, 0x0000003E,
3076 0x44C, 0x00000010,
3077 0x44D, 0x00000000,
3078 0x44E, 0x00000000,
3079 0x44F, 0x00000000,
3080 0x450, 0x00000000,
3081 0x451, 0x000000F0,
3082 0x452, 0x0000000F,
3083 0x453, 0x00000000,
3084 0x456, 0x0000005E,
3085 0x460, 0x00000066,
3086 0x461, 0x00000066,
3087 0x4C8, 0x0000003F,
3088 0x4C9, 0x000000FF,
3089 0x4CC, 0x000000FF,
3090 0x4CD, 0x000000FF,
3091 0x4CE, 0x00000001,
3092 0x500, 0x00000026,
3093 0x501, 0x000000A2,
3094 0x502, 0x0000002F,
3095 0x503, 0x00000000,
3096 0x504, 0x00000028,
3097 0x505, 0x000000A3,
3098 0x506, 0x0000005E,
3099 0x507, 0x00000000,
3100 0x508, 0x0000002B,
3101 0x509, 0x000000A4,
3102 0x50A, 0x0000005E,
3103 0x50B, 0x00000000,
3104 0x50C, 0x0000004F,
3105 0x50D, 0x000000A4,
3106 0x50E, 0x00000000,
3107 0x50F, 0x00000000,
3108 0x512, 0x0000001C,
3109 0x514, 0x0000000A,
3110 0x516, 0x0000000A,
3111 0x525, 0x0000004F,
3112 0x550, 0x00000010,
3113 0x551, 0x00000010,
3114 0x559, 0x00000002,
3115 0x55C, 0x00000050,
3116 0x55D, 0x000000FF,
3117 0x605, 0x00000030,
3118 0x607, 0x00000007,
3119 0x608, 0x0000000E,
3120 0x609, 0x0000002A,
3121 0x620, 0x000000FF,
3122 0x621, 0x000000FF,
3123 0x622, 0x000000FF,
3124 0x623, 0x000000FF,
3125 0x624, 0x000000FF,
3126 0x625, 0x000000FF,
3127 0x626, 0x000000FF,
3128 0x627, 0x000000FF,
3129 0x638, 0x00000050,
3130 0x63C, 0x0000000A,
3131 0x63D, 0x0000000A,
3132 0x63E, 0x0000000E,
3133 0x63F, 0x0000000E,
3134 0x640, 0x00000040,
3135 0x642, 0x00000040,
3136 0x643, 0x00000000,
3137 0x652, 0x000000C8,
3138 0x66E, 0x00000005,
3139 0x700, 0x00000021,
3140 0x701, 0x00000043,
3141 0x702, 0x00000065,
3142 0x703, 0x00000087,
3143 0x708, 0x00000021,
3144 0x709, 0x00000043,
3145 0x70A, 0x00000065,
3146 0x70B, 0x00000087,
3147 0x718, 0x00000040,
3148};
3149
3150u32 RTL8812AE_AGC_TAB_ARRAY[] = {
3151 0xFF0F07D8, 0xABCD,
3152 0x81C, 0xFC000001,
3153 0x81C, 0xFB020001,
3154 0x81C, 0xFA040001,
3155 0x81C, 0xF9060001,
3156 0x81C, 0xF8080001,
3157 0x81C, 0xF70A0001,
3158 0x81C, 0xF60C0001,
3159 0x81C, 0xF50E0001,
3160 0x81C, 0xF4100001,
3161 0x81C, 0xF3120001,
3162 0x81C, 0xF2140001,
3163 0x81C, 0xF1160001,
3164 0x81C, 0xF0180001,
3165 0x81C, 0xEF1A0001,
3166 0x81C, 0xEE1C0001,
3167 0x81C, 0xED1E0001,
3168 0x81C, 0xEC200001,
3169 0x81C, 0xEB220001,
3170 0x81C, 0xEA240001,
3171 0x81C, 0xCD260001,
3172 0x81C, 0xCC280001,
3173 0x81C, 0xCB2A0001,
3174 0x81C, 0xCA2C0001,
3175 0x81C, 0xC92E0001,
3176 0x81C, 0xC8300001,
3177 0x81C, 0xA6320001,
3178 0x81C, 0xA5340001,
3179 0x81C, 0xA4360001,
3180 0x81C, 0xA3380001,
3181 0x81C, 0xA23A0001,
3182 0x81C, 0x883C0001,
3183 0x81C, 0x873E0001,
3184 0x81C, 0x86400001,
3185 0x81C, 0x85420001,
3186 0x81C, 0x84440001,
3187 0x81C, 0x83460001,
3188 0x81C, 0x82480001,
3189 0x81C, 0x814A0001,
3190 0x81C, 0x484C0001,
3191 0x81C, 0x474E0001,
3192 0x81C, 0x46500001,
3193 0x81C, 0x45520001,
3194 0x81C, 0x44540001,
3195 0x81C, 0x43560001,
3196 0x81C, 0x42580001,
3197 0x81C, 0x415A0001,
3198 0x81C, 0x255C0001,
3199 0x81C, 0x245E0001,
3200 0x81C, 0x23600001,
3201 0x81C, 0x22620001,
3202 0x81C, 0x21640001,
3203 0x81C, 0x21660001,
3204 0x81C, 0x21680001,
3205 0x81C, 0x216A0001,
3206 0x81C, 0x216C0001,
3207 0x81C, 0x216E0001,
3208 0x81C, 0x21700001,
3209 0x81C, 0x21720001,
3210 0x81C, 0x21740001,
3211 0x81C, 0x21760001,
3212 0x81C, 0x21780001,
3213 0x81C, 0x217A0001,
3214 0x81C, 0x217C0001,
3215 0x81C, 0x217E0001,
3216 0xFF0F07D0, 0xCDEF,
3217 0x81C, 0xF9000001,
3218 0x81C, 0xF8020001,
3219 0x81C, 0xF7040001,
3220 0x81C, 0xF6060001,
3221 0x81C, 0xF5080001,
3222 0x81C, 0xF40A0001,
3223 0x81C, 0xF30C0001,
3224 0x81C, 0xF20E0001,
3225 0x81C, 0xF1100001,
3226 0x81C, 0xF0120001,
3227 0x81C, 0xEF140001,
3228 0x81C, 0xEE160001,
3229 0x81C, 0xED180001,
3230 0x81C, 0xEC1A0001,
3231 0x81C, 0xEB1C0001,
3232 0x81C, 0xEA1E0001,
3233 0x81C, 0xCD200001,
3234 0x81C, 0xCC220001,
3235 0x81C, 0xCB240001,
3236 0x81C, 0xCA260001,
3237 0x81C, 0xC9280001,
3238 0x81C, 0xC82A0001,
3239 0x81C, 0xC72C0001,
3240 0x81C, 0xC62E0001,
3241 0x81C, 0xA5300001,
3242 0x81C, 0xA4320001,
3243 0x81C, 0xA3340001,
3244 0x81C, 0xA2360001,
3245 0x81C, 0x88380001,
3246 0x81C, 0x873A0001,
3247 0x81C, 0x863C0001,
3248 0x81C, 0x853E0001,
3249 0x81C, 0x84400001,
3250 0x81C, 0x83420001,
3251 0x81C, 0x82440001,
3252 0x81C, 0x81460001,
3253 0x81C, 0x48480001,
3254 0x81C, 0x474A0001,
3255 0x81C, 0x464C0001,
3256 0x81C, 0x454E0001,
3257 0x81C, 0x44500001,
3258 0x81C, 0x43520001,
3259 0x81C, 0x42540001,
3260 0x81C, 0x41560001,
3261 0x81C, 0x25580001,
3262 0x81C, 0x245A0001,
3263 0x81C, 0x235C0001,
3264 0x81C, 0x225E0001,
3265 0x81C, 0x21600001,
3266 0x81C, 0x21620001,
3267 0x81C, 0x21640001,
3268 0x81C, 0x21660001,
3269 0x81C, 0x21680001,
3270 0x81C, 0x216A0001,
3271 0x81C, 0x236C0001,
3272 0x81C, 0x226E0001,
3273 0x81C, 0x21700001,
3274 0x81C, 0x21720001,
3275 0x81C, 0x21740001,
3276 0x81C, 0x21760001,
3277 0x81C, 0x21780001,
3278 0x81C, 0x217A0001,
3279 0x81C, 0x217C0001,
3280 0x81C, 0x217E0001,
3281 0xCDCDCDCD, 0xCDCD,
3282 0x81C, 0xFF000001,
3283 0x81C, 0xFF020001,
3284 0x81C, 0xFF040001,
3285 0x81C, 0xFF060001,
3286 0x81C, 0xFF080001,
3287 0x81C, 0xFE0A0001,
3288 0x81C, 0xFD0C0001,
3289 0x81C, 0xFC0E0001,
3290 0x81C, 0xFB100001,
3291 0x81C, 0xFA120001,
3292 0x81C, 0xF9140001,
3293 0x81C, 0xF8160001,
3294 0x81C, 0xF7180001,
3295 0x81C, 0xF61A0001,
3296 0x81C, 0xF51C0001,
3297 0x81C, 0xF41E0001,
3298 0x81C, 0xF3200001,
3299 0x81C, 0xF2220001,
3300 0x81C, 0xF1240001,
3301 0x81C, 0xF0260001,
3302 0x81C, 0xEF280001,
3303 0x81C, 0xEE2A0001,
3304 0x81C, 0xED2C0001,
3305 0x81C, 0xEC2E0001,
3306 0x81C, 0xEB300001,
3307 0x81C, 0xEA320001,
3308 0x81C, 0xE9340001,
3309 0x81C, 0xE8360001,
3310 0x81C, 0xE7380001,
3311 0x81C, 0xE63A0001,
3312 0x81C, 0xE53C0001,
3313 0x81C, 0xC73E0001,
3314 0x81C, 0xC6400001,
3315 0x81C, 0xC5420001,
3316 0x81C, 0xC4440001,
3317 0x81C, 0xC3460001,
3318 0x81C, 0xC2480001,
3319 0x81C, 0xC14A0001,
3320 0x81C, 0xA74C0001,
3321 0x81C, 0xA64E0001,
3322 0x81C, 0xA5500001,
3323 0x81C, 0xA4520001,
3324 0x81C, 0xA3540001,
3325 0x81C, 0xA2560001,
3326 0x81C, 0xA1580001,
3327 0x81C, 0x675A0001,
3328 0x81C, 0x665C0001,
3329 0x81C, 0x655E0001,
3330 0x81C, 0x64600001,
3331 0x81C, 0x63620001,
3332 0x81C, 0x48640001,
3333 0x81C, 0x47660001,
3334 0x81C, 0x46680001,
3335 0x81C, 0x456A0001,
3336 0x81C, 0x446C0001,
3337 0x81C, 0x436E0001,
3338 0x81C, 0x42700001,
3339 0x81C, 0x41720001,
3340 0x81C, 0x41740001,
3341 0x81C, 0x41760001,
3342 0x81C, 0x41780001,
3343 0x81C, 0x417A0001,
3344 0x81C, 0x417C0001,
3345 0x81C, 0x417E0001,
3346 0xFF0F07D8, 0xDEAD,
3347 0xFF0F0180, 0xABCD,
3348 0x81C, 0xFC800001,
3349 0x81C, 0xFB820001,
3350 0x81C, 0xFA840001,
3351 0x81C, 0xF9860001,
3352 0x81C, 0xF8880001,
3353 0x81C, 0xF78A0001,
3354 0x81C, 0xF68C0001,
3355 0x81C, 0xF58E0001,
3356 0x81C, 0xF4900001,
3357 0x81C, 0xF3920001,
3358 0x81C, 0xF2940001,
3359 0x81C, 0xF1960001,
3360 0x81C, 0xF0980001,
3361 0x81C, 0xEF9A0001,
3362 0x81C, 0xEE9C0001,
3363 0x81C, 0xED9E0001,
3364 0x81C, 0xECA00001,
3365 0x81C, 0xEBA20001,
3366 0x81C, 0xEAA40001,
3367 0x81C, 0xE9A60001,
3368 0x81C, 0xE8A80001,
3369 0x81C, 0xE7AA0001,
3370 0x81C, 0xE6AC0001,
3371 0x81C, 0xE5AE0001,
3372 0x81C, 0xE4B00001,
3373 0x81C, 0xE3B20001,
3374 0x81C, 0xA8B40001,
3375 0x81C, 0xA7B60001,
3376 0x81C, 0xA6B80001,
3377 0x81C, 0xA5BA0001,
3378 0x81C, 0xA4BC0001,
3379 0x81C, 0xA3BE0001,
3380 0x81C, 0xA2C00001,
3381 0x81C, 0xA1C20001,
3382 0x81C, 0x68C40001,
3383 0x81C, 0x67C60001,
3384 0x81C, 0x66C80001,
3385 0x81C, 0x65CA0001,
3386 0x81C, 0x64CC0001,
3387 0x81C, 0x47CE0001,
3388 0x81C, 0x46D00001,
3389 0x81C, 0x45D20001,
3390 0x81C, 0x44D40001,
3391 0x81C, 0x43D60001,
3392 0x81C, 0x42D80001,
3393 0x81C, 0x08DA0001,
3394 0x81C, 0x07DC0001,
3395 0x81C, 0x06DE0001,
3396 0x81C, 0x05E00001,
3397 0x81C, 0x04E20001,
3398 0x81C, 0x03E40001,
3399 0x81C, 0x02E60001,
3400 0x81C, 0x01E80001,
3401 0x81C, 0x01EA0001,
3402 0x81C, 0x01EC0001,
3403 0x81C, 0x01EE0001,
3404 0x81C, 0x01F00001,
3405 0x81C, 0x01F20001,
3406 0x81C, 0x01F40001,
3407 0x81C, 0x01F60001,
3408 0x81C, 0x01F80001,
3409 0x81C, 0x01FA0001,
3410 0x81C, 0x01FC0001,
3411 0x81C, 0x01FE0001,
3412 0xFF0F0280, 0xCDEF,
3413 0x81C, 0xFC800001,
3414 0x81C, 0xFB820001,
3415 0x81C, 0xFA840001,
3416 0x81C, 0xF9860001,
3417 0x81C, 0xF8880001,
3418 0x81C, 0xF78A0001,
3419 0x81C, 0xF68C0001,
3420 0x81C, 0xF58E0001,
3421 0x81C, 0xF4900001,
3422 0x81C, 0xF3920001,
3423 0x81C, 0xF2940001,
3424 0x81C, 0xF1960001,
3425 0x81C, 0xF0980001,
3426 0x81C, 0xEF9A0001,
3427 0x81C, 0xEE9C0001,
3428 0x81C, 0xED9E0001,
3429 0x81C, 0xECA00001,
3430 0x81C, 0xEBA20001,
3431 0x81C, 0xEAA40001,
3432 0x81C, 0xE9A60001,
3433 0x81C, 0xE8A80001,
3434 0x81C, 0xE7AA0001,
3435 0x81C, 0xE6AC0001,
3436 0x81C, 0xE5AE0001,
3437 0x81C, 0xE4B00001,
3438 0x81C, 0xE3B20001,
3439 0x81C, 0xA8B40001,
3440 0x81C, 0xA7B60001,
3441 0x81C, 0xA6B80001,
3442 0x81C, 0xA5BA0001,
3443 0x81C, 0xA4BC0001,
3444 0x81C, 0xA3BE0001,
3445 0x81C, 0xA2C00001,
3446 0x81C, 0xA1C20001,
3447 0x81C, 0x68C40001,
3448 0x81C, 0x67C60001,
3449 0x81C, 0x66C80001,
3450 0x81C, 0x65CA0001,
3451 0x81C, 0x64CC0001,
3452 0x81C, 0x47CE0001,
3453 0x81C, 0x46D00001,
3454 0x81C, 0x45D20001,
3455 0x81C, 0x44D40001,
3456 0x81C, 0x43D60001,
3457 0x81C, 0x42D80001,
3458 0x81C, 0x08DA0001,
3459 0x81C, 0x07DC0001,
3460 0x81C, 0x06DE0001,
3461 0x81C, 0x05E00001,
3462 0x81C, 0x04E20001,
3463 0x81C, 0x03E40001,
3464 0x81C, 0x02E60001,
3465 0x81C, 0x01E80001,
3466 0x81C, 0x01EA0001,
3467 0x81C, 0x01EC0001,
3468 0x81C, 0x01EE0001,
3469 0x81C, 0x01F00001,
3470 0x81C, 0x01F20001,
3471 0x81C, 0x01F40001,
3472 0x81C, 0x01F60001,
3473 0x81C, 0x01F80001,
3474 0x81C, 0x01FA0001,
3475 0x81C, 0x01FC0001,
3476 0x81C, 0x01FE0001,
3477 0xFF0F01C0, 0xCDEF,
3478 0x81C, 0xFC800001,
3479 0x81C, 0xFB820001,
3480 0x81C, 0xFA840001,
3481 0x81C, 0xF9860001,
3482 0x81C, 0xF8880001,
3483 0x81C, 0xF78A0001,
3484 0x81C, 0xF68C0001,
3485 0x81C, 0xF58E0001,
3486 0x81C, 0xF4900001,
3487 0x81C, 0xF3920001,
3488 0x81C, 0xF2940001,
3489 0x81C, 0xF1960001,
3490 0x81C, 0xF0980001,
3491 0x81C, 0xEF9A0001,
3492 0x81C, 0xEE9C0001,
3493 0x81C, 0xED9E0001,
3494 0x81C, 0xECA00001,
3495 0x81C, 0xEBA20001,
3496 0x81C, 0xEAA40001,
3497 0x81C, 0xE9A60001,
3498 0x81C, 0xE8A80001,
3499 0x81C, 0xE7AA0001,
3500 0x81C, 0xE6AC0001,
3501 0x81C, 0xE5AE0001,
3502 0x81C, 0xE4B00001,
3503 0x81C, 0xE3B20001,
3504 0x81C, 0xA8B40001,
3505 0x81C, 0xA7B60001,
3506 0x81C, 0xA6B80001,
3507 0x81C, 0xA5BA0001,
3508 0x81C, 0xA4BC0001,
3509 0x81C, 0xA3BE0001,
3510 0x81C, 0xA2C00001,
3511 0x81C, 0xA1C20001,
3512 0x81C, 0x68C40001,
3513 0x81C, 0x67C60001,
3514 0x81C, 0x66C80001,
3515 0x81C, 0x65CA0001,
3516 0x81C, 0x64CC0001,
3517 0x81C, 0x47CE0001,
3518 0x81C, 0x46D00001,
3519 0x81C, 0x45D20001,
3520 0x81C, 0x44D40001,
3521 0x81C, 0x43D60001,
3522 0x81C, 0x42D80001,
3523 0x81C, 0x08DA0001,
3524 0x81C, 0x07DC0001,
3525 0x81C, 0x06DE0001,
3526 0x81C, 0x05E00001,
3527 0x81C, 0x04E20001,
3528 0x81C, 0x03E40001,
3529 0x81C, 0x02E60001,
3530 0x81C, 0x01E80001,
3531 0x81C, 0x01EA0001,
3532 0x81C, 0x01EC0001,
3533 0x81C, 0x01EE0001,
3534 0x81C, 0x01F00001,
3535 0x81C, 0x01F20001,
3536 0x81C, 0x01F40001,
3537 0x81C, 0x01F60001,
3538 0x81C, 0x01F80001,
3539 0x81C, 0x01FA0001,
3540 0x81C, 0x01FC0001,
3541 0x81C, 0x01FE0001,
3542 0xFF0F02C0, 0xCDEF,
3543 0x81C, 0xFC800001,
3544 0x81C, 0xFB820001,
3545 0x81C, 0xFA840001,
3546 0x81C, 0xF9860001,
3547 0x81C, 0xF8880001,
3548 0x81C, 0xF78A0001,
3549 0x81C, 0xF68C0001,
3550 0x81C, 0xF58E0001,
3551 0x81C, 0xF4900001,
3552 0x81C, 0xF3920001,
3553 0x81C, 0xF2940001,
3554 0x81C, 0xF1960001,
3555 0x81C, 0xF0980001,
3556 0x81C, 0xEF9A0001,
3557 0x81C, 0xEE9C0001,
3558 0x81C, 0xED9E0001,
3559 0x81C, 0xECA00001,
3560 0x81C, 0xEBA20001,
3561 0x81C, 0xEAA40001,
3562 0x81C, 0xE9A60001,
3563 0x81C, 0xE8A80001,
3564 0x81C, 0xE7AA0001,
3565 0x81C, 0xE6AC0001,
3566 0x81C, 0xE5AE0001,
3567 0x81C, 0xE4B00001,
3568 0x81C, 0xE3B20001,
3569 0x81C, 0xA8B40001,
3570 0x81C, 0xA7B60001,
3571 0x81C, 0xA6B80001,
3572 0x81C, 0xA5BA0001,
3573 0x81C, 0xA4BC0001,
3574 0x81C, 0xA3BE0001,
3575 0x81C, 0xA2C00001,
3576 0x81C, 0xA1C20001,
3577 0x81C, 0x68C40001,
3578 0x81C, 0x67C60001,
3579 0x81C, 0x66C80001,
3580 0x81C, 0x65CA0001,
3581 0x81C, 0x64CC0001,
3582 0x81C, 0x47CE0001,
3583 0x81C, 0x46D00001,
3584 0x81C, 0x45D20001,
3585 0x81C, 0x44D40001,
3586 0x81C, 0x43D60001,
3587 0x81C, 0x42D80001,
3588 0x81C, 0x08DA0001,
3589 0x81C, 0x07DC0001,
3590 0x81C, 0x06DE0001,
3591 0x81C, 0x05E00001,
3592 0x81C, 0x04E20001,
3593 0x81C, 0x03E40001,
3594 0x81C, 0x02E60001,
3595 0x81C, 0x01E80001,
3596 0x81C, 0x01EA0001,
3597 0x81C, 0x01EC0001,
3598 0x81C, 0x01EE0001,
3599 0x81C, 0x01F00001,
3600 0x81C, 0x01F20001,
3601 0x81C, 0x01F40001,
3602 0x81C, 0x01F60001,
3603 0x81C, 0x01F80001,
3604 0x81C, 0x01FA0001,
3605 0x81C, 0x01FC0001,
3606 0x81C, 0x01FE0001,
3607 0xFF0F07D8, 0xCDEF,
3608 0x81C, 0xFC800001,
3609 0x81C, 0xFB820001,
3610 0x81C, 0xFA840001,
3611 0x81C, 0xF9860001,
3612 0x81C, 0xF8880001,
3613 0x81C, 0xF78A0001,
3614 0x81C, 0xF68C0001,
3615 0x81C, 0xF58E0001,
3616 0x81C, 0xF4900001,
3617 0x81C, 0xF3920001,
3618 0x81C, 0xF2940001,
3619 0x81C, 0xF1960001,
3620 0x81C, 0xF0980001,
3621 0x81C, 0xEF9A0001,
3622 0x81C, 0xEE9C0001,
3623 0x81C, 0xED9E0001,
3624 0x81C, 0xECA00001,
3625 0x81C, 0xEBA20001,
3626 0x81C, 0xEAA40001,
3627 0x81C, 0xE9A60001,
3628 0x81C, 0xE8A80001,
3629 0x81C, 0xE7AA0001,
3630 0x81C, 0xE6AC0001,
3631 0x81C, 0xE5AE0001,
3632 0x81C, 0xE4B00001,
3633 0x81C, 0xE3B20001,
3634 0x81C, 0xA8B40001,
3635 0x81C, 0xA7B60001,
3636 0x81C, 0xA6B80001,
3637 0x81C, 0xA5BA0001,
3638 0x81C, 0xA4BC0001,
3639 0x81C, 0xA3BE0001,
3640 0x81C, 0xA2C00001,
3641 0x81C, 0xA1C20001,
3642 0x81C, 0x68C40001,
3643 0x81C, 0x67C60001,
3644 0x81C, 0x66C80001,
3645 0x81C, 0x65CA0001,
3646 0x81C, 0x64CC0001,
3647 0x81C, 0x47CE0001,
3648 0x81C, 0x46D00001,
3649 0x81C, 0x45D20001,
3650 0x81C, 0x44D40001,
3651 0x81C, 0x43D60001,
3652 0x81C, 0x42D80001,
3653 0x81C, 0x08DA0001,
3654 0x81C, 0x07DC0001,
3655 0x81C, 0x06DE0001,
3656 0x81C, 0x05E00001,
3657 0x81C, 0x04E20001,
3658 0x81C, 0x03E40001,
3659 0x81C, 0x02E60001,
3660 0x81C, 0x01E80001,
3661 0x81C, 0x01EA0001,
3662 0x81C, 0x01EC0001,
3663 0x81C, 0x01EE0001,
3664 0x81C, 0x01F00001,
3665 0x81C, 0x01F20001,
3666 0x81C, 0x01F40001,
3667 0x81C, 0x01F60001,
3668 0x81C, 0x01F80001,
3669 0x81C, 0x01FA0001,
3670 0x81C, 0x01FC0001,
3671 0x81C, 0x01FE0001,
3672 0xFF0F07D0, 0xCDEF,
3673 0x81C, 0xFC800001,
3674 0x81C, 0xFB820001,
3675 0x81C, 0xFA840001,
3676 0x81C, 0xF9860001,
3677 0x81C, 0xF8880001,
3678 0x81C, 0xF78A0001,
3679 0x81C, 0xF68C0001,
3680 0x81C, 0xF58E0001,
3681 0x81C, 0xF4900001,
3682 0x81C, 0xF3920001,
3683 0x81C, 0xF2940001,
3684 0x81C, 0xF1960001,
3685 0x81C, 0xF0980001,
3686 0x81C, 0xEF9A0001,
3687 0x81C, 0xEE9C0001,
3688 0x81C, 0xED9E0001,
3689 0x81C, 0xECA00001,
3690 0x81C, 0xEBA20001,
3691 0x81C, 0xEAA40001,
3692 0x81C, 0xE9A60001,
3693 0x81C, 0xE8A80001,
3694 0x81C, 0xE7AA0001,
3695 0x81C, 0xE6AC0001,
3696 0x81C, 0xE5AE0001,
3697 0x81C, 0xE4B00001,
3698 0x81C, 0xE3B20001,
3699 0x81C, 0xA8B40001,
3700 0x81C, 0xA7B60001,
3701 0x81C, 0xA6B80001,
3702 0x81C, 0xA5BA0001,
3703 0x81C, 0xA4BC0001,
3704 0x81C, 0xA3BE0001,
3705 0x81C, 0xA2C00001,
3706 0x81C, 0xA1C20001,
3707 0x81C, 0x68C40001,
3708 0x81C, 0x67C60001,
3709 0x81C, 0x66C80001,
3710 0x81C, 0x65CA0001,
3711 0x81C, 0x64CC0001,
3712 0x81C, 0x47CE0001,
3713 0x81C, 0x46D00001,
3714 0x81C, 0x45D20001,
3715 0x81C, 0x44D40001,
3716 0x81C, 0x43D60001,
3717 0x81C, 0x42D80001,
3718 0x81C, 0x08DA0001,
3719 0x81C, 0x07DC0001,
3720 0x81C, 0x06DE0001,
3721 0x81C, 0x05E00001,
3722 0x81C, 0x04E20001,
3723 0x81C, 0x03E40001,
3724 0x81C, 0x02E60001,
3725 0x81C, 0x01E80001,
3726 0x81C, 0x01EA0001,
3727 0x81C, 0x01EC0001,
3728 0x81C, 0x01EE0001,
3729 0x81C, 0x01F00001,
3730 0x81C, 0x01F20001,
3731 0x81C, 0x01F40001,
3732 0x81C, 0x01F60001,
3733 0x81C, 0x01F80001,
3734 0x81C, 0x01FA0001,
3735 0x81C, 0x01FC0001,
3736 0x81C, 0x01FE0001,
3737 0xCDCDCDCD, 0xCDCD,
3738 0x81C, 0xFF800001,
3739 0x81C, 0xFF820001,
3740 0x81C, 0xFF840001,
3741 0x81C, 0xFE860001,
3742 0x81C, 0xFD880001,
3743 0x81C, 0xFC8A0001,
3744 0x81C, 0xFB8C0001,
3745 0x81C, 0xFA8E0001,
3746 0x81C, 0xF9900001,
3747 0x81C, 0xF8920001,
3748 0x81C, 0xF7940001,
3749 0x81C, 0xF6960001,
3750 0x81C, 0xF5980001,
3751 0x81C, 0xF49A0001,
3752 0x81C, 0xF39C0001,
3753 0x81C, 0xF29E0001,
3754 0x81C, 0xF1A00001,
3755 0x81C, 0xF0A20001,
3756 0x81C, 0xEFA40001,
3757 0x81C, 0xEEA60001,
3758 0x81C, 0xEDA80001,
3759 0x81C, 0xECAA0001,
3760 0x81C, 0xEBAC0001,
3761 0x81C, 0xEAAE0001,
3762 0x81C, 0xE9B00001,
3763 0x81C, 0xE8B20001,
3764 0x81C, 0xE7B40001,
3765 0x81C, 0xE6B60001,
3766 0x81C, 0xE5B80001,
3767 0x81C, 0xE4BA0001,
3768 0x81C, 0xE3BC0001,
3769 0x81C, 0xA8BE0001,
3770 0x81C, 0xA7C00001,
3771 0x81C, 0xA6C20001,
3772 0x81C, 0xA5C40001,
3773 0x81C, 0xA4C60001,
3774 0x81C, 0xA3C80001,
3775 0x81C, 0xA2CA0001,
3776 0x81C, 0xA1CC0001,
3777 0x81C, 0x68CE0001,
3778 0x81C, 0x67D00001,
3779 0x81C, 0x66D20001,
3780 0x81C, 0x65D40001,
3781 0x81C, 0x64D60001,
3782 0x81C, 0x47D80001,
3783 0x81C, 0x46DA0001,
3784 0x81C, 0x45DC0001,
3785 0x81C, 0x44DE0001,
3786 0x81C, 0x43E00001,
3787 0x81C, 0x42E20001,
3788 0x81C, 0x08E40001,
3789 0x81C, 0x07E60001,
3790 0x81C, 0x06E80001,
3791 0x81C, 0x05EA0001,
3792 0x81C, 0x04EC0001,
3793 0x81C, 0x03EE0001,
3794 0x81C, 0x02F00001,
3795 0x81C, 0x01F20001,
3796 0x81C, 0x01F40001,
3797 0x81C, 0x01F60001,
3798 0x81C, 0x01F80001,
3799 0x81C, 0x01FA0001,
3800 0x81C, 0x01FC0001,
3801 0x81C, 0x01FE0001,
3802 0xFF0F0180, 0xDEAD,
3803 0xC50, 0x00000022,
3804 0xC50, 0x00000020,
3805 0xE50, 0x00000022,
3806 0xE50, 0x00000020,
3807};
3808
3809u32 RTL8821AE_AGC_TAB_ARRAY[] = {
3810 0x81C, 0xBF000001,
3811 0x81C, 0xBF020001,
3812 0x81C, 0xBF040001,
3813 0x81C, 0xBF060001,
3814 0x81C, 0xBE080001,
3815 0x81C, 0xBD0A0001,
3816 0x81C, 0xBC0C0001,
3817 0x81C, 0xBA0E0001,
3818 0x81C, 0xB9100001,
3819 0x81C, 0xB8120001,
3820 0x81C, 0xB7140001,
3821 0x81C, 0xB6160001,
3822 0x81C, 0xB5180001,
3823 0x81C, 0xB41A0001,
3824 0x81C, 0xB31C0001,
3825 0x81C, 0xB21E0001,
3826 0x81C, 0xB1200001,
3827 0x81C, 0xB0220001,
3828 0x81C, 0xAF240001,
3829 0x81C, 0xAE260001,
3830 0x81C, 0xAD280001,
3831 0x81C, 0xAC2A0001,
3832 0x81C, 0xAB2C0001,
3833 0x81C, 0xAA2E0001,
3834 0x81C, 0xA9300001,
3835 0x81C, 0xA8320001,
3836 0x81C, 0xA7340001,
3837 0x81C, 0xA6360001,
3838 0x81C, 0xA5380001,
3839 0x81C, 0xA43A0001,
3840 0x81C, 0xA33C0001,
3841 0x81C, 0x673E0001,
3842 0x81C, 0x66400001,
3843 0x81C, 0x65420001,
3844 0x81C, 0x64440001,
3845 0x81C, 0x63460001,
3846 0x81C, 0x62480001,
3847 0x81C, 0x614A0001,
3848 0x81C, 0x474C0001,
3849 0x81C, 0x464E0001,
3850 0x81C, 0x45500001,
3851 0x81C, 0x44520001,
3852 0x81C, 0x43540001,
3853 0x81C, 0x42560001,
3854 0x81C, 0x41580001,
3855 0x81C, 0x285A0001,
3856 0x81C, 0x275C0001,
3857 0x81C, 0x265E0001,
3858 0x81C, 0x25600001,
3859 0x81C, 0x24620001,
3860 0x81C, 0x0A640001,
3861 0x81C, 0x09660001,
3862 0x81C, 0x08680001,
3863 0x81C, 0x076A0001,
3864 0x81C, 0x066C0001,
3865 0x81C, 0x056E0001,
3866 0x81C, 0x04700001,
3867 0x81C, 0x03720001,
3868 0x81C, 0x02740001,
3869 0x81C, 0x01760001,
3870 0x81C, 0x01780001,
3871 0x81C, 0x017A0001,
3872 0x81C, 0x017C0001,
3873 0x81C, 0x017E0001,
3874 0xFF0F02C0, 0xABCD,
3875 0x81C, 0xFB000101,
3876 0x81C, 0xFA020101,
3877 0x81C, 0xF9040101,
3878 0x81C, 0xF8060101,
3879 0x81C, 0xF7080101,
3880 0x81C, 0xF60A0101,
3881 0x81C, 0xF50C0101,
3882 0x81C, 0xF40E0101,
3883 0x81C, 0xF3100101,
3884 0x81C, 0xF2120101,
3885 0x81C, 0xF1140101,
3886 0x81C, 0xF0160101,
3887 0x81C, 0xEF180101,
3888 0x81C, 0xEE1A0101,
3889 0x81C, 0xED1C0101,
3890 0x81C, 0xEC1E0101,
3891 0x81C, 0xEB200101,
3892 0x81C, 0xEA220101,
3893 0x81C, 0xE9240101,
3894 0x81C, 0xE8260101,
3895 0x81C, 0xE7280101,
3896 0x81C, 0xE62A0101,
3897 0x81C, 0xE52C0101,
3898 0x81C, 0xE42E0101,
3899 0x81C, 0xE3300101,
3900 0x81C, 0xA5320101,
3901 0x81C, 0xA4340101,
3902 0x81C, 0xA3360101,
3903 0x81C, 0x87380101,
3904 0x81C, 0x863A0101,
3905 0x81C, 0x853C0101,
3906 0x81C, 0x843E0101,
3907 0x81C, 0x69400101,
3908 0x81C, 0x68420101,
3909 0x81C, 0x67440101,
3910 0x81C, 0x66460101,
3911 0x81C, 0x49480101,
3912 0x81C, 0x484A0101,
3913 0x81C, 0x474C0101,
3914 0x81C, 0x2A4E0101,
3915 0x81C, 0x29500101,
3916 0x81C, 0x28520101,
3917 0x81C, 0x27540101,
3918 0x81C, 0x26560101,
3919 0x81C, 0x25580101,
3920 0x81C, 0x245A0101,
3921 0x81C, 0x235C0101,
3922 0x81C, 0x055E0101,
3923 0x81C, 0x04600101,
3924 0x81C, 0x03620101,
3925 0x81C, 0x02640101,
3926 0x81C, 0x01660101,
3927 0x81C, 0x01680101,
3928 0x81C, 0x016A0101,
3929 0x81C, 0x016C0101,
3930 0x81C, 0x016E0101,
3931 0x81C, 0x01700101,
3932 0x81C, 0x01720101,
3933 0xCDCDCDCD, 0xCDCD,
3934 0x81C, 0xFF000101,
3935 0x81C, 0xFF020101,
3936 0x81C, 0xFE040101,
3937 0x81C, 0xFD060101,
3938 0x81C, 0xFC080101,
3939 0x81C, 0xFD0A0101,
3940 0x81C, 0xFC0C0101,
3941 0x81C, 0xFB0E0101,
3942 0x81C, 0xFA100101,
3943 0x81C, 0xF9120101,
3944 0x81C, 0xF8140101,
3945 0x81C, 0xF7160101,
3946 0x81C, 0xF6180101,
3947 0x81C, 0xF51A0101,
3948 0x81C, 0xF41C0101,
3949 0x81C, 0xF31E0101,
3950 0x81C, 0xF2200101,
3951 0x81C, 0xF1220101,
3952 0x81C, 0xF0240101,
3953 0x81C, 0xEF260101,
3954 0x81C, 0xEE280101,
3955 0x81C, 0xED2A0101,
3956 0x81C, 0xEC2C0101,
3957 0x81C, 0xEB2E0101,
3958 0x81C, 0xEA300101,
3959 0x81C, 0xE9320101,
3960 0x81C, 0xE8340101,
3961 0x81C, 0xE7360101,
3962 0x81C, 0xE6380101,
3963 0x81C, 0xE53A0101,
3964 0x81C, 0xE43C0101,
3965 0x81C, 0xE33E0101,
3966 0x81C, 0xA5400101,
3967 0x81C, 0xA4420101,
3968 0x81C, 0xA3440101,
3969 0x81C, 0x87460101,
3970 0x81C, 0x86480101,
3971 0x81C, 0x854A0101,
3972 0x81C, 0x844C0101,
3973 0x81C, 0x694E0101,
3974 0x81C, 0x68500101,
3975 0x81C, 0x67520101,
3976 0x81C, 0x66540101,
3977 0x81C, 0x49560101,
3978 0x81C, 0x48580101,
3979 0x81C, 0x475A0101,
3980 0x81C, 0x2A5C0101,
3981 0x81C, 0x295E0101,
3982 0x81C, 0x28600101,
3983 0x81C, 0x27620101,
3984 0x81C, 0x26640101,
3985 0x81C, 0x25660101,
3986 0x81C, 0x24680101,
3987 0x81C, 0x236A0101,
3988 0x81C, 0x056C0101,
3989 0x81C, 0x046E0101,
3990 0x81C, 0x03700101,
3991 0x81C, 0x02720101,
3992 0xFF0F02C0, 0xDEAD,
3993 0x81C, 0x01740101,
3994 0x81C, 0x01760101,
3995 0x81C, 0x01780101,
3996 0x81C, 0x017A0101,
3997 0x81C, 0x017C0101,
3998 0x81C, 0x017E0101,
3999 0xC50, 0x00000022,
4000 0xC50, 0x00000020,
4001
4002};
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/table.h b/drivers/staging/rtl8821ae/rtl8821ae/table.h
new file mode 100644
index 000000000000..b9d7b266a33a
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/table.h
@@ -0,0 +1,62 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Created on 2010/ 5/18, 1:41
27 *
28 * Larry Finger <Larry.Finger@lwfinger.net>
29 *
30 *****************************************************************************/
31
32#ifndef __RTL8821AE_TABLE__H_
33#define __RTL8821AE_TABLE__H_
34
35#include <linux/types.h>
36#define RTL8821AEPHY_REG_1TARRAYLEN 344
37extern u32 RTL8821AE_PHY_REG_ARRAY[];
38#define RTL8812AEPHY_REG_1TARRAYLEN 490
39extern u32 RTL8812AE_PHY_REG_ARRAY[];
40#define RTL8821AEPHY_REG_ARRAY_PGLEN 90
41extern u32 RTL8821AE_PHY_REG_ARRAY_PG[];
42#define RTL8812AEPHY_REG_ARRAY_PGLEN 276
43extern u32 RTL8812AE_PHY_REG_ARRAY_PG[];
44//#define RTL8723BE_RADIOA_1TARRAYLEN 206
45//extern u8 *RTL8821AE_TXPWR_LMT_ARRAY[];
46#define RTL8812AE_RADIOA_1TARRAYLEN 1264
47extern u32 RTL8812AE_RADIOA_ARRAY[];
48#define RTL8812AE_RADIOB_1TARRAYLEN 1240
49extern u32 RTL8812AE_RADIOB_ARRAY[];
50#define RTL8821AE_RADIOA_1TARRAYLEN 1176
51extern u32 RTL8821AE_RADIOA_ARRAY[];
52#define RTL8821AEMAC_1T_ARRAYLEN 194
53extern u32 RTL8821AE_MAC_REG_ARRAY[];
54#define RTL8812AEMAC_1T_ARRAYLEN 214
55extern u32 RTL8812AE_MAC_REG_ARRAY[];
56#define RTL8821AEAGCTAB_1TARRAYLEN 382
57extern u32 RTL8821AE_AGC_TAB_ARRAY[];
58#define RTL8812AEAGCTAB_1TARRAYLEN 1312
59extern u32 RTL8812AE_AGC_TAB_ARRAY[];
60
61
62#endif
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/trx.c b/drivers/staging/rtl8821ae/rtl8821ae/trx.c
new file mode 100644
index 000000000000..75ae4387fe19
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/trx.c
@@ -0,0 +1,1050 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../base.h"
33#include "../stats.h"
34#include "reg.h"
35#include "def.h"
36#include "phy.h"
37#include "trx.h"
38#include "led.h"
39#include "dm.h"
40#include "phy.h"
41u8 _rtl8821ae_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
42{
43 u16 fc = rtl_get_fc(skb);
44
45 if (unlikely(ieee80211_is_beacon(fc)))
46 return QSLT_BEACON;
47 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
48 return QSLT_MGNT;
49
50 return skb->priority;
51}
52
53/* mac80211's rate_idx is like this:
54 *
55 * 2.4G band:rx_status->band == IEEE80211_BAND_2GHZ
56 *
57 * B/G rate:
58 * (rx_status->flag & RX_FLAG_HT) = 0,
59 * DESC_RATE1M-->DESC_RATE54M ==> idx is 0-->11,
60 *
61 * N rate:
62 * (rx_status->flag & RX_FLAG_HT) = 1,
63 * DESC_RATEMCS0-->DESC_RATEMCS15 ==> idx is 0-->15
64 *
65 * 5G band:rx_status->band == IEEE80211_BAND_5GHZ
66 * A rate:
67 * (rx_status->flag & RX_FLAG_HT) = 0,
68 * DESC_RATE6M-->DESC_RATE54M ==> idx is 0-->7,
69 *
70 * N rate:
71 * (rx_status->flag & RX_FLAG_HT) = 1,
72 * DESC_RATEMCS0-->DESC_RATEMCS15 ==> idx is 0-->15
73 */
74static int _rtl8821ae_rate_mapping(struct ieee80211_hw *hw,
75 bool isht, u8 desc_rate)
76{
77 int rate_idx;
78
79 if (false == isht) {
80#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
81 if (IEEE80211_BAND_2GHZ == hw->conf.chandef.chan->band) {
82#else
83 if (IEEE80211_BAND_2GHZ == hw->conf.channel->band) {
84#endif
85 switch (desc_rate) {
86 case DESC_RATE1M:
87 rate_idx = 0;
88 break;
89 case DESC_RATE2M:
90 rate_idx = 1;
91 break;
92 case DESC_RATE5_5M:
93 rate_idx = 2;
94 break;
95 case DESC_RATE11M:
96 rate_idx = 3;
97 break;
98 case DESC_RATE6M:
99 rate_idx = 4;
100 break;
101 case DESC_RATE9M:
102 rate_idx = 5;
103 break;
104 case DESC_RATE12M:
105 rate_idx = 6;
106 break;
107 case DESC_RATE18M:
108 rate_idx = 7;
109 break;
110 case DESC_RATE24M:
111 rate_idx = 8;
112 break;
113 case DESC_RATE36M:
114 rate_idx = 9;
115 break;
116 case DESC_RATE48M:
117 rate_idx = 10;
118 break;
119 case DESC_RATE54M:
120 rate_idx = 11;
121 break;
122 default:
123 rate_idx = 0;
124 break;
125 }
126 } else {
127 switch (desc_rate) {
128 case DESC_RATE6M:
129 rate_idx = 0;
130 break;
131 case DESC_RATE9M:
132 rate_idx = 1;
133 break;
134 case DESC_RATE12M:
135 rate_idx = 2;
136 break;
137 case DESC_RATE18M:
138 rate_idx = 3;
139 break;
140 case DESC_RATE24M:
141 rate_idx = 4;
142 break;
143 case DESC_RATE36M:
144 rate_idx = 5;
145 break;
146 case DESC_RATE48M:
147 rate_idx = 6;
148 break;
149 case DESC_RATE54M:
150 rate_idx = 7;
151 break;
152 default:
153 rate_idx = 0;
154 break;
155 }
156 }
157 } else {
158 switch(desc_rate) {
159 case DESC_RATEMCS0:
160 rate_idx = 0;
161 break;
162 case DESC_RATEMCS1:
163 rate_idx = 1;
164 break;
165 case DESC_RATEMCS2:
166 rate_idx = 2;
167 break;
168 case DESC_RATEMCS3:
169 rate_idx = 3;
170 break;
171 case DESC_RATEMCS4:
172 rate_idx = 4;
173 break;
174 case DESC_RATEMCS5:
175 rate_idx = 5;
176 break;
177 case DESC_RATEMCS6:
178 rate_idx = 6;
179 break;
180 case DESC_RATEMCS7:
181 rate_idx = 7;
182 break;
183 case DESC_RATEMCS8:
184 rate_idx = 8;
185 break;
186 case DESC_RATEMCS9:
187 rate_idx = 9;
188 break;
189 case DESC_RATEMCS10:
190 rate_idx = 10;
191 break;
192 case DESC_RATEMCS11:
193 rate_idx = 11;
194 break;
195 case DESC_RATEMCS12:
196 rate_idx = 12;
197 break;
198 case DESC_RATEMCS13:
199 rate_idx = 13;
200 break;
201 case DESC_RATEMCS14:
202 rate_idx = 14;
203 break;
204 case DESC_RATEMCS15:
205 rate_idx = 15;
206 break;
207 default:
208 rate_idx = 0;
209 break;
210 }
211 }
212 return rate_idx;
213}
214
215static void _rtl8821ae_query_rxphystatus(struct ieee80211_hw *hw,
216 struct rtl_stats *pstatus, u8 *pdesc,
217 struct rx_fwinfo_8821ae *p_drvinfo, bool bpacket_match_bssid,
218 bool bpacket_toself, bool b_packet_beacon)
219{
220 struct rtl_priv *rtlpriv = rtl_priv(hw);
221 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
222 struct phy_sts_cck_8821ae_t *cck_buf;
223 struct phy_status_rpt *p_phystRpt = (struct phy_status_rpt *)p_drvinfo;
224 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
225 char rx_pwr_all = 0, rx_pwr[4];
226 u8 rf_rx_num = 0, evm, pwdb_all;
227 u8 i, max_spatial_stream;
228 u32 rssi, total_rssi = 0;
229 bool b_is_cck = pstatus->b_is_cck;
230 u8 lan_idx,vga_idx;
231
232 /* Record it for next packet processing */
233 pstatus->b_packet_matchbssid = bpacket_match_bssid;
234 pstatus->b_packet_toself = bpacket_toself;
235 pstatus->b_packet_beacon = b_packet_beacon;
236 pstatus->rx_mimo_signalquality[0] = -1;
237 pstatus->rx_mimo_signalquality[1] = -1;
238
239 if (b_is_cck) {
240 u8 cck_highpwr;
241 u8 cck_agc_rpt;
242 /* CCK Driver info Structure is not the same as OFDM packet. */
243 cck_buf = (struct phy_sts_cck_8821ae_t *)p_drvinfo;
244 cck_agc_rpt = cck_buf->cck_agc_rpt;
245
246 /* (1)Hardware does not provide RSSI for CCK */
247 /* (2)PWDB, Average PWDB cacluated by
248 * hardware (for rate adaptive) */
249 if (ppsc->rfpwr_state == ERFON)
250 cck_highpwr = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
251 BIT(9));
252 else
253 cck_highpwr = false;
254
255 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
256 vga_idx = (cck_agc_rpt & 0x1f);
257 switch (lan_idx) {
258 case 7:
259 if(vga_idx <= 27)
260 rx_pwr_all = -100 + 2*(27-vga_idx); /*VGA_idx = 27~2*/
261 else
262 rx_pwr_all = -100;
263 break;
264 case 6:
265 rx_pwr_all = -48 + 2*(2-vga_idx); /*VGA_idx = 2~0*/
266 break;
267 case 5:
268 rx_pwr_all = -42 + 2*(7-vga_idx); /*VGA_idx = 7~5*/
269 break;
270 case 4:
271 rx_pwr_all = -36 + 2*(7-vga_idx); /*VGA_idx = 7~4*/
272 break;
273 case 3:
274 rx_pwr_all = -24 + 2*(7-vga_idx); /*VGA_idx = 7~0*/
275 break;
276 case 2:
277 if(cck_highpwr)
278 rx_pwr_all = -12 + 2*(5-vga_idx); /*VGA_idx = 5~0*/
279 else
280 rx_pwr_all = -6+ 2*(5-vga_idx);
281 break;
282 case 1:
283 rx_pwr_all = 8-2*vga_idx;
284 break;
285 case 0:
286 rx_pwr_all = 14-2*vga_idx;
287 break;
288 default:
289 break;
290 }
291 rx_pwr_all += 6;
292 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
293 /* CCK gain is smaller than OFDM/MCS gain, */
294 /* so we add gain diff by experiences,
295 * the val is 6 */
296 pwdb_all += 6;
297 if(pwdb_all > 100)
298 pwdb_all = 100;
299 /* modify the offset to make the same
300 * gain index with OFDM. */
301 if(pwdb_all > 34 && pwdb_all <= 42)
302 pwdb_all -= 2;
303 else if(pwdb_all > 26 && pwdb_all <= 34)
304 pwdb_all -= 6;
305 else if(pwdb_all > 14 && pwdb_all <= 26)
306 pwdb_all -= 8;
307 else if(pwdb_all > 4 && pwdb_all <= 14)
308 pwdb_all -= 4;
309 if (cck_highpwr == false){
310 if (pwdb_all >= 80)
311 pwdb_all =((pwdb_all-80)<<1)+((pwdb_all-80)>>1)+80;
312 else if((pwdb_all <= 78) && (pwdb_all >= 20))
313 pwdb_all += 3;
314 if(pwdb_all>100)
315 pwdb_all = 100;
316 }
317
318 pstatus->rx_pwdb_all = pwdb_all;
319 pstatus->recvsignalpower = rx_pwr_all;
320
321 /* (3) Get Signal Quality (EVM) */
322 if (bpacket_match_bssid) {
323 u8 sq;
324
325 if (pstatus->rx_pwdb_all > 40)
326 sq = 100;
327 else {
328 sq = cck_buf->sq_rpt;
329 if (sq > 64)
330 sq = 0;
331 else if (sq < 20)
332 sq = 100;
333 else
334 sq = ((64 - sq) * 100) / 44;
335 }
336
337 pstatus->signalquality = sq;
338 pstatus->rx_mimo_signalquality[0] = sq;
339 pstatus->rx_mimo_signalquality[1] = -1;
340 }
341 } else {
342 rtlpriv->dm.brfpath_rxenable[0] =
343 rtlpriv->dm.brfpath_rxenable[1] = true;
344
345 /* (1)Get RSSI for HT rate */
346 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
347
348 /* we will judge RF RX path now. */
349 if (rtlpriv->dm.brfpath_rxenable[i])
350 rf_rx_num++;
351
352 rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
353
354 /* Translate DBM to percentage. */
355 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
356 total_rssi += rssi;
357
358 /* Get Rx snr value in DB */
359 rtlpriv->stats.rx_snr_db[i] = (long)(p_drvinfo->rxsnr[i] / 2);
360
361 /* Record Signal Strength for next packet */
362 if (bpacket_match_bssid)
363 pstatus->rx_mimo_signalstrength[i] = (u8) rssi;
364 }
365
366 /* (2)PWDB, Average PWDB cacluated by
367 * hardware (for rate adaptive) */
368 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
369
370 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
371 pstatus->rx_pwdb_all = pwdb_all;
372 pstatus->rxpower = rx_pwr_all;
373 pstatus->recvsignalpower = rx_pwr_all;
374
375 /* (3)EVM of HT rate */
376 if (pstatus->b_is_ht && pstatus->rate >= DESC_RATEMCS8 &&
377 pstatus->rate <= DESC_RATEMCS15)
378 max_spatial_stream = 2;
379 else
380 max_spatial_stream = 1;
381
382 for (i = 0; i < max_spatial_stream; i++) {
383 evm = rtl_evm_db_to_percentage(p_drvinfo->rxevm[i]);
384
385 if (bpacket_match_bssid) {
386 /* Fill value in RFD, Get the first
387 * spatial stream only */
388 if (i == 0)
389 pstatus->signalquality = (u8) (evm & 0xff);
390 pstatus->rx_mimo_signalquality[i] = (u8) (evm & 0xff);
391 }
392 }
393 }
394
395 /* UI BSS List signal strength(in percentage),
396 * make it good looking, from 0~100. */
397 if (b_is_cck)
398 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
399 pwdb_all));
400 else if (rf_rx_num != 0)
401 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
402 total_rssi /= rf_rx_num));
403 /*HW antenna diversity*/
404 rtldm->fat_table.antsel_rx_keep_0 = p_phystRpt->ant_sel;
405 rtldm->fat_table.antsel_rx_keep_1 = p_phystRpt->ant_sel_b;
406 rtldm->fat_table.antsel_rx_keep_2 = p_phystRpt->antsel_rx_keep_2;
407
408}
409#if 0
410static void _rtl8821ae_smart_antenna(struct ieee80211_hw *hw,
411 struct rtl_stats *pstatus)
412{
413 struct rtl_dm *rtldm= rtl_dm(rtl_priv(hw));
414 struct rtl_efuse *rtlefuse =rtl_efuse(rtl_priv(hw));
415 u8 antsel_tr_mux;
416 struct fast_ant_trainning *pfat_table = &(rtldm->fat_table);
417
418 if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV) {
419 if (pfat_table->fat_state == FAT_TRAINING_STATE) {
420 if (pstatus->b_packet_toself) {
421 antsel_tr_mux = (pfat_table->antsel_rx_keep_2 << 2) |
422 (pfat_table->antsel_rx_keep_1 << 1) | pfat_table->antsel_rx_keep_0;
423 pfat_table->ant_sum_rssi[antsel_tr_mux] += pstatus->rx_pwdb_all;
424 pfat_table->ant_rssi_cnt[antsel_tr_mux]++;
425 }
426 }
427 } else if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
428 (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)) {
429 if (pstatus->b_packet_toself || pstatus->b_packet_matchbssid) {
430 antsel_tr_mux = (pfat_table->antsel_rx_keep_2 << 2) |
431 (pfat_table->antsel_rx_keep_1 << 1) | pfat_table->antsel_rx_keep_0;
432 rtl8821ae_dm_ant_sel_statistics(hw, antsel_tr_mux, 0, pstatus->rx_pwdb_all);
433 }
434
435 }
436}
437#endif
438static void _rtl8821ae_translate_rx_signal_stuff(struct ieee80211_hw *hw,
439 struct sk_buff *skb, struct rtl_stats *pstatus,
440 u8 *pdesc, struct rx_fwinfo_8821ae *p_drvinfo)
441{
442 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
443 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
444 struct ieee80211_hdr *hdr;
445 u8 *tmp_buf;
446 u8 *praddr;
447 u8 *psaddr;
448 u16 fc, type;
449 bool b_packet_matchbssid, b_packet_toself, b_packet_beacon;
450
451 tmp_buf = skb->data + pstatus->rx_drvinfo_size + pstatus->rx_bufshift;
452
453 hdr = (struct ieee80211_hdr *)tmp_buf;
454 fc = le16_to_cpu(hdr->frame_control);
455 type = WLAN_FC_GET_TYPE(fc);
456 praddr = hdr->addr1;
457 psaddr = ieee80211_get_SA(hdr);
458 memcpy(pstatus->psaddr, psaddr, ETH_ALEN);
459
460 b_packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) &&
461 (!ether_addr_equal(mac->bssid, (fc & IEEE80211_FCTL_TODS) ?
462 hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ?
463 hdr->addr2 : hdr->addr3)) && (!pstatus->b_hwerror) &&
464 (!pstatus->b_crc) && (!pstatus->b_icv));
465
466 b_packet_toself = b_packet_matchbssid &&
467 (!ether_addr_equal(praddr, rtlefuse->dev_addr));
468
469 if (ieee80211_is_beacon(fc))
470 b_packet_beacon = true;
471 else
472 b_packet_beacon = false;
473
474 if (b_packet_beacon && b_packet_matchbssid)
475 rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++;
476
477 _rtl8821ae_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
478 b_packet_matchbssid, b_packet_toself,
479 b_packet_beacon);
480 /*_rtl8821ae_smart_antenna(hw, pstatus); */
481 rtl_process_phyinfo(hw, tmp_buf, pstatus);
482}
483
484static void _rtl8821ae_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
485 u8 *virtualaddress)
486{
487 u32 dwtmp = 0;
488 memset(virtualaddress, 0, 8);
489
490 SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
491 if (ptcb_desc->empkt_num == 1)
492 dwtmp = ptcb_desc->empkt_len[0];
493 else {
494 dwtmp = ptcb_desc->empkt_len[0];
495 dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
496 dwtmp += ptcb_desc->empkt_len[1];
497 }
498 SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
499
500 if (ptcb_desc->empkt_num <= 3)
501 dwtmp = ptcb_desc->empkt_len[2];
502 else {
503 dwtmp = ptcb_desc->empkt_len[2];
504 dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
505 dwtmp += ptcb_desc->empkt_len[3];
506 }
507 SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
508 if (ptcb_desc->empkt_num <= 5)
509 dwtmp = ptcb_desc->empkt_len[4];
510 else {
511 dwtmp = ptcb_desc->empkt_len[4];
512 dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
513 dwtmp += ptcb_desc->empkt_len[5];
514 }
515 SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
516 SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
517 if (ptcb_desc->empkt_num <= 7)
518 dwtmp = ptcb_desc->empkt_len[6];
519 else {
520 dwtmp = ptcb_desc->empkt_len[6];
521 dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
522 dwtmp += ptcb_desc->empkt_len[7];
523 }
524 SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
525 if (ptcb_desc->empkt_num <= 9)
526 dwtmp = ptcb_desc->empkt_len[8];
527 else {
528 dwtmp = ptcb_desc->empkt_len[8];
529 dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
530 dwtmp += ptcb_desc->empkt_len[9];
531 }
532 SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
533}
534
535bool rtl8821ae_rx_query_desc(struct ieee80211_hw *hw,
536 struct rtl_stats *status,
537 struct ieee80211_rx_status *rx_status,
538 u8 *pdesc, struct sk_buff *skb)
539{
540 struct rtl_priv *rtlpriv = rtl_priv(hw);
541 struct rx_fwinfo_8821ae *p_drvinfo;
542 struct ieee80211_hdr *hdr;
543
544 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
545
546 status->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
547 status->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
548 RX_DRV_INFO_SIZE_UNIT;
549 status->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
550 status->b_icv = (u16) GET_RX_DESC_ICV(pdesc);
551 status->b_crc = (u16) GET_RX_DESC_CRC32(pdesc);
552 status->b_hwerror = (status->b_crc | status->b_icv);
553 status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
554 status->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
555 status->b_shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
556 status->b_isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
557 status->b_isfirst_ampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
558 status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
559 status->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
560 status->macid = GET_RX_DESC_MACID(pdesc);
561 status->b_is_ht = (bool)GET_RX_DESC_RXHT(pdesc);
562
563 status->b_is_cck = RX_HAL_IS_CCK_RATE(status->rate);
564
565 if (GET_RX_STATUS_DESC_RPT_SEL(pdesc))
566 status->packet_report_type = C2H_PACKET;
567 else
568 status->packet_report_type = NORMAL_RX;
569
570 if (GET_RX_STATUS_DESC_PATTERN_MATCH(pdesc))
571 status->wake_match = BIT(2);
572 else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
573 status->wake_match = BIT(1);
574 else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
575 status->wake_match = BIT(0);
576 else
577 status->wake_match = 0;
578
579 if (status->wake_match)
580 RT_TRACE(COMP_RXDESC,DBG_LOUD,
581 ("GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",status->wake_match ));
582#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
583 rx_status->freq = hw->conf.chandef.chan->center_freq;
584 rx_status->band = hw->conf.chandef.chan->band;
585#else
586 rx_status->freq = hw->conf.channel->center_freq;
587 rx_status->band = hw->conf.channel->band;
588#endif
589
590 hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size
591 + status->rx_bufshift);
592
593 if (status->b_crc)
594 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
595
596 if (status->rx_is40Mhzpacket)
597 rx_status->flag |= RX_FLAG_40MHZ;
598
599 if (status->b_is_ht)
600 rx_status->flag |= RX_FLAG_HT;
601
602 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
603
604 /* hw will set status->decrypted true, if it finds the
605 * frame is open data frame or mgmt frame. */
606 /* So hw will not decryption robust managment frame
607 * for IEEE80211w but still set status->decrypted
608 * true, so here we should set it back to undecrypted
609 * for IEEE80211w frame, and mac80211 sw will help
610 * to decrypt it */
611 if (status->decrypted) {
612 if (!hdr) {
613 WARN_ON_ONCE(true);
614 pr_err("decrypted is true but hdr NULL, from skb %p\n",
615 rtl_get_hdr(skb));
616 return false;
617 }
618
619 if ((ieee80211_is_robust_mgmt_frame(hdr)) &&
620 (ieee80211_has_protected(hdr->frame_control)))
621 rx_status->flag &= ~RX_FLAG_DECRYPTED;
622 else
623 rx_status->flag |= RX_FLAG_DECRYPTED;
624 }
625
626 /* rate_idx: index of data rate into band's
627 * supported rates or MCS index if HT rates
628 * are use (RX_FLAG_HT)*/
629 /* Notice: this is diff with windows define */
630 rx_status->rate_idx = _rtl8821ae_rate_mapping(hw,
631 status->b_is_ht, status->rate);
632
633 rx_status->mactime = status->timestamp_low;
634 if (phystatus == true) {
635 p_drvinfo = (struct rx_fwinfo_8821ae *)(skb->data +
636 status->rx_bufshift);
637
638 _rtl8821ae_translate_rx_signal_stuff(hw,
639 skb, status, pdesc,
640 p_drvinfo);
641 }
642
643 /*rx_status->qual = status->signal; */
644 rx_status->signal = status->recvsignalpower + 10;
645 /*rx_status->noise = -status->noise; */
646 if (status->packet_report_type == TX_REPORT2){
647 status->macid_valid_entry[0] = GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
648 status->macid_valid_entry[1] = GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
649 }
650 return true;
651}
652
653/*<delete in kernel start>*/
654#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
655void rtl8821ae_tx_fill_desc(struct ieee80211_hw *hw,
656 struct ieee80211_hdr *hdr, u8 *pdesc_tx, u8 *txbd,
657 struct ieee80211_tx_info *info, struct sk_buff *skb,
658 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
659#else
660/*<delete in kernel end>*/
661void rtl8821ae_tx_fill_desc(struct ieee80211_hw *hw,
662 struct ieee80211_hdr *hdr, u8 *pdesc_tx, u8 *txbd,
663 struct ieee80211_tx_info *info,
664 struct ieee80211_sta *sta,
665 struct sk_buff *skb,
666 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
667/*<delete in kernel start>*/
668#endif
669/*<delete in kernel end>*/
670{
671 struct rtl_priv *rtlpriv = rtl_priv(hw);
672 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
673 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
674 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
675/*<delete in kernel start>*/
676#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
677 struct ieee80211_sta *sta = info->control.sta;
678#endif
679/*<delete in kernel end>*/
680 u8 *pdesc = (u8 *) pdesc_tx;
681 u16 seq_number;
682 u16 fc = le16_to_cpu(hdr->frame_control);
683 unsigned int buf_len = 0;
684 unsigned int skb_len = skb->len;
685 u8 fw_qsel = _rtl8821ae_map_hwqueue_to_fwqueue(skb, hw_queue);
686 bool b_firstseg = ((hdr->seq_ctrl &
687 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
688 bool b_lastseg = ((hdr->frame_control &
689 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
690 dma_addr_t mapping;
691 u8 bw_40 = 0;
692 u8 short_gi = 0;
693
694 if (mac->opmode == NL80211_IFTYPE_STATION) {
695 bw_40 = mac->bw_40;
696 } else if (mac->opmode == NL80211_IFTYPE_AP ||
697 mac->opmode == NL80211_IFTYPE_ADHOC) {
698 if (sta)
699 bw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
700 }
701 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
702 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
703 /* reserve 8 byte for AMPDU early mode */
704 if (rtlhal->b_earlymode_enable) {
705 skb_push(skb, EM_HDR_LEN);
706 memset(skb->data, 0, EM_HDR_LEN);
707 }
708 buf_len = skb->len;
709 mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
710 PCI_DMA_TODEVICE);
711 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
712 RT_TRACE(COMP_SEND, DBG_TRACE,
713 ("DMA mapping error"));
714 return;
715 }
716 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_8821ae));
717 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
718 b_firstseg = true;
719 b_lastseg = true;
720 }
721 if (b_firstseg) {
722 if (rtlhal->b_earlymode_enable) {
723 SET_TX_DESC_PKT_OFFSET(pdesc, 1);
724 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN + EM_HDR_LEN);
725 if (ptcb_desc->empkt_num) {
726 RT_TRACE(COMP_SEND, DBG_TRACE,
727 ("Insert 8 byte.pTcb->EMPktNum:%d\n",
728 ptcb_desc->empkt_num));
729 _rtl8821ae_insert_emcontent(ptcb_desc, (u8 *)(skb->data));
730 }
731 } else {
732 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
733 }
734
735 /* ptcb_desc->use_driver_rate = true; */
736 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
737 if (ptcb_desc->hw_rate > DESC_RATEMCS0) {
738 short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
739 } else {
740 short_gi = (ptcb_desc->use_shortpreamble) ? 1 :0;
741 }
742 SET_TX_DESC_DATA_SHORTGI(pdesc, short_gi);
743
744 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
745 SET_TX_DESC_AGG_ENABLE(pdesc, 1);
746 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
747 }
748 SET_TX_DESC_SEQ(pdesc, seq_number);
749 SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcb_desc->b_rts_enable &&
750 !ptcb_desc->b_cts_enable) ? 1 : 0));
751 SET_TX_DESC_HW_RTS_ENABLE(pdesc,0);
752 SET_TX_DESC_CTS2SELF(pdesc, ((ptcb_desc->b_cts_enable) ? 1 : 0));
753 /* SET_TX_DESC_RTS_STBC(pdesc, ((ptcb_desc->b_rts_stbc) ? 1 : 0));*/
754
755 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
756 /* SET_TX_DESC_RTS_BW(pdesc, 0);*/
757 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
758 SET_TX_DESC_RTS_SHORT(pdesc, ((ptcb_desc->rts_rate <= DESC_RATE54M) ?
759 (ptcb_desc->b_rts_use_shortpreamble ? 1 : 0) :
760 (ptcb_desc->b_rts_use_shortgi ? 1 : 0)));
761
762 if(ptcb_desc->btx_enable_sw_calc_duration)
763 SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
764
765 if (bw_40) {
766 if (ptcb_desc->b_packet_bw) {
767 SET_TX_DESC_DATA_BW(pdesc, 1);
768 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
769 } else {
770 SET_TX_DESC_DATA_BW(pdesc, 0);
771 SET_TX_DESC_TX_SUB_CARRIER(pdesc, mac->cur_40_prime_sc);
772 }
773 } else {
774 SET_TX_DESC_DATA_BW(pdesc, 0);
775 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
776 }
777
778 SET_TX_DESC_LINIP(pdesc, 0);
779 SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb_len);
780 if (sta) {
781 u8 ampdu_density = sta->ht_cap.ampdu_density;
782 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
783 }
784 if (info->control.hw_key) {
785 struct ieee80211_key_conf *keyconf = info->control.hw_key;
786/*<delete in kernel start>*/
787#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
788/*<delete in kernel end>*/
789 switch (keyconf->cipher) {
790 case WLAN_CIPHER_SUITE_WEP40:
791 case WLAN_CIPHER_SUITE_WEP104:
792 case WLAN_CIPHER_SUITE_TKIP:
793 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
794 break;
795 case WLAN_CIPHER_SUITE_CCMP:
796 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
797 break;
798 default:
799 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
800 break;
801
802 }
803/*<delete in kernel start>*/
804#else
805 switch (keyconf->alg) {
806 case ALG_WEP:
807 case ALG_TKIP:
808 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
809 break;
810 case ALG_CCMP:
811 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
812 break;
813 default:
814 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
815 break;
816
817 }
818#endif
819/*<delete in kernel end>*/
820 }
821
822 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
823 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
824 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
825 SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ? 1 : 0);
826 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
827
828#if 0
829 SET_TX_DESC_USE_RATE(pdesc, 1);
830 SET_TX_DESC_TX_RATE(pdesc, 0x04);
831
832 SET_TX_DESC_RETRY_LIMIT_ENABLE(pdesc, 1);
833 SET_TX_DESC_DATA_RETRY_LIMIT(pdesc, 0x3f);
834#endif
835
836 /*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
837 /* Set TxRate and RTSRate in TxDesc */
838 /* This prevent Tx initial rate of new-coming packets */
839 /* from being overwritten by retried packet rate.*/
840 if (!ptcb_desc->use_driver_rate) {
841 /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
842 /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
843 }
844 if (ieee80211_is_data_qos(fc)) {
845 if (mac->rdg_en) {
846 RT_TRACE(COMP_SEND, DBG_TRACE,
847 ("Enable RDG function.\n"));
848 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
849 SET_TX_DESC_HTC(pdesc, 1);
850 }
851 }
852 }
853
854 SET_TX_DESC_FIRST_SEG(pdesc, (b_firstseg ? 1 : 0));
855 SET_TX_DESC_LAST_SEG(pdesc, (b_lastseg ? 1 : 0));
856 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) buf_len);
857 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping));
858 //if (rtlpriv->dm.b_useramask) {
859 if(1){
860 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
861 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
862 } else {
863 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
864 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
865 }
866/* if (ieee80211_is_data_qos(fc))
867 SET_TX_DESC_QOS(pdesc, 1);
868*/
869 if (!ieee80211_is_data_qos(fc)) {
870 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
871 SET_TX_DESC_HWSEQ_SEL(pdesc, 0);
872 }
873 SET_TX_DESC_MORE_FRAG(pdesc, (b_lastseg ? 0 : 1));
874 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
875 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
876 SET_TX_DESC_BMC(pdesc, 1);
877 }
878
879 rtl8821ae_dm_set_tx_ant_by_tx_info(hw,pdesc,ptcb_desc->mac_id);
880 RT_TRACE(COMP_SEND, DBG_TRACE, ("\n"));
881}
882
883void rtl8821ae_tx_fill_cmddesc(struct ieee80211_hw *hw,
884 u8 *pdesc, bool b_firstseg,
885 bool b_lastseg, struct sk_buff *skb)
886{
887 struct rtl_priv *rtlpriv = rtl_priv(hw);
888 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
889 u8 fw_queue = QSLT_BEACON;
890
891 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
892 skb->data, skb->len,
893 PCI_DMA_TODEVICE);
894
895 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
896 RT_TRACE(COMP_SEND, DBG_TRACE,
897 ("DMA mapping error"));
898 return;
899 }
900 CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
901
902 SET_TX_DESC_FIRST_SEG(pdesc, 1);
903 SET_TX_DESC_LAST_SEG(pdesc, 1);
904
905 SET_TX_DESC_PKT_SIZE((u8 *) pdesc, (u16) (skb->len));
906
907 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
908
909 SET_TX_DESC_USE_RATE(pdesc, 1);
910 SET_TX_DESC_TX_RATE(pdesc, DESC_RATE1M);
911 SET_TX_DESC_DISABLE_FB(pdesc, 1);
912
913 SET_TX_DESC_DATA_BW(pdesc, 0);
914
915 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
916
917 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
918/*
919 if(IsCtrlNDPA(VirtualAddress) || IsMgntNDPA(VirtualAddress))
920 {
921 SET_TX_DESC_DATA_RETRY_LIMIT_8812(pDesc, 5);
922 SET_TX_DESC_RETRY_LIMIT_ENABLE_8812(pDesc, 1);
923
924 if(IsMgntNDPA(VirtualAddress))
925 {
926 SET_TX_DESC_NDPA_8812(pDesc, 1);
927 SET_TX_DESC_RTS_SC_8812(pDesc, SCMapping_8812(Adapter, pTcb));
928 }
929 else
930 {
931 SET_TX_DESC_NDPA_8812(pDesc, 2);
932 SET_TX_DESC_RTS_SC_8812(pDesc, SCMapping_8812(Adapter, pTcb));
933 }
934 }*/
935
936 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) (skb->len));
937
938 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping));
939
940 SET_TX_DESC_MACID(pdesc, 0);
941
942 SET_TX_DESC_OWN(pdesc, 1);
943
944 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
945 "H2C Tx Cmd Content\n",
946 pdesc, TX_DESC_SIZE);
947}
948
949void rtl8821ae_set_desc(struct ieee80211_hw * hw, u8 *pdesc, bool istx, u8 desc_name, u8 *val)
950{
951 if (istx == true) {
952 switch (desc_name) {
953 case HW_DESC_OWN:
954 SET_TX_DESC_OWN(pdesc, 1);
955 break;
956 case HW_DESC_TX_NEXTDESC_ADDR:
957 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val);
958 break;
959 default:
960 RT_ASSERT(false, ("ERR txdesc :%d"
961 " not process\n", desc_name));
962 break;
963 }
964 } else {
965 switch (desc_name) {
966 case HW_DESC_RXOWN:
967 SET_RX_DESC_OWN(pdesc, 1);
968 break;
969 case HW_DESC_RXBUFF_ADDR:
970 SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *) val);
971 break;
972 case HW_DESC_RXPKT_LEN:
973 SET_RX_DESC_PKT_LEN(pdesc, *(u32 *) val);
974 break;
975 case HW_DESC_RXERO:
976 SET_RX_DESC_EOR(pdesc, 1);
977 break;
978 default:
979 RT_ASSERT(false, ("ERR rxdesc :%d "
980 "not process\n", desc_name));
981 break;
982 }
983 }
984}
985
986u32 rtl8821ae_get_desc(u8 *pdesc, bool istx, u8 desc_name)
987{
988 u32 ret = 0;
989
990 if (istx == true) {
991 switch (desc_name) {
992 case HW_DESC_OWN:
993 ret = GET_TX_DESC_OWN(pdesc);
994 break;
995 case HW_DESC_TXBUFF_ADDR:
996 ret = GET_TX_DESC_TX_BUFFER_ADDRESS(pdesc);
997 break;
998 default:
999 RT_ASSERT(false, ("ERR txdesc :%d "
1000 "not process\n", desc_name));
1001 break;
1002 }
1003 } else {
1004 switch (desc_name) {
1005 case HW_DESC_OWN:
1006 ret = GET_RX_DESC_OWN(pdesc);
1007 break;
1008 case HW_DESC_RXPKT_LEN:
1009 ret = GET_RX_DESC_PKT_LEN(pdesc);
1010 break;
1011 default:
1012 RT_ASSERT(false, ("ERR rxdesc :%d "
1013 "not process\n", desc_name));
1014 break;
1015 }
1016 }
1017 return ret;
1018}
1019
1020bool rtl8821ae_is_tx_desc_closed(struct ieee80211_hw *hw,
1021 u8 hw_queue, u16 index)
1022{
1023 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1024 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
1025 u8 *entry = (u8 *)(&ring->desc[ring->idx]);
1026 u8 own = (u8) rtl8821ae_get_desc(entry, true, HW_DESC_OWN);
1027
1028 /*
1029 *beacon packet will only use the first
1030 *descriptor defautly,and the own may not
1031 *be cleared by the hardware
1032 */
1033 if (own)
1034 return false;
1035 else
1036 return true;
1037}
1038
1039
1040void rtl8821ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
1041{
1042 struct rtl_priv *rtlpriv = rtl_priv(hw);
1043
1044 if (hw_queue == BEACON_QUEUE) {
1045 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4));
1046 } else {
1047 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG,
1048 BIT(0) << (hw_queue));
1049 }
1050}
diff --git a/drivers/staging/rtl8821ae/rtl8821ae/trx.h b/drivers/staging/rtl8821ae/rtl8821ae/trx.h
new file mode 100644
index 000000000000..da93e5c7ece7
--- /dev/null
+++ b/drivers/staging/rtl8821ae/rtl8821ae/trx.h
@@ -0,0 +1,641 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL8821AE_TRX_H__
31#define __RTL8821AE_TRX_H__
32
33#define TX_DESC_SIZE 40
34#define TX_DESC_AGGR_SUBFRAME_SIZE 32
35
36#define RX_DESC_SIZE 32
37#define RX_DRV_INFO_SIZE_UNIT 8
38
39#define TX_DESC_NEXT_DESC_OFFSET 40
40#define USB_HWDESC_HEADER_LEN 40
41#define CRCLENGTH 4
42
43#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
44 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
45#define SET_TX_DESC_OFFSET(__pdesc, __val) \
46 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
47#define SET_TX_DESC_BMC(__pdesc, __val) \
48 SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
49#define SET_TX_DESC_HTC(__pdesc, __val) \
50 SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
51#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
52 SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
53#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
54 SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
55#define SET_TX_DESC_LINIP(__pdesc, __val) \
56 SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
57#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
58 SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
59#define SET_TX_DESC_GF(__pdesc, __val) \
60 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
61#define SET_TX_DESC_OWN(__pdesc, __val) \
62 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
63
64#define GET_TX_DESC_PKT_SIZE(__pdesc) \
65 LE_BITS_TO_4BYTE(__pdesc, 0, 16)
66#define GET_TX_DESC_OFFSET(__pdesc) \
67 LE_BITS_TO_4BYTE(__pdesc, 16, 8)
68#define GET_TX_DESC_BMC(__pdesc) \
69 LE_BITS_TO_4BYTE(__pdesc, 24, 1)
70#define GET_TX_DESC_HTC(__pdesc) \
71 LE_BITS_TO_4BYTE(__pdesc, 25, 1)
72#define GET_TX_DESC_LAST_SEG(__pdesc) \
73 LE_BITS_TO_4BYTE(__pdesc, 26, 1)
74#define GET_TX_DESC_FIRST_SEG(__pdesc) \
75 LE_BITS_TO_4BYTE(__pdesc, 27, 1)
76#define GET_TX_DESC_LINIP(__pdesc) \
77 LE_BITS_TO_4BYTE(__pdesc, 28, 1)
78#define GET_TX_DESC_NO_ACM(__pdesc) \
79 LE_BITS_TO_4BYTE(__pdesc, 29, 1)
80#define GET_TX_DESC_GF(__pdesc) \
81 LE_BITS_TO_4BYTE(__pdesc, 30, 1)
82#define GET_TX_DESC_OWN(__pdesc) \
83 LE_BITS_TO_4BYTE(__pdesc, 31, 1)
84
85#define SET_TX_DESC_MACID(__pdesc, __val) \
86 SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 7, __val)
87#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
88 SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
89#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
90 SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
91#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
92 SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
93#define SET_TX_DESC_PIFS(__pdesc, __val) \
94 SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
95#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
96 SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 5, __val)
97#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
98 SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
99#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
100 SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val)
101#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
102 SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 5, __val)
103
104
105#define SET_TX_DESC_PAID(__pdesc, __val) \
106 SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 9, __val)
107#define SET_TX_DESC_CCA_RTS(__pdesc, __val) \
108 SET_BITS_TO_LE_4BYTE(__pdesc+8, 10, 2, __val)
109#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
110 SET_BITS_TO_LE_4BYTE(__pdesc+8, 12, 1, __val)
111#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
112 SET_BITS_TO_LE_4BYTE(__pdesc+8, 13, 1, __val)
113#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
114 SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 2, __val)
115#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
116 SET_BITS_TO_LE_4BYTE(__pdesc+8, 16, 1, __val)
117#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
118 SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
119#define SET_TX_DESC_RAW(__pdesc, __val) \
120 SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
121#define SET_TX_DESC_SPE_RPT(__pdesc, __val) \
122 SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
123#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
124 SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
125#define SET_TX_DESC_BT_INT(__pdesc, __val) \
126 SET_BITS_TO_LE_4BYTE(__pdesc+8, 23, 1, __val)
127#define SET_TX_DESC_GID(__pdesc, __val) \
128 SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 6, __val)
129
130
131#define SET_TX_DESC_WHEADER_LEN(__pdesc, __val) \
132 SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 4, __val)
133#define SET_TX_DESC_CHK_EN(__pdesc, __val) \
134 SET_BITS_TO_LE_4BYTE(__pdesc+12, 4, 1, __val)
135#define SET_TX_DESC_EARLY_MODE(__pdesc, __val) \
136 SET_BITS_TO_LE_4BYTE(__pdesc+12, 5, 1, __val)
137#define SET_TX_DESC_HWSEQ_SEL(__pdesc, __val) \
138 SET_BITS_TO_LE_4BYTE(__pdesc+12, 6, 2, __val)
139#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
140 SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 1, __val)
141#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
142 SET_BITS_TO_LE_4BYTE(__pdesc+12, 9, 1, __val)
143#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
144 SET_BITS_TO_LE_4BYTE(__pdesc+12, 10, 1, __val)
145#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
146 SET_BITS_TO_LE_4BYTE(__pdesc+12, 11, 1, __val)
147#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
148 SET_BITS_TO_LE_4BYTE(__pdesc+12, 12, 1, __val)
149#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
150 SET_BITS_TO_LE_4BYTE(__pdesc+12, 13, 1, __val)
151#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
152 SET_BITS_TO_LE_4BYTE(__pdesc+12, 15, 1, __val)
153#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
154 SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 1, __val)
155#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
156 SET_BITS_TO_LE_4BYTE(__pdesc+12, 17, 5, __val)
157#define SET_TX_DESC_NDPA(__pdesc, __val) \
158 SET_BITS_TO_LE_4BYTE(__pdesc+12, 22, 2, __val)
159#define SET_TX_DESC_AMPDU_MAX_TIME(__pdesc, __val) \
160 SET_BITS_TO_LE_4BYTE(__pdesc+12, 24, 8, __val)
161#define SET_TX_DESC_TX_ANT(__pdesc, __val) \
162 SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 4, __val)
163
164#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
165 SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 7, __val)
166#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
167 SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 5, __val)
168#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
169 SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 4, __val)
170#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
171 SET_BITS_TO_LE_4BYTE(__pdesc+16, 17, 1, __val)
172#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
173 SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 6, __val)
174#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
175 SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 5, __val)
176
177
178#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
179 SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 4, __val)
180#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
181 SET_BITS_TO_LE_1BYTE(__pdesc+20, 6, 1, __val)
182#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
183 SET_BITS_TO_LE_4BYTE(__pdesc+20, 5, 2, __val)
184#define SET_TX_DESC_DATA_LDPC(__pdesc, __val) \
185 SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val)
186#define SET_TX_DESC_DATA_STBC(__pdesc, __val) \
187 SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 2, __val)
188#define SET_TX_DESC_CTROL_STBC(__pdesc, __val) \
189 SET_BITS_TO_LE_4BYTE(__pdesc+20, 10, 2, __val)
190#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
191 SET_BITS_TO_LE_4BYTE(__pdesc+20, 12, 1, __val)
192#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
193 SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val)
194
195
196#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
197 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val)
198
199#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
200 LE_BITS_TO_4BYTE(__pdesc+28, 0, 16)
201
202#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
203 SET_BITS_TO_LE_4BYTE(__pdesc+32, 15, 1, __val)
204
205#define SET_TX_DESC_SEQ(__pdesc, __val) \
206 SET_BITS_TO_LE_4BYTE(__pdesc+36, 12, 12, __val)
207
208#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
209 SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
210
211#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
212 LE_BITS_TO_4BYTE(__pdesc+40, 0, 32)
213
214
215#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
216 SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 32, __val)
217
218#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
219 LE_BITS_TO_4BYTE(__pdesc+48, 0, 32)
220
221#define GET_RX_DESC_PKT_LEN(__pdesc) \
222 LE_BITS_TO_4BYTE(__pdesc, 0, 14)
223#define GET_RX_DESC_CRC32(__pdesc) \
224 LE_BITS_TO_4BYTE(__pdesc, 14, 1)
225#define GET_RX_DESC_ICV(__pdesc) \
226 LE_BITS_TO_4BYTE(__pdesc, 15, 1)
227#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
228 LE_BITS_TO_4BYTE(__pdesc, 16, 4)
229#define GET_RX_DESC_SECURITY(__pdesc) \
230 LE_BITS_TO_4BYTE(__pdesc, 20, 3)
231#define GET_RX_DESC_QOS(__pdesc) \
232 LE_BITS_TO_4BYTE(__pdesc, 23, 1)
233#define GET_RX_DESC_SHIFT(__pdesc) \
234 LE_BITS_TO_4BYTE(__pdesc, 24, 2)
235#define GET_RX_DESC_PHYST(__pdesc) \
236 LE_BITS_TO_4BYTE(__pdesc, 26, 1)
237#define GET_RX_DESC_SWDEC(__pdesc) \
238 LE_BITS_TO_4BYTE(__pdesc, 27, 1)
239#define GET_RX_DESC_LS(__pdesc) \
240 LE_BITS_TO_4BYTE(__pdesc, 28, 1)
241#define GET_RX_DESC_FS(__pdesc) \
242 LE_BITS_TO_4BYTE(__pdesc, 29, 1)
243#define GET_RX_DESC_EOR(__pdesc) \
244 LE_BITS_TO_4BYTE(__pdesc, 30, 1)
245#define GET_RX_DESC_OWN(__pdesc) \
246 LE_BITS_TO_4BYTE(__pdesc, 31, 1)
247
248#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
249 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
250#define SET_RX_DESC_EOR(__pdesc, __val) \
251 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
252#define SET_RX_DESC_OWN(__pdesc, __val) \
253 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
254
255#define GET_RX_DESC_MACID(__pdesc) \
256 LE_BITS_TO_4BYTE(__pdesc+4, 0, 7)
257#define GET_RX_DESC_TID(__pdesc) \
258 LE_BITS_TO_4BYTE(__pdesc+4, 8, 4)
259#define GET_RX_DESC_AMSDU(__pdesc) \
260 LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
261#define GET_RX_STATUS_DESC_RXID_MATCH(__pdesc) \
262 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
263#define GET_RX_DESC_PAGGR(__pdesc) \
264 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
265#define GET_RX_DESC_A1_FIT(__pdesc) \
266 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
267#define GET_RX_DESC_CHKERR(__pdesc) \
268 LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
269#define GET_RX_DESC_IPVER(__pdesc) \
270 LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
271#define GET_RX_STATUS_DESC_IS_TCPUDP(__pdesc) \
272 LE_BITS_TO_4BYTE(__pdesc+4, 22, 1)
273#define GET_RX_STATUS_DESC_CHK_VLD(__pdesc) \
274 LE_BITS_TO_4BYTE(__pdesc+4, 23, 1)
275#define GET_RX_DESC_PAM(__pdesc) \
276 LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
277#define GET_RX_DESC_PWR(__pdesc) \
278 LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
279#define GET_RX_DESC_MD(__pdesc) \
280 LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
281#define GET_RX_DESC_MF(__pdesc) \
282 LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
283#define GET_RX_DESC_TYPE(__pdesc) \
284 LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
285#define GET_RX_DESC_MC(__pdesc) \
286 LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
287#define GET_RX_DESC_BC(__pdesc) \
288 LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
289
290
291#define GET_RX_DESC_SEQ(__pdesc) \
292 LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
293#define GET_RX_DESC_FRAG(__pdesc) \
294 LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
295#define GET_RX_STATUS_DESC_RX_IS_QOS(__pdesc) \
296 LE_BITS_TO_4BYTE(__pdesc+8, 16, 1)
297#define GET_RX_STATUS_DESC_WLANHD_IV_LEN(__pdesc) \
298 LE_BITS_TO_4BYTE(__pdesc+8, 18, 6)
299#define GET_RX_STATUS_DESC_RPT_SEL(__pdesc) \
300 LE_BITS_TO_4BYTE(__pdesc+8, 28, 1)
301
302
303#define GET_RX_DESC_RXMCS(__pdesc) \
304 LE_BITS_TO_4BYTE(__pdesc+12, 0, 7)
305#define GET_RX_DESC_RXHT(__pdesc) \
306 LE_BITS_TO_4BYTE(__pdesc+12, 6, 1)
307#define GET_RX_STATUS_DESC_RX_GF(__pdesc) \
308 LE_BITS_TO_4BYTE(__pdesc+12, 7, 1)
309#define GET_RX_DESC_HTC(__pdesc) \
310 LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
311#define GET_RX_STATUS_DESC_EOSP(__pdesc) \
312 LE_BITS_TO_4BYTE( __pdesc+12, 11, 1)
313#define GET_RX_STATUS_DESC_BSSID_FIT(__pdesc) \
314 LE_BITS_TO_4BYTE( __pdesc+12, 12, 2)
315
316#define GET_RX_STATUS_DESC_PATTERN_MATCH(__pdesc) \
317 LE_BITS_TO_4BYTE( __pdesc+12, 29, 1)
318#define GET_RX_STATUS_DESC_UNICAST_MATCH(__pdesc) \
319 LE_BITS_TO_4BYTE( __pdesc+12, 30, 1)
320#define GET_RX_STATUS_DESC_MAGIC_MATCH(__pdesc) \
321 LE_BITS_TO_4BYTE( __pdesc+12, 31, 1)
322
323#define GET_RX_DESC_SPLCP(__pdesc) \
324 LE_BITS_TO_4BYTE(__pdesc+16, 0, 1)
325#define GET_RX_STATUS_DESC_LDPC(__pdesc) \
326 LE_BITS_TO_4BYTE(__pdesc+16, 1, 1)
327#define GET_RX_STATUS_DESC_STBC(__pdesc) \
328 LE_BITS_TO_4BYTE(__pdesc+16, 2, 1)
329#define GET_RX_DESC_BW(__pdesc) \
330 LE_BITS_TO_4BYTE(__pdesc+16, 4, 2)
331
332#define GET_RX_DESC_TSFL(__pdesc) \
333 LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
334
335#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
336 LE_BITS_TO_4BYTE(__pdesc+24, 0, 32)
337#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
338 LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
339
340#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
341 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
342#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
343 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
344
345
346/* TX report 2 format in Rx desc*/
347
348#define GET_RX_RPT2_DESC_PKT_LEN(__pRxStatusDesc) \
349 LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9)
350#define GET_RX_RPT2_DESC_MACID_VALID_1(__pRxStatusDesc) \
351 LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32)
352#define GET_RX_RPT2_DESC_MACID_VALID_2(__pRxStatusDesc) \
353 LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
354
355#define SET_EARLYMODE_PKTNUM(__paddr, __value) \
356 SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __value)
357#define SET_EARLYMODE_LEN0(__paddr, __value) \
358 SET_BITS_TO_LE_4BYTE(__paddr, 4, 12, __value)
359#define SET_EARLYMODE_LEN1(__paddr, __value) \
360 SET_BITS_TO_LE_4BYTE(__paddr, 16, 12, __value)
361#define SET_EARLYMODE_LEN2_1(__paddr, __value) \
362 SET_BITS_TO_LE_4BYTE(__paddr, 28, 4, __value)
363#define SET_EARLYMODE_LEN2_2(__paddr, __value) \
364 SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 8, __value)
365#define SET_EARLYMODE_LEN3(__paddr, __value) \
366 SET_BITS_TO_LE_4BYTE(__paddr+4, 8, 12, __value)
367#define SET_EARLYMODE_LEN4(__paddr, __value) \
368 SET_BITS_TO_LE_4BYTE(__paddr+4, 20, 12, __value)
369
370#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
371do { \
372 if(_size > TX_DESC_NEXT_DESC_OFFSET) \
373 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
374 else \
375 memset(__pdesc, 0, _size); \
376} while (0);
377
378#define RX_HAL_IS_CCK_RATE(rxmcs)\
379 (rxmcs == DESC_RATE1M ||\
380 rxmcs == DESC_RATE2M ||\
381 rxmcs == DESC_RATE5_5M ||\
382 rxmcs == DESC_RATE11M)
383
384#define IS_LITTLE_ENDIAN 1
385
386struct phy_rx_agc_info_t {
387 #if IS_LITTLE_ENDIAN
388 u8 gain:7,trsw:1;
389 #else
390 u8 trsw:1,gain:7;
391 #endif
392};
393struct phy_status_rpt{
394 struct phy_rx_agc_info_t path_agc[2];
395 u8 ch_corr[2];
396 u8 cck_sig_qual_ofdm_pwdb_all;
397 u8 cck_agc_rpt_ofdm_cfosho_a;
398 u8 cck_rpt_b_ofdm_cfosho_b;
399 u8 rsvd_1;//ch_corr_msb;
400 u8 noise_power_db_msb;
401 u8 path_cfotail[2];
402 u8 pcts_mask[2];
403 u8 stream_rxevm[2];
404 u8 path_rxsnr[2];
405 u8 noise_power_db_lsb;
406 u8 rsvd_2[3];
407 u8 stream_csi[2];
408 u8 stream_target_csi[2];
409 u8 sig_evm;
410 u8 rsvd_3;
411#if IS_LITTLE_ENDIAN
412 u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
413 u8 sgi_en:1;
414 u8 rxsc:2;
415 u8 idle_long:1;
416 u8 r_ant_train_en:1;
417 u8 ant_sel_b:1;
418 u8 ant_sel:1;
419#else /* _BIG_ENDIAN_ */
420 u8 ant_sel:1;
421 u8 ant_sel_b:1;
422 u8 r_ant_train_en:1;
423 u8 idle_long:1;
424 u8 rxsc:2;
425 u8 sgi_en:1;
426 u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
427#endif
428}__packed;
429
430struct rx_fwinfo_8821ae {
431 u8 gain_trsw[4];
432 u8 pwdb_all;
433 u8 cfosho[4];
434 u8 cfotail[4];
435 char rxevm[2];
436 char rxsnr[4];
437 u8 pdsnr[2];
438 u8 csi_current[2];
439 u8 csi_target[2];
440 u8 sigevm;
441 u8 max_ex_pwr;
442 u8 ex_intf_flag:1;
443 u8 sgi_en:1;
444 u8 rxsc:2;
445 u8 reserve:4;
446} __packed;
447
448struct tx_desc_8821ae {
449 u32 pktsize:16;
450 u32 offset:8;
451 u32 bmc:1;
452 u32 htc:1;
453 u32 lastseg:1;
454 u32 firstseg:1;
455 u32 linip:1;
456 u32 noacm:1;
457 u32 gf:1;
458 u32 own:1;
459
460 u32 macid:6;
461 u32 rsvd0:2;
462 u32 queuesel:5;
463 u32 rd_nav_ext:1;
464 u32 lsig_txop_en:1;
465 u32 pifs:1;
466 u32 rateid:4;
467 u32 nav_usehdr:1;
468 u32 en_descid:1;
469 u32 sectype:2;
470 u32 pktoffset:8;
471
472 u32 rts_rc:6;
473 u32 data_rc:6;
474 u32 agg_en:1;
475 u32 rdg_en:1;
476 u32 bar_retryht:2;
477 u32 agg_break:1;
478 u32 morefrag:1;
479 u32 raw:1;
480 u32 ccx:1;
481 u32 ampdudensity:3;
482 u32 bt_int:1;
483 u32 ant_sela:1;
484 u32 ant_selb:1;
485 u32 txant_cck:2;
486 u32 txant_l:2;
487 u32 txant_ht:2;
488
489 u32 nextheadpage:8;
490 u32 tailpage:8;
491 u32 seq:12;
492 u32 cpu_handle:1;
493 u32 tag1:1;
494 u32 trigger_int:1;
495 u32 hwseq_en:1;
496
497 u32 rtsrate:5;
498 u32 apdcfe:1;
499 u32 qos:1;
500 u32 hwseq_ssn:1;
501 u32 userrate:1;
502 u32 dis_rtsfb:1;
503 u32 dis_datafb:1;
504 u32 cts2self:1;
505 u32 rts_en:1;
506 u32 hwrts_en:1;
507 u32 portid:1;
508 u32 pwr_status:3;
509 u32 waitdcts:1;
510 u32 cts2ap_en:1;
511 u32 txsc:2;
512 u32 stbc:2;
513 u32 txshort:1;
514 u32 txbw:1;
515 u32 rtsshort:1;
516 u32 rtsbw:1;
517 u32 rtssc:2;
518 u32 rtsstbc:2;
519
520 u32 txrate:6;
521 u32 shortgi:1;
522 u32 ccxt:1;
523 u32 txrate_fb_lmt:5;
524 u32 rtsrate_fb_lmt:4;
525 u32 retrylmt_en:1;
526 u32 txretrylmt:6;
527 u32 usb_txaggnum:8;
528
529 u32 txagca:5;
530 u32 txagcb:5;
531 u32 usemaxlen:1;
532 u32 maxaggnum:5;
533 u32 mcsg1maxlen:4;
534 u32 mcsg2maxlen:4;
535 u32 mcsg3maxlen:4;
536 u32 mcs7sgimaxlen:4;
537
538 u32 txbuffersize:16;
539 u32 sw_offset30:8;
540 u32 sw_offset31:4;
541 u32 rsvd1:1;
542 u32 antsel_c:1;
543 u32 null_0:1;
544 u32 null_1:1;
545
546 u32 txbuffaddr;
547 u32 txbufferaddr64;
548 u32 nextdescaddress;
549 u32 nextdescaddress64;
550
551 u32 reserve_pass_pcie_mm_limit[4];
552} __packed;
553
554struct rx_desc_8821ae {
555 u32 length:14;
556 u32 crc32:1;
557 u32 icverror:1;
558 u32 drv_infosize:4;
559 u32 security:3;
560 u32 qos:1;
561 u32 shift:2;
562 u32 phystatus:1;
563 u32 swdec:1;
564 u32 lastseg:1;
565 u32 firstseg:1;
566 u32 eor:1;
567 u32 own:1;
568
569 u32 macid:6;
570 u32 tid:4;
571 u32 hwrsvd:5;
572 u32 paggr:1;
573 u32 faggr:1;
574 u32 a1_fit:4;
575 u32 a2_fit:4;
576 u32 pam:1;
577 u32 pwr:1;
578 u32 moredata:1;
579 u32 morefrag:1;
580 u32 type:2;
581 u32 mc:1;
582 u32 bc:1;
583
584 u32 seq:12;
585 u32 frag:4;
586 u32 nextpktlen:14;
587 u32 nextind:1;
588 u32 rsvd:1;
589
590 u32 rxmcs:6;
591 u32 rxht:1;
592 u32 amsdu:1;
593 u32 splcp:1;
594 u32 bandwidth:1;
595 u32 htc:1;
596 u32 tcpchk_rpt:1;
597 u32 ipcchk_rpt:1;
598 u32 tcpchk_valid:1;
599 u32 hwpcerr:1;
600 u32 hwpcind:1;
601 u32 iv0:16;
602
603 u32 iv1;
604
605 u32 tsfl;
606
607 u32 bufferaddress;
608 u32 bufferaddress64;
609
610} __packed;
611
612/*<delete in kernel start>*/
613#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
614void rtl8821ae_tx_fill_desc(struct ieee80211_hw *hw,
615 struct ieee80211_hdr *hdr, u8 *pdesc_tx, u8 *txbd,
616 struct ieee80211_tx_info *info, struct sk_buff *skb,
617 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
618#else
619/*<delete in kernel end>*/
620void rtl8821ae_tx_fill_desc(struct ieee80211_hw *hw,
621 struct ieee80211_hdr *hdr, u8 *pdesc_tx, u8 *txbd,
622 struct ieee80211_tx_info *info,
623 struct ieee80211_sta *sta,
624 struct sk_buff *skb,
625 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
626/*<delete in kernel start>*/
627#endif
628/*<delete in kernel end>*/
629bool rtl8821ae_rx_query_desc(struct ieee80211_hw *hw,
630 struct rtl_stats *status,
631 struct ieee80211_rx_status *rx_status,
632 u8 *pdesc, struct sk_buff *skb);
633void rtl8821ae_set_desc(struct ieee80211_hw * hw, u8 *pdesc, bool istx, u8 desc_name, u8 *val);
634u32 rtl8821ae_get_desc(u8 *pdesc, bool istx, u8 desc_name);
635bool rtl8821ae_is_tx_desc_closed(struct ieee80211_hw *hw,
636 u8 hw_queue, u16 index);
637void rtl8821ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
638void rtl8821ae_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
639 bool b_firstseg, bool b_lastseg,
640 struct sk_buff *skb);
641#endif
diff --git a/drivers/staging/rtl8821ae/stats.c b/drivers/staging/rtl8821ae/stats.c
new file mode 100644
index 000000000000..a20c0f8f65ec
--- /dev/null
+++ b/drivers/staging/rtl8821ae/stats.c
@@ -0,0 +1,283 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29#include "wifi.h"
30#include "stats.h"
31#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
32#include <linux/export.h>
33#endif
34
35u8 rtl_query_rxpwrpercentage(char antpower)
36{
37 if ((antpower <= -100) || (antpower >= 20))
38 return 0;
39 else if (antpower >= 0)
40 return 100;
41 else
42 return (100 + antpower);
43}
44//EXPORT_SYMBOL(rtl_query_rxpwrpercentage);
45
46u8 rtl_evm_db_to_percentage(char value)
47{
48 char ret_val;
49 ret_val = value;
50
51 if (ret_val >= 0)
52 ret_val = 0;
53 if (ret_val <= -33)
54 ret_val = -33;
55 ret_val = 0 - ret_val;
56 ret_val *= 3;
57 if (ret_val == 99)
58 ret_val = 100;
59
60 return ret_val;
61}
62//EXPORT_SYMBOL(rtl_evm_db_to_percentage);
63
64long rtl_translate_todbm(struct ieee80211_hw *hw,
65 u8 signal_strength_index)
66{
67 long signal_power;
68
69 signal_power = (long)((signal_strength_index + 1) >> 1);
70 signal_power -= 95;
71 return signal_power;
72}
73
74long rtl_signal_scale_mapping(struct ieee80211_hw *hw, long currsig)
75{
76 long retsig;
77
78 if (currsig >= 61 && currsig <= 100)
79 retsig = 90 + ((currsig - 60) / 4);
80 else if (currsig >= 41 && currsig <= 60)
81 retsig = 78 + ((currsig - 40) / 2);
82 else if (currsig >= 31 && currsig <= 40)
83 retsig = 66 + (currsig - 30);
84 else if (currsig >= 21 && currsig <= 30)
85 retsig = 54 + (currsig - 20);
86 else if (currsig >= 5 && currsig <= 20)
87 retsig = 42 + (((currsig - 5) * 2) / 3);
88 else if (currsig == 4)
89 retsig = 36;
90 else if (currsig == 3)
91 retsig = 27;
92 else if (currsig == 2)
93 retsig = 18;
94 else if (currsig == 1)
95 retsig = 9;
96 else
97 retsig = currsig;
98
99 return retsig;
100}
101//EXPORT_SYMBOL(rtl_signal_scale_mapping);
102
103void rtl_process_ui_rssi(struct ieee80211_hw *hw, struct rtl_stats *pstatus)
104{
105 struct rtl_priv *rtlpriv = rtl_priv(hw);
106 struct rtl_phy *rtlphy = &(rtlpriv->phy);
107 u8 rfpath;
108 u32 last_rssi, tmpval;
109
110 if (!pstatus->b_packet_toself && !pstatus->b_packet_beacon)
111 return;
112
113 rtlpriv->stats.pwdb_all_cnt += pstatus->rx_pwdb_all;
114 rtlpriv->stats.rssi_calculate_cnt++;
115
116 if (rtlpriv->stats.ui_rssi.total_num++ >= PHY_RSSI_SLID_WIN_MAX) {
117 rtlpriv->stats.ui_rssi.total_num = PHY_RSSI_SLID_WIN_MAX;
118 last_rssi = rtlpriv->stats.ui_rssi.elements[
119 rtlpriv->stats.ui_rssi.index];
120 rtlpriv->stats.ui_rssi.total_val -= last_rssi;
121 }
122 rtlpriv->stats.ui_rssi.total_val += pstatus->signalstrength;
123 rtlpriv->stats.ui_rssi.elements[rtlpriv->stats.ui_rssi.index++] =
124 pstatus->signalstrength;
125 if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
126 rtlpriv->stats.ui_rssi.index = 0;
127 tmpval = rtlpriv->stats.ui_rssi.total_val /
128 rtlpriv->stats.ui_rssi.total_num;
129 rtlpriv->stats.signal_strength = rtl_translate_todbm(hw,
130 (u8) tmpval);
131 pstatus->rssi = rtlpriv->stats.signal_strength;
132
133 if (pstatus->b_is_cck)
134 return;
135
136 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
137 rfpath++) {
138 if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
139 rtlpriv->stats.rx_rssi_percentage[rfpath] =
140 pstatus->rx_mimo_signalstrength[rfpath];
141
142 }
143 if (pstatus->rx_mimo_signalstrength[rfpath] >
144 rtlpriv->stats.rx_rssi_percentage[rfpath]) {
145 rtlpriv->stats.rx_rssi_percentage[rfpath] =
146 ((rtlpriv->stats.rx_rssi_percentage[rfpath] *
147 (RX_SMOOTH_FACTOR - 1)) +
148 (pstatus->rx_mimo_signalstrength[rfpath])) /
149 (RX_SMOOTH_FACTOR);
150 rtlpriv->stats.rx_rssi_percentage[rfpath] =
151 rtlpriv->stats.rx_rssi_percentage[rfpath] + 1;
152 } else {
153 rtlpriv->stats.rx_rssi_percentage[rfpath] =
154 ((rtlpriv->stats.rx_rssi_percentage[rfpath] *
155 (RX_SMOOTH_FACTOR - 1)) +
156 (pstatus->rx_mimo_signalstrength[rfpath])) /
157 (RX_SMOOTH_FACTOR);
158 }
159 rtlpriv->stats.rx_snr_db[rfpath] = pstatus->rx_snr[rfpath];
160 rtlpriv->stats.rx_evm_dbm[rfpath] =
161 pstatus->rx_mimo_evm_dbm[rfpath];
162 rtlpriv->stats.rx_cfo_short[rfpath] =
163 pstatus->cfo_short[rfpath];
164 rtlpriv->stats.rx_cfo_tail[rfpath] = pstatus->cfo_tail[rfpath];
165 }
166}
167
168static void rtl_update_rxsignalstatistics(struct ieee80211_hw *hw,
169 struct rtl_stats *pstatus)
170{
171 struct rtl_priv *rtlpriv = rtl_priv(hw);
172 int weighting = 0;
173
174 if (rtlpriv->stats.recv_signal_power == 0)
175 rtlpriv->stats.recv_signal_power = pstatus->recvsignalpower;
176 if (pstatus->recvsignalpower > rtlpriv->stats.recv_signal_power)
177 weighting = 5;
178 else if (pstatus->recvsignalpower < rtlpriv->stats.recv_signal_power)
179 weighting = (-5);
180 rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power *
181 5 + pstatus->recvsignalpower + weighting) / 6;
182}
183
184static void rtl_process_pwdb(struct ieee80211_hw *hw, struct rtl_stats *pstatus)
185{
186 struct rtl_priv *rtlpriv = rtl_priv(hw);
187 struct rtl_sta_info *drv_priv = NULL;
188 struct ieee80211_sta *sta = NULL;
189 long undecorated_smoothed_pwdb;
190
191 rcu_read_lock();
192 if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
193 sta = rtl_find_sta(hw, pstatus->psaddr);
194
195 /* adhoc or ap mode */
196 if (sta) {
197 drv_priv = (struct rtl_sta_info *) sta->drv_priv;
198 undecorated_smoothed_pwdb =
199 drv_priv->rssi_stat.undecorated_smoothed_pwdb;
200 } else {
201 undecorated_smoothed_pwdb =
202 rtlpriv->dm.undecorated_smoothed_pwdb;
203 }
204
205 if (undecorated_smoothed_pwdb < 0)
206 undecorated_smoothed_pwdb = pstatus->rx_pwdb_all;
207 if (pstatus->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
208 undecorated_smoothed_pwdb = (((undecorated_smoothed_pwdb) *
209 (RX_SMOOTH_FACTOR - 1)) +
210 (pstatus->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
211 undecorated_smoothed_pwdb = undecorated_smoothed_pwdb + 1;
212 } else {
213 undecorated_smoothed_pwdb = (((undecorated_smoothed_pwdb) *
214 (RX_SMOOTH_FACTOR - 1)) +
215 (pstatus->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
216 }
217
218 if(sta) {
219 drv_priv->rssi_stat.undecorated_smoothed_pwdb =
220 undecorated_smoothed_pwdb;
221 } else {
222 rtlpriv->dm.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb;
223 }
224 rcu_read_unlock();
225
226 rtl_update_rxsignalstatistics(hw, pstatus);
227}
228
229static void rtl_process_ui_link_quality(struct ieee80211_hw *hw,
230 struct rtl_stats *pstatus)
231{
232 struct rtl_priv *rtlpriv = rtl_priv(hw);
233 u32 last_evm, n_stream, tmpval;
234
235 if (pstatus->signalquality == 0)
236 return;
237
238 if (rtlpriv->stats.ui_link_quality.total_num++ >=
239 PHY_LINKQUALITY_SLID_WIN_MAX) {
240 rtlpriv->stats.ui_link_quality.total_num =
241 PHY_LINKQUALITY_SLID_WIN_MAX;
242 last_evm = rtlpriv->stats.ui_link_quality.elements[
243 rtlpriv->stats.ui_link_quality.index];
244 rtlpriv->stats.ui_link_quality.total_val -= last_evm;
245 }
246 rtlpriv->stats.ui_link_quality.total_val += pstatus->signalquality;
247 rtlpriv->stats.ui_link_quality.elements[
248 rtlpriv->stats.ui_link_quality.index++] =
249 pstatus->signalquality;
250 if (rtlpriv->stats.ui_link_quality.index >=
251 PHY_LINKQUALITY_SLID_WIN_MAX)
252 rtlpriv->stats.ui_link_quality.index = 0;
253 tmpval = rtlpriv->stats.ui_link_quality.total_val /
254 rtlpriv->stats.ui_link_quality.total_num;
255 rtlpriv->stats.signal_quality = tmpval;
256 rtlpriv->stats.last_sigstrength_inpercent = tmpval;
257 for (n_stream = 0; n_stream < 2; n_stream++) {
258 if (pstatus->rx_mimo_signalquality[n_stream] != -1) {
259 if (rtlpriv->stats.rx_evm_percentage[n_stream] == 0) {
260 rtlpriv->stats.rx_evm_percentage[n_stream] =
261 pstatus->rx_mimo_signalquality[n_stream];
262 }
263 rtlpriv->stats.rx_evm_percentage[n_stream] =
264 ((rtlpriv->stats.rx_evm_percentage[n_stream]
265 * (RX_SMOOTH_FACTOR - 1)) +
266 (pstatus->rx_mimo_signalquality[n_stream] * 1)) /
267 (RX_SMOOTH_FACTOR);
268 }
269 }
270}
271
272void rtl_process_phyinfo(struct ieee80211_hw *hw, u8 *buffer,
273 struct rtl_stats *pstatus)
274{
275
276 if (!pstatus->b_packet_matchbssid)
277 return;
278
279 rtl_process_ui_rssi(hw, pstatus);
280 rtl_process_pwdb(hw, pstatus);
281 rtl_process_ui_link_quality(hw, pstatus);
282}
283//EXPORT_SYMBOL(rtl_process_phyinfo);
diff --git a/drivers/staging/rtl8821ae/stats.h b/drivers/staging/rtl8821ae/stats.h
new file mode 100644
index 000000000000..d69d0cfd7e14
--- /dev/null
+++ b/drivers/staging/rtl8821ae/stats.h
@@ -0,0 +1,46 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_STATS_H__
31#define __RTL_STATS_H__
32
33#define PHY_RSSI_SLID_WIN_MAX 100
34#define PHY_LINKQUALITY_SLID_WIN_MAX 20
35#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
36
37/* Rx smooth factor */
38#define RX_SMOOTH_FACTOR 20
39
40u8 rtl_query_rxpwrpercentage(char antpower);
41u8 rtl_evm_db_to_percentage(char value);
42long rtl_signal_scale_mapping(struct ieee80211_hw *hw, long currsig);
43void rtl_process_phyinfo(struct ieee80211_hw *hw, u8 *buffer,
44 struct rtl_stats *pstatus);
45
46#endif
diff --git a/drivers/staging/rtl8821ae/wifi.h b/drivers/staging/rtl8821ae/wifi.h
new file mode 100644
index 000000000000..cfe88a1efd55
--- /dev/null
+++ b/drivers/staging/rtl8821ae/wifi.h
@@ -0,0 +1,2532 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL_WIFI_H__
31#define __RTL_WIFI_H__
32
33#include <linux/interrupt.h>
34#include <linux/sched.h>
35#include <linux/firmware.h>
36#include <linux/version.h>
37#include <linux/etherdevice.h>
38#include <net/mac80211.h>
39#include "debug.h"
40
41
42#define RF_CHANGE_BY_INIT 0
43#define RF_CHANGE_BY_IPS BIT(28)
44#define RF_CHANGE_BY_PS BIT(29)
45#define RF_CHANGE_BY_HW BIT(30)
46#define RF_CHANGE_BY_SW BIT(31)
47
48#define IQK_ADDA_REG_NUM 16
49#define IQK_MAC_REG_NUM 4
50#define IQK_THRESHOLD 8
51
52#define MAX_KEY_LEN 61
53#define KEY_BUF_SIZE 5
54
55/* QoS related. */
56/*aci: 0x00 Best Effort*/
57/*aci: 0x01 Background*/
58/*aci: 0x10 Video*/
59/*aci: 0x11 Voice*/
60/*Max: define total number.*/
61#define AC0_BE 0
62#define AC1_BK 1
63#define AC2_VI 2
64#define AC3_VO 3
65#define AC_MAX 4
66#define QOS_QUEUE_NUM 4
67#define RTL_MAC80211_NUM_QUEUE 5
68
69#define QBSS_LOAD_SIZE 5
70#define MAX_WMMELE_LENGTH 64
71
72#define TOTAL_CAM_ENTRY 32
73
74/*slot time for 11g. */
75#define RTL_SLOT_TIME_9 9
76#define RTL_SLOT_TIME_20 20
77
78/*related with tcp/ip. */
79/*if_ehther.h*/
80#define ETH_P_PAE 0x888E /*Port Access Entity
81 *(IEEE 802.1X) */
82#define ETH_P_IP 0x0800 /*Internet Protocol packet */
83#define ETH_P_ARP 0x0806 /*Address Resolution packet */
84#define SNAP_SIZE 6
85#define PROTOC_TYPE_SIZE 2
86
87/*related with 802.11 frame*/
88#define MAC80211_3ADDR_LEN 24
89#define MAC80211_4ADDR_LEN 30
90
91#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max
92 * channel number */
93#define CHANNEL_MAX_NUMBER_2G 14
94#define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
95 *"phy_GetChnlGroup8812A" and
96 * "Hal_ReadTxPowerInfo8812A"*/
97#define CHANNEL_MAX_NUMBER_5G_80M 7
98#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, ch4~9, ch10~14
99 * total three groups */
100#define MAX_PG_GROUP 13
101#define CHANNEL_GROUP_MAX_2G 3
102#define CHANNEL_GROUP_IDX_5GL 3
103#define CHANNEL_GROUP_IDX_5GM 6
104#define CHANNEL_GROUP_IDX_5GH 9
105#define CHANNEL_GROUP_MAX_5G 9
106#define CHANNEL_MAX_NUMBER_2G 14
107#define AVG_THERMAL_NUM 8
108#define AVG_THERMAL_NUM_92E 4
109#define AVG_THERMAL_NUM_88E 4
110#define AVG_THERMAL_NUM_8723BE 4
111#define MAX_TID_COUNT 9
112#define MAX_NUM_RATES 264
113
114/*for 88E use*/
115/*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
116#define MAX_TX_COUNT 4
117#define MAX_RF_PATH 4
118#define MAX_CHNL_GROUP_24G 6
119#define MAX_CHNL_GROUP_5G 14
120
121/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
122#define MAX_TX_QUEUE 9
123
124#define TX_PWR_BY_RATE_NUM_BAND 2
125#define TX_PWR_BY_RATE_NUM_RF 4
126#define TX_PWR_BY_RATE_NUM_SECTION 12
127#define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
128#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
129
130#define DELTA_SWINGIDX_SIZE 30
131#define BAND_NUM 3
132/*Now, it's just for 8192ee
133 *not OK yet, keep it 0*/
134#define DMA_IS_64BIT 0
135#define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
136
137struct txpower_info_2g {
138 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
139 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
140 /*If only one tx, only BW20 and OFDM are used.*/
141 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
142 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
143 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
144 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
145};
146
147struct txpower_info_5g {
148 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
149 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
150 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
151 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
152 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
153 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
154 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
155};
156
157
158/* for early mode */
159#define EM_HDR_LEN 8
160#define FCS_LEN 4
161
162#define MAX_VIRTUAL_MAC 1
163
164enum rf_tx_num {
165 RF_1TX = 0,
166 RF_2TX,
167 RF_MAX_TX_NUM,
168 RF_TX_NUM_NONIMPLEMENT,
169};
170
171enum rate_section {
172 CCK = 0,
173 OFDM,
174 HT_MCS0_MCS7,
175 HT_MCS8_MCS15,
176 VHT_1SSMCS0_1SSMCS9,
177 VHT_2SSMCS0_2SSMCS9,
178};
179
180enum intf_type {
181 INTF_PCI = 0,
182 INTF_USB = 1,
183};
184
185enum radio_path {
186 RF90_PATH_A = 0,
187 RF90_PATH_B = 1,
188 RF90_PATH_C = 2,
189 RF90_PATH_D = 3,
190};
191
192enum rt_eeprom_type {
193 EEPROM_93C46,
194 EEPROM_93C56,
195 EEPROM_BOOT_EFUSE,
196};
197
198enum rtl_status {
199 RTL_STATUS_INTERFACE_START = 0,
200};
201
202enum hardware_type {
203 HARDWARE_TYPE_RTL8192E,
204 HARDWARE_TYPE_RTL8192U,
205 HARDWARE_TYPE_RTL8192SE,
206 HARDWARE_TYPE_RTL8192SU,
207 HARDWARE_TYPE_RTL8192CE,
208 HARDWARE_TYPE_RTL8192CU,
209 HARDWARE_TYPE_RTL8192DE,
210 HARDWARE_TYPE_RTL8192DU,
211 HARDWARE_TYPE_RTL8723AE,
212 HARDWARE_TYPE_RTL8188EE,
213 HARDWARE_TYPE_RTL8723BE,
214 HARDWARE_TYPE_RTL8192EE,
215 HARDWARE_TYPE_RTL8821AE,
216 HARDWARE_TYPE_RTL8812AE,
217 /* keep it last */
218 HARDWARE_TYPE_NUM
219};
220
221enum scan_operation_backup_opt {
222 SCAN_OPT_BACKUP_BAND0=0,
223 SCAN_OPT_BACKUP_BAND1,
224 SCAN_OPT_RESTORE,
225 SCAN_OPT_MAX
226};
227
228/*RF state.*/
229enum rf_pwrstate {
230 ERFON,
231 ERFSLEEP,
232 ERFOFF
233};
234
235struct bb_reg_def {
236 u32 rfintfs;
237 u32 rfintfi;
238 u32 rfintfo;
239 u32 rfintfe;
240 u32 rf3wire_offset;
241 u32 rflssi_select;
242 u32 rftxgain_stage;
243 u32 rfhssi_para1;
244 u32 rfhssi_para2;
245 u32 rfswitch_control;
246 u32 rfagc_control1;
247 u32 rfagc_control2;
248 u32 rfrxiq_imbalance;
249 u32 rfrx_afe;
250 u32 rftxiq_imbalance;
251 u32 rftx_afe;
252 u32 rflssi_readback;
253 u32 rflssi_readbackpi;
254};
255
256enum io_type {
257 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
258 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
259 IO_CMD_RESUME_DM_BY_SCAN = 2,
260};
261
262enum hw_variables {
263 HW_VAR_ETHER_ADDR,
264 HW_VAR_MULTICAST_REG,
265 HW_VAR_BASIC_RATE,
266 HW_VAR_BSSID,
267 HW_VAR_MEDIA_STATUS,
268 HW_VAR_SECURITY_CONF,
269 HW_VAR_BEACON_INTERVAL,
270 HW_VAR_ATIM_WINDOW,
271 HW_VAR_LISTEN_INTERVAL,
272 HW_VAR_CS_COUNTER,
273 HW_VAR_DEFAULTKEY0,
274 HW_VAR_DEFAULTKEY1,
275 HW_VAR_DEFAULTKEY2,
276 HW_VAR_DEFAULTKEY3,
277 HW_VAR_SIFS,
278 HW_VAR_DIFS,
279 HW_VAR_EIFS,
280 HW_VAR_SLOT_TIME,
281 HW_VAR_ACK_PREAMBLE,
282 HW_VAR_CW_CONFIG,
283 HW_VAR_CW_VALUES,
284 HW_VAR_RATE_FALLBACK_CONTROL,
285 HW_VAR_CONTENTION_WINDOW,
286 HW_VAR_RETRY_COUNT,
287 HW_VAR_TR_SWITCH,
288 HW_VAR_COMMAND,
289 HW_VAR_WPA_CONFIG,
290 HW_VAR_AMPDU_MIN_SPACE,
291 HW_VAR_SHORTGI_DENSITY,
292 HW_VAR_AMPDU_FACTOR,
293 HW_VAR_MCS_RATE_AVAILABLE,
294 HW_VAR_AC_PARAM,
295 HW_VAR_ACM_CTRL,
296 HW_VAR_DIS_Req_Qsize,
297 HW_VAR_CCX_CHNL_LOAD,
298 HW_VAR_CCX_NOISE_HISTOGRAM,
299 HW_VAR_CCX_CLM_NHM,
300 HW_VAR_TxOPLimit,
301 HW_VAR_TURBO_MODE,
302 HW_VAR_RF_STATE,
303 HW_VAR_RF_OFF_BY_HW,
304 HW_VAR_BUS_SPEED,
305 HW_VAR_SET_DEV_POWER,
306
307 HW_VAR_RCR,
308 HW_VAR_RATR_0,
309 HW_VAR_RRSR,
310 HW_VAR_CPU_RST,
311 HW_VAR_CECHK_BSSID,
312 HW_VAR_LBK_MODE,
313 HW_VAR_AES_11N_FIX,
314 HW_VAR_USB_RX_AGGR,
315 HW_VAR_USER_CONTROL_TURBO_MODE,
316 HW_VAR_RETRY_LIMIT,
317 HW_VAR_INIT_TX_RATE,
318 HW_VAR_TX_RATE_REG,
319 HW_VAR_EFUSE_USAGE,
320 HW_VAR_EFUSE_BYTES,
321 HW_VAR_AUTOLOAD_STATUS,
322 HW_VAR_RF_2R_DISABLE,
323 HW_VAR_SET_RPWM,
324 HW_VAR_H2C_FW_PWRMODE,
325 HW_VAR_H2C_FW_JOINBSSRPT,
326 HW_VAR_H2C_FW_MEDIASTATUSRPT,
327 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
328 HW_VAR_FW_PSMODE_STATUS,
329 HW_VAR_RESUME_CLK_ON,
330 HW_VAR_FW_LPS_ACTION,
331 HW_VAR_1X1_RECV_COMBINE,
332 HW_VAR_STOP_SEND_BEACON,
333 HW_VAR_TSF_TIMER,
334 HW_VAR_IO_CMD,
335
336 HW_VAR_RF_RECOVERY,
337 HW_VAR_H2C_FW_UPDATE_GTK,
338 HW_VAR_WF_MASK,
339 HW_VAR_WF_CRC,
340 HW_VAR_WF_IS_MAC_ADDR,
341 HW_VAR_H2C_FW_OFFLOAD,
342 HW_VAR_RESET_WFCRC,
343
344 HW_VAR_HANDLE_FW_C2H,
345 HW_VAR_DL_FW_RSVD_PAGE,
346 HW_VAR_AID,
347 HW_VAR_HW_SEQ_ENABLE,
348 HW_VAR_CORRECT_TSF,
349 HW_VAR_BCN_VALID,
350 HW_VAR_FWLPS_RF_ON,
351 HW_VAR_DUAL_TSF_RST,
352 HW_VAR_SWITCH_EPHY_WoWLAN,
353 HW_VAR_INT_MIGRATION,
354 HW_VAR_INT_AC,
355 HW_VAR_RF_TIMING,
356
357 HAL_DEF_WOWLAN,
358 HW_VAR_MRC,
359 HW_VAR_KEEP_ALIVE,
360 HW_VAR_NAV_UPPER,
361};
362
363enum rt_media_status {
364 RT_MEDIA_DISCONNECT = 0,
365 RT_MEDIA_CONNECT = 1
366};
367
368enum rt_oem_id {
369 RT_CID_DEFAULT = 0,
370 RT_CID_8187_ALPHA0 = 1,
371 RT_CID_8187_SERCOMM_PS = 2,
372 RT_CID_8187_HW_LED = 3,
373 RT_CID_8187_NETGEAR = 4,
374 RT_CID_WHQL = 5,
375 RT_CID_819x_CAMEO = 6,
376 RT_CID_819x_RUNTOP = 7,
377 RT_CID_819x_Senao = 8,
378 RT_CID_TOSHIBA = 9,
379 RT_CID_819x_Netcore = 10,
380 RT_CID_Nettronix = 11,
381 RT_CID_DLINK = 12,
382 RT_CID_PRONET = 13,
383 RT_CID_COREGA = 14,
384 RT_CID_819x_ALPHA = 15,
385 RT_CID_819x_Sitecom = 16,
386 RT_CID_CCX = 17,
387 RT_CID_819x_Lenovo = 18,
388 RT_CID_819x_QMI = 19,
389 RT_CID_819x_Edimax_Belkin = 20,
390 RT_CID_819x_Sercomm_Belkin = 21,
391 RT_CID_819x_CAMEO1 = 22,
392 RT_CID_819x_MSI = 23,
393 RT_CID_819x_Acer = 24,
394 RT_CID_819x_HP = 27,
395 RT_CID_819x_CLEVO = 28,
396 RT_CID_819x_Arcadyan_Belkin = 29,
397 RT_CID_819x_SAMSUNG = 30,
398 RT_CID_819x_WNC_COREGA = 31,
399 RT_CID_819x_Foxcoon = 32,
400 RT_CID_819x_DELL = 33,
401 RT_CID_819x_PRONETS = 34,
402 RT_CID_819x_Edimax_ASUS = 35,
403 RT_CID_NETGEAR = 36,
404 RT_CID_PLANEX = 37,
405 RT_CID_CC_C = 38,
406};
407
408enum hw_descs {
409 HW_DESC_OWN,
410 HW_DESC_RXOWN,
411 HW_DESC_TX_NEXTDESC_ADDR,
412 HW_DESC_TXBUFF_ADDR,
413 HW_DESC_RXBUFF_ADDR,
414 HW_DESC_RXPKT_LEN,
415 HW_DESC_RXERO,
416 HW_DESC_RX_PREPARE,
417};
418
419enum prime_sc {
420 PRIME_CHNL_OFFSET_DONT_CARE = 0,
421 PRIME_CHNL_OFFSET_LOWER = 1,
422 PRIME_CHNL_OFFSET_UPPER = 2,
423};
424
425enum rf_type {
426 RF_1T1R = 0,
427 RF_1T2R = 1,
428 RF_2T2R = 2,
429 RF_2T2R_GREEN = 3,
430};
431
432enum ht_channel_width {
433 HT_CHANNEL_WIDTH_20 = 0,
434 HT_CHANNEL_WIDTH_20_40 = 1,
435 HT_CHANNEL_WIDTH_80 = 2,
436};
437
438/* Ref: 802.11i sepc D10.0 7.3.2.25.1
439Cipher Suites Encryption Algorithms */
440enum rt_enc_alg {
441 NO_ENCRYPTION = 0,
442 WEP40_ENCRYPTION = 1,
443 TKIP_ENCRYPTION = 2,
444 RSERVED_ENCRYPTION = 3,
445 AESCCMP_ENCRYPTION = 4,
446 WEP104_ENCRYPTION = 5,
447 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
448};
449
450enum rtl_hal_state {
451 _HAL_STATE_STOP = 0,
452 _HAL_STATE_START = 1,
453};
454
455enum rtl_var_map {
456 /*reg map */
457 SYS_ISO_CTRL = 0,
458 SYS_FUNC_EN,
459 SYS_CLK,
460 MAC_RCR_AM,
461 MAC_RCR_AB,
462 MAC_RCR_ACRC32,
463 MAC_RCR_ACF,
464 MAC_RCR_AAP,
465 MAC_HIMR,
466 MAC_HIMRE,
467 MAC_HSISR,
468
469 /*efuse map */
470 EFUSE_TEST,
471 EFUSE_CTRL,
472 EFUSE_CLK,
473 EFUSE_CLK_CTRL,
474 EFUSE_PWC_EV12V,
475 EFUSE_FEN_ELDR,
476 EFUSE_LOADER_CLK_EN,
477 EFUSE_ANA8M,
478 EFUSE_HWSET_MAX_SIZE,
479 EFUSE_MAX_SECTION_MAP,
480 EFUSE_REAL_CONTENT_SIZE,
481 EFUSE_OOB_PROTECT_BYTES_LEN,
482 EFUSE_ACCESS,
483 /*CAM map */
484 RWCAM,
485 WCAMI,
486 RCAMO,
487 CAMDBG,
488 SECR,
489 SEC_CAM_NONE,
490 SEC_CAM_WEP40,
491 SEC_CAM_TKIP,
492 SEC_CAM_AES,
493 SEC_CAM_WEP104,
494
495 /*IMR map */
496 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
497 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
498 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
499 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
500 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
501 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
502 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
503 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
504 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
505 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
506 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
507 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
508 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
509 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
510 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
511 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
512 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
513 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
514 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
515 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
516 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
517 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
518 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
519 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
520 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
521 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
522 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
523 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
524 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
525 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
526 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
527 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
528 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
529 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
530 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
531 * RTL_IMR_TBDER) */
532 RTL_IMR_C2HCMD, /*fw interrupt*/
533
534 /*CCK Rates, TxHT = 0 */
535 RTL_RC_CCK_RATE1M,
536 RTL_RC_CCK_RATE2M,
537 RTL_RC_CCK_RATE5_5M,
538 RTL_RC_CCK_RATE11M,
539
540 /*OFDM Rates, TxHT = 0 */
541 RTL_RC_OFDM_RATE6M,
542 RTL_RC_OFDM_RATE9M,
543 RTL_RC_OFDM_RATE12M,
544 RTL_RC_OFDM_RATE18M,
545 RTL_RC_OFDM_RATE24M,
546 RTL_RC_OFDM_RATE36M,
547 RTL_RC_OFDM_RATE48M,
548 RTL_RC_OFDM_RATE54M,
549
550 RTL_RC_HT_RATEMCS7,
551 RTL_RC_HT_RATEMCS15,
552
553 /*keep it last */
554 RTL_VAR_MAP_MAX,
555};
556
557/*Firmware PS mode for control LPS.*/
558enum _fw_ps_mode {
559 FW_PS_ACTIVE_MODE = 0,
560 FW_PS_MIN_MODE = 1,
561 FW_PS_MAX_MODE = 2,
562 FW_PS_DTIM_MODE = 3,
563 FW_PS_VOIP_MODE = 4,
564 FW_PS_UAPSD_WMM_MODE = 5,
565 FW_PS_UAPSD_MODE = 6,
566 FW_PS_IBSS_MODE = 7,
567 FW_PS_WWLAN_MODE = 8,
568 FW_PS_PM_Radio_Off = 9,
569 FW_PS_PM_Card_Disable = 10,
570};
571
572enum rt_psmode {
573 EACTIVE, /*Active/Continuous access. */
574 EMAXPS, /*Max power save mode. */
575 EFASTPS, /*Fast power save mode. */
576 EAUTOPS, /*Auto power save mode. */
577};
578
579/*LED related.*/
580enum led_ctl_mode {
581 LED_CTL_POWER_ON = 1,
582 LED_CTL_LINK = 2,
583 LED_CTL_NO_LINK = 3,
584 LED_CTL_TX = 4,
585 LED_CTL_RX = 5,
586 LED_CTL_SITE_SURVEY = 6,
587 LED_CTL_POWER_OFF = 7,
588 LED_CTL_START_TO_LINK = 8,
589 LED_CTL_START_WPS = 9,
590 LED_CTL_STOP_WPS = 10,
591};
592
593enum rtl_led_pin {
594 LED_PIN_GPIO0,
595 LED_PIN_LED0,
596 LED_PIN_LED1,
597 LED_PIN_LED2
598};
599
600/*QoS related.*/
601/*acm implementation method.*/
602enum acm_method {
603 eAcmWay0_SwAndHw = 0,
604 eAcmWay1_HW = 1,
605 eAcmWay2_SW = 2,
606};
607
608enum macphy_mode {
609 SINGLEMAC_SINGLEPHY = 0,
610 DUALMAC_DUALPHY,
611 DUALMAC_SINGLEPHY,
612};
613
614enum band_type {
615 BAND_ON_2_4G = 0,
616 BAND_ON_5G,
617 BAND_ON_BOTH,
618 BANDMAX
619};
620
621/*aci/aifsn Field.
622Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
623union aci_aifsn {
624 u8 char_data;
625
626 struct {
627 u8 aifsn:4;
628 u8 acm:1;
629 u8 aci:2;
630 u8 reserved:1;
631 } f; /* Field */
632};
633
634/*mlme related.*/
635enum wireless_mode {
636 WIRELESS_MODE_UNKNOWN = 0x00,
637 WIRELESS_MODE_A = 0x01,
638 WIRELESS_MODE_B = 0x02,
639 WIRELESS_MODE_G = 0x04,
640 WIRELESS_MODE_AUTO = 0x08,
641 WIRELESS_MODE_N_24G = 0x10,
642 WIRELESS_MODE_N_5G = 0x20,
643 WIRELESS_MODE_AC_5G = 0x40,
644 WIRELESS_MODE_AC_24G = 0x80
645};
646
647enum ratr_table_mode {
648 RATR_INX_WIRELESS_NGB = 0, // BGN 40 Mhz 2SS 1SS
649 RATR_INX_WIRELESS_NG = 1, // GN or N
650 RATR_INX_WIRELESS_NB = 2, // BGN 20 Mhz 2SS 1SS or BN
651 RATR_INX_WIRELESS_N = 3,
652 RATR_INX_WIRELESS_GB = 4,
653 RATR_INX_WIRELESS_G = 5,
654 RATR_INX_WIRELESS_B = 6,
655 RATR_INX_WIRELESS_MC = 7,
656 RATR_INX_WIRELESS_AC_5N = 8,
657 RATR_INX_WIRELESS_AC_24N = 9,
658};
659
660enum rtl_link_state {
661 MAC80211_NOLINK = 0,
662 MAC80211_LINKING = 1,
663 MAC80211_LINKED = 2,
664 MAC80211_LINKED_SCANNING = 3,
665};
666
667enum act_category {
668 ACT_CAT_QOS = 1,
669 ACT_CAT_DLS = 2,
670 ACT_CAT_BA = 3,
671 ACT_CAT_HT = 7,
672 ACT_CAT_WMM = 17,
673};
674
675enum ba_action {
676 ACT_ADDBAREQ = 0,
677 ACT_ADDBARSP = 1,
678 ACT_DELBA = 2,
679};
680
681enum rt_polarity_ctl {
682 RT_POLARITY_LOW_ACT = 0,
683 RT_POLARITY_HIGH_ACT = 1,
684};
685
686
687struct octet_string {
688 u8 *octet;
689 u16 length;
690};
691
692struct rtl_hdr_3addr {
693 __le16 frame_ctl;
694 __le16 duration_id;
695 u8 addr1[ETH_ALEN];
696 u8 addr2[ETH_ALEN];
697 u8 addr3[ETH_ALEN];
698 __le16 seq_ctl;
699 u8 payload[0];
700} __packed;
701
702struct rtl_info_element {
703 u8 id;
704 u8 len;
705 u8 data[0];
706} __packed;
707
708struct rtl_probe_rsp {
709 struct rtl_hdr_3addr header;
710 u32 time_stamp[2];
711 __le16 beacon_interval;
712 __le16 capability;
713 /*SSID, supported rates, FH params, DS params,
714 CF params, IBSS params, TIM (if beacon), RSN */
715 struct rtl_info_element info_element[0];
716} __packed;
717
718/*LED related.*/
719/*ledpin Identify how to implement this SW led.*/
720struct rtl_led {
721 void *hw;
722 enum rtl_led_pin ledpin;
723 bool b_ledon;
724};
725
726struct rtl_led_ctl {
727 bool bled_opendrain;
728 struct rtl_led sw_led0;
729 struct rtl_led sw_led1;
730};
731
732struct rtl_qos_parameters {
733 __le16 cw_min;
734 __le16 cw_max;
735 u8 aifs;
736 u8 flag;
737 __le16 tx_op;
738} __packed;
739
740struct rt_smooth_data {
741 u32 elements[100]; /*array to store values */
742 u32 index; /*index to current array to store */
743 u32 total_num; /*num of valid elements */
744 u32 total_val; /*sum of valid elements */
745};
746
747struct rtl_ht_agg {
748 u16 txq_id;
749 u16 wait_for_ba;
750 u16 start_idx;
751 u64 bitmap;
752 u32 rate_n_flags;
753 u8 agg_state;
754 u8 rx_agg_state;
755};
756
757struct rtl_tid_data {
758 u16 seq_number;
759 struct rtl_ht_agg agg;
760};
761
762struct rssi_sta{
763 long undecorated_smoothed_pwdb;
764};
765
766struct rtl_sta_info {
767 struct list_head list;
768 u8 ratr_index;
769 u8 wireless_mode;
770 u8 mimo_ps;
771 u8 mac_addr[6];
772 struct rtl_tid_data tids[MAX_TID_COUNT];
773
774 /* just used for ap adhoc or mesh*/
775 struct rssi_sta rssi_stat;
776} __packed;
777
778#ifdef VIF_TODO
779struct rtl_vif {
780 unsigned int id;
781 /* struct ieee80211_vif __rcu *vif; */
782 struct ieee80211_vif *vif;
783};
784
785struct rtl_vif_info {
786 struct list_head list;
787 bool active;
788 unsigned int id;
789 struct sk_buff *beacon;
790 bool enable_beacon;
791};
792
793struct vif_priv {
794 struct list_head vif_list;
795
796 /* interface mode settings */
797 unsigned long vif_bitmap;
798 unsigned int vifs;
799 struct rtl_vif vif[MAX_VIRTUAL_MAC];
800
801 /* beaconing */
802 spinlock_t beacon_lock;
803 unsigned int global_pretbtt;
804 unsigned int global_beacon_int;
805 /* struct rtl_vif_info __rcu *beacon_iter; */
806 struct rtl_vif_info *beacon_iter;
807 unsigned int beacon_enabled;
808};
809#endif
810
811struct false_alarm_statistics {
812 u32 cnt_parity_fail;
813 u32 cnt_rate_illegal;
814 u32 cnt_crc8_fail;
815 u32 cnt_mcs_fail;
816 u32 cnt_fast_fsync_fail;
817 u32 cnt_sb_search_fail;
818 u32 cnt_ofdm_fail;
819 u32 cnt_cck_fail;
820 u32 cnt_all;
821 u32 cnt_ofdm_cca;
822 u32 cnt_cck_cca;
823 u32 cnt_cca_all;
824 u32 cnt_bw_usc;
825 u32 cnt_bw_lsc;
826};
827
828struct init_gain {
829 u8 xaagccore1;
830 u8 xbagccore1;
831 u8 xcagccore1;
832 u8 xdagccore1;
833 u8 cca;
834
835};
836
837struct wireless_stats {
838 unsigned long txbytesunicast;
839 unsigned long txbytesmulticast;
840 unsigned long txbytesbroadcast;
841 unsigned long rxbytesunicast;
842
843 long rx_snr_db[4];
844 /*Correct smoothed ss in Dbm, only used
845 in driver to report real power now. */
846 long recv_signal_power;
847 long signal_quality;
848 long last_sigstrength_inpercent;
849
850 u32 rssi_calculate_cnt;
851 u32 pwdb_all_cnt;
852
853 /*Transformed, in dbm. Beautified signal
854 strength for UI, not correct. */
855 long signal_strength;
856
857 u8 rx_rssi_percentage[4];
858 u8 rx_evm_dbm[4];
859 u8 rx_evm_percentage[2];
860
861 u16 rx_cfo_short[4];
862 u16 rx_cfo_tail[4];
863
864 struct rt_smooth_data ui_rssi;
865 struct rt_smooth_data ui_link_quality;
866};
867
868struct rate_adaptive {
869 u8 rate_adaptive_disabled;
870 u8 ratr_state;
871 u16 reserve;
872
873 u32 high_rssi_thresh_for_ra;
874 u32 high2low_rssi_thresh_for_ra;
875 u8 low2high_rssi_thresh_for_ra;
876 u32 low_rssi_thresh_for_ra;
877 u32 upper_rssi_threshold_ratr;
878 u32 middleupper_rssi_threshold_ratr;
879 u32 middle_rssi_threshold_ratr;
880 u32 middlelow_rssi_threshold_ratr;
881 u32 low_rssi_threshold_ratr;
882 u32 ultralow_rssi_threshold_ratr;
883 u32 low_rssi_threshold_ratr_40m;
884 u32 low_rssi_threshold_ratr_20m;
885 u8 ping_rssi_enable;
886 u32 ping_rssi_ratr;
887 u32 ping_rssi_thresh_for_ra;
888 u32 last_ratr;
889 u8 pre_ratr_state;
890 u8 ldpc_thres;
891 bool use_ldpc;
892 bool lower_rts_rate;
893 bool is_special_data;
894};
895
896struct regd_pair_mapping {
897 u16 reg_dmnenum;
898 u16 reg_5ghz_ctl;
899 u16 reg_2ghz_ctl;
900};
901
902struct dynamic_primary_cca{
903 u8 pricca_flag;
904 u8 intf_flag;
905 u8 intf_type;
906 u8 dup_rts_flag;
907 u8 monitor_flag;
908 u8 ch_offset;
909 u8 mf_state;
910};
911
912struct rtl_regulatory {
913 char alpha2[2];
914 u16 country_code;
915 u16 max_power_level;
916 u32 tp_scale;
917 u16 current_rd;
918 u16 current_rd_ext;
919 int16_t power_limit;
920 struct regd_pair_mapping *regpair;
921};
922
923struct rtl_rfkill {
924 bool rfkill_state; /*0 is off, 1 is on */
925};
926
927/*for P2P PS**/
928#define P2P_MAX_NOA_NUM 2
929
930enum p2p_role {
931 P2P_ROLE_DISABLE = 0,
932 P2P_ROLE_DEVICE = 1,
933 P2P_ROLE_CLIENT = 2,
934 P2P_ROLE_GO = 3
935};
936
937enum p2p_ps_state {
938 P2P_PS_DISABLE = 0,
939 P2P_PS_ENABLE = 1,
940 P2P_PS_SCAN = 2,
941 P2P_PS_SCAN_DONE = 3,
942 P2P_PS_ALLSTASLEEP = 4, // for P2P GO
943};
944
945enum p2p_ps_mode {
946 P2P_PS_NONE = 0,
947 P2P_PS_CTWINDOW = 1,
948 P2P_PS_NOA = 2,
949 P2P_PS_MIX = 3, // CTWindow and NoA
950};
951
952struct rtl_p2p_ps_info {
953 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
954 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
955 u8 noa_index; /* Identifies and instance of Notice of Absence timing. */
956 /* Client traffic window. A period of time in TU after TBTT. */
957 u8 ctwindow;
958 u8 opp_ps; /* opportunistic power save. */
959 u8 noa_num; /* number of NoA descriptor in P2P IE. */
960 /* Count for owner, Type of client. */
961 u8 noa_count_type[P2P_MAX_NOA_NUM];
962 /* Max duration for owner, preferred or
963 * min acceptable duration for client. */
964 u32 noa_duration[P2P_MAX_NOA_NUM];
965 /* Length of interval for owner, preferred or
966 * max acceptable interval of client. */
967 u32 noa_interval[P2P_MAX_NOA_NUM];
968 /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */
969 u32 noa_start_time[P2P_MAX_NOA_NUM];
970};
971
972 struct p2p_ps_offload_t {
973 u8 Offload_En:1;
974 u8 role:1; /* 1: Owner, 0: Client */
975 u8 CTWindow_En:1;
976 u8 NoA0_En:1;
977 u8 NoA1_En:1;
978 u8 AllStaSleep:1;
979 u8 discovery:1;
980 u8 reserved:1;
981};
982
983#define IQK_MATRIX_REG_NUM 8
984#define IQK_MATRIX_SETTINGS_NUM (14+24+21) // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
985struct iqk_matrix_regs {
986 bool b_iqk_done;
987 long value[1][IQK_MATRIX_REG_NUM];
988};
989
990struct rtl_phy {
991 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
992 struct init_gain initgain_backup;
993 enum io_type current_io_type;
994
995 u8 rf_mode;
996 u8 rf_type;
997 u8 current_chan_bw;
998 u8 set_bwmode_inprogress;
999 u8 sw_chnl_inprogress;
1000 u8 sw_chnl_stage;
1001 u8 sw_chnl_step;
1002 u8 current_channel;
1003 u8 h2c_box_num;
1004 u8 set_io_inprogress;
1005 u8 lck_inprogress;
1006
1007 /* record for power tracking */
1008 s32 reg_e94;
1009 s32 reg_e9c;
1010 s32 reg_ea4;
1011 s32 reg_eac;
1012 s32 reg_eb4;
1013 s32 reg_ebc;
1014 s32 reg_ec4;
1015 s32 reg_ecc;
1016 u8 rfpienable;
1017 u8 reserve_0;
1018 u16 reserve_1;
1019 u32 reg_c04, reg_c08, reg_874;
1020 u32 adda_backup[16];
1021 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1022 u32 iqk_bb_backup[10];
1023 bool iqk_initialized;
1024
1025 bool rfpath_rx_enable[MAX_RF_PATH];
1026 /*Jaguar*/
1027 u8 reg_837;
1028 /* Dul mac */
1029 bool b_need_iqk;
1030 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
1031
1032 bool b_rfpi_enable;
1033
1034 bool b_iqk_in_progress;
1035
1036 u8 pwrgroup_cnt;
1037 u8 bcck_high_power;
1038 /* this is for 88E & 8723A */
1039 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
1040 /* this is for 92EE */
1041 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1042 [TX_PWR_BY_RATE_NUM_RF]
1043 [TX_PWR_BY_RATE_NUM_RF]
1044 [TX_PWR_BY_RATE_NUM_SECTION];
1045 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1046 [TX_PWR_BY_RATE_NUM_RF]
1047 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1048
1049 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1050 [TX_PWR_BY_RATE_NUM_RF]
1051 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1052 u8 default_initialgain[4];
1053
1054 /* the current Tx power level */
1055 u8 cur_cck_txpwridx;
1056 u8 cur_ofdm24g_txpwridx;
1057 u8 cur_bw20_txpwridx;
1058 u8 cur_bw40_txpwridx;
1059
1060 u32 rfreg_chnlval[2];
1061 bool b_apk_done;
1062 u32 reg_rf3c[2]; /* pathA / pathB */
1063
1064 u32 backup_rf_0x1a;/*92ee*/
1065 /* bfsync */
1066 u8 framesync;
1067 u32 framesync_c34;
1068
1069 u8 num_total_rfpath;
1070 u16 rf_pathmap;
1071
1072 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1073
1074 enum rt_polarity_ctl polarity_ctl;
1075};
1076
1077#define RTL_AGG_STOP 0
1078#define RTL_AGG_PROGRESS 1
1079#define RTL_AGG_START 2
1080#define RTL_AGG_OPERATIONAL 3
1081#define RTL_RX_AGG_START 1
1082#define RTL_RX_AGG_STOP 0
1083
1084struct rtl_priv;
1085struct rtl_io {
1086 struct device *dev;
1087
1088 /*PCI MEM map */
1089 unsigned long pci_mem_end; /*shared mem end */
1090 unsigned long pci_mem_start; /*shared mem start */
1091
1092 /*PCI IO map */
1093 unsigned long pci_base_addr; /*device I/O address */
1094
1095 void (*write8_async) (struct rtl_priv * rtlpriv, u32 addr, u8 val);
1096 void (*write16_async) (struct rtl_priv * rtlpriv, u32 addr, u16 val);
1097 void (*write32_async) (struct rtl_priv * rtlpriv, u32 addr, u32 val);
1098
1099 u8(*read8_sync) (struct rtl_priv * rtlpriv, u32 addr);
1100 u16(*read16_sync) (struct rtl_priv * rtlpriv, u32 addr);
1101 u32(*read32_sync) (struct rtl_priv * rtlpriv, u32 addr);
1102
1103};
1104
1105struct rtl_mac {
1106 u8 mac_addr[ETH_ALEN];
1107 u8 mac80211_registered;
1108 u8 beacon_enabled;
1109
1110 u32 tx_ss_num;
1111 u32 rx_ss_num;
1112
1113 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1114 struct ieee80211_hw *hw;
1115 struct ieee80211_vif *vif;
1116 enum nl80211_iftype opmode;
1117
1118 /*Probe Beacon management */
1119 enum rtl_link_state link_state;
1120
1121 int n_channels;
1122 int n_bitrates;
1123
1124 bool offchan_deley;
1125 u8 p2p; /*using p2p role*/
1126 bool p2p_in_use;
1127
1128 /*filters */
1129 u32 rx_conf;
1130
1131 bool act_scanning;
1132 u8 cnt_after_linked;
1133 bool skip_scan;
1134
1135 /* early mode */
1136 /* skb wait queue */
1137 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1138
1139 /*RDG*/
1140 bool rdg_en;
1141
1142 /*AP*/
1143 u8 bssid[6];
1144 u32 vendor;
1145 u32 basic_rates; /* b/g rates */
1146 u8 ht_enable;
1147 u8 bw_40;
1148 u8 mode; /* wireless mode */
1149 u8 slot_time;
1150 u8 short_preamble;
1151 u8 use_cts_protect;
1152 u8 cur_40_prime_sc;
1153 u8 cur_40_prime_sc_bk;
1154 u8 cur_80_prime_sc;
1155 u64 tsf;
1156 u8 retry_short;
1157 u8 retry_long;
1158 u16 assoc_id;
1159 bool bhiddenssid;
1160
1161 /*IBSS*/
1162 int beacon_interval;
1163
1164 /*AMPDU*/
1165 u8 min_space_cfg; /*For Min spacing configurations */
1166 u8 max_mss_density;
1167 u8 current_ampdu_factor;
1168 u8 current_ampdu_density;
1169
1170 /*QOS & EDCA */
1171 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1172 struct rtl_qos_parameters ac[AC_MAX];
1173};
1174
1175struct rtl_hal {
1176 struct ieee80211_hw *hw;
1177
1178 bool driver_is_goingto_unload;
1179 bool up_first_time;
1180 bool bfirst_init;
1181 bool being_init_adapter;
1182 bool b_bbrf_ready;
1183 bool b_mac_func_enable;
1184 bool b_pre_edcca_enable;
1185
1186 enum intf_type interface;
1187 u16 hw_type; /*92c or 92d or 92s and so on */
1188 u8 ic_class;
1189 u8 oem_id;
1190 u32 version; /*version of chip */
1191 u8 state; /*stop 0, start 1 */
1192 u8 boad_type;
1193
1194 /*firmware */
1195 u32 fwsize;
1196 u8 *pfirmware;
1197 u16 fw_version;
1198 u16 fw_subversion;
1199 bool b_h2c_setinprogress;
1200 u8 last_hmeboxnum;
1201 bool bfw_ready;
1202
1203 /*Reserve page start offset except beacon in TxQ. */
1204 u8 fw_rsvdpage_startoffset;
1205 u8 h2c_txcmd_seq;
1206 u8 current_ra_rate;
1207
1208 /* FW Cmd IO related */
1209 u16 fwcmd_iomap;
1210 u32 fwcmd_ioparam;
1211 bool set_fwcmd_inprogress;
1212 u8 current_fwcmd_io;
1213
1214 bool bfw_clk_change_in_progress;
1215 bool ballow_sw_to_change_hwclc;
1216 u8 fw_ps_state;
1217 struct p2p_ps_offload_t p2p_ps_offload;
1218 /**/
1219 bool driver_going2unload;
1220
1221 /*AMPDU init min space*/
1222 u8 minspace_cfg; /*For Min spacing configurations */
1223
1224 /* Dul mac */
1225 enum macphy_mode macphymode;
1226 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1227 enum band_type current_bandtypebackup;
1228 enum band_type bandset;
1229 /* dual MAC 0--Mac0 1--Mac1 */
1230 u32 interfaceindex;
1231 /* just for DulMac S3S4 */
1232 u8 macphyctl_reg;
1233 bool b_earlymode_enable;
1234 u8 max_earlymode_num;
1235 /* Dul mac*/
1236 bool during_mac0init_radiob;
1237 bool during_mac1init_radioa;
1238 bool reloadtxpowerindex;
1239 /* True if IMR or IQK have done
1240 for 2.4G in scan progress */
1241 bool b_load_imrandiqk_setting_for2g;
1242
1243 bool disable_amsdu_8k;
1244 bool bmaster_of_dmsp;
1245 bool bslave_of_dmsp;
1246
1247 u16 rx_tag;/*for 92ee*/
1248 u8 rts_en;
1249};
1250
1251struct rtl_security {
1252 /*default 0 */
1253 bool use_sw_sec;
1254
1255 bool being_setkey;
1256 bool use_defaultkey;
1257 /*Encryption Algorithm for Unicast Packet */
1258 enum rt_enc_alg pairwise_enc_algorithm;
1259 /*Encryption Algorithm for Brocast/Multicast */
1260 enum rt_enc_alg group_enc_algorithm;
1261 /*Cam Entry Bitmap */
1262 u32 hwsec_cam_bitmap;
1263 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1264 /*local Key buffer, indx 0 is for
1265 pairwise key 1-4 is for agoup key. */
1266 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1267 u8 key_len[KEY_BUF_SIZE];
1268
1269 /*The pointer of Pairwise Key,
1270 it always points to KeyBuf[4] */
1271 u8 *pairwise_key;
1272};
1273
1274struct rtl_dig {
1275 u8 dig_enable_flag;
1276 u8 dig_ext_port_stage;
1277
1278 u32 rssi_lowthresh;
1279 u32 rssi_highthresh;
1280
1281 u32 fa_lowthresh;
1282 u32 fa_highthresh;
1283
1284 u8 cursta_connectstate;
1285 u8 presta_connectstate;
1286 u8 curmultista_connectstate;
1287
1288 u8 pre_igvalue;
1289 u8 cur_igvalue;
1290
1291 char backoff_val;
1292 char backoff_val_range_max;
1293 char backoff_val_range_min;
1294 u8 rx_gain_range_max;
1295 u8 rx_gain_range_min;
1296 u8 rssi_val_min;
1297 u8 min_undecorated_pwdb_for_dm;
1298 long last_min_undecorated_pwdb_for_dm;
1299
1300 u8 pre_cck_pd_state;
1301 u8 cur_cck_pd_state;
1302
1303 u8 large_fa_hit;
1304 u8 forbidden_igi;
1305 u32 recover_cnt;
1306
1307};
1308
1309struct rtl_pstbl {
1310 u8 pre_ccastate;
1311 u8 cur_ccasate;
1312
1313 u8 pre_rfstate;
1314 u8 cur_rfstate;
1315
1316 long rssi_val_min;
1317
1318};
1319
1320#define ASSOCIATE_ENTRY_NUM 32+1
1321
1322struct fast_ant_trainning{
1323 u8 bssid[6];
1324 u8 antsel_rx_keep_0;
1325 u8 antsel_rx_keep_1;
1326 u8 antsel_rx_keep_2;
1327 u32 ant_sum_rssi[7];
1328 u32 ant_rssi_cnt[7];
1329 u32 ant_ave_rssi[7];
1330 u8 fat_state;
1331 u32 train_idx;
1332 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1333 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1334 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1335 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1336 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1337 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1338 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1339 u8 rx_idle_ant;
1340 bool b_becomelinked;
1341};
1342
1343struct dm_phy_dbg_info {
1344 char rx_snrdb[4];
1345 u64 num_qry_phy_status;
1346 u64 num_qry_phy_status_cck;
1347 u64 num_qry_phy_status_ofdm;
1348 u16 num_qry_beacon_pkt;
1349 u16 num_non_be_pkt;
1350 s32 rx_evm[4];
1351};
1352
1353struct rtl_dm {
1354 /*PHY status for DM */
1355 long entry_min_undecoratedsmoothed_pwdb;
1356 long undecorated_smoothed_pwdb; /*out dm */
1357 long entry_max_undecoratedsmoothed_pwdb;
1358 bool b_dm_initialgain_enable;
1359 bool bdynamic_txpower_enable;
1360 bool bcurrent_turbo_edca;
1361 bool bis_any_nonbepkts; /*out dm */
1362 bool bis_cur_rdlstate;
1363 bool btxpower_trackinginit;
1364 bool b_disable_framebursting;
1365 bool b_cck_inch14;
1366 bool btxpower_tracking;
1367 bool b_useramask;
1368 bool brfpath_rxenable[4];
1369 bool binform_fw_driverctrldm;
1370 bool bcurrent_mrc_switch;
1371 u8 txpowercount;
1372
1373 u8 thermalvalue_rxgain;
1374 u8 thermalvalue_iqk;
1375 u8 thermalvalue_lck;
1376 u8 thermalvalue;
1377 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1378 u8 thermalvalue_avg_index;
1379 bool bdone_txpower;
1380 u8 last_dtp_lvl;
1381 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1382 u8 dm_flag; /*Indicate if each dynamic mechanism's status. */
1383 u8 dm_type;
1384 u8 txpower_track_control;
1385 bool binterrupt_migration;
1386 bool bdisable_tx_int;
1387 char ofdm_index[MAX_RF_PATH];
1388 u8 default_ofdm_index;
1389 u8 default_cck_index;
1390 char cck_index;
1391 char delta_power_index[MAX_RF_PATH];
1392 char delta_power_index_last[MAX_RF_PATH];
1393 char power_index_offset[MAX_RF_PATH];
1394 char aboslute_ofdm_swing_idx[MAX_RF_PATH];
1395 char remnant_ofdm_swing_idx[MAX_RF_PATH];
1396 char remnant_cck_idx;
1397 bool modify_txagc_flag_path_a;
1398 bool modify_txagc_flag_path_b;
1399
1400 bool b_one_entry_only;
1401 struct dm_phy_dbg_info dbginfo;
1402 /* Dynamic ATC switch */
1403
1404 bool atc_status;
1405 bool large_cfo_hit;
1406 bool is_freeze;
1407 int cfo_tail[2];
1408 int cfo_ave_pre;
1409 int crystal_cap;
1410 u8 cfo_threshold;
1411 u32 packet_count;
1412 u32 packet_count_pre;
1413 u8 tx_rate;
1414
1415
1416 /*88e tx power tracking*/
1417 u8 bb_swing_idx_ofdm[2];
1418 u8 bb_swing_idx_ofdm_current;
1419 u8 bb_swing_idx_ofdm_base[MAX_RF_PATH];
1420 bool bb_swing_flag_Ofdm;
1421 u8 bb_swing_idx_cck;
1422 u8 bb_swing_idx_cck_current;
1423 u8 bb_swing_idx_cck_base;
1424 bool bb_swing_flag_cck;
1425
1426 char bb_swing_diff_2g;
1427 char bb_swing_diff_5g;
1428
1429 u8 delta_swing_table_idx_24gccka_p[DELTA_SWINGIDX_SIZE];
1430 u8 delta_swing_table_idx_24gccka_n[DELTA_SWINGIDX_SIZE];
1431 u8 delta_swing_table_idx_24gcckb_p[DELTA_SWINGIDX_SIZE];
1432 u8 delta_swing_table_idx_24gcckb_n[DELTA_SWINGIDX_SIZE];
1433 u8 delta_swing_table_idx_24ga_p[DELTA_SWINGIDX_SIZE];
1434 u8 delta_swing_table_idx_24ga_n[DELTA_SWINGIDX_SIZE];
1435 u8 delta_swing_table_idx_24gb_p[DELTA_SWINGIDX_SIZE];
1436 u8 delta_swing_table_idx_24gb_n[DELTA_SWINGIDX_SIZE];
1437 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
1438 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
1439 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE];
1440 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE];
1441 u8 delta_swing_table_idx_24ga_p_8188e[DELTA_SWINGIDX_SIZE];
1442 u8 delta_swing_table_idx_24ga_n_8188e[DELTA_SWINGIDX_SIZE];
1443
1444
1445 /* DMSP */
1446 bool supp_phymode_switch;
1447
1448 /* DulMac */
1449 struct rtl_dig dm_digtable;
1450 struct rtl_pstbl dm_pstable;
1451 struct fast_ant_trainning fat_table;
1452
1453 u8 resp_tx_path;
1454 u8 path_sel;
1455 u32 patha_sum;
1456 u32 pathb_sum;
1457 u32 patha_cnt;
1458 u32 pathb_cnt;
1459
1460 u8 pre_channel;
1461 u8 *p_channel;
1462 u8 linked_interval;
1463
1464 u64 last_tx_ok_cnt;
1465 u64 last_rx_ok_cnt;
1466};
1467
1468#define EFUSE_MAX_LOGICAL_SIZE 256
1469
1470struct rtl_efuse {
1471 bool bautoLoad_ok;
1472 bool bootfromefuse;
1473 u16 max_physical_size;
1474
1475 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1476 u16 efuse_usedbytes;
1477 u8 efuse_usedpercentage;
1478#ifdef EFUSE_REPG_WORKAROUND
1479 bool efuse_re_pg_sec1flag;
1480 u8 efuse_re_pg_data[8];
1481#endif
1482
1483 u8 autoload_failflag;
1484 u8 autoload_status;
1485
1486 short epromtype;
1487 u16 eeprom_vid;
1488 u16 eeprom_did;
1489 u16 eeprom_svid;
1490 u16 eeprom_smid;
1491 u8 eeprom_oemid;
1492 u16 eeprom_channelplan;
1493 u8 eeprom_version;
1494
1495 u8 dev_addr[6];
1496 u8 board_type;
1497 u8 wowlan_enable;
1498 u8 antenna_div_cfg;
1499 u8 antenna_div_type;
1500
1501 bool b_txpwr_fromeprom;
1502 u8 eeprom_crystalcap;
1503 u8 eeprom_tssi[2];
1504 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1505 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1506 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1507 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1508 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1509 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1510
1511
1512 u8 internal_pa_5g[2]; /* pathA / pathB */
1513 u8 eeprom_c9;
1514 u8 eeprom_cc;
1515
1516 /*For power group */
1517 u8 eeprom_pwrgroup[2][3];
1518 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1519 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1520
1521 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1522 /*For HT 40MHZ pwr */
1523 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1524 /*For HT 40MHZ pwr */
1525 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1526 char txpwr_cckdiff[MAX_RF_PATH][MAX_TX_COUNT]; /*CCK_24G_Diff*/
1527 /*HT 20<->40 Pwr diff */
1528 char txpwr_ht20diff[MAX_RF_PATH][MAX_TX_COUNT]; /*BW20_24G_Diff*/
1529 char txpwr_ht40diff[MAX_RF_PATH][MAX_TX_COUNT];/*BW40_24G_Diff*/
1530 /*For HT<->legacy pwr diff */
1531 char txpwr_legacyhtdiff[MAX_RF_PATH][MAX_TX_COUNT];/*OFDM_24G_Diff*/
1532
1533 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1534 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1535 char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1536 char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1537 char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1538 char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1539
1540 u8 txpwr_safetyflag; /* Band edge enable flag */
1541 u16 eeprom_txpowerdiff;
1542 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1543 u8 antenna_txpwdiff[3];
1544
1545 u8 eeprom_regulatory;
1546 u8 eeprom_thermalmeter;
1547 u8 thermalmeter[2];/*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
1548 u16 tssi_13dbm;
1549 u8 crystalcap; /* CrystalCap. */
1550 u8 delta_iqk;
1551 u8 delta_lck;
1552
1553 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1554 bool b_apk_thermalmeterignore;
1555
1556 bool b1x1_recvcombine;
1557 bool b1ss_support;
1558
1559 /*channel plan */
1560 u8 channel_plan;
1561};
1562
1563struct rtl_ps_ctl {
1564 bool pwrdomain_protect;
1565 bool b_in_powersavemode;
1566 bool rfchange_inprogress;
1567 bool b_swrf_processing;
1568 bool b_hwradiooff;
1569 /*
1570 * just for PCIE ASPM
1571 * If it supports ASPM, Offset[560h] = 0x40,
1572 * otherwise Offset[560h] = 0x00.
1573 * */
1574 bool b_support_aspm;
1575 bool b_support_backdoor;
1576
1577 /*for LPS */
1578 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1579 bool b_swctrl_lps;
1580 bool b_fwctrl_lps;
1581 u8 fwctrl_psmode;
1582 /*For Fw control LPS mode */
1583 u8 b_reg_fwctrl_lps;
1584 /*Record Fw PS mode status. */
1585 bool b_fw_current_inpsmode;
1586 u8 reg_max_lps_awakeintvl;
1587 bool report_linked;
1588 bool b_low_power_enable;/*for 32k*/
1589
1590 /*for IPS */
1591 bool b_inactiveps;
1592
1593 u32 rfoff_reason;
1594
1595 /*RF OFF Level */
1596 u32 cur_ps_level;
1597 u32 reg_rfps_level;
1598
1599 /*just for PCIE ASPM */
1600 u8 const_amdpci_aspm;
1601
1602 enum rf_pwrstate inactive_pwrstate;
1603 enum rf_pwrstate rfpwr_state; /*cur power state */
1604
1605 /* for SW LPS*/
1606 bool sw_ps_enabled;
1607 bool state;
1608 bool state_inap;
1609 bool multi_buffered;
1610 u16 nullfunc_seq;
1611 unsigned int dtim_counter;
1612 unsigned int sleep_ms;
1613 unsigned long last_sleep_jiffies;
1614 unsigned long last_awake_jiffies;
1615 unsigned long last_delaylps_stamp_jiffies;
1616 unsigned long last_dtim;
1617 unsigned long last_beacon;
1618 unsigned long last_action;
1619 unsigned long last_slept;
1620
1621 /*For P2P PS */
1622 struct rtl_p2p_ps_info p2p_ps_info;
1623 u8 pwr_mode;
1624 u8 smart_ps;
1625};
1626
1627struct rtl_stats {
1628 u8 psaddr[ETH_ALEN];
1629 u32 mac_time[2];
1630 s8 rssi;
1631 u8 signal;
1632 u8 noise;
1633 u8 rate; /* hw desc rate */
1634 u8 rawdata;
1635 u8 received_channel;
1636 u8 control;
1637 u8 mask;
1638 u8 freq;
1639 u16 len;
1640 u64 tsf;
1641 u32 beacon_time;
1642 u8 nic_type;
1643 u16 length;
1644 u8 signalquality; /*in 0-100 index. */
1645 /*
1646 * Real power in dBm for this packet,
1647 * no beautification and aggregation.
1648 * */
1649 s32 recvsignalpower;
1650 s8 rxpower; /*in dBm Translate from PWdB */
1651 u8 signalstrength; /*in 0-100 index. */
1652 u16 b_hwerror:1;
1653 u16 b_crc:1;
1654 u16 b_icv:1;
1655 u16 b_shortpreamble:1;
1656 u16 antenna:1;
1657 u16 decrypted:1;
1658 u16 wakeup:1;
1659 u32 timestamp_low;
1660 u32 timestamp_high;
1661 bool b_shift;
1662
1663 u8 rx_drvinfo_size;
1664 u8 rx_bufshift;
1665 bool b_isampdu;
1666 bool b_isfirst_ampdu;
1667 bool rx_is40Mhzpacket;
1668 u32 rx_pwdb_all;
1669 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1670 s8 rx_mimo_signalquality[4];
1671 u8 rx_mimo_evm_dbm[4];
1672 u16 cfo_short[4]; /* per-path's Cfo_short */
1673 u16 cfo_tail[4];
1674
1675 u8 rx_pwr[4]; /* per-path's pwdb */
1676 u8 rx_snr[4]; /* per-path's SNR */
1677 u8 bandwidth;
1678 u8 bt_coex_pwr_adjust;
1679 bool b_packet_matchbssid;
1680 bool b_is_cck;
1681 bool b_is_ht;
1682 bool b_packet_toself;
1683 bool b_packet_beacon; /*for rssi */
1684 char cck_adc_pwdb[4]; /*for rx path selection */
1685
1686 u8 packet_report_type;
1687
1688 u32 macid;
1689 u8 wake_match;
1690 u32 bt_rx_rssi_percentage;
1691 u32 macid_valid_entry[2];
1692};
1693
1694struct rt_link_detect {
1695 /* count for raoming */
1696 u32 bcn_rx_inperiod;
1697 u32 roam_times;
1698
1699 u32 num_tx_in4period[4];
1700 u32 num_rx_in4period[4];
1701
1702 u32 num_tx_inperiod;
1703 u32 num_rx_inperiod;
1704
1705 bool b_busytraffic;
1706 bool b_tx_busy_traffic;
1707 bool b_rx_busy_traffic;
1708 bool b_higher_busytraffic;
1709 bool b_higher_busyrxtraffic;
1710
1711 u32 tidtx_in4period[MAX_TID_COUNT][4];
1712 u32 tidtx_inperiod[MAX_TID_COUNT];
1713 bool higher_busytxtraffic[MAX_TID_COUNT];
1714};
1715
1716struct rtl_tcb_desc {
1717 u8 b_packet_bw:1;
1718 u8 b_multicast:1;
1719 u8 b_broadcast:1;
1720
1721 u8 b_rts_stbc:1;
1722 u8 b_rts_enable:1;
1723 u8 b_cts_enable:1;
1724 u8 b_rts_use_shortpreamble:1;
1725 u8 b_rts_use_shortgi:1;
1726 u8 rts_sc:1;
1727 u8 b_rts_bw:1;
1728 u8 rts_rate;
1729
1730 u8 use_shortgi:1;
1731 u8 use_shortpreamble:1;
1732 u8 use_driver_rate:1;
1733 u8 disable_ratefallback:1;
1734
1735 u8 ratr_index;
1736 u8 mac_id;
1737 u8 hw_rate;
1738
1739 u8 b_last_inipkt:1;
1740 u8 b_cmd_or_init:1;
1741 u8 queue_index;
1742
1743 /* early mode */
1744 u8 empkt_num;
1745 /* The max value by HW */
1746 u32 empkt_len[10];
1747 bool btx_enable_sw_calc_duration;
1748 /* used for hal construct pkt,
1749 * we may set desc when tx */
1750 u8 self_desc;
1751};
1752
1753struct proxim {
1754 bool proxim_on;
1755
1756 void *proximity_priv;
1757 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
1758 struct sk_buff *skb);
1759 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
1760};
1761
1762struct rtl_hal_ops {
1763 int (*init_sw_vars) (struct ieee80211_hw * hw);
1764 void (*deinit_sw_vars) (struct ieee80211_hw * hw);
1765 void (*read_eeprom_info) (struct ieee80211_hw * hw);
1766 void (*interrupt_recognized) (struct ieee80211_hw * hw,
1767 u32 * p_inta, u32 * p_intb);
1768 int (*hw_init) (struct ieee80211_hw * hw);
1769 void (*hw_disable) (struct ieee80211_hw * hw);
1770 void (*hw_suspend) (struct ieee80211_hw * hw);
1771 void (*hw_resume) (struct ieee80211_hw * hw);
1772 void (*enable_interrupt) (struct ieee80211_hw * hw);
1773 void (*disable_interrupt) (struct ieee80211_hw * hw);
1774 int (*set_network_type) (struct ieee80211_hw * hw,
1775 enum nl80211_iftype type);
1776 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1777 bool check_bssid);
1778 void (*set_bw_mode) (struct ieee80211_hw * hw,
1779 enum nl80211_channel_type ch_type);
1780 u8(*switch_channel) (struct ieee80211_hw * hw);
1781 void (*set_qos) (struct ieee80211_hw * hw, int aci);
1782 void (*set_bcn_reg) (struct ieee80211_hw * hw);
1783 void (*set_bcn_intv) (struct ieee80211_hw * hw);
1784 void (*update_interrupt_mask) (struct ieee80211_hw * hw,
1785 u32 add_msr, u32 rm_msr);
1786 void (*get_hw_reg) (struct ieee80211_hw * hw, u8 variable, u8 * val);
1787 void (*set_hw_reg) (struct ieee80211_hw * hw, u8 variable, u8 * val);
1788 void (*update_rate_tbl) (struct ieee80211_hw * hw,
1789 struct ieee80211_sta *sta, u8 rssi_level);
1790 void (*pre_fill_tx_bd_desc) (struct ieee80211_hw *hw, u8 *tx_bd_desc,
1791 u8 *desc, u8 queue_index,
1792 struct sk_buff *skb, dma_addr_t addr);
1793 u16 (*rx_desc_buff_remained_cnt) (struct ieee80211_hw *hw,
1794 u8 queue_index);
1795 void (*rx_check_dma_ok) (struct ieee80211_hw *hw, u8 *header_desc,
1796 u8 queue_index);
1797 void (*fill_tx_desc) (struct ieee80211_hw * hw,
1798 struct ieee80211_hdr * hdr,
1799 u8 * pdesc_tx, u8 * pbd_desc,
1800 struct ieee80211_tx_info * info,
1801/*<delete in kernel start>*/
1802#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
1803/*<delete in kernel end>*/
1804 struct ieee80211_sta *sta,
1805/*<delete in kernel start>*/
1806#endif
1807/*<delete in kernel end>*/
1808 struct sk_buff * skb, u8 hw_queue,
1809 struct rtl_tcb_desc *ptcb_desc);
1810 void (*fill_tx_cmddesc) (struct ieee80211_hw * hw, u8 * pdesc,
1811 bool b_firstseg, bool b_lastseg,
1812 struct sk_buff * skb);
1813 bool(*query_rx_desc) (struct ieee80211_hw * hw,
1814 struct rtl_stats * status,
1815 struct ieee80211_rx_status * rx_status,
1816 u8 * pdesc, struct sk_buff * skb);
1817 void (*set_channel_access) (struct ieee80211_hw * hw);
1818 bool(*radio_onoff_checking) (struct ieee80211_hw * hw, u8 * valid);
1819 void (*dm_watchdog) (struct ieee80211_hw * hw);
1820 void (*scan_operation_backup) (struct ieee80211_hw * hw, u8 operation);
1821 bool(*set_rf_power_state) (struct ieee80211_hw * hw,
1822 enum rf_pwrstate rfpwr_state);
1823 void (*led_control) (struct ieee80211_hw * hw,
1824 enum led_ctl_mode ledaction);
1825 void (*set_desc) (struct ieee80211_hw *hw, u8 * pdesc, bool istx,
1826 u8 desc_name, u8 * val);
1827 u32(*get_desc) (u8 * pdesc, bool istx, u8 desc_name);
1828 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
1829 u8 hw_queue, u16 index);
1830 void (*tx_polling) (struct ieee80211_hw * hw, u8 hw_queue);
1831 void (*enable_hw_sec) (struct ieee80211_hw * hw);
1832 void (*set_key) (struct ieee80211_hw * hw, u32 key_index,
1833 u8 * p_macaddr, bool is_group, u8 enc_algo,
1834 bool is_wepkey, bool clear_all);
1835 void (*init_sw_leds) (struct ieee80211_hw * hw);
1836 u32(*get_bbreg) (struct ieee80211_hw * hw, u32 regaddr, u32 bitmask);
1837 void (*set_bbreg) (struct ieee80211_hw * hw, u32 regaddr, u32 bitmask,
1838 u32 data);
1839 u32(*get_rfreg) (struct ieee80211_hw * hw, enum radio_path rfpath,
1840 u32 regaddr, u32 bitmask);
1841 void (*set_rfreg) (struct ieee80211_hw * hw, enum radio_path rfpath,
1842 u32 regaddr, u32 bitmask, u32 data);
1843 void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1844 bool allow_all_da, bool write_into_reg);
1845 void (*linked_set_reg) (struct ieee80211_hw * hw);
1846 void (*check_switch_to_dmdp) (struct ieee80211_hw * hw);
1847 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
1848 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
1849 void (*c2h_command_handle) (struct ieee80211_hw *hw);
1850 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw, bool mstate);
1851 void (*bt_turn_off_bt_coexist_before_enter_lps) (struct ieee80211_hw *hw);
1852 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
1853 u32 cmd_len, u8 *p_cmdbuffer);
1854 bool (*get_btc_status) (void);
1855 u32 (*rx_command_packet_handler)(struct ieee80211_hw *hw, struct rtl_stats status, struct sk_buff *skb);
1856};
1857
1858struct rtl_intf_ops {
1859 /*com */
1860 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1861 int (*adapter_start) (struct ieee80211_hw * hw);
1862 void (*adapter_stop) (struct ieee80211_hw * hw);
1863 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1864 struct rtl_priv **buddy_priv);
1865
1866/*<delete in kernel start>*/
1867#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1868 int (*adapter_tx) (struct ieee80211_hw * hw, struct sk_buff * skb,
1869 struct rtl_tcb_desc *ptcb_desc);
1870#else
1871/*<delete in kernel end>*/
1872 int (*adapter_tx) (struct ieee80211_hw *hw,
1873 struct ieee80211_sta *sta,
1874 struct sk_buff *skb,
1875 struct rtl_tcb_desc *ptcb_desc);
1876/*<delete in kernel start>*/
1877#endif
1878/*<delete in kernel end>*/
1879#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
1880 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
1881#else
1882 void (*flush)(struct ieee80211_hw *hw, bool drop);
1883#endif
1884 int (*reset_trx_ring) (struct ieee80211_hw * hw);
1885/*<delete in kernel start>*/
1886#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
1887 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1888#else
1889/*<delete in kernel end>*/
1890 bool (*waitq_insert) (struct ieee80211_hw *hw,
1891 struct ieee80211_sta *sta,
1892 struct sk_buff *skb);
1893/*<delete in kernel start>*/
1894#endif
1895/*<delete in kernel end>*/
1896
1897 /*pci */
1898 void (*disable_aspm) (struct ieee80211_hw * hw);
1899 void (*enable_aspm) (struct ieee80211_hw * hw);
1900
1901 /*usb */
1902};
1903
1904struct rtl_mod_params {
1905 /* default: 0 = using hardware encryption */
1906 bool sw_crypto;
1907
1908 /* default: 1 = using no linked power save */
1909 bool b_inactiveps;
1910
1911 /* default: 1 = using linked sw power save */
1912 bool b_swctrl_lps;
1913
1914 /* default: 1 = using linked fw power save */
1915 bool b_fwctrl_lps;
1916};
1917
1918struct rtl_hal_cfg {
1919 u8 bar_id;
1920 bool write_readback;
1921 char *name;
1922 char *fw_name;
1923 struct rtl_hal_ops *ops;
1924 struct rtl_mod_params *mod_params;
1925
1926 /*this map used for some registers or vars
1927 defined int HAL but used in MAIN */
1928 u32 maps[RTL_VAR_MAP_MAX];
1929
1930};
1931
1932struct rtl_locks {
1933 /* mutex */
1934 struct mutex conf_mutex;
1935
1936 /*spin lock */
1937 spinlock_t ips_lock;
1938 spinlock_t irq_th_lock;
1939 spinlock_t h2c_lock;
1940 spinlock_t rf_ps_lock;
1941 spinlock_t rf_lock;
1942 spinlock_t lps_lock;
1943 spinlock_t waitq_lock;
1944 spinlock_t entry_list_lock;
1945
1946 /*FW clock change */
1947 spinlock_t fw_ps_lock;
1948
1949 /*Dul mac*/
1950 spinlock_t cck_and_rw_pagea_lock;
1951
1952 /*Easy concurrent*/
1953 spinlock_t check_sendpkt_lock;
1954
1955 spinlock_t iqk_lock;
1956};
1957
1958struct rtl_works {
1959 struct ieee80211_hw *hw;
1960
1961 /*timer */
1962 struct timer_list watchdog_timer;
1963 struct timer_list dualmac_easyconcurrent_retrytimer;
1964 struct timer_list fw_clockoff_timer;
1965 struct timer_list fast_antenna_trainning_timer;
1966 /*task */
1967 struct tasklet_struct irq_tasklet;
1968 struct tasklet_struct irq_prepare_bcn_tasklet;
1969
1970 /*work queue */
1971 struct workqueue_struct *rtl_wq;
1972 struct delayed_work watchdog_wq;
1973 struct delayed_work ips_nic_off_wq;
1974
1975 /* For SW LPS */
1976 struct delayed_work ps_work;
1977 struct delayed_work ps_rfon_wq;
1978 struct delayed_work fwevt_wq;
1979};
1980
1981struct rtl_debug {
1982 u32 dbgp_type[DBGP_TYPE_MAX];
1983 u32 global_debuglevel;
1984 u64 global_debugcomponents;
1985
1986 /* add for proc debug */
1987 struct proc_dir_entry *proc_dir;
1988 char proc_name[20];
1989};
1990
1991#define MIMO_PS_STATIC 0
1992#define MIMO_PS_DYNAMIC 1
1993#define MIMO_PS_NOLIMIT 3
1994
1995struct rtl_dualmac_easy_concurrent_ctl {
1996 enum band_type currentbandtype_backfordmdp;
1997 bool bclose_bbandrf_for_dmsp;
1998 bool bchange_to_dmdp;
1999 bool bchange_to_dmsp;
2000 bool bswitch_in_process;
2001};
2002
2003struct rtl_dmsp_ctl {
2004 bool bactivescan_for_slaveofdmsp;
2005 bool bscan_for_anothermac_fordmsp;
2006 bool bscan_for_itself_fordmsp;
2007 bool bwritedig_for_anothermacofdmsp;
2008 u32 curdigvalue_for_anothermacofdmsp;
2009 bool bchangecckpdstate_for_anothermacofdmsp;
2010 u8 curcckpdstate_for_anothermacofdmsp;
2011 bool bchangetxhighpowerlvl_for_anothermacofdmsp;
2012 u8 curtxhighlvl_for_anothermacofdmsp;
2013 long rssivalmin_for_anothermacofdmsp;
2014};
2015
2016struct rtl_global_var {
2017 /* from this list we can get
2018 * other adapter's rtl_priv */
2019 struct list_head glb_priv_list;
2020 spinlock_t glb_list_lock;
2021};
2022
2023struct rtl_btc_info {
2024 u8 bt_type;
2025 u8 btcoexist;
2026 u8 ant_num;
2027};
2028
2029struct rtl_btc_ops {
2030 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2031 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2032 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2033 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2034 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2035 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2036 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2037 enum rt_media_status mstatus);
2038 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2039 void (*btc_halt_notify) (void);
2040 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2041 u8 * tmp_buf, u8 length);
2042 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2043 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2044 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2045};
2046
2047struct rtl_bt_coexist {
2048 struct rtl_btc_ops *btc_ops;
2049 struct rtl_btc_info btc_info;
2050};
2051
2052
2053struct rtl_priv {
2054 struct list_head list;
2055#ifdef VIF_TODO
2056 struct vif_priv vif_priv;
2057#endif
2058 struct rtl_priv *buddy_priv;
2059 struct rtl_global_var *glb_var;
2060 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2061 struct rtl_dmsp_ctl dmsp_ctl;
2062 struct rtl_locks locks;
2063 struct rtl_works works;
2064 struct rtl_mac mac80211;
2065 struct rtl_hal rtlhal;
2066 struct rtl_regulatory regd;
2067 struct rtl_rfkill rfkill;
2068 struct rtl_io io;
2069 struct rtl_phy phy;
2070 struct rtl_dm dm;
2071 struct rtl_security sec;
2072 struct rtl_efuse efuse;
2073
2074 struct rtl_ps_ctl psc;
2075 struct rate_adaptive ra;
2076 struct dynamic_primary_cca primarycca;
2077 struct wireless_stats stats;
2078 struct rt_link_detect link_info;
2079 struct false_alarm_statistics falsealm_cnt;
2080
2081 struct rtl_rate_priv *rate_priv;
2082
2083 struct rtl_debug dbg;
2084
2085 /* sta entry list for ap adhoc or mesh */
2086 struct list_head entry_list;
2087
2088 /*
2089 *hal_cfg : for diff cards
2090 *intf_ops : for diff interrface usb/pcie
2091 */
2092 struct rtl_hal_cfg *cfg;
2093 struct rtl_intf_ops *intf_ops;
2094
2095 /*this var will be set by set_bit,
2096 and was used to indicate status of
2097 interface or hardware */
2098 unsigned long status;
2099
2100 /* intel Proximity, should be alloc mem
2101 * in intel Proximity module and can only
2102 * be used in intel Proximity mode */
2103 struct proxim proximity;
2104
2105 /*for bt coexist use*/
2106 struct rtl_bt_coexist btcoexist;
2107
2108 /* seperate 92ee from other ICs,
2109 * 92ee use new trx flow. */
2110 bool use_new_trx_flow;
2111 /*This must be the last item so
2112 that it points to the data allocated
2113 beyond this structure like:
2114 rtl_pci_priv or rtl_usb_priv */
2115 u8 priv[0];
2116};
2117
2118#define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2119#define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2120#define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2121#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2122#define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2123#define rtl_sec(rtlpriv) (&((rtlpriv)->sec))
2124#define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2125/***************************************
2126 Bluetooth Co-existance Related
2127****************************************/
2128
2129enum bt_ant_num {
2130 ANT_X2 = 0,
2131 ANT_X1 = 1,
2132};
2133
2134enum bt_co_type {
2135 BT_2WIRE = 0,
2136 BT_ISSC_3WIRE = 1,
2137 BT_ACCEL = 2,
2138 BT_CSR_BC4 = 3,
2139 BT_CSR_BC8 = 4,
2140 BT_RTL8756 = 5,
2141 BT_RTL8723A = 6,
2142 BT_RTL8821A = 7,
2143 BT_RTL8723B = 8,
2144 BT_RTL8192E = 9,
2145 BT_RTL8812A = 11,
2146};
2147
2148enum bt_total_ant_num{
2149 ANT_TOTAL_X2 = 0,
2150 ANT_TOTAL_X1 = 1
2151};
2152
2153enum bt_cur_state {
2154 BT_OFF = 0,
2155 BT_ON = 1,
2156};
2157
2158enum bt_service_type {
2159 BT_SCO = 0,
2160 BT_A2DP = 1,
2161 BT_HID = 2,
2162 BT_HID_IDLE = 3,
2163 BT_SCAN = 4,
2164 BT_IDLE = 5,
2165 BT_OTHER_ACTION = 6,
2166 BT_BUSY = 7,
2167 BT_OTHERBUSY = 8,
2168 BT_PAN = 9,
2169};
2170
2171enum bt_radio_shared {
2172 BT_RADIO_SHARED = 0,
2173 BT_RADIO_INDIVIDUAL = 1,
2174};
2175
2176struct bt_coexist_info {
2177
2178 /* EEPROM BT info. */
2179 u8 eeprom_bt_coexist;
2180 u8 eeprom_bt_type;
2181 u8 eeprom_bt_ant_num;
2182 u8 eeprom_bt_ant_isolation;
2183 u8 eeprom_bt_radio_shared;
2184
2185 u8 bt_coexistence;
2186 u8 bt_ant_num;
2187 u8 bt_coexist_type;
2188 u8 bt_state;
2189 u8 bt_cur_state; /* 0:on, 1:off */
2190 u8 bt_ant_isolation; /* 0:good, 1:bad */
2191 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2192 u8 bt_service;
2193 u8 bt_radio_shared_type;
2194 u8 bt_rfreg_origin_1e;
2195 u8 bt_rfreg_origin_1f;
2196 u8 bt_rssi_state;
2197 u32 ratio_tx;
2198 u32 ratio_pri;
2199 u32 bt_edca_ul;
2200 u32 bt_edca_dl;
2201
2202 bool b_init_set;
2203 bool b_bt_busy_traffic;
2204 bool b_bt_traffic_mode_set;
2205 bool b_bt_non_traffic_mode_set;
2206
2207 bool b_fw_coexist_all_off;
2208 bool b_sw_coexist_all_off;
2209 bool b_hw_coexist_all_off;
2210 u32 current_state;
2211 u32 previous_state;
2212 u32 current_state_h;
2213 u32 previous_state_h;
2214
2215 u8 bt_pre_rssi_state;
2216 u8 bt_pre_rssi_state1;
2217
2218 u8 b_reg_bt_iso;
2219 u8 b_reg_bt_sco;
2220 bool b_balance_on;
2221 u8 bt_active_zero_cnt;
2222 bool b_cur_bt_disabled;
2223 bool b_pre_bt_disabled;
2224
2225 u8 bt_profile_case;
2226 u8 bt_profile_action;
2227 bool b_bt_busy;
2228 bool b_hold_for_bt_operation;
2229 u8 lps_counter;
2230};
2231
2232
2233/****************************************
2234 mem access macro define start
2235 Call endian free function when
2236 1. Read/write packet content.
2237 2. Before write integer to IO.
2238 3. After read integer from IO.
2239****************************************/
2240/* Convert little data endian to host */
2241#define EF1BYTE(_val) \
2242 ((u8)(_val))
2243#define EF2BYTE(_val) \
2244 (le16_to_cpu(_val))
2245#define EF4BYTE(_val) \
2246 (le32_to_cpu(_val))
2247
2248/* Read data from memory */
2249#define READEF1BYTE(_ptr) \
2250 EF1BYTE(*((u8 *)(_ptr)))
2251#define READEF2BYTE(_ptr) \
2252 EF2BYTE(*((u16 *)(_ptr)))
2253#define READEF4BYTE(_ptr) \
2254 EF4BYTE(*((u32 *)(_ptr)))
2255
2256/* Write data to memory */
2257#define WRITEEF1BYTE(_ptr, _val) \
2258 (*((u8 *)(_ptr)))=EF1BYTE(_val)
2259#define WRITEEF2BYTE(_ptr, _val) \
2260 (*((u16 *)(_ptr)))=EF2BYTE(_val)
2261#define WRITEEF4BYTE(_ptr, _val) \
2262 (*((u32 *)(_ptr)))=EF4BYTE(_val)
2263
2264/*Example:
2265BIT_LEN_MASK_32(0) => 0x00000000
2266BIT_LEN_MASK_32(1) => 0x00000001
2267BIT_LEN_MASK_32(2) => 0x00000003
2268BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
2269#define BIT_LEN_MASK_32(__bitlen) \
2270 (0xFFFFFFFF >> (32 - (__bitlen)))
2271#define BIT_LEN_MASK_16(__bitlen) \
2272 (0xFFFF >> (16 - (__bitlen)))
2273#define BIT_LEN_MASK_8(__bitlen) \
2274 (0xFF >> (8 - (__bitlen)))
2275
2276/*Example:
2277BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2278BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/
2279#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2280 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2281#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2282 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2283#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2284 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2285
2286/*Description:
2287Return 4-byte value in host byte ordering from
22884-byte pointer in little-endian system.*/
2289#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2290 (EF4BYTE(*((u32 *)(__pstart))))
2291#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2292 (EF2BYTE(*((u16 *)(__pstart))))
2293#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2294 (EF1BYTE(*((u8 *)(__pstart))))
2295
2296/*Description:
2297Translate subfield (continuous bits in little-endian) of 4-byte
2298value to host byte ordering.*/
2299#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2300 ( \
2301 ( LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset) ) & \
2302 BIT_LEN_MASK_32(__bitlen) \
2303 )
2304#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2305 ( \
2306 ( LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset) ) & \
2307 BIT_LEN_MASK_16(__bitlen) \
2308 )
2309#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2310 ( \
2311 ( LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset) ) & \
2312 BIT_LEN_MASK_8(__bitlen) \
2313 )
2314
2315/*Description:
2316Mask subfield (continuous bits in little-endian) of 4-byte value
2317and return the result in 4-byte value in host byte ordering.*/
2318#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2319 ( \
2320 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2321 ( ~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) ) \
2322 )
2323#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2324 ( \
2325 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2326 ( ~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) ) \
2327 )
2328#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2329 ( \
2330 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2331 ( ~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) ) \
2332 )
2333
2334/*Description:
2335Set subfield of little-endian 4-byte value to specified value. */
2336#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2337 *((u32 *)(__pstart)) = EF4BYTE \
2338 ( \
2339 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2340 ( (((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset) )\
2341 );
2342#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2343 *((u16 *)(__pstart)) = EF2BYTE \
2344 ( \
2345 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2346 ( (((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset) )\
2347 );
2348#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2349 *((u8 *)(__pstart)) = EF1BYTE \
2350 ( \
2351 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2352 ( (((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset) ) \
2353 );
2354
2355#define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2356 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2357
2358/****************************************
2359 mem access macro define end
2360****************************************/
2361
2362#define byte(x,n) ((x >> (8 * n)) & 0xff)
2363
2364#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2365#define RTL_WATCH_DOG_TIME 2000
2366#define MSECS(t) msecs_to_jiffies(t)
2367#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS)
2368#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
2369#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
2370#define WLAN_FC_MORE_DATA(fc) ((fc) & IEEE80211_FCTL_MOREDATA)
2371#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
2372#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
2373#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
2374
2375#define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2376#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2377#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2378/*NIC halt, re-initialize hw parameters*/
2379#define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2380#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2381#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2382/*Always enable ASPM and Clock Req in initialization.*/
2383#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2384/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2385#define RT_PS_LEVEL_ASPM BIT(7)
2386/*When LPS is on, disable 2R if no packet is received or transmittd.*/
2387#define RT_RF_LPS_DISALBE_2R BIT(30)
2388#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2389#define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2390 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2391#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2392 (ppsc->cur_ps_level &= (~(_ps_flg)))
2393#define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2394 (ppsc->cur_ps_level |= _ps_flg)
2395
2396#define container_of_dwork_rtl(x,y,z) \
2397 container_of(container_of(x, struct delayed_work, work), y, z)
2398
2399#define FILL_OCTET_STRING(_os,_octet,_len) \
2400 (_os).octet=(u8*)(_octet); \
2401 (_os).length=(_len);
2402
2403#define CP_MACADDR(des,src) \
2404 ((des)[0]=(src)[0],(des)[1]=(src)[1],\
2405 (des)[2]=(src)[2],(des)[3]=(src)[3],\
2406 (des)[4]=(src)[4],(des)[5]=(src)[5])
2407
2408static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2409{
2410 return rtlpriv->io.read8_sync(rtlpriv, addr);
2411}
2412
2413static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2414{
2415 return rtlpriv->io.read16_sync(rtlpriv, addr);
2416}
2417
2418static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2419{
2420 return rtlpriv->io.read32_sync(rtlpriv, addr);
2421}
2422
2423static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2424{
2425 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2426
2427 if (rtlpriv->cfg->write_readback)
2428 rtlpriv->io.read8_sync(rtlpriv, addr);
2429}
2430
2431static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2432{
2433 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2434
2435 if (rtlpriv->cfg->write_readback)
2436 rtlpriv->io.read16_sync(rtlpriv, addr);
2437}
2438
2439static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2440 u32 addr, u32 val32)
2441{
2442 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2443
2444 if (rtlpriv->cfg->write_readback)
2445 rtlpriv->io.read32_sync(rtlpriv, addr);
2446}
2447
2448static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2449 u32 regaddr, u32 bitmask)
2450{
2451 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
2452 regaddr,
2453 bitmask);
2454}
2455
2456static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2457 u32 bitmask, u32 data)
2458{
2459 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
2460 regaddr, bitmask,
2461 data);
2462
2463}
2464
2465static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2466 enum radio_path rfpath, u32 regaddr,
2467 u32 bitmask)
2468{
2469 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
2470 rfpath,
2471 regaddr,
2472 bitmask);
2473}
2474
2475static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2476 enum radio_path rfpath, u32 regaddr,
2477 u32 bitmask, u32 data)
2478{
2479 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
2480 rfpath, regaddr,
2481 bitmask, data);
2482}
2483
2484static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2485{
2486 return (_HAL_STATE_STOP == rtlhal->state);
2487}
2488
2489static inline void set_hal_start(struct rtl_hal *rtlhal)
2490{
2491 rtlhal->state = _HAL_STATE_START;
2492}
2493
2494static inline void set_hal_stop(struct rtl_hal *rtlhal)
2495{
2496 rtlhal->state = _HAL_STATE_STOP;
2497}
2498
2499static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2500{
2501 return rtlphy->rf_type;
2502}
2503
2504static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2505{
2506 return (struct ieee80211_hdr *)(skb->data);
2507}
2508
2509static inline u16 rtl_get_fc(struct sk_buff *skb)
2510{
2511 return le16_to_cpu(rtl_get_hdr(skb)->frame_control);
2512}
2513
2514static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2515{
2516 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2517}
2518
2519static inline u16 rtl_get_tid(struct sk_buff *skb)
2520{
2521 return rtl_get_tid_h(rtl_get_hdr(skb));
2522}
2523
2524static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2525 u8 *mac_addr)
2526{
2527 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2528 return ieee80211_find_sta(mac->vif, mac_addr);
2529}
2530
2531struct ieee80211_hw *rtl_pci_get_hw_pointer(void);
2532#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 19:50:14 -0400