diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-20 04:40:42 -0500 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-20 04:41:07 -0500 |
commit | fe4402931e43e81a4129eba41d05cf8907603af5 (patch) | |
tree | ae9d438fa649bf12fd8d7119370eeca7b4d7ebb6 | |
parent | 417ae1476de3ae9689a374d70565f41b3474641e (diff) | |
parent | 4efe070896e1f7373c98a13713e659d1f5dee52a (diff) |
Merge branch 'drm-intel-fixes' into drm-intel-next
Apply the SandyBridge stability fixes from -fixes.
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 25 |
2 files changed, 30 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4c71f5692dae..77b153093cf1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -513,6 +513,10 @@ | |||
513 | #define GEN6_BLITTER_SYNC_STATUS (1 << 24) | 513 | #define GEN6_BLITTER_SYNC_STATUS (1 << 24) |
514 | #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) | 514 | #define GEN6_BLITTER_USER_INTERRUPT (1 << 22) |
515 | 515 | ||
516 | #define GEN6_BLITTER_ECOSKPD 0x221d0 | ||
517 | #define GEN6_BLITTER_LOCK_SHIFT 16 | ||
518 | #define GEN6_BLITTER_FBC_NOTIFY (1<<3) | ||
519 | |||
516 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 | 520 | #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 |
517 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) | 521 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) |
518 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) | 522 | #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) |
@@ -2631,6 +2635,8 @@ | |||
2631 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 | 2635 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 |
2632 | 2636 | ||
2633 | #define PCH_DSPCLK_GATE_D 0x42020 | 2637 | #define PCH_DSPCLK_GATE_D 0x42020 |
2638 | # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) | ||
2639 | # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) | ||
2634 | # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) | 2640 | # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) |
2635 | # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) | 2641 | # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) |
2636 | 2642 | ||
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2c2ecab6627f..36958fdabdce 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1718,6 +1718,26 @@ static bool g4x_fbc_enabled(struct drm_device *dev) | |||
1718 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | 1718 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
1719 | } | 1719 | } |
1720 | 1720 | ||
1721 | static void sandybridge_blit_fbc_update(struct drm_device *dev) | ||
1722 | { | ||
1723 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
1724 | u32 blt_ecoskpd; | ||
1725 | |||
1726 | /* Make sure blitter notifies FBC of writes */ | ||
1727 | __gen6_force_wake_get(dev_priv); | ||
1728 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); | ||
1729 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | ||
1730 | GEN6_BLITTER_LOCK_SHIFT; | ||
1731 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | ||
1732 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | ||
1733 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | ||
1734 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | ||
1735 | GEN6_BLITTER_LOCK_SHIFT); | ||
1736 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | ||
1737 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | ||
1738 | __gen6_force_wake_put(dev_priv); | ||
1739 | } | ||
1740 | |||
1721 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | 1741 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1722 | { | 1742 | { |
1723 | struct drm_device *dev = crtc->dev; | 1743 | struct drm_device *dev = crtc->dev; |
@@ -1771,6 +1791,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |||
1771 | I915_WRITE(SNB_DPFC_CTL_SA, | 1791 | I915_WRITE(SNB_DPFC_CTL_SA, |
1772 | SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence); | 1792 | SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence); |
1773 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | 1793 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
1794 | sandybridge_blit_fbc_update(dev); | ||
1774 | } | 1795 | } |
1775 | 1796 | ||
1776 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); | 1797 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
@@ -6818,7 +6839,9 @@ void intel_enable_clock_gating(struct drm_device *dev) | |||
6818 | 6839 | ||
6819 | if (IS_GEN5(dev)) { | 6840 | if (IS_GEN5(dev)) { |
6820 | /* Required for FBC */ | 6841 | /* Required for FBC */ |
6821 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; | 6842 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | |
6843 | DPFCRUNIT_CLOCK_GATE_DISABLE | | ||
6844 | DPFDUNIT_CLOCK_GATE_DISABLE; | ||
6822 | /* Required for CxSR */ | 6845 | /* Required for CxSR */ |
6823 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | 6846 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; |
6824 | 6847 | ||