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authorStephane Viau <sviau@codeaurora.org>2015-04-30 13:45:52 -0400
committerRob Clark <robdclark@gmail.com>2015-05-14 11:29:20 -0400
commitfe34464df5e8bd4b09db170477f32db4eade0444 (patch)
treedc2fd1c3722d63aeb84ca336f3830cbe4a348bc5
parent651ad3f52b9d0b11b8ebe94c3810ac89f9f75653 (diff)
drm/msm/mdp5: Fix iteration on INTF config array
The current iteration in get_dsi_id_from_intf() is wrong: instead of iterating until hw_cfg->intf.count, we need to iterate until MDP5_INTF_NUM_MAX here. Let's take the example of msm8x16: hw_cfg->intf.count = 1 intfs[0] = INTF_Disabled intfs[1] = INTF_DSI If we stop iterating once i reaches hw_cfg->intf.count (== 1), we will miss the test for intfs[1]. Actually, this hw_cfg->intf.count entry is quite confusing and is not (or *should not be*) used anywhere else; let's remove it. Signed-off-by: Stephane Viau <sviau@codeaurora.org>
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c34
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h9
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c12
3 files changed, 29 insertions, 26 deletions
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
index e001e6b2296a..8b9a7931b162 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
@@ -72,14 +72,13 @@ const struct mdp5_cfg_hw msm8x74_config = {
72 .base = { 0x12d00, 0x12e00, 0x12f00 }, 72 .base = { 0x12d00, 0x12e00, 0x12f00 },
73 }, 73 },
74 .intf = { 74 .intf = {
75 .count = 4,
76 .base = { 0x12500, 0x12700, 0x12900, 0x12b00 }, 75 .base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
77 }, 76 .connect = {
78 .intfs = { 77 [0] = INTF_eDP,
79 [0] = INTF_eDP, 78 [1] = INTF_DSI,
80 [1] = INTF_DSI, 79 [2] = INTF_DSI,
81 [2] = INTF_DSI, 80 [3] = INTF_HDMI,
82 [3] = INTF_HDMI, 81 },
83 }, 82 },
84 .max_clk = 200000000, 83 .max_clk = 200000000,
85}; 84};
@@ -142,14 +141,13 @@ const struct mdp5_cfg_hw apq8084_config = {
142 .base = { 0x12f00, 0x13000, 0x13100, 0x13200 }, 141 .base = { 0x12f00, 0x13000, 0x13100, 0x13200 },
143 }, 142 },
144 .intf = { 143 .intf = {
145 .count = 5,
146 .base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 }, 144 .base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
147 }, 145 .connect = {
148 .intfs = { 146 [0] = INTF_eDP,
149 [0] = INTF_eDP, 147 [1] = INTF_DSI,
150 [1] = INTF_DSI, 148 [2] = INTF_DSI,
151 [2] = INTF_DSI, 149 [3] = INTF_HDMI,
152 [3] = INTF_HDMI, 150 },
153 }, 151 },
154 .max_clk = 320000000, 152 .max_clk = 320000000,
155}; 153};
@@ -196,10 +194,12 @@ const struct mdp5_cfg_hw msm8x16_config = {
196 194
197 }, 195 },
198 .intf = { 196 .intf = {
199 .count = 1, /* INTF_1 */ 197 .base = { 0x00000, 0x6b800 },
200 .base = { 0x6B800 }, 198 .connect = {
199 [0] = INTF_DISABLED,
200 [1] = INTF_DSI,
201 },
201 }, 202 },
202 /* TODO enable .intfs[] with [1] = INTF_DSI, once DSI is implemented */
203 .max_clk = 320000000, 203 .max_clk = 320000000,
204}; 204};
205 205
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
index 3a551b0892d8..69349abe59f2 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
@@ -59,6 +59,11 @@ struct mdp5_smp_block {
59 59
60#define MDP5_INTF_NUM_MAX 5 60#define MDP5_INTF_NUM_MAX 5
61 61
62struct mdp5_intf_block {
63 uint32_t base[MAX_BASES];
64 u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
65};
66
62struct mdp5_cfg_hw { 67struct mdp5_cfg_hw {
63 char *name; 68 char *name;
64 69
@@ -72,9 +77,7 @@ struct mdp5_cfg_hw {
72 struct mdp5_sub_block dspp; 77 struct mdp5_sub_block dspp;
73 struct mdp5_sub_block ad; 78 struct mdp5_sub_block ad;
74 struct mdp5_sub_block pp; 79 struct mdp5_sub_block pp;
75 struct mdp5_sub_block intf; 80 struct mdp5_intf_block intf;
76
77 u32 intfs[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
78 81
79 uint32_t max_clk; 82 uint32_t max_clk;
80}; 83};
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index dfa8beb9343a..bbacf9d2b738 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -206,8 +206,8 @@ static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
206 206
207static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) 207static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
208{ 208{
209 const int intf_cnt = hw_cfg->intf.count; 209 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
210 const u32 *intfs = hw_cfg->intfs; 210 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
211 int id = 0, i; 211 int id = 0, i;
212 212
213 for (i = 0; i < intf_cnt; i++) { 213 for (i = 0; i < intf_cnt; i++) {
@@ -228,7 +228,7 @@ static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num)
228 struct msm_drm_private *priv = dev->dev_private; 228 struct msm_drm_private *priv = dev->dev_private;
229 const struct mdp5_cfg_hw *hw_cfg = 229 const struct mdp5_cfg_hw *hw_cfg =
230 mdp5_cfg_get_hw_config(mdp5_kms->cfg); 230 mdp5_cfg_get_hw_config(mdp5_kms->cfg);
231 enum mdp5_intf_type intf_type = hw_cfg->intfs[intf_num]; 231 enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num];
232 struct drm_encoder *encoder; 232 struct drm_encoder *encoder;
233 int ret = 0; 233 int ret = 0;
234 234
@@ -365,7 +365,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
365 /* Construct encoders and modeset initialize connector devices 365 /* Construct encoders and modeset initialize connector devices
366 * for each external display interface. 366 * for each external display interface.
367 */ 367 */
368 for (i = 0; i < ARRAY_SIZE(hw_cfg->intfs); i++) { 368 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
369 ret = modeset_init_intf(mdp5_kms, i); 369 ret = modeset_init_intf(mdp5_kms, i);
370 if (ret) 370 if (ret)
371 goto fail; 371 goto fail;
@@ -514,8 +514,8 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
514 */ 514 */
515 mdp5_enable(mdp5_kms); 515 mdp5_enable(mdp5_kms);
516 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { 516 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) {
517 if (!config->hw->intf.base[i] || 517 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) ||
518 mdp5_cfg_intf_is_virtual(config->hw->intfs[i])) 518 !config->hw->intf.base[i])
519 continue; 519 continue;
520 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); 520 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
521 } 521 }