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authorBruce Allan <bruce.w.allan@intel.com>2011-12-21 04:47:10 -0500
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2012-01-26 22:00:19 -0500
commitfe2ddfb510f9d305a6654c7538c5c8faf326a16c (patch)
treef18e0d3839909b56ba6760d83ffa700ed9e6e960
parentc8243ee0488d9bc12995ca7ea02f651db820622e (diff)
e1000e: split lib.c into three more-appropriate files
The generic lib.c file contains code relative to the various MACs, NVM and Manageability supported by the driver. This patch splits the file into three which are specific to those areas similar to how the PHY-specific code is in phy.c and code specific to the 80003es2lan, 8257x, and ichX MAC families are in their own files. The generic code that is applicable to all MAC/PHY parts supported by the driver remains in netdev.c, param.c and ethtool.c files. No change in functionality, just moving code around for ease of maintenance, with some whitespace and other checkpatch cleanups. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/e1000e/Makefile3
-rw-r--r--drivers/net/ethernet/intel/e1000e/mac.c (renamed from drivers/net/ethernet/intel/e1000e/lib.c)1019
-rw-r--r--drivers/net/ethernet/intel/e1000e/manage.c377
-rw-r--r--drivers/net/ethernet/intel/e1000e/nvm.c647
4 files changed, 1051 insertions, 995 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/Makefile b/drivers/net/ethernet/intel/e1000e/Makefile
index 948c05db5d68..8b888e5f6a06 100644
--- a/drivers/net/ethernet/intel/e1000e/Makefile
+++ b/drivers/net/ethernet/intel/e1000e/Makefile
@@ -33,5 +33,6 @@
33obj-$(CONFIG_E1000E) += e1000e.o 33obj-$(CONFIG_E1000E) += e1000e.o
34 34
35e1000e-objs := 82571.o ich8lan.o 80003es2lan.o \ 35e1000e-objs := 82571.o ich8lan.o 80003es2lan.o \
36 lib.o phy.o param.o ethtool.o netdev.o 36 mac.o manage.o nvm.o phy.o \
37 param.o ethtool.o netdev.o
37 38
diff --git a/drivers/net/ethernet/intel/e1000e/lib.c b/drivers/net/ethernet/intel/e1000e/mac.c
index e2678bda8599..64b6f439338a 100644
--- a/drivers/net/ethernet/intel/e1000e/lib.c
+++ b/drivers/net/ethernet/intel/e1000e/mac.c
@@ -28,19 +28,6 @@
28 28
29#include "e1000.h" 29#include "e1000.h"
30 30
31enum e1000_mng_mode {
32 e1000_mng_mode_none = 0,
33 e1000_mng_mode_asf,
34 e1000_mng_mode_pt,
35 e1000_mng_mode_ipmi,
36 e1000_mng_mode_host_if_only
37};
38
39#define E1000_FACTPS_MNGCG 0x20000000
40
41/* Intel(R) Active Management Technology signature */
42#define E1000_IAMT_SIGNATURE 0x544D4149
43
44/** 31/**
45 * e1000e_get_bus_info_pcie - Get PCIe bus information 32 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure 33 * @hw: pointer to the HW structure
@@ -151,7 +138,7 @@ void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
151void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) 138void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
152{ 139{
153 u32 i; 140 u32 i;
154 u8 mac_addr[ETH_ALEN] = {0}; 141 u8 mac_addr[ETH_ALEN] = { 0 };
155 142
156 /* Setup the receive address */ 143 /* Setup the receive address */
157 e_dbg("Programming MAC Address into RAR[0]\n"); 144 e_dbg("Programming MAC Address into RAR[0]\n");
@@ -159,7 +146,7 @@ void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
159 e1000e_rar_set(hw, hw->mac.addr, 0); 146 e1000e_rar_set(hw, hw->mac.addr, 0);
160 147
161 /* Zero out the other (rar_entry_count - 1) receive addresses */ 148 /* Zero out the other (rar_entry_count - 1) receive addresses */
162 e_dbg("Clearing RAR[1-%u]\n", rar_count-1); 149 e_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
163 for (i = 1; i < rar_count; i++) 150 for (i = 1; i < rar_count; i++)
164 e1000e_rar_set(hw, mac_addr, i); 151 e1000e_rar_set(hw, mac_addr, i);
165} 152}
@@ -192,7 +179,7 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
192 goto out; 179 goto out;
193 180
194 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 181 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
195 &nvm_alt_mac_addr_offset); 182 &nvm_alt_mac_addr_offset);
196 if (ret_val) { 183 if (ret_val) {
197 e_dbg("NVM Read Error\n"); 184 e_dbg("NVM Read Error\n");
198 goto out; 185 goto out;
@@ -251,11 +238,10 @@ void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
251 * HW expects these in little endian so we reverse the byte order 238 * HW expects these in little endian so we reverse the byte order
252 * from network order (big endian) to little endian 239 * from network order (big endian) to little endian
253 */ 240 */
254 rar_low = ((u32) addr[0] | 241 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
255 ((u32) addr[1] << 8) | 242 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
256 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
257 243
258 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 244 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
259 245
260 /* If MAC address zero, no need to set the AV bit */ 246 /* If MAC address zero, no need to set the AV bit */
261 if (rar_low || rar_high) 247 if (rar_low || rar_high)
@@ -315,7 +301,7 @@ static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
315 * values resulting from each mc_filter_type... 301 * values resulting from each mc_filter_type...
316 * [0] [1] [2] [3] [4] [5] 302 * [0] [1] [2] [3] [4] [5]
317 * 01 AA 00 12 34 56 303 * 01 AA 00 12 34 56
318 * LSB MSB 304 * LSB MSB
319 * 305 *
320 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 306 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
321 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 307 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
@@ -338,7 +324,7 @@ static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
338 } 324 }
339 325
340 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 326 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
341 (((u16) mc_addr[5]) << bit_shift))); 327 (((u16)mc_addr[5]) << bit_shift)));
342 328
343 return hash_value; 329 return hash_value;
344} 330}
@@ -362,7 +348,7 @@ void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
362 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 348 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
363 349
364 /* update mta_shadow from mc_addr_list */ 350 /* update mta_shadow from mc_addr_list */
365 for (i = 0; (u32) i < mc_addr_count; i++) { 351 for (i = 0; (u32)i < mc_addr_count; i++) {
366 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 352 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
367 353
368 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 354 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
@@ -458,7 +444,7 @@ s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
458 return ret_val; 444 return ret_val;
459 445
460 if (!link) 446 if (!link)
461 return ret_val; /* No link detected */ 447 return ret_val; /* No link detected */
462 448
463 mac->get_link_status = false; 449 mac->get_link_status = false;
464 450
@@ -701,8 +687,7 @@ static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
701 687
702 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 688 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
703 hw->fc.requested_mode = e1000_fc_none; 689 hw->fc.requested_mode = e1000_fc_none;
704 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 690 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
705 NVM_WORD0F_ASM_DIR)
706 hw->fc.requested_mode = e1000_fc_tx_pause; 691 hw->fc.requested_mode = e1000_fc_tx_pause;
707 else 692 else
708 hw->fc.requested_mode = e1000_fc_full; 693 hw->fc.requested_mode = e1000_fc_full;
@@ -748,8 +733,7 @@ s32 e1000e_setup_link(struct e1000_hw *hw)
748 */ 733 */
749 hw->fc.current_mode = hw->fc.requested_mode; 734 hw->fc.current_mode = hw->fc.requested_mode;
750 735
751 e_dbg("After fix-ups FlowControl is now = %x\n", 736 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
752 hw->fc.current_mode);
753 737
754 /* Call the necessary media_type subroutine to configure the link. */ 738 /* Call the necessary media_type subroutine to configure the link. */
755 ret_val = mac->ops.setup_physical_interface(hw); 739 ret_val = mac->ops.setup_physical_interface(hw);
@@ -1195,9 +1179,9 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1195 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1179 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1196 */ 1180 */
1197 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1181 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1198 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1182 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1199 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1183 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1200 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1184 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1201 hw->fc.current_mode = e1000_fc_tx_pause; 1185 hw->fc.current_mode = e1000_fc_tx_pause;
1202 e_dbg("Flow Control = Tx PAUSE frames only.\n"); 1186 e_dbg("Flow Control = Tx PAUSE frames only.\n");
1203 } 1187 }
@@ -1261,7 +1245,8 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1261 * Read the status register for the current speed/duplex and store the current 1245 * Read the status register for the current speed/duplex and store the current
1262 * speed and duplex for copper connections. 1246 * speed and duplex for copper connections.
1263 **/ 1247 **/
1264s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex) 1248s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1249 u16 *duplex)
1265{ 1250{
1266 u32 status; 1251 u32 status;
1267 1252
@@ -1294,7 +1279,8 @@ s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *dup
1294 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1279 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1295 * for fiber/serdes links. 1280 * for fiber/serdes links.
1296 **/ 1281 **/
1297s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex) 1282s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed,
1283 u16 *duplex)
1298{ 1284{
1299 *speed = SPEED_1000; 1285 *speed = SPEED_1000;
1300 *duplex = FULL_DUPLEX; 1286 *duplex = FULL_DUPLEX;
@@ -1497,11 +1483,10 @@ s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1497 ledctl = er32(LEDCTL); 1483 ledctl = er32(LEDCTL);
1498 hw->mac.ledctl_default = ledctl; 1484 hw->mac.ledctl_default = ledctl;
1499 /* Turn off LED0 */ 1485 /* Turn off LED0 */
1500 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1486 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1501 E1000_LEDCTL_LED0_BLINK | 1487 E1000_LEDCTL_LED0_MODE_MASK);
1502 E1000_LEDCTL_LED0_MODE_MASK);
1503 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1488 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1504 E1000_LEDCTL_LED0_MODE_SHIFT); 1489 E1000_LEDCTL_LED0_MODE_SHIFT);
1505 ew32(LEDCTL, ledctl); 1490 ew32(LEDCTL, ledctl);
1506 } else if (hw->phy.media_type == e1000_media_type_copper) { 1491 } else if (hw->phy.media_type == e1000_media_type_copper) {
1507 ew32(LEDCTL, hw->mac.ledctl_mode1); 1492 ew32(LEDCTL, hw->mac.ledctl_mode1);
@@ -1537,7 +1522,7 @@ s32 e1000e_blink_led_generic(struct e1000_hw *hw)
1537 if (hw->phy.media_type == e1000_media_type_fiber) { 1522 if (hw->phy.media_type == e1000_media_type_fiber) {
1538 /* always blink LED0 for PCI-E fiber */ 1523 /* always blink LED0 for PCI-E fiber */
1539 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1524 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1540 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1525 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1541 } else { 1526 } else {
1542 /* 1527 /*
1543 * set the blink bit for each LED that's "on" (0x0E) 1528 * set the blink bit for each LED that's "on" (0x0E)
@@ -1650,8 +1635,7 @@ s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1650 ew32(CTRL, ctrl); 1635 ew32(CTRL, ctrl);
1651 1636
1652 while (timeout) { 1637 while (timeout) {
1653 if (!(er32(STATUS) & 1638 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
1654 E1000_STATUS_GIO_MASTER_ENABLE))
1655 break; 1639 break;
1656 udelay(100); 1640 udelay(100);
1657 timeout--; 1641 timeout--;
@@ -1716,7 +1700,7 @@ void e1000e_update_adaptive(struct e1000_hw *hw)
1716 mac->current_ifs_val = mac->ifs_min_val; 1700 mac->current_ifs_val = mac->ifs_min_val;
1717 else 1701 else
1718 mac->current_ifs_val += 1702 mac->current_ifs_val +=
1719 mac->ifs_step_size; 1703 mac->ifs_step_size;
1720 ew32(AIT, mac->current_ifs_val); 1704 ew32(AIT, mac->current_ifs_val);
1721 } 1705 }
1722 } 1706 }
@@ -1731,956 +1715,3 @@ void e1000e_update_adaptive(struct e1000_hw *hw)
1731out: 1715out:
1732 return; 1716 return;
1733} 1717}
1734
1735/**
1736 * e1000_raise_eec_clk - Raise EEPROM clock
1737 * @hw: pointer to the HW structure
1738 * @eecd: pointer to the EEPROM
1739 *
1740 * Enable/Raise the EEPROM clock bit.
1741 **/
1742static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1743{
1744 *eecd = *eecd | E1000_EECD_SK;
1745 ew32(EECD, *eecd);
1746 e1e_flush();
1747 udelay(hw->nvm.delay_usec);
1748}
1749
1750/**
1751 * e1000_lower_eec_clk - Lower EEPROM clock
1752 * @hw: pointer to the HW structure
1753 * @eecd: pointer to the EEPROM
1754 *
1755 * Clear/Lower the EEPROM clock bit.
1756 **/
1757static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1758{
1759 *eecd = *eecd & ~E1000_EECD_SK;
1760 ew32(EECD, *eecd);
1761 e1e_flush();
1762 udelay(hw->nvm.delay_usec);
1763}
1764
1765/**
1766 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1767 * @hw: pointer to the HW structure
1768 * @data: data to send to the EEPROM
1769 * @count: number of bits to shift out
1770 *
1771 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1772 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1773 * In order to do this, "data" must be broken down into bits.
1774 **/
1775static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1776{
1777 struct e1000_nvm_info *nvm = &hw->nvm;
1778 u32 eecd = er32(EECD);
1779 u32 mask;
1780
1781 mask = 0x01 << (count - 1);
1782 if (nvm->type == e1000_nvm_eeprom_spi)
1783 eecd |= E1000_EECD_DO;
1784
1785 do {
1786 eecd &= ~E1000_EECD_DI;
1787
1788 if (data & mask)
1789 eecd |= E1000_EECD_DI;
1790
1791 ew32(EECD, eecd);
1792 e1e_flush();
1793
1794 udelay(nvm->delay_usec);
1795
1796 e1000_raise_eec_clk(hw, &eecd);
1797 e1000_lower_eec_clk(hw, &eecd);
1798
1799 mask >>= 1;
1800 } while (mask);
1801
1802 eecd &= ~E1000_EECD_DI;
1803 ew32(EECD, eecd);
1804}
1805
1806/**
1807 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1808 * @hw: pointer to the HW structure
1809 * @count: number of bits to shift in
1810 *
1811 * In order to read a register from the EEPROM, we need to shift 'count' bits
1812 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1813 * the EEPROM (setting the SK bit), and then reading the value of the data out
1814 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1815 * always be clear.
1816 **/
1817static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1818{
1819 u32 eecd;
1820 u32 i;
1821 u16 data;
1822
1823 eecd = er32(EECD);
1824
1825 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1826 data = 0;
1827
1828 for (i = 0; i < count; i++) {
1829 data <<= 1;
1830 e1000_raise_eec_clk(hw, &eecd);
1831
1832 eecd = er32(EECD);
1833
1834 eecd &= ~E1000_EECD_DI;
1835 if (eecd & E1000_EECD_DO)
1836 data |= 1;
1837
1838 e1000_lower_eec_clk(hw, &eecd);
1839 }
1840
1841 return data;
1842}
1843
1844/**
1845 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1846 * @hw: pointer to the HW structure
1847 * @ee_reg: EEPROM flag for polling
1848 *
1849 * Polls the EEPROM status bit for either read or write completion based
1850 * upon the value of 'ee_reg'.
1851 **/
1852s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1853{
1854 u32 attempts = 100000;
1855 u32 i, reg = 0;
1856
1857 for (i = 0; i < attempts; i++) {
1858 if (ee_reg == E1000_NVM_POLL_READ)
1859 reg = er32(EERD);
1860 else
1861 reg = er32(EEWR);
1862
1863 if (reg & E1000_NVM_RW_REG_DONE)
1864 return 0;
1865
1866 udelay(5);
1867 }
1868
1869 return -E1000_ERR_NVM;
1870}
1871
1872/**
1873 * e1000e_acquire_nvm - Generic request for access to EEPROM
1874 * @hw: pointer to the HW structure
1875 *
1876 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1877 * Return successful if access grant bit set, else clear the request for
1878 * EEPROM access and return -E1000_ERR_NVM (-1).
1879 **/
1880s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1881{
1882 u32 eecd = er32(EECD);
1883 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1884
1885 ew32(EECD, eecd | E1000_EECD_REQ);
1886 eecd = er32(EECD);
1887
1888 while (timeout) {
1889 if (eecd & E1000_EECD_GNT)
1890 break;
1891 udelay(5);
1892 eecd = er32(EECD);
1893 timeout--;
1894 }
1895
1896 if (!timeout) {
1897 eecd &= ~E1000_EECD_REQ;
1898 ew32(EECD, eecd);
1899 e_dbg("Could not acquire NVM grant\n");
1900 return -E1000_ERR_NVM;
1901 }
1902
1903 return 0;
1904}
1905
1906/**
1907 * e1000_standby_nvm - Return EEPROM to standby state
1908 * @hw: pointer to the HW structure
1909 *
1910 * Return the EEPROM to a standby state.
1911 **/
1912static void e1000_standby_nvm(struct e1000_hw *hw)
1913{
1914 struct e1000_nvm_info *nvm = &hw->nvm;
1915 u32 eecd = er32(EECD);
1916
1917 if (nvm->type == e1000_nvm_eeprom_spi) {
1918 /* Toggle CS to flush commands */
1919 eecd |= E1000_EECD_CS;
1920 ew32(EECD, eecd);
1921 e1e_flush();
1922 udelay(nvm->delay_usec);
1923 eecd &= ~E1000_EECD_CS;
1924 ew32(EECD, eecd);
1925 e1e_flush();
1926 udelay(nvm->delay_usec);
1927 }
1928}
1929
1930/**
1931 * e1000_stop_nvm - Terminate EEPROM command
1932 * @hw: pointer to the HW structure
1933 *
1934 * Terminates the current command by inverting the EEPROM's chip select pin.
1935 **/
1936static void e1000_stop_nvm(struct e1000_hw *hw)
1937{
1938 u32 eecd;
1939
1940 eecd = er32(EECD);
1941 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1942 /* Pull CS high */
1943 eecd |= E1000_EECD_CS;
1944 e1000_lower_eec_clk(hw, &eecd);
1945 }
1946}
1947
1948/**
1949 * e1000e_release_nvm - Release exclusive access to EEPROM
1950 * @hw: pointer to the HW structure
1951 *
1952 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1953 **/
1954void e1000e_release_nvm(struct e1000_hw *hw)
1955{
1956 u32 eecd;
1957
1958 e1000_stop_nvm(hw);
1959
1960 eecd = er32(EECD);
1961 eecd &= ~E1000_EECD_REQ;
1962 ew32(EECD, eecd);
1963}
1964
1965/**
1966 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1967 * @hw: pointer to the HW structure
1968 *
1969 * Setups the EEPROM for reading and writing.
1970 **/
1971static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1972{
1973 struct e1000_nvm_info *nvm = &hw->nvm;
1974 u32 eecd = er32(EECD);
1975 u8 spi_stat_reg;
1976
1977 if (nvm->type == e1000_nvm_eeprom_spi) {
1978 u16 timeout = NVM_MAX_RETRY_SPI;
1979
1980 /* Clear SK and CS */
1981 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1982 ew32(EECD, eecd);
1983 e1e_flush();
1984 udelay(1);
1985
1986 /*
1987 * Read "Status Register" repeatedly until the LSB is cleared.
1988 * The EEPROM will signal that the command has been completed
1989 * by clearing bit 0 of the internal status register. If it's
1990 * not cleared within 'timeout', then error out.
1991 */
1992 while (timeout) {
1993 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1994 hw->nvm.opcode_bits);
1995 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
1996 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
1997 break;
1998
1999 udelay(5);
2000 e1000_standby_nvm(hw);
2001 timeout--;
2002 }
2003
2004 if (!timeout) {
2005 e_dbg("SPI NVM Status error\n");
2006 return -E1000_ERR_NVM;
2007 }
2008 }
2009
2010 return 0;
2011}
2012
2013/**
2014 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
2015 * @hw: pointer to the HW structure
2016 * @offset: offset of word in the EEPROM to read
2017 * @words: number of words to read
2018 * @data: word read from the EEPROM
2019 *
2020 * Reads a 16 bit word from the EEPROM using the EERD register.
2021 **/
2022s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2023{
2024 struct e1000_nvm_info *nvm = &hw->nvm;
2025 u32 i, eerd = 0;
2026 s32 ret_val = 0;
2027
2028 /*
2029 * A check for invalid values: offset too large, too many words,
2030 * too many words for the offset, and not enough words.
2031 */
2032 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2033 (words == 0)) {
2034 e_dbg("nvm parameter(s) out of bounds\n");
2035 return -E1000_ERR_NVM;
2036 }
2037
2038 for (i = 0; i < words; i++) {
2039 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
2040 E1000_NVM_RW_REG_START;
2041
2042 ew32(EERD, eerd);
2043 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
2044 if (ret_val)
2045 break;
2046
2047 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
2048 }
2049
2050 return ret_val;
2051}
2052
2053/**
2054 * e1000e_write_nvm_spi - Write to EEPROM using SPI
2055 * @hw: pointer to the HW structure
2056 * @offset: offset within the EEPROM to be written to
2057 * @words: number of words to write
2058 * @data: 16 bit word(s) to be written to the EEPROM
2059 *
2060 * Writes data to EEPROM at offset using SPI interface.
2061 *
2062 * If e1000e_update_nvm_checksum is not called after this function , the
2063 * EEPROM will most likely contain an invalid checksum.
2064 **/
2065s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2066{
2067 struct e1000_nvm_info *nvm = &hw->nvm;
2068 s32 ret_val;
2069 u16 widx = 0;
2070
2071 /*
2072 * A check for invalid values: offset too large, too many words,
2073 * and not enough words.
2074 */
2075 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2076 (words == 0)) {
2077 e_dbg("nvm parameter(s) out of bounds\n");
2078 return -E1000_ERR_NVM;
2079 }
2080
2081 ret_val = nvm->ops.acquire(hw);
2082 if (ret_val)
2083 return ret_val;
2084
2085 while (widx < words) {
2086 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2087
2088 ret_val = e1000_ready_nvm_eeprom(hw);
2089 if (ret_val) {
2090 nvm->ops.release(hw);
2091 return ret_val;
2092 }
2093
2094 e1000_standby_nvm(hw);
2095
2096 /* Send the WRITE ENABLE command (8 bit opcode) */
2097 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2098 nvm->opcode_bits);
2099
2100 e1000_standby_nvm(hw);
2101
2102 /*
2103 * Some SPI eeproms use the 8th address bit embedded in the
2104 * opcode
2105 */
2106 if ((nvm->address_bits == 8) && (offset >= 128))
2107 write_opcode |= NVM_A8_OPCODE_SPI;
2108
2109 /* Send the Write command (8-bit opcode + addr) */
2110 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2111 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2112 nvm->address_bits);
2113
2114 /* Loop to allow for up to whole page write of eeprom */
2115 while (widx < words) {
2116 u16 word_out = data[widx];
2117 word_out = (word_out >> 8) | (word_out << 8);
2118 e1000_shift_out_eec_bits(hw, word_out, 16);
2119 widx++;
2120
2121 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2122 e1000_standby_nvm(hw);
2123 break;
2124 }
2125 }
2126 }
2127
2128 usleep_range(10000, 20000);
2129 nvm->ops.release(hw);
2130 return 0;
2131}
2132
2133/**
2134 * e1000_read_pba_string_generic - Read device part number
2135 * @hw: pointer to the HW structure
2136 * @pba_num: pointer to device part number
2137 * @pba_num_size: size of part number buffer
2138 *
2139 * Reads the product board assembly (PBA) number from the EEPROM and stores
2140 * the value in pba_num.
2141 **/
2142s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
2143 u32 pba_num_size)
2144{
2145 s32 ret_val;
2146 u16 nvm_data;
2147 u16 pba_ptr;
2148 u16 offset;
2149 u16 length;
2150
2151 if (pba_num == NULL) {
2152 e_dbg("PBA string buffer was null\n");
2153 ret_val = E1000_ERR_INVALID_ARGUMENT;
2154 goto out;
2155 }
2156
2157 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2158 if (ret_val) {
2159 e_dbg("NVM Read Error\n");
2160 goto out;
2161 }
2162
2163 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
2164 if (ret_val) {
2165 e_dbg("NVM Read Error\n");
2166 goto out;
2167 }
2168
2169 /*
2170 * if nvm_data is not ptr guard the PBA must be in legacy format which
2171 * means pba_ptr is actually our second data word for the PBA number
2172 * and we can decode it into an ascii string
2173 */
2174 if (nvm_data != NVM_PBA_PTR_GUARD) {
2175 e_dbg("NVM PBA number is not stored as string\n");
2176
2177 /* we will need 11 characters to store the PBA */
2178 if (pba_num_size < 11) {
2179 e_dbg("PBA string buffer too small\n");
2180 return E1000_ERR_NO_SPACE;
2181 }
2182
2183 /* extract hex string from data and pba_ptr */
2184 pba_num[0] = (nvm_data >> 12) & 0xF;
2185 pba_num[1] = (nvm_data >> 8) & 0xF;
2186 pba_num[2] = (nvm_data >> 4) & 0xF;
2187 pba_num[3] = nvm_data & 0xF;
2188 pba_num[4] = (pba_ptr >> 12) & 0xF;
2189 pba_num[5] = (pba_ptr >> 8) & 0xF;
2190 pba_num[6] = '-';
2191 pba_num[7] = 0;
2192 pba_num[8] = (pba_ptr >> 4) & 0xF;
2193 pba_num[9] = pba_ptr & 0xF;
2194
2195 /* put a null character on the end of our string */
2196 pba_num[10] = '\0';
2197
2198 /* switch all the data but the '-' to hex char */
2199 for (offset = 0; offset < 10; offset++) {
2200 if (pba_num[offset] < 0xA)
2201 pba_num[offset] += '0';
2202 else if (pba_num[offset] < 0x10)
2203 pba_num[offset] += 'A' - 0xA;
2204 }
2205
2206 goto out;
2207 }
2208
2209 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
2210 if (ret_val) {
2211 e_dbg("NVM Read Error\n");
2212 goto out;
2213 }
2214
2215 if (length == 0xFFFF || length == 0) {
2216 e_dbg("NVM PBA number section invalid length\n");
2217 ret_val = E1000_ERR_NVM_PBA_SECTION;
2218 goto out;
2219 }
2220 /* check if pba_num buffer is big enough */
2221 if (pba_num_size < (((u32)length * 2) - 1)) {
2222 e_dbg("PBA string buffer too small\n");
2223 ret_val = E1000_ERR_NO_SPACE;
2224 goto out;
2225 }
2226
2227 /* trim pba length from start of string */
2228 pba_ptr++;
2229 length--;
2230
2231 for (offset = 0; offset < length; offset++) {
2232 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
2233 if (ret_val) {
2234 e_dbg("NVM Read Error\n");
2235 goto out;
2236 }
2237 pba_num[offset * 2] = (u8)(nvm_data >> 8);
2238 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
2239 }
2240 pba_num[offset * 2] = '\0';
2241
2242out:
2243 return ret_val;
2244}
2245
2246/**
2247 * e1000_read_mac_addr_generic - Read device MAC address
2248 * @hw: pointer to the HW structure
2249 *
2250 * Reads the device MAC address from the EEPROM and stores the value.
2251 * Since devices with two ports use the same EEPROM, we increment the
2252 * last bit in the MAC address for the second port.
2253 **/
2254s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
2255{
2256 u32 rar_high;
2257 u32 rar_low;
2258 u16 i;
2259
2260 rar_high = er32(RAH(0));
2261 rar_low = er32(RAL(0));
2262
2263 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
2264 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
2265
2266 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
2267 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
2268
2269 for (i = 0; i < ETH_ALEN; i++)
2270 hw->mac.addr[i] = hw->mac.perm_addr[i];
2271
2272 return 0;
2273}
2274
2275/**
2276 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2277 * @hw: pointer to the HW structure
2278 *
2279 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2280 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2281 **/
2282s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2283{
2284 s32 ret_val;
2285 u16 checksum = 0;
2286 u16 i, nvm_data;
2287
2288 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2289 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2290 if (ret_val) {
2291 e_dbg("NVM Read Error\n");
2292 return ret_val;
2293 }
2294 checksum += nvm_data;
2295 }
2296
2297 if (checksum != (u16) NVM_SUM) {
2298 e_dbg("NVM Checksum Invalid\n");
2299 return -E1000_ERR_NVM;
2300 }
2301
2302 return 0;
2303}
2304
2305/**
2306 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2307 * @hw: pointer to the HW structure
2308 *
2309 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2310 * up to the checksum. Then calculates the EEPROM checksum and writes the
2311 * value to the EEPROM.
2312 **/
2313s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2314{
2315 s32 ret_val;
2316 u16 checksum = 0;
2317 u16 i, nvm_data;
2318
2319 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2320 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2321 if (ret_val) {
2322 e_dbg("NVM Read Error while updating checksum.\n");
2323 return ret_val;
2324 }
2325 checksum += nvm_data;
2326 }
2327 checksum = (u16) NVM_SUM - checksum;
2328 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2329 if (ret_val)
2330 e_dbg("NVM Write Error while updating checksum.\n");
2331
2332 return ret_val;
2333}
2334
2335/**
2336 * e1000e_reload_nvm - Reloads EEPROM
2337 * @hw: pointer to the HW structure
2338 *
2339 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2340 * extended control register.
2341 **/
2342void e1000e_reload_nvm(struct e1000_hw *hw)
2343{
2344 u32 ctrl_ext;
2345
2346 udelay(10);
2347 ctrl_ext = er32(CTRL_EXT);
2348 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2349 ew32(CTRL_EXT, ctrl_ext);
2350 e1e_flush();
2351}
2352
2353/**
2354 * e1000_calculate_checksum - Calculate checksum for buffer
2355 * @buffer: pointer to EEPROM
2356 * @length: size of EEPROM to calculate a checksum for
2357 *
2358 * Calculates the checksum for some buffer on a specified length. The
2359 * checksum calculated is returned.
2360 **/
2361static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2362{
2363 u32 i;
2364 u8 sum = 0;
2365
2366 if (!buffer)
2367 return 0;
2368
2369 for (i = 0; i < length; i++)
2370 sum += buffer[i];
2371
2372 return (u8) (0 - sum);
2373}
2374
2375/**
2376 * e1000_mng_enable_host_if - Checks host interface is enabled
2377 * @hw: pointer to the HW structure
2378 *
2379 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2380 *
2381 * This function checks whether the HOST IF is enabled for command operation
2382 * and also checks whether the previous command is completed. It busy waits
2383 * in case of previous command is not completed.
2384 **/
2385static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2386{
2387 u32 hicr;
2388 u8 i;
2389
2390 if (!(hw->mac.arc_subsystem_valid)) {
2391 e_dbg("ARC subsystem not valid.\n");
2392 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2393 }
2394
2395 /* Check that the host interface is enabled. */
2396 hicr = er32(HICR);
2397 if ((hicr & E1000_HICR_EN) == 0) {
2398 e_dbg("E1000_HOST_EN bit disabled.\n");
2399 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2400 }
2401 /* check the previous command is completed */
2402 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2403 hicr = er32(HICR);
2404 if (!(hicr & E1000_HICR_C))
2405 break;
2406 mdelay(1);
2407 }
2408
2409 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2410 e_dbg("Previous command timeout failed .\n");
2411 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2412 }
2413
2414 return 0;
2415}
2416
2417/**
2418 * e1000e_check_mng_mode_generic - check management mode
2419 * @hw: pointer to the HW structure
2420 *
2421 * Reads the firmware semaphore register and returns true (>0) if
2422 * manageability is enabled, else false (0).
2423 **/
2424bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2425{
2426 u32 fwsm = er32(FWSM);
2427
2428 return (fwsm & E1000_FWSM_MODE_MASK) ==
2429 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2430}
2431
2432/**
2433 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2434 * @hw: pointer to the HW structure
2435 *
2436 * Enables packet filtering on transmit packets if manageability is enabled
2437 * and host interface is enabled.
2438 **/
2439bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2440{
2441 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2442 u32 *buffer = (u32 *)&hw->mng_cookie;
2443 u32 offset;
2444 s32 ret_val, hdr_csum, csum;
2445 u8 i, len;
2446
2447 hw->mac.tx_pkt_filtering = true;
2448
2449 /* No manageability, no filtering */
2450 if (!e1000e_check_mng_mode(hw)) {
2451 hw->mac.tx_pkt_filtering = false;
2452 goto out;
2453 }
2454
2455 /*
2456 * If we can't read from the host interface for whatever
2457 * reason, disable filtering.
2458 */
2459 ret_val = e1000_mng_enable_host_if(hw);
2460 if (ret_val) {
2461 hw->mac.tx_pkt_filtering = false;
2462 goto out;
2463 }
2464
2465 /* Read in the header. Length and offset are in dwords. */
2466 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2467 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2468 for (i = 0; i < len; i++)
2469 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2470 hdr_csum = hdr->checksum;
2471 hdr->checksum = 0;
2472 csum = e1000_calculate_checksum((u8 *)hdr,
2473 E1000_MNG_DHCP_COOKIE_LENGTH);
2474 /*
2475 * If either the checksums or signature don't match, then
2476 * the cookie area isn't considered valid, in which case we
2477 * take the safe route of assuming Tx filtering is enabled.
2478 */
2479 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2480 hw->mac.tx_pkt_filtering = true;
2481 goto out;
2482 }
2483
2484 /* Cookie area is valid, make the final check for filtering. */
2485 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2486 hw->mac.tx_pkt_filtering = false;
2487 goto out;
2488 }
2489
2490out:
2491 return hw->mac.tx_pkt_filtering;
2492}
2493
2494/**
2495 * e1000_mng_write_cmd_header - Writes manageability command header
2496 * @hw: pointer to the HW structure
2497 * @hdr: pointer to the host interface command header
2498 *
2499 * Writes the command header after does the checksum calculation.
2500 **/
2501static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2502 struct e1000_host_mng_command_header *hdr)
2503{
2504 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2505
2506 /* Write the whole command header structure with new checksum. */
2507
2508 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2509
2510 length >>= 2;
2511 /* Write the relevant command block into the ram area. */
2512 for (i = 0; i < length; i++) {
2513 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2514 *((u32 *) hdr + i));
2515 e1e_flush();
2516 }
2517
2518 return 0;
2519}
2520
2521/**
2522 * e1000_mng_host_if_write - Write to the manageability host interface
2523 * @hw: pointer to the HW structure
2524 * @buffer: pointer to the host interface buffer
2525 * @length: size of the buffer
2526 * @offset: location in the buffer to write to
2527 * @sum: sum of the data (not checksum)
2528 *
2529 * This function writes the buffer content at the offset given on the host if.
2530 * It also does alignment considerations to do the writes in most efficient
2531 * way. Also fills up the sum of the buffer in *buffer parameter.
2532 **/
2533static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2534 u16 length, u16 offset, u8 *sum)
2535{
2536 u8 *tmp;
2537 u8 *bufptr = buffer;
2538 u32 data = 0;
2539 u16 remaining, i, j, prev_bytes;
2540
2541 /* sum = only sum of the data and it is not checksum */
2542
2543 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2544 return -E1000_ERR_PARAM;
2545
2546 tmp = (u8 *)&data;
2547 prev_bytes = offset & 0x3;
2548 offset >>= 2;
2549
2550 if (prev_bytes) {
2551 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2552 for (j = prev_bytes; j < sizeof(u32); j++) {
2553 *(tmp + j) = *bufptr++;
2554 *sum += *(tmp + j);
2555 }
2556 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2557 length -= j - prev_bytes;
2558 offset++;
2559 }
2560
2561 remaining = length & 0x3;
2562 length -= remaining;
2563
2564 /* Calculate length in DWORDs */
2565 length >>= 2;
2566
2567 /*
2568 * The device driver writes the relevant command block into the
2569 * ram area.
2570 */
2571 for (i = 0; i < length; i++) {
2572 for (j = 0; j < sizeof(u32); j++) {
2573 *(tmp + j) = *bufptr++;
2574 *sum += *(tmp + j);
2575 }
2576
2577 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2578 }
2579 if (remaining) {
2580 for (j = 0; j < sizeof(u32); j++) {
2581 if (j < remaining)
2582 *(tmp + j) = *bufptr++;
2583 else
2584 *(tmp + j) = 0;
2585
2586 *sum += *(tmp + j);
2587 }
2588 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2589 }
2590
2591 return 0;
2592}
2593
2594/**
2595 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2596 * @hw: pointer to the HW structure
2597 * @buffer: pointer to the host interface
2598 * @length: size of the buffer
2599 *
2600 * Writes the DHCP information to the host interface.
2601 **/
2602s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2603{
2604 struct e1000_host_mng_command_header hdr;
2605 s32 ret_val;
2606 u32 hicr;
2607
2608 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2609 hdr.command_length = length;
2610 hdr.reserved1 = 0;
2611 hdr.reserved2 = 0;
2612 hdr.checksum = 0;
2613
2614 /* Enable the host interface */
2615 ret_val = e1000_mng_enable_host_if(hw);
2616 if (ret_val)
2617 return ret_val;
2618
2619 /* Populate the host interface with the contents of "buffer". */
2620 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2621 sizeof(hdr), &(hdr.checksum));
2622 if (ret_val)
2623 return ret_val;
2624
2625 /* Write the manageability command header */
2626 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2627 if (ret_val)
2628 return ret_val;
2629
2630 /* Tell the ARC a new command is pending. */
2631 hicr = er32(HICR);
2632 ew32(HICR, hicr | E1000_HICR_C);
2633
2634 return 0;
2635}
2636
2637/**
2638 * e1000e_enable_mng_pass_thru - Check if management passthrough is needed
2639 * @hw: pointer to the HW structure
2640 *
2641 * Verifies the hardware needs to leave interface enabled so that frames can
2642 * be directed to and from the management interface.
2643 **/
2644bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2645{
2646 u32 manc;
2647 u32 fwsm, factps;
2648 bool ret_val = false;
2649
2650 manc = er32(MANC);
2651
2652 if (!(manc & E1000_MANC_RCV_TCO_EN))
2653 goto out;
2654
2655 if (hw->mac.has_fwsm) {
2656 fwsm = er32(FWSM);
2657 factps = er32(FACTPS);
2658
2659 if (!(factps & E1000_FACTPS_MNGCG) &&
2660 ((fwsm & E1000_FWSM_MODE_MASK) ==
2661 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2662 ret_val = true;
2663 goto out;
2664 }
2665 } else if ((hw->mac.type == e1000_82574) ||
2666 (hw->mac.type == e1000_82583)) {
2667 u16 data;
2668
2669 factps = er32(FACTPS);
2670 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
2671
2672 if (!(factps & E1000_FACTPS_MNGCG) &&
2673 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
2674 (e1000_mng_mode_pt << 13))) {
2675 ret_val = true;
2676 goto out;
2677 }
2678 } else if ((manc & E1000_MANC_SMBUS_EN) &&
2679 !(manc & E1000_MANC_ASF_EN)) {
2680 ret_val = true;
2681 goto out;
2682 }
2683
2684out:
2685 return ret_val;
2686}
diff --git a/drivers/net/ethernet/intel/e1000e/manage.c b/drivers/net/ethernet/intel/e1000e/manage.c
new file mode 100644
index 000000000000..3dae2655ec70
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/manage.c
@@ -0,0 +1,377 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31enum e1000_mng_mode {
32 e1000_mng_mode_none = 0,
33 e1000_mng_mode_asf,
34 e1000_mng_mode_pt,
35 e1000_mng_mode_ipmi,
36 e1000_mng_mode_host_if_only
37};
38
39#define E1000_FACTPS_MNGCG 0x20000000
40
41/* Intel(R) Active Management Technology signature */
42#define E1000_IAMT_SIGNATURE 0x544D4149
43
44/**
45 * e1000_calculate_checksum - Calculate checksum for buffer
46 * @buffer: pointer to EEPROM
47 * @length: size of EEPROM to calculate a checksum for
48 *
49 * Calculates the checksum for some buffer on a specified length. The
50 * checksum calculated is returned.
51 **/
52static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
53{
54 u32 i;
55 u8 sum = 0;
56
57 if (!buffer)
58 return 0;
59
60 for (i = 0; i < length; i++)
61 sum += buffer[i];
62
63 return (u8)(0 - sum);
64}
65
66/**
67 * e1000_mng_enable_host_if - Checks host interface is enabled
68 * @hw: pointer to the HW structure
69 *
70 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
71 *
72 * This function checks whether the HOST IF is enabled for command operation
73 * and also checks whether the previous command is completed. It busy waits
74 * in case of previous command is not completed.
75 **/
76static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
77{
78 u32 hicr;
79 u8 i;
80
81 if (!(hw->mac.arc_subsystem_valid)) {
82 e_dbg("ARC subsystem not valid.\n");
83 return -E1000_ERR_HOST_INTERFACE_COMMAND;
84 }
85
86 /* Check that the host interface is enabled. */
87 hicr = er32(HICR);
88 if ((hicr & E1000_HICR_EN) == 0) {
89 e_dbg("E1000_HOST_EN bit disabled.\n");
90 return -E1000_ERR_HOST_INTERFACE_COMMAND;
91 }
92 /* check the previous command is completed */
93 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
94 hicr = er32(HICR);
95 if (!(hicr & E1000_HICR_C))
96 break;
97 mdelay(1);
98 }
99
100 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
101 e_dbg("Previous command timeout failed .\n");
102 return -E1000_ERR_HOST_INTERFACE_COMMAND;
103 }
104
105 return 0;
106}
107
108/**
109 * e1000e_check_mng_mode_generic - check management mode
110 * @hw: pointer to the HW structure
111 *
112 * Reads the firmware semaphore register and returns true (>0) if
113 * manageability is enabled, else false (0).
114 **/
115bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
116{
117 u32 fwsm = er32(FWSM);
118
119 return (fwsm & E1000_FWSM_MODE_MASK) ==
120 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
121}
122
123/**
124 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
125 * @hw: pointer to the HW structure
126 *
127 * Enables packet filtering on transmit packets if manageability is enabled
128 * and host interface is enabled.
129 **/
130bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
131{
132 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
133 u32 *buffer = (u32 *)&hw->mng_cookie;
134 u32 offset;
135 s32 ret_val, hdr_csum, csum;
136 u8 i, len;
137
138 hw->mac.tx_pkt_filtering = true;
139
140 /* No manageability, no filtering */
141 if (!e1000e_check_mng_mode(hw)) {
142 hw->mac.tx_pkt_filtering = false;
143 goto out;
144 }
145
146 /*
147 * If we can't read from the host interface for whatever
148 * reason, disable filtering.
149 */
150 ret_val = e1000_mng_enable_host_if(hw);
151 if (ret_val) {
152 hw->mac.tx_pkt_filtering = false;
153 goto out;
154 }
155
156 /* Read in the header. Length and offset are in dwords. */
157 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
158 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
159 for (i = 0; i < len; i++)
160 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF,
161 offset + i);
162 hdr_csum = hdr->checksum;
163 hdr->checksum = 0;
164 csum = e1000_calculate_checksum((u8 *)hdr,
165 E1000_MNG_DHCP_COOKIE_LENGTH);
166 /*
167 * If either the checksums or signature don't match, then
168 * the cookie area isn't considered valid, in which case we
169 * take the safe route of assuming Tx filtering is enabled.
170 */
171 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
172 hw->mac.tx_pkt_filtering = true;
173 goto out;
174 }
175
176 /* Cookie area is valid, make the final check for filtering. */
177 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
178 hw->mac.tx_pkt_filtering = false;
179 goto out;
180 }
181
182out:
183 return hw->mac.tx_pkt_filtering;
184}
185
186/**
187 * e1000_mng_write_cmd_header - Writes manageability command header
188 * @hw: pointer to the HW structure
189 * @hdr: pointer to the host interface command header
190 *
191 * Writes the command header after does the checksum calculation.
192 **/
193static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
194 struct e1000_host_mng_command_header *hdr)
195{
196 u16 i, length = sizeof(struct e1000_host_mng_command_header);
197
198 /* Write the whole command header structure with new checksum. */
199
200 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
201
202 length >>= 2;
203 /* Write the relevant command block into the ram area. */
204 for (i = 0; i < length; i++) {
205 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i, *((u32 *)hdr + i));
206 e1e_flush();
207 }
208
209 return 0;
210}
211
212/**
213 * e1000_mng_host_if_write - Write to the manageability host interface
214 * @hw: pointer to the HW structure
215 * @buffer: pointer to the host interface buffer
216 * @length: size of the buffer
217 * @offset: location in the buffer to write to
218 * @sum: sum of the data (not checksum)
219 *
220 * This function writes the buffer content at the offset given on the host if.
221 * It also does alignment considerations to do the writes in most efficient
222 * way. Also fills up the sum of the buffer in *buffer parameter.
223 **/
224static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
225 u16 length, u16 offset, u8 *sum)
226{
227 u8 *tmp;
228 u8 *bufptr = buffer;
229 u32 data = 0;
230 u16 remaining, i, j, prev_bytes;
231
232 /* sum = only sum of the data and it is not checksum */
233
234 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
235 return -E1000_ERR_PARAM;
236
237 tmp = (u8 *)&data;
238 prev_bytes = offset & 0x3;
239 offset >>= 2;
240
241 if (prev_bytes) {
242 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
243 for (j = prev_bytes; j < sizeof(u32); j++) {
244 *(tmp + j) = *bufptr++;
245 *sum += *(tmp + j);
246 }
247 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
248 length -= j - prev_bytes;
249 offset++;
250 }
251
252 remaining = length & 0x3;
253 length -= remaining;
254
255 /* Calculate length in DWORDs */
256 length >>= 2;
257
258 /*
259 * The device driver writes the relevant command block into the
260 * ram area.
261 */
262 for (i = 0; i < length; i++) {
263 for (j = 0; j < sizeof(u32); j++) {
264 *(tmp + j) = *bufptr++;
265 *sum += *(tmp + j);
266 }
267
268 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
269 }
270 if (remaining) {
271 for (j = 0; j < sizeof(u32); j++) {
272 if (j < remaining)
273 *(tmp + j) = *bufptr++;
274 else
275 *(tmp + j) = 0;
276
277 *sum += *(tmp + j);
278 }
279 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
280 }
281
282 return 0;
283}
284
285/**
286 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
287 * @hw: pointer to the HW structure
288 * @buffer: pointer to the host interface
289 * @length: size of the buffer
290 *
291 * Writes the DHCP information to the host interface.
292 **/
293s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
294{
295 struct e1000_host_mng_command_header hdr;
296 s32 ret_val;
297 u32 hicr;
298
299 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
300 hdr.command_length = length;
301 hdr.reserved1 = 0;
302 hdr.reserved2 = 0;
303 hdr.checksum = 0;
304
305 /* Enable the host interface */
306 ret_val = e1000_mng_enable_host_if(hw);
307 if (ret_val)
308 return ret_val;
309
310 /* Populate the host interface with the contents of "buffer". */
311 ret_val = e1000_mng_host_if_write(hw, buffer, length,
312 sizeof(hdr), &(hdr.checksum));
313 if (ret_val)
314 return ret_val;
315
316 /* Write the manageability command header */
317 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
318 if (ret_val)
319 return ret_val;
320
321 /* Tell the ARC a new command is pending. */
322 hicr = er32(HICR);
323 ew32(HICR, hicr | E1000_HICR_C);
324
325 return 0;
326}
327
328/**
329 * e1000e_enable_mng_pass_thru - Check if management passthrough is needed
330 * @hw: pointer to the HW structure
331 *
332 * Verifies the hardware needs to leave interface enabled so that frames can
333 * be directed to and from the management interface.
334 **/
335bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
336{
337 u32 manc;
338 u32 fwsm, factps;
339 bool ret_val = false;
340
341 manc = er32(MANC);
342
343 if (!(manc & E1000_MANC_RCV_TCO_EN))
344 goto out;
345
346 if (hw->mac.has_fwsm) {
347 fwsm = er32(FWSM);
348 factps = er32(FACTPS);
349
350 if (!(factps & E1000_FACTPS_MNGCG) &&
351 ((fwsm & E1000_FWSM_MODE_MASK) ==
352 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
353 ret_val = true;
354 goto out;
355 }
356 } else if ((hw->mac.type == e1000_82574) ||
357 (hw->mac.type == e1000_82583)) {
358 u16 data;
359
360 factps = er32(FACTPS);
361 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
362
363 if (!(factps & E1000_FACTPS_MNGCG) &&
364 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
365 (e1000_mng_mode_pt << 13))) {
366 ret_val = true;
367 goto out;
368 }
369 } else if ((manc & E1000_MANC_SMBUS_EN) &&
370 !(manc & E1000_MANC_ASF_EN)) {
371 ret_val = true;
372 goto out;
373 }
374
375out:
376 return ret_val;
377}
diff --git a/drivers/net/ethernet/intel/e1000e/nvm.c b/drivers/net/ethernet/intel/e1000e/nvm.c
new file mode 100644
index 000000000000..dbdaa0052b1a
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/nvm.c
@@ -0,0 +1,647 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/**
32 * e1000_raise_eec_clk - Raise EEPROM clock
33 * @hw: pointer to the HW structure
34 * @eecd: pointer to the EEPROM
35 *
36 * Enable/Raise the EEPROM clock bit.
37 **/
38static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
39{
40 *eecd = *eecd | E1000_EECD_SK;
41 ew32(EECD, *eecd);
42 e1e_flush();
43 udelay(hw->nvm.delay_usec);
44}
45
46/**
47 * e1000_lower_eec_clk - Lower EEPROM clock
48 * @hw: pointer to the HW structure
49 * @eecd: pointer to the EEPROM
50 *
51 * Clear/Lower the EEPROM clock bit.
52 **/
53static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
54{
55 *eecd = *eecd & ~E1000_EECD_SK;
56 ew32(EECD, *eecd);
57 e1e_flush();
58 udelay(hw->nvm.delay_usec);
59}
60
61/**
62 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
63 * @hw: pointer to the HW structure
64 * @data: data to send to the EEPROM
65 * @count: number of bits to shift out
66 *
67 * We need to shift 'count' bits out to the EEPROM. So, the value in the
68 * "data" parameter will be shifted out to the EEPROM one bit at a time.
69 * In order to do this, "data" must be broken down into bits.
70 **/
71static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
72{
73 struct e1000_nvm_info *nvm = &hw->nvm;
74 u32 eecd = er32(EECD);
75 u32 mask;
76
77 mask = 0x01 << (count - 1);
78 if (nvm->type == e1000_nvm_eeprom_spi)
79 eecd |= E1000_EECD_DO;
80
81 do {
82 eecd &= ~E1000_EECD_DI;
83
84 if (data & mask)
85 eecd |= E1000_EECD_DI;
86
87 ew32(EECD, eecd);
88 e1e_flush();
89
90 udelay(nvm->delay_usec);
91
92 e1000_raise_eec_clk(hw, &eecd);
93 e1000_lower_eec_clk(hw, &eecd);
94
95 mask >>= 1;
96 } while (mask);
97
98 eecd &= ~E1000_EECD_DI;
99 ew32(EECD, eecd);
100}
101
102/**
103 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
104 * @hw: pointer to the HW structure
105 * @count: number of bits to shift in
106 *
107 * In order to read a register from the EEPROM, we need to shift 'count' bits
108 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
109 * the EEPROM (setting the SK bit), and then reading the value of the data out
110 * "DO" bit. During this "shifting in" process the data in "DI" bit should
111 * always be clear.
112 **/
113static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
114{
115 u32 eecd;
116 u32 i;
117 u16 data;
118
119 eecd = er32(EECD);
120
121 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
122 data = 0;
123
124 for (i = 0; i < count; i++) {
125 data <<= 1;
126 e1000_raise_eec_clk(hw, &eecd);
127
128 eecd = er32(EECD);
129
130 eecd &= ~E1000_EECD_DI;
131 if (eecd & E1000_EECD_DO)
132 data |= 1;
133
134 e1000_lower_eec_clk(hw, &eecd);
135 }
136
137 return data;
138}
139
140/**
141 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
142 * @hw: pointer to the HW structure
143 * @ee_reg: EEPROM flag for polling
144 *
145 * Polls the EEPROM status bit for either read or write completion based
146 * upon the value of 'ee_reg'.
147 **/
148s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
149{
150 u32 attempts = 100000;
151 u32 i, reg = 0;
152
153 for (i = 0; i < attempts; i++) {
154 if (ee_reg == E1000_NVM_POLL_READ)
155 reg = er32(EERD);
156 else
157 reg = er32(EEWR);
158
159 if (reg & E1000_NVM_RW_REG_DONE)
160 return 0;
161
162 udelay(5);
163 }
164
165 return -E1000_ERR_NVM;
166}
167
168/**
169 * e1000e_acquire_nvm - Generic request for access to EEPROM
170 * @hw: pointer to the HW structure
171 *
172 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
173 * Return successful if access grant bit set, else clear the request for
174 * EEPROM access and return -E1000_ERR_NVM (-1).
175 **/
176s32 e1000e_acquire_nvm(struct e1000_hw *hw)
177{
178 u32 eecd = er32(EECD);
179 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
180
181 ew32(EECD, eecd | E1000_EECD_REQ);
182 eecd = er32(EECD);
183
184 while (timeout) {
185 if (eecd & E1000_EECD_GNT)
186 break;
187 udelay(5);
188 eecd = er32(EECD);
189 timeout--;
190 }
191
192 if (!timeout) {
193 eecd &= ~E1000_EECD_REQ;
194 ew32(EECD, eecd);
195 e_dbg("Could not acquire NVM grant\n");
196 return -E1000_ERR_NVM;
197 }
198
199 return 0;
200}
201
202/**
203 * e1000_standby_nvm - Return EEPROM to standby state
204 * @hw: pointer to the HW structure
205 *
206 * Return the EEPROM to a standby state.
207 **/
208static void e1000_standby_nvm(struct e1000_hw *hw)
209{
210 struct e1000_nvm_info *nvm = &hw->nvm;
211 u32 eecd = er32(EECD);
212
213 if (nvm->type == e1000_nvm_eeprom_spi) {
214 /* Toggle CS to flush commands */
215 eecd |= E1000_EECD_CS;
216 ew32(EECD, eecd);
217 e1e_flush();
218 udelay(nvm->delay_usec);
219 eecd &= ~E1000_EECD_CS;
220 ew32(EECD, eecd);
221 e1e_flush();
222 udelay(nvm->delay_usec);
223 }
224}
225
226/**
227 * e1000_stop_nvm - Terminate EEPROM command
228 * @hw: pointer to the HW structure
229 *
230 * Terminates the current command by inverting the EEPROM's chip select pin.
231 **/
232static void e1000_stop_nvm(struct e1000_hw *hw)
233{
234 u32 eecd;
235
236 eecd = er32(EECD);
237 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
238 /* Pull CS high */
239 eecd |= E1000_EECD_CS;
240 e1000_lower_eec_clk(hw, &eecd);
241 }
242}
243
244/**
245 * e1000e_release_nvm - Release exclusive access to EEPROM
246 * @hw: pointer to the HW structure
247 *
248 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
249 **/
250void e1000e_release_nvm(struct e1000_hw *hw)
251{
252 u32 eecd;
253
254 e1000_stop_nvm(hw);
255
256 eecd = er32(EECD);
257 eecd &= ~E1000_EECD_REQ;
258 ew32(EECD, eecd);
259}
260
261/**
262 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
263 * @hw: pointer to the HW structure
264 *
265 * Setups the EEPROM for reading and writing.
266 **/
267static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
268{
269 struct e1000_nvm_info *nvm = &hw->nvm;
270 u32 eecd = er32(EECD);
271 u8 spi_stat_reg;
272
273 if (nvm->type == e1000_nvm_eeprom_spi) {
274 u16 timeout = NVM_MAX_RETRY_SPI;
275
276 /* Clear SK and CS */
277 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
278 ew32(EECD, eecd);
279 e1e_flush();
280 udelay(1);
281
282 /*
283 * Read "Status Register" repeatedly until the LSB is cleared.
284 * The EEPROM will signal that the command has been completed
285 * by clearing bit 0 of the internal status register. If it's
286 * not cleared within 'timeout', then error out.
287 */
288 while (timeout) {
289 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
290 hw->nvm.opcode_bits);
291 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
292 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
293 break;
294
295 udelay(5);
296 e1000_standby_nvm(hw);
297 timeout--;
298 }
299
300 if (!timeout) {
301 e_dbg("SPI NVM Status error\n");
302 return -E1000_ERR_NVM;
303 }
304 }
305
306 return 0;
307}
308
309/**
310 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
311 * @hw: pointer to the HW structure
312 * @offset: offset of word in the EEPROM to read
313 * @words: number of words to read
314 * @data: word read from the EEPROM
315 *
316 * Reads a 16 bit word from the EEPROM using the EERD register.
317 **/
318s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
319{
320 struct e1000_nvm_info *nvm = &hw->nvm;
321 u32 i, eerd = 0;
322 s32 ret_val = 0;
323
324 /*
325 * A check for invalid values: offset too large, too many words,
326 * too many words for the offset, and not enough words.
327 */
328 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
329 (words == 0)) {
330 e_dbg("nvm parameter(s) out of bounds\n");
331 return -E1000_ERR_NVM;
332 }
333
334 for (i = 0; i < words; i++) {
335 eerd = ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) +
336 E1000_NVM_RW_REG_START;
337
338 ew32(EERD, eerd);
339 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
340 if (ret_val)
341 break;
342
343 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
344 }
345
346 return ret_val;
347}
348
349/**
350 * e1000e_write_nvm_spi - Write to EEPROM using SPI
351 * @hw: pointer to the HW structure
352 * @offset: offset within the EEPROM to be written to
353 * @words: number of words to write
354 * @data: 16 bit word(s) to be written to the EEPROM
355 *
356 * Writes data to EEPROM at offset using SPI interface.
357 *
358 * If e1000e_update_nvm_checksum is not called after this function , the
359 * EEPROM will most likely contain an invalid checksum.
360 **/
361s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
362{
363 struct e1000_nvm_info *nvm = &hw->nvm;
364 s32 ret_val;
365 u16 widx = 0;
366
367 /*
368 * A check for invalid values: offset too large, too many words,
369 * and not enough words.
370 */
371 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
372 (words == 0)) {
373 e_dbg("nvm parameter(s) out of bounds\n");
374 return -E1000_ERR_NVM;
375 }
376
377 ret_val = nvm->ops.acquire(hw);
378 if (ret_val)
379 return ret_val;
380
381 while (widx < words) {
382 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
383
384 ret_val = e1000_ready_nvm_eeprom(hw);
385 if (ret_val) {
386 nvm->ops.release(hw);
387 return ret_val;
388 }
389
390 e1000_standby_nvm(hw);
391
392 /* Send the WRITE ENABLE command (8 bit opcode) */
393 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
394 nvm->opcode_bits);
395
396 e1000_standby_nvm(hw);
397
398 /*
399 * Some SPI eeproms use the 8th address bit embedded in the
400 * opcode
401 */
402 if ((nvm->address_bits == 8) && (offset >= 128))
403 write_opcode |= NVM_A8_OPCODE_SPI;
404
405 /* Send the Write command (8-bit opcode + addr) */
406 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
407 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
408 nvm->address_bits);
409
410 /* Loop to allow for up to whole page write of eeprom */
411 while (widx < words) {
412 u16 word_out = data[widx];
413 word_out = (word_out >> 8) | (word_out << 8);
414 e1000_shift_out_eec_bits(hw, word_out, 16);
415 widx++;
416
417 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
418 e1000_standby_nvm(hw);
419 break;
420 }
421 }
422 }
423
424 usleep_range(10000, 20000);
425 nvm->ops.release(hw);
426 return 0;
427}
428
429/**
430 * e1000_read_pba_string_generic - Read device part number
431 * @hw: pointer to the HW structure
432 * @pba_num: pointer to device part number
433 * @pba_num_size: size of part number buffer
434 *
435 * Reads the product board assembly (PBA) number from the EEPROM and stores
436 * the value in pba_num.
437 **/
438s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
439 u32 pba_num_size)
440{
441 s32 ret_val;
442 u16 nvm_data;
443 u16 pba_ptr;
444 u16 offset;
445 u16 length;
446
447 if (pba_num == NULL) {
448 e_dbg("PBA string buffer was null\n");
449 ret_val = E1000_ERR_INVALID_ARGUMENT;
450 goto out;
451 }
452
453 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
454 if (ret_val) {
455 e_dbg("NVM Read Error\n");
456 goto out;
457 }
458
459 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
460 if (ret_val) {
461 e_dbg("NVM Read Error\n");
462 goto out;
463 }
464
465 /*
466 * if nvm_data is not ptr guard the PBA must be in legacy format which
467 * means pba_ptr is actually our second data word for the PBA number
468 * and we can decode it into an ascii string
469 */
470 if (nvm_data != NVM_PBA_PTR_GUARD) {
471 e_dbg("NVM PBA number is not stored as string\n");
472
473 /* we will need 11 characters to store the PBA */
474 if (pba_num_size < 11) {
475 e_dbg("PBA string buffer too small\n");
476 return E1000_ERR_NO_SPACE;
477 }
478
479 /* extract hex string from data and pba_ptr */
480 pba_num[0] = (nvm_data >> 12) & 0xF;
481 pba_num[1] = (nvm_data >> 8) & 0xF;
482 pba_num[2] = (nvm_data >> 4) & 0xF;
483 pba_num[3] = nvm_data & 0xF;
484 pba_num[4] = (pba_ptr >> 12) & 0xF;
485 pba_num[5] = (pba_ptr >> 8) & 0xF;
486 pba_num[6] = '-';
487 pba_num[7] = 0;
488 pba_num[8] = (pba_ptr >> 4) & 0xF;
489 pba_num[9] = pba_ptr & 0xF;
490
491 /* put a null character on the end of our string */
492 pba_num[10] = '\0';
493
494 /* switch all the data but the '-' to hex char */
495 for (offset = 0; offset < 10; offset++) {
496 if (pba_num[offset] < 0xA)
497 pba_num[offset] += '0';
498 else if (pba_num[offset] < 0x10)
499 pba_num[offset] += 'A' - 0xA;
500 }
501
502 goto out;
503 }
504
505 ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
506 if (ret_val) {
507 e_dbg("NVM Read Error\n");
508 goto out;
509 }
510
511 if (length == 0xFFFF || length == 0) {
512 e_dbg("NVM PBA number section invalid length\n");
513 ret_val = E1000_ERR_NVM_PBA_SECTION;
514 goto out;
515 }
516 /* check if pba_num buffer is big enough */
517 if (pba_num_size < (((u32)length * 2) - 1)) {
518 e_dbg("PBA string buffer too small\n");
519 ret_val = E1000_ERR_NO_SPACE;
520 goto out;
521 }
522
523 /* trim pba length from start of string */
524 pba_ptr++;
525 length--;
526
527 for (offset = 0; offset < length; offset++) {
528 ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
529 if (ret_val) {
530 e_dbg("NVM Read Error\n");
531 goto out;
532 }
533 pba_num[offset * 2] = (u8)(nvm_data >> 8);
534 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
535 }
536 pba_num[offset * 2] = '\0';
537
538out:
539 return ret_val;
540}
541
542/**
543 * e1000_read_mac_addr_generic - Read device MAC address
544 * @hw: pointer to the HW structure
545 *
546 * Reads the device MAC address from the EEPROM and stores the value.
547 * Since devices with two ports use the same EEPROM, we increment the
548 * last bit in the MAC address for the second port.
549 **/
550s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
551{
552 u32 rar_high;
553 u32 rar_low;
554 u16 i;
555
556 rar_high = er32(RAH(0));
557 rar_low = er32(RAL(0));
558
559 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
560 hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8));
561
562 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
563 hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8));
564
565 for (i = 0; i < ETH_ALEN; i++)
566 hw->mac.addr[i] = hw->mac.perm_addr[i];
567
568 return 0;
569}
570
571/**
572 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
573 * @hw: pointer to the HW structure
574 *
575 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
576 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
577 **/
578s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
579{
580 s32 ret_val;
581 u16 checksum = 0;
582 u16 i, nvm_data;
583
584 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
585 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
586 if (ret_val) {
587 e_dbg("NVM Read Error\n");
588 return ret_val;
589 }
590 checksum += nvm_data;
591 }
592
593 if (checksum != (u16)NVM_SUM) {
594 e_dbg("NVM Checksum Invalid\n");
595 return -E1000_ERR_NVM;
596 }
597
598 return 0;
599}
600
601/**
602 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
603 * @hw: pointer to the HW structure
604 *
605 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
606 * up to the checksum. Then calculates the EEPROM checksum and writes the
607 * value to the EEPROM.
608 **/
609s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
610{
611 s32 ret_val;
612 u16 checksum = 0;
613 u16 i, nvm_data;
614
615 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
616 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
617 if (ret_val) {
618 e_dbg("NVM Read Error while updating checksum.\n");
619 return ret_val;
620 }
621 checksum += nvm_data;
622 }
623 checksum = (u16)NVM_SUM - checksum;
624 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
625 if (ret_val)
626 e_dbg("NVM Write Error while updating checksum.\n");
627
628 return ret_val;
629}
630
631/**
632 * e1000e_reload_nvm - Reloads EEPROM
633 * @hw: pointer to the HW structure
634 *
635 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
636 * extended control register.
637 **/
638void e1000e_reload_nvm(struct e1000_hw *hw)
639{
640 u32 ctrl_ext;
641
642 udelay(10);
643 ctrl_ext = er32(CTRL_EXT);
644 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
645 ew32(CTRL_EXT, ctrl_ext);
646 e1e_flush();
647}
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