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authorPaul Mundt <lethal@linux-sh.org>2009-09-28 02:22:10 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-09-28 02:22:10 -0400
commitfe1dbfd3f992d5432d7463a5bd6c2fc96d3eccd8 (patch)
tree0f8f4b9f5d6ebfb99b0764e91131f7c39eced13c
parent421f7a5dbdd1720c718eed187c46cf202529cf7d (diff)
sh: magicpanelr2 and dreamcast can use the generic I/O base.
There is now no need for the magicpanelr2 and dreamcast platforms to set their own I/O port bas values, given that the generic machvec code now sets this to P2SEG for everyone. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/boards/board-magicpanelr2.c2
-rw-r--r--arch/sh/boards/mach-dreamcast/setup.c2
2 files changed, 0 insertions, 4 deletions
diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c
index 0a37c8bfc959..99ffc5f1c0dd 100644
--- a/arch/sh/boards/board-magicpanelr2.c
+++ b/arch/sh/boards/board-magicpanelr2.c
@@ -205,8 +205,6 @@ static void __init setup_port_multiplexing(void)
205 205
206static void __init mpr2_setup(char **cmdline_p) 206static void __init mpr2_setup(char **cmdline_p)
207{ 207{
208 __set_io_port_base(0xa0000000);
209
210 /* set Pin Select Register A: 208 /* set Pin Select Register A:
211 * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, 209 * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2,
212 * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND 210 * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND
diff --git a/arch/sh/boards/mach-dreamcast/setup.c b/arch/sh/boards/mach-dreamcast/setup.c
index ebe99227d4e6..a4b7402d6176 100644
--- a/arch/sh/boards/mach-dreamcast/setup.c
+++ b/arch/sh/boards/mach-dreamcast/setup.c
@@ -42,8 +42,6 @@ static void __init dreamcast_setup(char **cmdline_p)
42 /* Acknowledge any previous events */ 42 /* Acknowledge any previous events */
43 /* XXX */ 43 /* XXX */
44 44
45 __set_io_port_base(0xa0000000);
46
47 /* Assign all virtual IRQs to the System ASIC int. handler */ 45 /* Assign all virtual IRQs to the System ASIC int. handler */
48 for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) 46 for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
49 set_irq_chip_and_handler(i, &systemasic_int, 47 set_irq_chip_and_handler(i, &systemasic_int,