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authorHans Verkuil <hans.verkuil@cisco.com>2014-08-21 10:01:23 -0400
committerMauro Carvalho Chehab <m.chehab@samsung.com>2014-09-03 09:38:57 -0400
commitfe10b84e7f6c4c8c3dc8cf63be324bc13f5acd68 (patch)
tree258feb91bf2b98e1b94bea41f42cc4ac12af2d2d
parent8ae632b11775254c5e555ee8c42b7d19baeb1473 (diff)
[media] mt2063: fix sparse warnings
drivers/media/tuners/mt2063.c:1238:56: warning: cast truncates bits from constant value (ffffff0f becomes f) drivers/media/tuners/mt2063.c:1313:62: warning: cast truncates bits from constant value (ffffff7f becomes 7f) drivers/media/tuners/mt2063.c:1321:62: warning: cast truncates bits from constant value (ffffff7f becomes 7f) Cast to u8 is unnecessary. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
-rw-r--r--drivers/media/tuners/mt2063.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/media/tuners/mt2063.c b/drivers/media/tuners/mt2063.c
index f640dcf4a81d..9e9c5eb4cb66 100644
--- a/drivers/media/tuners/mt2063.c
+++ b/drivers/media/tuners/mt2063.c
@@ -1216,7 +1216,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1216 if (status >= 0) { 1216 if (status >= 0) {
1217 val = 1217 val =
1218 (state-> 1218 (state->
1219 reg[MT2063_REG_PD1_TGT] & (u8) ~0x40) | (RFAGCEN[Mode] 1219 reg[MT2063_REG_PD1_TGT] & ~0x40) | (RFAGCEN[Mode]
1220 ? 0x40 : 1220 ? 0x40 :
1221 0x00); 1221 0x00);
1222 if (state->reg[MT2063_REG_PD1_TGT] != val) 1222 if (state->reg[MT2063_REG_PD1_TGT] != val)
@@ -1225,7 +1225,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1225 1225
1226 /* LNARin */ 1226 /* LNARin */
1227 if (status >= 0) { 1227 if (status >= 0) {
1228 u8 val = (state->reg[MT2063_REG_CTRL_2C] & (u8) ~0x03) | 1228 u8 val = (state->reg[MT2063_REG_CTRL_2C] & ~0x03) |
1229 (LNARIN[Mode] & 0x03); 1229 (LNARIN[Mode] & 0x03);
1230 if (state->reg[MT2063_REG_CTRL_2C] != val) 1230 if (state->reg[MT2063_REG_CTRL_2C] != val)
1231 status |= mt2063_setreg(state, MT2063_REG_CTRL_2C, val); 1231 status |= mt2063_setreg(state, MT2063_REG_CTRL_2C, val);
@@ -1235,19 +1235,19 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1235 if (status >= 0) { 1235 if (status >= 0) {
1236 val = 1236 val =
1237 (state-> 1237 (state->
1238 reg[MT2063_REG_FIFF_CTRL2] & (u8) ~0xF0) | 1238 reg[MT2063_REG_FIFF_CTRL2] & ~0xF0) |
1239 (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4); 1239 (FIFFQEN[Mode] << 7) | (FIFFQ[Mode] << 4);
1240 if (state->reg[MT2063_REG_FIFF_CTRL2] != val) { 1240 if (state->reg[MT2063_REG_FIFF_CTRL2] != val) {
1241 status |= 1241 status |=
1242 mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val); 1242 mt2063_setreg(state, MT2063_REG_FIFF_CTRL2, val);
1243 /* trigger FIFF calibration, needed after changing FIFFQ */ 1243 /* trigger FIFF calibration, needed after changing FIFFQ */
1244 val = 1244 val =
1245 (state->reg[MT2063_REG_FIFF_CTRL] | (u8) 0x01); 1245 (state->reg[MT2063_REG_FIFF_CTRL] | 0x01);
1246 status |= 1246 status |=
1247 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val); 1247 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
1248 val = 1248 val =
1249 (state-> 1249 (state->
1250 reg[MT2063_REG_FIFF_CTRL] & (u8) ~0x01); 1250 reg[MT2063_REG_FIFF_CTRL] & ~0x01);
1251 status |= 1251 status |=
1252 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val); 1252 mt2063_setreg(state, MT2063_REG_FIFF_CTRL, val);
1253 } 1253 }
@@ -1259,7 +1259,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1259 1259
1260 /* acLNAmax */ 1260 /* acLNAmax */
1261 if (status >= 0) { 1261 if (status >= 0) {
1262 u8 val = (state->reg[MT2063_REG_LNA_OV] & (u8) ~0x1F) | 1262 u8 val = (state->reg[MT2063_REG_LNA_OV] & ~0x1F) |
1263 (ACLNAMAX[Mode] & 0x1F); 1263 (ACLNAMAX[Mode] & 0x1F);
1264 if (state->reg[MT2063_REG_LNA_OV] != val) 1264 if (state->reg[MT2063_REG_LNA_OV] != val)
1265 status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val); 1265 status |= mt2063_setreg(state, MT2063_REG_LNA_OV, val);
@@ -1267,7 +1267,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1267 1267
1268 /* LNATGT */ 1268 /* LNATGT */
1269 if (status >= 0) { 1269 if (status >= 0) {
1270 u8 val = (state->reg[MT2063_REG_LNA_TGT] & (u8) ~0x3F) | 1270 u8 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x3F) |
1271 (LNATGT[Mode] & 0x3F); 1271 (LNATGT[Mode] & 0x3F);
1272 if (state->reg[MT2063_REG_LNA_TGT] != val) 1272 if (state->reg[MT2063_REG_LNA_TGT] != val)
1273 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val); 1273 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
@@ -1275,7 +1275,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1275 1275
1276 /* ACRF */ 1276 /* ACRF */
1277 if (status >= 0) { 1277 if (status >= 0) {
1278 u8 val = (state->reg[MT2063_REG_RF_OV] & (u8) ~0x1F) | 1278 u8 val = (state->reg[MT2063_REG_RF_OV] & ~0x1F) |
1279 (ACRFMAX[Mode] & 0x1F); 1279 (ACRFMAX[Mode] & 0x1F);
1280 if (state->reg[MT2063_REG_RF_OV] != val) 1280 if (state->reg[MT2063_REG_RF_OV] != val)
1281 status |= mt2063_setreg(state, MT2063_REG_RF_OV, val); 1281 status |= mt2063_setreg(state, MT2063_REG_RF_OV, val);
@@ -1283,7 +1283,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1283 1283
1284 /* PD1TGT */ 1284 /* PD1TGT */
1285 if (status >= 0) { 1285 if (status >= 0) {
1286 u8 val = (state->reg[MT2063_REG_PD1_TGT] & (u8) ~0x3F) | 1286 u8 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x3F) |
1287 (PD1TGT[Mode] & 0x3F); 1287 (PD1TGT[Mode] & 0x3F);
1288 if (state->reg[MT2063_REG_PD1_TGT] != val) 1288 if (state->reg[MT2063_REG_PD1_TGT] != val)
1289 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); 1289 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);
@@ -1294,7 +1294,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1294 u8 val = ACFIFMAX[Mode]; 1294 u8 val = ACFIFMAX[Mode];
1295 if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5) 1295 if (state->reg[MT2063_REG_PART_REV] != MT2063_B3 && val > 5)
1296 val = 5; 1296 val = 5;
1297 val = (state->reg[MT2063_REG_FIF_OV] & (u8) ~0x1F) | 1297 val = (state->reg[MT2063_REG_FIF_OV] & ~0x1F) |
1298 (val & 0x1F); 1298 (val & 0x1F);
1299 if (state->reg[MT2063_REG_FIF_OV] != val) 1299 if (state->reg[MT2063_REG_FIF_OV] != val)
1300 status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val); 1300 status |= mt2063_setreg(state, MT2063_REG_FIF_OV, val);
@@ -1302,7 +1302,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1302 1302
1303 /* PD2TGT */ 1303 /* PD2TGT */
1304 if (status >= 0) { 1304 if (status >= 0) {
1305 u8 val = (state->reg[MT2063_REG_PD2_TGT] & (u8) ~0x3F) | 1305 u8 val = (state->reg[MT2063_REG_PD2_TGT] & ~0x3F) |
1306 (PD2TGT[Mode] & 0x3F); 1306 (PD2TGT[Mode] & 0x3F);
1307 if (state->reg[MT2063_REG_PD2_TGT] != val) 1307 if (state->reg[MT2063_REG_PD2_TGT] != val)
1308 status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val); 1308 status |= mt2063_setreg(state, MT2063_REG_PD2_TGT, val);
@@ -1310,7 +1310,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1310 1310
1311 /* Ignore ATN Overload */ 1311 /* Ignore ATN Overload */
1312 if (status >= 0) { 1312 if (status >= 0) {
1313 val = (state->reg[MT2063_REG_LNA_TGT] & (u8) ~0x80) | 1313 val = (state->reg[MT2063_REG_LNA_TGT] & ~0x80) |
1314 (RFOVDIS[Mode] ? 0x80 : 0x00); 1314 (RFOVDIS[Mode] ? 0x80 : 0x00);
1315 if (state->reg[MT2063_REG_LNA_TGT] != val) 1315 if (state->reg[MT2063_REG_LNA_TGT] != val)
1316 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val); 1316 status |= mt2063_setreg(state, MT2063_REG_LNA_TGT, val);
@@ -1318,7 +1318,7 @@ static u32 MT2063_SetReceiverMode(struct mt2063_state *state,
1318 1318
1319 /* Ignore FIF Overload */ 1319 /* Ignore FIF Overload */
1320 if (status >= 0) { 1320 if (status >= 0) {
1321 val = (state->reg[MT2063_REG_PD1_TGT] & (u8) ~0x80) | 1321 val = (state->reg[MT2063_REG_PD1_TGT] & ~0x80) |
1322 (FIFOVDIS[Mode] ? 0x80 : 0x00); 1322 (FIFOVDIS[Mode] ? 0x80 : 0x00);
1323 if (state->reg[MT2063_REG_PD1_TGT] != val) 1323 if (state->reg[MT2063_REG_PD1_TGT] != val)
1324 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val); 1324 status |= mt2063_setreg(state, MT2063_REG_PD1_TGT, val);