diff options
author | Nicolas Pitre <nico@cam.org> | 2009-04-22 15:08:17 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-04-23 18:25:41 -0400 |
commit | fdd8b079e33d4711527ace19798e9db99a056469 (patch) | |
tree | 31c8f9d286dfb6fb8e7e306732cd51bea24d69a3 | |
parent | ae1036a2f4e8f83b544ddce4f875a1e4e2ac7b62 (diff) |
[ARM] 5460/1: Orion: reduce namespace pollution
Symbols like SOFT_RESET are way too generic to be exported at large.
To avoid this, let's move the mbus bridge register defines into a
separate file and include it where needed. This affects mach-kirkwood,
mach-loki, mach-mv78xx0 and mach-orion5x simultaneously as they all
share code in plat-orion which relies on those defines.
Some other defines have been moved to narrower scopes, or simply deleted
when they had no user.
This fixes compilation problem with mpt2sas on the above listed
platforms.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
29 files changed, 223 insertions, 147 deletions
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 16dc9ea08393..eeb00240d784 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
24 | #include <asm/mach/time.h> | 24 | #include <asm/mach/time.h> |
25 | #include <mach/kirkwood.h> | 25 | #include <mach/kirkwood.h> |
26 | #include <mach/bridge-regs.h> | ||
26 | #include <plat/cache-feroceon-l2.h> | 27 | #include <plat/cache-feroceon-l2.h> |
27 | #include <plat/ehci-orion.h> | 28 | #include <plat/ehci-orion.h> |
28 | #include <plat/mvsdio.h> | 29 | #include <plat/mvsdio.h> |
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h new file mode 100644 index 000000000000..4f7029f521cc --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-kirkwood/include/mach/bridge-regs.h | ||
3 | * | ||
4 | * Mbus-L to Mbus Bridge Registers | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_BRIDGE_REGS_H | ||
12 | #define __ASM_ARCH_BRIDGE_REGS_H | ||
13 | |||
14 | #include <mach/kirkwood.h> | ||
15 | |||
16 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | ||
17 | #define CPU_RESET 0x00000002 | ||
18 | |||
19 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
20 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
21 | |||
22 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
23 | #define SOFT_RESET 0x00000001 | ||
24 | |||
25 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
26 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
27 | #define BRIDGE_INT_TIMER0 0x0002 | ||
28 | #define BRIDGE_INT_TIMER1 0x0004 | ||
29 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | ||
30 | |||
31 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
32 | #define IRQ_CAUSE_LOW_OFF 0x0000 | ||
33 | #define IRQ_MASK_LOW_OFF 0x0004 | ||
34 | #define IRQ_CAUSE_HIGH_OFF 0x0010 | ||
35 | #define IRQ_MASK_HIGH_OFF 0x0014 | ||
36 | |||
37 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
38 | |||
39 | #define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) | ||
40 | #define L2_WRITETHROUGH 0x00000010 | ||
41 | |||
42 | #endif | ||
diff --git a/arch/arm/mach-kirkwood/include/mach/debug-macro.S b/arch/arm/mach-kirkwood/include/mach/debug-macro.S index c0cc5b5c82ac..a4a55c199d77 100644 --- a/arch/arm/mach-kirkwood/include/mach/debug-macro.S +++ b/arch/arm/mach-kirkwood/include/mach/debug-macro.S | |||
@@ -6,7 +6,7 @@ | |||
6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
7 | */ | 7 | */ |
8 | 8 | ||
9 | #include <mach/kirkwood.h> | 9 | #include <mach/bridge-regs.h> |
10 | 10 | ||
11 | .macro addruart,rx | 11 | .macro addruart,rx |
12 | mrc p15, 0, \rx, c1, c0 | 12 | mrc p15, 0, \rx, c1, c0 |
diff --git a/arch/arm/mach-kirkwood/include/mach/entry-macro.S b/arch/arm/mach-kirkwood/include/mach/entry-macro.S index 83e0cba77b36..8939d36f893c 100644 --- a/arch/arm/mach-kirkwood/include/mach/entry-macro.S +++ b/arch/arm/mach-kirkwood/include/mach/entry-macro.S | |||
@@ -8,7 +8,7 @@ | |||
8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <mach/kirkwood.h> | 11 | #include <mach/bridge-regs.h> |
12 | 12 | ||
13 | .macro disable_fiq | 13 | .macro disable_fiq |
14 | .endm | 14 | .endm |
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index 38c986853590..b3e13958821d 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h | |||
@@ -44,44 +44,6 @@ | |||
44 | #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M | 44 | #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M |
45 | 45 | ||
46 | /* | 46 | /* |
47 | * MBUS bridge registers. | ||
48 | */ | ||
49 | #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) | ||
50 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | ||
51 | #define CPU_RESET 0x00000002 | ||
52 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
53 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
54 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
55 | #define SOFT_RESET 0x00000001 | ||
56 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
57 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
58 | #define BRIDGE_INT_TIMER0 0x0002 | ||
59 | #define BRIDGE_INT_TIMER1 0x0004 | ||
60 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | ||
61 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
62 | #define IRQ_CAUSE_LOW_OFF 0x0000 | ||
63 | #define IRQ_MASK_LOW_OFF 0x0004 | ||
64 | #define IRQ_CAUSE_HIGH_OFF 0x0010 | ||
65 | #define IRQ_MASK_HIGH_OFF 0x0014 | ||
66 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
67 | #define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) | ||
68 | #define L2_WRITETHROUGH 0x00000010 | ||
69 | |||
70 | /* | ||
71 | * Supported devices and revisions. | ||
72 | */ | ||
73 | #define MV88F6281_DEV_ID 0x6281 | ||
74 | #define MV88F6281_REV_Z0 0 | ||
75 | #define MV88F6281_REV_A0 2 | ||
76 | |||
77 | #define MV88F6192_DEV_ID 0x6192 | ||
78 | #define MV88F6192_REV_Z0 0 | ||
79 | #define MV88F6192_REV_A0 2 | ||
80 | |||
81 | #define MV88F6180_DEV_ID 0x6180 | ||
82 | #define MV88F6180_REV_A0 2 | ||
83 | |||
84 | /* | ||
85 | * Register Map | 47 | * Register Map |
86 | */ | 48 | */ |
87 | #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) | 49 | #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) |
@@ -99,6 +61,8 @@ | |||
99 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | 61 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) |
100 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) | 62 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) |
101 | 63 | ||
64 | #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) | ||
65 | |||
102 | #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) | 66 | #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) |
103 | 67 | ||
104 | #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) | 68 | #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) |
@@ -119,5 +83,18 @@ | |||
119 | 83 | ||
120 | #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) | 84 | #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) |
121 | 85 | ||
86 | /* | ||
87 | * Supported devices and revisions. | ||
88 | */ | ||
89 | #define MV88F6281_DEV_ID 0x6281 | ||
90 | #define MV88F6281_REV_Z0 0 | ||
91 | #define MV88F6281_REV_A0 2 | ||
92 | |||
93 | #define MV88F6192_DEV_ID 0x6192 | ||
94 | #define MV88F6192_REV_Z0 0 | ||
95 | #define MV88F6192_REV_A0 2 | ||
96 | |||
97 | #define MV88F6180_DEV_ID 0x6180 | ||
98 | #define MV88F6180_REV_A0 2 | ||
122 | 99 | ||
123 | #endif | 100 | #endif |
diff --git a/arch/arm/mach-kirkwood/include/mach/system.h b/arch/arm/mach-kirkwood/include/mach/system.h index 23a1914c1da8..7568e95d279b 100644 --- a/arch/arm/mach-kirkwood/include/mach/system.h +++ b/arch/arm/mach-kirkwood/include/mach/system.h | |||
@@ -9,8 +9,7 @@ | |||
9 | #ifndef __ASM_ARCH_SYSTEM_H | 9 | #ifndef __ASM_ARCH_SYSTEM_H |
10 | #define __ASM_ARCH_SYSTEM_H | 10 | #define __ASM_ARCH_SYSTEM_H |
11 | 11 | ||
12 | #include <mach/hardware.h> | 12 | #include <mach/bridge-regs.h> |
13 | #include <mach/kirkwood.h> | ||
14 | 13 | ||
15 | static inline void arch_idle(void) | 14 | static inline void arch_idle(void) |
16 | { | 15 | { |
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c index 06083b23bb44..28020abf49e1 100644 --- a/arch/arm/mach-kirkwood/irq.c +++ b/arch/arm/mach-kirkwood/irq.c | |||
@@ -12,6 +12,7 @@ | |||
12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
13 | #include <linux/irq.h> | 13 | #include <linux/irq.h> |
14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
15 | #include <mach/bridge-regs.h> | ||
15 | #include <plat/irq.h> | 16 | #include <plat/irq.h> |
16 | #include <asm/gpio.h> | 17 | #include <asm/gpio.h> |
17 | #include "common.h" | 18 | #include "common.h" |
diff --git a/arch/arm/mach-loki/addr-map.c b/arch/arm/mach-loki/addr-map.c index 0332d8f5c18c..b9537c97beba 100644 --- a/arch/arm/mach-loki/addr-map.c +++ b/arch/arm/mach-loki/addr-map.c | |||
@@ -38,6 +38,7 @@ | |||
38 | /* | 38 | /* |
39 | * CPU Address Decode Windows registers | 39 | * CPU Address Decode Windows registers |
40 | */ | 40 | */ |
41 | #define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x)) | ||
41 | #define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4)) | 42 | #define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4)) |
42 | #define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4)) | 43 | #define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4)) |
43 | #define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4)) | 44 | #define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4)) |
diff --git a/arch/arm/mach-loki/include/mach/bridge-regs.h b/arch/arm/mach-loki/include/mach/bridge-regs.h new file mode 100644 index 000000000000..a3fabf70044f --- /dev/null +++ b/arch/arm/mach-loki/include/mach/bridge-regs.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-loki/include/mach/bridge-regs.h | ||
3 | * | ||
4 | * This file is licensed under the terms of the GNU General Public | ||
5 | * License version 2. This program is licensed "as is" without any | ||
6 | * warranty of any kind, whether express or implied. | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARCH_BRIDGE_REGS_H | ||
10 | #define __ASM_ARCH_BRIDGE_REGS_H | ||
11 | |||
12 | #include <mach/loki.h> | ||
13 | |||
14 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
15 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
16 | |||
17 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
18 | #define SOFT_RESET 0x00000001 | ||
19 | |||
20 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
21 | |||
22 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
23 | #define BRIDGE_INT_TIMER0 0x0002 | ||
24 | #define BRIDGE_INT_TIMER1 0x0004 | ||
25 | #define BRIDGE_INT_TIMER1_CLR 0x0004 | ||
26 | |||
27 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
28 | #define IRQ_CAUSE_OFF 0x0000 | ||
29 | #define IRQ_MASK_OFF 0x0004 | ||
30 | |||
31 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
32 | |||
33 | #endif | ||
diff --git a/arch/arm/mach-loki/include/mach/entry-macro.S b/arch/arm/mach-loki/include/mach/entry-macro.S index 332af38ec13c..bc917ed3a62d 100644 --- a/arch/arm/mach-loki/include/mach/entry-macro.S +++ b/arch/arm/mach-loki/include/mach/entry-macro.S | |||
@@ -8,7 +8,7 @@ | |||
8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <mach/loki.h> | 11 | #include <mach/bridge-regs.h> |
12 | 12 | ||
13 | .macro disable_fiq | 13 | .macro disable_fiq |
14 | .endm | 14 | .endm |
diff --git a/arch/arm/mach-loki/include/mach/loki.h b/arch/arm/mach-loki/include/mach/loki.h index c00af6ba5578..bfca7c265f43 100644 --- a/arch/arm/mach-loki/include/mach/loki.h +++ b/arch/arm/mach-loki/include/mach/loki.h | |||
@@ -58,20 +58,6 @@ | |||
58 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) | 58 | #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) |
59 | 59 | ||
60 | #define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000) | 60 | #define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000) |
61 | #define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x)) | ||
62 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
63 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
64 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
65 | #define SOFT_RESET 0x00000001 | ||
66 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
67 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
68 | #define BRIDGE_INT_TIMER0 0x0002 | ||
69 | #define BRIDGE_INT_TIMER1 0x0004 | ||
70 | #define BRIDGE_INT_TIMER1_CLR 0x0004 | ||
71 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
72 | #define IRQ_CAUSE_OFF 0x0000 | ||
73 | #define IRQ_MASK_OFF 0x0004 | ||
74 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
75 | 61 | ||
76 | #define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000) | 62 | #define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000) |
77 | 63 | ||
diff --git a/arch/arm/mach-loki/include/mach/system.h b/arch/arm/mach-loki/include/mach/system.h index c1de36fe9b37..71895199a534 100644 --- a/arch/arm/mach-loki/include/mach/system.h +++ b/arch/arm/mach-loki/include/mach/system.h | |||
@@ -9,8 +9,7 @@ | |||
9 | #ifndef __ASM_ARCH_SYSTEM_H | 9 | #ifndef __ASM_ARCH_SYSTEM_H |
10 | #define __ASM_ARCH_SYSTEM_H | 10 | #define __ASM_ARCH_SYSTEM_H |
11 | 11 | ||
12 | #include <mach/hardware.h> | 12 | #include <mach/bridge-regs.h> |
13 | #include <mach/loki.h> | ||
14 | 13 | ||
15 | static inline void arch_idle(void) | 14 | static inline void arch_idle(void) |
16 | { | 15 | { |
diff --git a/arch/arm/mach-loki/irq.c b/arch/arm/mach-loki/irq.c index e1f97338d5b7..76b211bfcca2 100644 --- a/arch/arm/mach-loki/irq.c +++ b/arch/arm/mach-loki/irq.c | |||
@@ -12,6 +12,7 @@ | |||
12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
13 | #include <linux/irq.h> | 13 | #include <linux/irq.h> |
14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
15 | #include <mach/bridge-regs.h> | ||
15 | #include <plat/irq.h> | 16 | #include <plat/irq.h> |
16 | #include "common.h" | 17 | #include "common.h" |
17 | 18 | ||
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index a575daaa62d1..9ba595083dab 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <asm/mach/map.h> | 20 | #include <asm/mach/map.h> |
21 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
22 | #include <mach/mv78xx0.h> | 22 | #include <mach/mv78xx0.h> |
23 | #include <mach/bridge-regs.h> | ||
23 | #include <plat/cache-feroceon-l2.h> | 24 | #include <plat/cache-feroceon-l2.h> |
24 | #include <plat/ehci-orion.h> | 25 | #include <plat/ehci-orion.h> |
25 | #include <plat/orion_nand.h> | 26 | #include <plat/orion_nand.h> |
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h new file mode 100644 index 000000000000..2d14c4fe294d --- /dev/null +++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | ||
3 | * | ||
4 | * This file is licensed under the terms of the GNU General Public | ||
5 | * License version 2. This program is licensed "as is" without any | ||
6 | * warranty of any kind, whether express or implied. | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARCH_BRIDGE_REGS_H | ||
10 | #define __ASM_ARCH_BRIDGE_REGS_H | ||
11 | |||
12 | #include <mach/mv78xx0.h> | ||
13 | |||
14 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | ||
15 | #define L2_WRITETHROUGH 0x00020000 | ||
16 | |||
17 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
18 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
19 | |||
20 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
21 | #define SOFT_RESET 0x00000001 | ||
22 | |||
23 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
24 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
25 | #define BRIDGE_INT_TIMER0 0x0002 | ||
26 | #define BRIDGE_INT_TIMER1 0x0004 | ||
27 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | ||
28 | |||
29 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
30 | #define IRQ_CAUSE_ERR_OFF 0x0000 | ||
31 | #define IRQ_CAUSE_LOW_OFF 0x0004 | ||
32 | #define IRQ_CAUSE_HIGH_OFF 0x0008 | ||
33 | #define IRQ_MASK_ERR_OFF 0x000c | ||
34 | #define IRQ_MASK_LOW_OFF 0x0010 | ||
35 | #define IRQ_MASK_HIGH_OFF 0x0014 | ||
36 | |||
37 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
38 | |||
39 | #endif | ||
diff --git a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S index fbfb2693ce6c..66ae2d29e773 100644 --- a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S +++ b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S | |||
@@ -8,7 +8,7 @@ | |||
8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <mach/mv78xx0.h> | 11 | #include <mach/bridge-regs.h> |
12 | 12 | ||
13 | .macro disable_fiq | 13 | .macro disable_fiq |
14 | .endm | 14 | .endm |
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index 582cffc733ad..d715b92b0908 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
@@ -59,37 +59,6 @@ | |||
59 | * Core-specific peripheral registers. | 59 | * Core-specific peripheral registers. |
60 | */ | 60 | */ |
61 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) | 61 | #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) |
62 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | ||
63 | #define L2_WRITETHROUGH 0x00020000 | ||
64 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
65 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
66 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
67 | #define SOFT_RESET 0x00000001 | ||
68 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
69 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
70 | #define BRIDGE_INT_TIMER0 0x0002 | ||
71 | #define BRIDGE_INT_TIMER1 0x0004 | ||
72 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | ||
73 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
74 | #define IRQ_CAUSE_ERR_OFF 0x0000 | ||
75 | #define IRQ_CAUSE_LOW_OFF 0x0004 | ||
76 | #define IRQ_CAUSE_HIGH_OFF 0x0008 | ||
77 | #define IRQ_MASK_ERR_OFF 0x000c | ||
78 | #define IRQ_MASK_LOW_OFF 0x0010 | ||
79 | #define IRQ_MASK_HIGH_OFF 0x0014 | ||
80 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
81 | |||
82 | /* | ||
83 | * Supported devices and revisions. | ||
84 | */ | ||
85 | #define MV78X00_Z0_DEV_ID 0x6381 | ||
86 | #define MV78X00_REV_Z0 1 | ||
87 | |||
88 | #define MV78100_DEV_ID 0x7810 | ||
89 | #define MV78100_REV_A0 1 | ||
90 | |||
91 | #define MV78200_DEV_ID 0x7820 | ||
92 | #define MV78200_REV_A0 1 | ||
93 | 62 | ||
94 | /* | 63 | /* |
95 | * Register Map | 64 | * Register Map |
@@ -135,5 +104,16 @@ | |||
135 | 104 | ||
136 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) | 105 | #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) |
137 | 106 | ||
107 | /* | ||
108 | * Supported devices and revisions. | ||
109 | */ | ||
110 | #define MV78X00_Z0_DEV_ID 0x6381 | ||
111 | #define MV78X00_REV_Z0 1 | ||
112 | |||
113 | #define MV78100_DEV_ID 0x7810 | ||
114 | #define MV78100_REV_A0 1 | ||
115 | |||
116 | #define MV78200_DEV_ID 0x7820 | ||
117 | #define MV78200_REV_A0 1 | ||
138 | 118 | ||
139 | #endif | 119 | #endif |
diff --git a/arch/arm/mach-mv78xx0/include/mach/system.h b/arch/arm/mach-mv78xx0/include/mach/system.h index 1d6350b22d0b..66e7ce4e90bd 100644 --- a/arch/arm/mach-mv78xx0/include/mach/system.h +++ b/arch/arm/mach-mv78xx0/include/mach/system.h | |||
@@ -9,8 +9,7 @@ | |||
9 | #ifndef __ASM_ARCH_SYSTEM_H | 9 | #ifndef __ASM_ARCH_SYSTEM_H |
10 | #define __ASM_ARCH_SYSTEM_H | 10 | #define __ASM_ARCH_SYSTEM_H |
11 | 11 | ||
12 | #include <mach/hardware.h> | 12 | #include <mach/bridge-regs.h> |
13 | #include <mach/mv78xx0.h> | ||
14 | 13 | ||
15 | static inline void arch_idle(void) | 14 | static inline void arch_idle(void) |
16 | { | 15 | { |
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 30b7e4bcdbc7..f289b0ea7dcf 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c | |||
@@ -13,7 +13,7 @@ | |||
13 | #include <linux/pci.h> | 13 | #include <linux/pci.h> |
14 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
15 | #include <asm/gpio.h> | 15 | #include <asm/gpio.h> |
16 | #include <mach/mv78xx0.h> | 16 | #include <mach/bridge-regs.h> |
17 | #include <plat/irq.h> | 17 | #include <plat/irq.h> |
18 | #include "common.h" | 18 | #include "common.h" |
19 | 19 | ||
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c index 719957e05d9e..c14d12137276 100644 --- a/arch/arm/mach-orion5x/addr-map.c +++ b/arch/arm/mach-orion5x/addr-map.c | |||
@@ -57,12 +57,14 @@ | |||
57 | /* | 57 | /* |
58 | * Helpers to get DDR bank info | 58 | * Helpers to get DDR bank info |
59 | */ | 59 | */ |
60 | #define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) | ||
60 | #define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3)) | 61 | #define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3)) |
61 | #define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3)) | 62 | #define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3)) |
62 | 63 | ||
63 | /* | 64 | /* |
64 | * CPU Address Decode Windows registers | 65 | * CPU Address Decode Windows registers |
65 | */ | 66 | */ |
67 | #define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) | ||
66 | #define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) | 68 | #define CPU_WIN_CTRL(n) ORION5X_BRIDGE_REG(0x000 | ((n) << 4)) |
67 | #define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) | 69 | #define CPU_WIN_BASE(n) ORION5X_BRIDGE_REG(0x004 | ((n) << 4)) |
68 | #define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) | 70 | #define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) |
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h new file mode 100644 index 000000000000..be896e59d3e7 --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-orion5x/include/mach/bridge-regs.h | ||
3 | * | ||
4 | * Orion CPU Bridge Registers | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_BRIDGE_REGS_H | ||
12 | #define __ASM_ARCH_BRIDGE_REGS_H | ||
13 | |||
14 | #include <mach/orion5x.h> | ||
15 | |||
16 | #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100) | ||
17 | |||
18 | #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) | ||
19 | |||
20 | #define CPU_RESET_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) | ||
21 | #define WDT_RESET 0x0002 | ||
22 | |||
23 | #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) | ||
24 | |||
25 | #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C) | ||
26 | |||
27 | #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110) | ||
28 | #define WDT_INT_REQ 0x0008 | ||
29 | |||
30 | #define BRIDGE_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x114) | ||
31 | #define BRIDGE_INT_TIMER0 0x0002 | ||
32 | #define BRIDGE_INT_TIMER1 0x0004 | ||
33 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | ||
34 | |||
35 | #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200) | ||
36 | |||
37 | #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204) | ||
38 | |||
39 | #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) | ||
40 | |||
41 | #endif | ||
diff --git a/arch/arm/mach-orion5x/include/mach/entry-macro.S b/arch/arm/mach-orion5x/include/mach/entry-macro.S index 4351937035cd..d658992e5401 100644 --- a/arch/arm/mach-orion5x/include/mach/entry-macro.S +++ b/arch/arm/mach-orion5x/include/mach/entry-macro.S | |||
@@ -8,7 +8,7 @@ | |||
8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <mach/orion5x.h> | 11 | #include <mach/bridge-regs.h> |
12 | 12 | ||
13 | .macro disable_fiq | 13 | .macro disable_fiq |
14 | .endm | 14 | .endm |
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 67bda31406dd..377a773ae53f 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h | |||
@@ -61,30 +61,10 @@ | |||
61 | #define ORION5X_PCI_MEM_SIZE SZ_128M | 61 | #define ORION5X_PCI_MEM_SIZE SZ_128M |
62 | 62 | ||
63 | /******************************************************************************* | 63 | /******************************************************************************* |
64 | * Supported Devices & Revisions | ||
65 | ******************************************************************************/ | ||
66 | /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ | ||
67 | #define MV88F5181_DEV_ID 0x5181 | ||
68 | #define MV88F5181_REV_B1 3 | ||
69 | #define MV88F5181L_REV_A0 8 | ||
70 | #define MV88F5181L_REV_A1 9 | ||
71 | /* Orion-NAS (88F5182) */ | ||
72 | #define MV88F5182_DEV_ID 0x5182 | ||
73 | #define MV88F5182_REV_A2 2 | ||
74 | /* Orion-2 (88F5281) */ | ||
75 | #define MV88F5281_DEV_ID 0x5281 | ||
76 | #define MV88F5281_REV_D0 4 | ||
77 | #define MV88F5281_REV_D1 5 | ||
78 | #define MV88F5281_REV_D2 6 | ||
79 | /* Orion-1-90 (88F6183) */ | ||
80 | #define MV88F6183_DEV_ID 0x6183 | ||
81 | #define MV88F6183_REV_B0 3 | ||
82 | |||
83 | /******************************************************************************* | ||
84 | * Orion Registers Map | 64 | * Orion Registers Map |
85 | ******************************************************************************/ | 65 | ******************************************************************************/ |
66 | |||
86 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) | 67 | #define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) |
87 | #define ORION5X_DDR_REG(x) (ORION5X_DDR_VIRT_BASE | (x)) | ||
88 | 68 | ||
89 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) | 69 | #define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) |
90 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) | 70 | #define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) |
@@ -97,34 +77,25 @@ | |||
97 | #define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) | 77 | #define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) |
98 | 78 | ||
99 | #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) | 79 | #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) |
100 | #define ORION5X_BRIDGE_REG(x) (ORION5X_BRIDGE_VIRT_BASE | (x)) | ||
101 | #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) | ||
102 | 80 | ||
103 | #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) | 81 | #define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) |
104 | #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) | ||
105 | 82 | ||
106 | #define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) | 83 | #define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) |
107 | #define ORION5X_PCIE_REG(x) (ORION5X_PCIE_VIRT_BASE | (x)) | ||
108 | 84 | ||
109 | #define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) | 85 | #define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) |
110 | #define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) | 86 | #define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) |
111 | #define ORION5X_USB0_REG(x) (ORION5X_USB0_VIRT_BASE | (x)) | ||
112 | 87 | ||
113 | #define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) | 88 | #define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) |
114 | #define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) | 89 | #define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) |
115 | #define ORION5X_XOR_REG(x) (ORION5X_XOR_VIRT_BASE | (x)) | ||
116 | 90 | ||
117 | #define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) | 91 | #define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) |
118 | #define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) | 92 | #define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) |
119 | #define ORION5X_ETH_REG(x) (ORION5X_ETH_VIRT_BASE | (x)) | ||
120 | 93 | ||
121 | #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) | 94 | #define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) |
122 | #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) | 95 | #define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) |
123 | #define ORION5X_SATA_REG(x) (ORION5X_SATA_VIRT_BASE | (x)) | ||
124 | 96 | ||
125 | #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) | 97 | #define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) |
126 | #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) | 98 | #define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) |
127 | #define ORION5X_USB1_REG(x) (ORION5X_USB1_VIRT_BASE | (x)) | ||
128 | 99 | ||
129 | /******************************************************************************* | 100 | /******************************************************************************* |
130 | * Device Bus Registers | 101 | * Device Bus Registers |
@@ -142,23 +113,24 @@ | |||
142 | #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) | 113 | #define DEV_BUS_INT_CAUSE ORION5X_DEV_BUS_REG(0x4d0) |
143 | #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) | 114 | #define DEV_BUS_INT_MASK ORION5X_DEV_BUS_REG(0x4d4) |
144 | 115 | ||
145 | /*************************************************************************** | 116 | /******************************************************************************* |
146 | * Orion CPU Bridge Registers | 117 | * Supported Devices & Revisions |
147 | **************************************************************************/ | 118 | ******************************************************************************/ |
148 | #define CPU_CONF ORION5X_BRIDGE_REG(0x100) | 119 | /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ |
149 | #define CPU_CTRL ORION5X_BRIDGE_REG(0x104) | 120 | #define MV88F5181_DEV_ID 0x5181 |
150 | #define CPU_RESET_MASK ORION5X_BRIDGE_REG(0x108) | 121 | #define MV88F5181_REV_B1 3 |
151 | #define WDT_RESET 0x0002 | 122 | #define MV88F5181L_REV_A0 8 |
152 | #define CPU_SOFT_RESET ORION5X_BRIDGE_REG(0x10c) | 123 | #define MV88F5181L_REV_A1 9 |
153 | #define POWER_MNG_CTRL_REG ORION5X_BRIDGE_REG(0x11C) | 124 | /* Orion-NAS (88F5182) */ |
154 | #define BRIDGE_CAUSE ORION5X_BRIDGE_REG(0x110) | 125 | #define MV88F5182_DEV_ID 0x5182 |
155 | #define WDT_INT_REQ 0x0008 | 126 | #define MV88F5182_REV_A2 2 |
156 | #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) | 127 | /* Orion-2 (88F5281) */ |
157 | #define BRIDGE_INT_TIMER0 0x0002 | 128 | #define MV88F5281_DEV_ID 0x5281 |
158 | #define BRIDGE_INT_TIMER1 0x0004 | 129 | #define MV88F5281_REV_D0 4 |
159 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | 130 | #define MV88F5281_REV_D1 5 |
160 | #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) | 131 | #define MV88F5281_REV_D2 6 |
161 | #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) | 132 | /* Orion-1-90 (88F6183) */ |
162 | 133 | #define MV88F6183_DEV_ID 0x6183 | |
134 | #define MV88F6183_REV_B0 3 | ||
163 | 135 | ||
164 | #endif | 136 | #endif |
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h index 9b8db1dcfa83..e912490fff23 100644 --- a/arch/arm/mach-orion5x/include/mach/system.h +++ b/arch/arm/mach-orion5x/include/mach/system.h | |||
@@ -11,8 +11,7 @@ | |||
11 | #ifndef __ASM_ARCH_SYSTEM_H | 11 | #ifndef __ASM_ARCH_SYSTEM_H |
12 | #define __ASM_ARCH_SYSTEM_H | 12 | #define __ASM_ARCH_SYSTEM_H |
13 | 13 | ||
14 | #include <mach/hardware.h> | 14 | #include <mach/bridge-regs.h> |
15 | #include <mach/orion5x.h> | ||
16 | 15 | ||
17 | static inline void arch_idle(void) | 16 | static inline void arch_idle(void) |
18 | { | 17 | { |
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index e03f7b45cb0d..d7512b925a85 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c | |||
@@ -15,7 +15,7 @@ | |||
15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <asm/gpio.h> | 17 | #include <asm/gpio.h> |
18 | #include <mach/orion5x.h> | 18 | #include <mach/bridge-regs.h> |
19 | #include <plat/irq.h> | 19 | #include <plat/irq.h> |
20 | #include "common.h" | 20 | #include "common.h" |
21 | 21 | ||
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c index 68acca98e638..41e6d5033d54 100644 --- a/arch/arm/mach-orion5x/mss2-setup.c +++ b/arch/arm/mach-orion5x/mss2-setup.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
27 | #include <asm/mach/pci.h> | 27 | #include <asm/mach/pci.h> |
28 | #include <mach/orion5x.h> | 28 | #include <mach/orion5x.h> |
29 | #include <mach/bridge-regs.h> | ||
29 | #include "common.h" | 30 | #include "common.h" |
30 | #include "mpp.h" | 31 | #include "mpp.h" |
31 | 32 | ||
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index d0a785a3b880..36dc5413cc97 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c | |||
@@ -196,6 +196,7 @@ static int __init pcie_setup(struct pci_sys_data *sys) | |||
196 | /***************************************************************************** | 196 | /***************************************************************************** |
197 | * PCI controller | 197 | * PCI controller |
198 | ****************************************************************************/ | 198 | ****************************************************************************/ |
199 | #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) | ||
199 | #define PCI_MODE ORION5X_PCI_REG(0xd00) | 200 | #define PCI_MODE ORION5X_PCI_REG(0xd00) |
200 | #define PCI_CMD ORION5X_PCI_REG(0xc00) | 201 | #define PCI_CMD ORION5X_PCI_REG(0xc00) |
201 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) | 202 | #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) |
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 6fa2923e6dca..bdeb166b4b20 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c | |||
@@ -16,7 +16,7 @@ | |||
16 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
17 | #include <linux/irq.h> | 17 | #include <linux/irq.h> |
18 | #include <asm/mach/time.h> | 18 | #include <asm/mach/time.h> |
19 | #include <mach/hardware.h> | 19 | #include <mach/bridge-regs.h> |
20 | 20 | ||
21 | /* | 21 | /* |
22 | * Number of timer ticks per jiffy. | 22 | * Number of timer ticks per jiffy. |
diff --git a/drivers/watchdog/orion5x_wdt.c b/drivers/watchdog/orion5x_wdt.c index 7529616739d2..2cde568e4fb0 100644 --- a/drivers/watchdog/orion5x_wdt.c +++ b/drivers/watchdog/orion5x_wdt.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/uaccess.h> | 22 | #include <linux/uaccess.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/spinlock.h> | 24 | #include <linux/spinlock.h> |
25 | #include <mach/bridge-regs.h> | ||
25 | #include <plat/orion5x_wdt.h> | 26 | #include <plat/orion5x_wdt.h> |
26 | 27 | ||
27 | /* | 28 | /* |