diff options
author | Mark Rutland <mark.rutland@arm.com> | 2012-11-12 11:46:40 -0500 |
---|---|---|
committer | Mark Rutland <mark.rutland@arm.com> | 2013-01-31 10:51:22 -0500 |
commit | fd5583a4c271ec03e2da04196aaaab177b385eb8 (patch) | |
tree | be1867cb175da753b36b8b63dd00f7a36f94cd9c | |
parent | b8e243431fa11f542a0fd94e939543bcb7d236ee (diff) |
arm: arch_timer: split cntfrq accessor
The CNTFRQ register is not duplicated for physical and virtual timers,
and accessing it as if it were is confusing.
Instead, use a separate accessor which doesn't take the access type
as a parameter.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-rw-r--r-- | arch/arm/kernel/arch_timer.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c index eb78f43cf290..f31c9ee18af2 100644 --- a/arch/arm/kernel/arch_timer.c +++ b/arch/arm/kernel/arch_timer.c | |||
@@ -51,8 +51,7 @@ static bool arch_timer_use_virtual = true; | |||
51 | #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) | 51 | #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) |
52 | 52 | ||
53 | #define ARCH_TIMER_REG_CTRL 0 | 53 | #define ARCH_TIMER_REG_CTRL 0 |
54 | #define ARCH_TIMER_REG_FREQ 1 | 54 | #define ARCH_TIMER_REG_TVAL 1 |
55 | #define ARCH_TIMER_REG_TVAL 2 | ||
56 | 55 | ||
57 | #define ARCH_TIMER_PHYS_ACCESS 0 | 56 | #define ARCH_TIMER_PHYS_ACCESS 0 |
58 | #define ARCH_TIMER_VIRT_ACCESS 1 | 57 | #define ARCH_TIMER_VIRT_ACCESS 1 |
@@ -101,9 +100,6 @@ static inline u32 arch_timer_reg_read(const int access, const int reg) | |||
101 | case ARCH_TIMER_REG_TVAL: | 100 | case ARCH_TIMER_REG_TVAL: |
102 | asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); | 101 | asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); |
103 | break; | 102 | break; |
104 | case ARCH_TIMER_REG_FREQ: | ||
105 | asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); | ||
106 | break; | ||
107 | } | 103 | } |
108 | } | 104 | } |
109 | 105 | ||
@@ -121,6 +117,13 @@ static inline u32 arch_timer_reg_read(const int access, const int reg) | |||
121 | return val; | 117 | return val; |
122 | } | 118 | } |
123 | 119 | ||
120 | static inline u32 arch_timer_get_cntfrq(void) | ||
121 | { | ||
122 | u32 val; | ||
123 | asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); | ||
124 | return val; | ||
125 | } | ||
126 | |||
124 | static inline u64 arch_counter_get_cntpct(void) | 127 | static inline u64 arch_counter_get_cntpct(void) |
125 | { | 128 | { |
126 | u64 cval; | 129 | u64 cval; |
@@ -253,8 +256,7 @@ static int arch_timer_available(void) | |||
253 | u32 freq; | 256 | u32 freq; |
254 | 257 | ||
255 | if (arch_timer_rate == 0) { | 258 | if (arch_timer_rate == 0) { |
256 | freq = arch_timer_reg_read(ARCH_TIMER_PHYS_ACCESS, | 259 | freq = arch_timer_get_cntfrq(); |
257 | ARCH_TIMER_REG_FREQ); | ||
258 | 260 | ||
259 | /* Check the timer frequency. */ | 261 | /* Check the timer frequency. */ |
260 | if (freq == 0) { | 262 | if (freq == 0) { |