amd-xgbe: Add traffic class support

This patch adds support for traffic classes as well as support
for Data Center Bridging interfaces related to traffic classes
and priority flow control.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

8 files changed, 508 insertions, 27 deletions

diff --git a/drivers/net/ethernet/amd/Kconfig b/drivers/net/ethernet/amd/Kconfig
index 98ef8ff8fa08..8319c99331b0 100644
--- a/drivers/net/ethernet/amd/Kconfig
+++ b/drivers/net/ethernet/amd/Kconfig
@@ -192,4 +192,14 @@ config AMD_XGBE
           To compile this driver as a module, choose M here: the module
           will be called amd-xgbe.
 
+config AMD_XGBE_DCB
+        bool "Data Center Bridging (DCB) support"
+        default n
+        depends on AMD_XGBE && DCB
+        ---help---
+          Say Y here to enable Data Center Bridging (DCB) support in the
+          driver.
+
+          If unsure, say N.
+
 endif # NET_VENDOR_AMD
diff --git a/drivers/net/ethernet/amd/xgbe/Makefile b/drivers/net/ethernet/amd/xgbe/Makefile
index 66c49b43e5f2..171a7e68048d 100644
--- a/drivers/net/ethernet/amd/xgbe/Makefile
+++ b/drivers/net/ethernet/amd/xgbe/Makefile
@@ -4,4 +4,5 @@ amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \
                  xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \
                  xgbe-ptp.o
 
+amd-xgbe-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o
 amd-xgbe-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
index 646702cd75fb..cc25a3a9e7cf 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
@@ -322,6 +322,9 @@
 #define MAC_MACA_INC                    4
 #define MAC_HTR_INC                     4
 
+#define MAC_RQC2_INC                    4
+#define MAC_RQC2_Q_PER_REG              4
+
 /* MAC register entry bit positions and sizes */
 #define MAC_HWF0R_ADDMACADRSEL_INDEX    18
 #define MAC_HWF0R_ADDMACADRSEL_WIDTH    5
@@ -361,6 +364,8 @@
 #define MAC_HWF1R_HASHTBLSZ_WIDTH       3
 #define MAC_HWF1R_L3L4FNUM_INDEX        27
 #define MAC_HWF1R_L3L4FNUM_WIDTH        4
+#define MAC_HWF1R_NUMTC_INDEX           21
+#define MAC_HWF1R_NUMTC_WIDTH           3
 #define MAC_HWF1R_RSSEN_INDEX           20
 #define MAC_HWF1R_RSSEN_WIDTH           1
 #define MAC_HWF1R_RXFIFOSIZE_INDEX      0
@@ -433,8 +438,12 @@
 #define MAC_RCR_LM_WIDTH                1
 #define MAC_RCR_RE_INDEX                0
 #define MAC_RCR_RE_WIDTH                1
+#define MAC_RFCR_PFCE_INDEX             8
+#define MAC_RFCR_PFCE_WIDTH             1
 #define MAC_RFCR_RFE_INDEX              0
 #define MAC_RFCR_RFE_WIDTH              1
+#define MAC_RFCR_UP_INDEX               1
+#define MAC_RFCR_UP_WIDTH               1
 #define MAC_RQC0R_RXQ0EN_INDEX          0
 #define MAC_RQC0R_RXQ0EN_WIDTH          2
 #define MAC_SSIR_SNSINC_INDEX           8
@@ -704,6 +713,8 @@
 
 #define MTL_RQDCM_INC                   4
 #define MTL_RQDCM_Q_PER_REG             4
+#define MTL_TCPM_INC                    4
+#define MTL_TCPM_TC_PER_REG             4
 
 /* MTL register entry bit positions and sizes */
 #define MTL_OMR_ETSALG_INDEX            5
@@ -722,9 +733,6 @@
 #define MTL_Q_TQOMR                     0x00
 #define MTL_Q_TQUR                      0x04
 #define MTL_Q_TQDR                      0x08
-#define MTL_Q_TCECR                     0x10
-#define MTL_Q_TCESR                     0x14
-#define MTL_Q_TCQWR                     0x18
 #define MTL_Q_RQOMR                     0x40
 #define MTL_Q_RQMPOCR                   0x44
 #define MTL_Q_RQDR                      0x4c
@@ -732,8 +740,6 @@
 #define MTL_Q_ISR                       0x74
 
 /* MTL queue register entry bit positions and sizes */
-#define MTL_Q_TCQWR_QW_INDEX            0
-#define MTL_Q_TCQWR_QW_WIDTH            21
 #define MTL_Q_RQOMR_EHFC_INDEX          7
 #define MTL_Q_RQOMR_EHFC_WIDTH          1
 #define MTL_Q_RQOMR_RFA_INDEX           8
@@ -748,6 +754,8 @@
 #define MTL_Q_RQOMR_RTC_WIDTH           2
 #define MTL_Q_TQOMR_FTQ_INDEX           0
 #define MTL_Q_TQOMR_FTQ_WIDTH           1
+#define MTL_Q_TQOMR_Q2TCMAP_INDEX       8
+#define MTL_Q_TQOMR_Q2TCMAP_WIDTH       3
 #define MTL_Q_TQOMR_TQS_INDEX           16
 #define MTL_Q_TQOMR_TQS_WIDTH           10
 #define MTL_Q_TQOMR_TSF_INDEX           1
@@ -794,10 +802,14 @@
 #define MTL_TC_INC                      MTL_Q_INC
 
 #define MTL_TC_ETSCR                    0x10
+#define MTL_TC_ETSSR                    0x14
+#define MTL_TC_QWR                      0x18
 
 /* MTL traffic class register entry bit positions and sizes */
 #define MTL_TC_ETSCR_TSA_INDEX          0
 #define MTL_TC_ETSCR_TSA_WIDTH          2
+#define MTL_TC_QWR_QW_INDEX             0
+#define MTL_TC_QWR_QW_WIDTH             21
 
 /* MTL traffic class register value */
 #define MTL_TSA_SP                      0x00
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dcb.c b/drivers/net/ethernet/amd/xgbe/xgbe-dcb.c
new file mode 100644
index 000000000000..7d6a49b24321
--- /dev/null
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dcb.c
@@ -0,0 +1,270 @@
+/*
+ * AMD 10Gb Ethernet driver
+ *
+ * This file is available to you under your choice of the following two
+ * licenses:
+ *
+ * License 1: GPLv2
+ *
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
+ *
+ * This file is free software; you may copy, redistribute and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file incorporates work covered by the following copyright and
+ * permission notice:
+ *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
+ *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
+ *     Inc. unless otherwise expressly agreed to in writing between Synopsys
+ *     and you.
+ *
+ *     The Software IS NOT an item of Licensed Software or Licensed Product